199 lines
7.7 KiB
C
199 lines
7.7 KiB
C
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#ifndef _I2C_H
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#define _I2C_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct i2c_adapter;
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/**
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* struct i2c_msg - an I2C transaction segment beginning with START
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* @addr: Slave address, either seven or ten bits. When this is a ten
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* bit address, I2C_M_TEN must be set in @flags and the adapter
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* must support I2C_FUNC_10BIT_ADDR.
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* @flags: I2C_M_RD is handled by all adapters. No other flags may be
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* provided unless the adapter exported the relevant I2C_FUNC_*
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* flags through i2c_check_functionality().
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* @len: Number of data bytes in @buf being read from or written to the
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* I2C slave address. For read transactions where I2C_M_RECV_LEN
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* is set, the caller guarantees that this buffer can hold up to
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* 32 bytes in addition to the initial length byte sent by the
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* slave (plus, if used, the SMBus PEC); and this value will be
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* incremented by the number of block data bytes received.
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* @buf: The buffer into which data is read, or from which it's written.
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*
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* An i2c_msg is the low level representation of one segment of an I2C
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* transaction. It is visible to drivers in the @i2c_transfer() procedure,
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* to userspace from i2c-dev, and to I2C adapter drivers through the
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* @i2c_adapter.@master_xfer() method.
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*
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* Except when I2C "protocol mangling" is used, all I2C adapters implement
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* the standard rules for I2C transactions. Each transaction begins with a
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* START. That is followed by the slave address, and a bit encoding read
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* versus write. Then follow all the data bytes, possibly including a byte
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* with SMBus PEC. The transfer terminates with a NAK, or when all those
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* bytes have been transferred and ACKed. If this is the last message in a
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* group, it is followed by a STOP. Otherwise it is followed by the next
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* @i2c_msg transaction segment, beginning with a (repeated) START.
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*
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* Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
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* passing certain @flags may have changed those standard protocol behaviors.
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* Those flags are only for use with broken/nonconforming slaves, and with
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* adapters which are known to support the specific mangling options they
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* need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
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*/
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struct i2c_msg {
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uint16_t addr; /* slave address */
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uint16_t flags;
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#define I2C_M_RD 0x0001 /* read data, from slave to master */
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/* I2C_M_RD is guaranteed to be 0x0001! */
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#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
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#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
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#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_NOSTART */
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#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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uint16_t len; /* msg length */
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uint8_t *buf; /* pointer to msg data */
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};
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/* To determine what functionality is present */
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#define I2C_FUNC_I2C 0x00000001
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#define I2C_FUNC_10BIT_ADDR 0x00000002
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#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_IGNORE_NAK etc. */
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#define I2C_FUNC_SMBUS_PEC 0x00000008
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#define I2C_FUNC_NOSTART 0x00000010 /* I2C_M_NOSTART */
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#define I2C_FUNC_SLAVE 0x00000020
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#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
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#define I2C_FUNC_SMBUS_QUICK 0x00010000
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#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
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#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
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#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000
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#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000
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#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000
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#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000
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#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
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#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000
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#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
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#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
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#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
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#define I2C_FUNC_SMBUS_HOST_NOTIFY 0x10000000
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#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
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I2C_FUNC_SMBUS_WRITE_BYTE)
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#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \
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I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
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#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \
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I2C_FUNC_SMBUS_WRITE_WORD_DATA)
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#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
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I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
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#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \
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I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
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#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_PROC_CALL | \
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I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK | \
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I2C_FUNC_SMBUS_PEC)
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/*
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* Data for SMBus Messages
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*/
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#define I2C_SMBUS_BLOCK_MAX 32 /* As specified in SMBus standard */
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union i2c_smbus_data {
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uint8_t byte;
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uint16_t word;
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uint8_t block[I2C_SMBUS_BLOCK_MAX + 2]; /* block[0] is used for length */
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/* and one more for user-space compatibility */
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};
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/* i2c_smbus_xfer read or write markers */
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#define I2C_SMBUS_READ 1
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#define I2C_SMBUS_WRITE 0
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/* SMBus transaction types (size parameter in the above functions)
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Note: these no longer correspond to the (arbitrary) PIIX4 internal codes! */
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#define I2C_SMBUS_QUICK 0
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#define I2C_SMBUS_BYTE 1
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#define I2C_SMBUS_BYTE_DATA 2
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#define I2C_SMBUS_WORD_DATA 3
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#define I2C_SMBUS_PROC_CALL 4
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#define I2C_SMBUS_BLOCK_DATA 5
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#define I2C_SMBUS_I2C_BLOCK_BROKEN 6
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#define I2C_SMBUS_BLOCK_PROC_CALL 7 /* SMBus 2.0 */
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#define I2C_SMBUS_I2C_BLOCK_DATA 8
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/*flags for the client struct: */
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#define I2C_CLIENT_PEC 0x04 /* Use Packet Error Checking */
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#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */
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/* Must equal I2C_M_TEN below */
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#define I2C_CLIENT_SLAVE 0x20 /* we are the slave */
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#define I2C_CLIENT_HOST_NOTIFY 0x40 /* We want to use I2C host notify */
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#define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */
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#define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */
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/* Must match I2C_M_STOP|IGNORE_NAK */
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enum i2c_slave_event {
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I2C_SLAVE_READ_REQUESTED,
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I2C_SLAVE_WRITE_REQUESTED,
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I2C_SLAVE_READ_PROCESSED,
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I2C_SLAVE_WRITE_RECEIVED,
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I2C_SLAVE_STOP,
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};
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typedef int (*i2c_slave_cb_t)(struct i2c_adapter *, enum i2c_slave_event, u8 *);
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struct i2c_algorithm {
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/* master_xfer should return the number of messages successfully
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processed, or a negative value on error */
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int (*master_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num);
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int (*reg_slave)(struct i2c_adapter *adap);
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int (*unreg_slave)(struct i2c_adapter *adap);
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};
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/*
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* i2c_adapter is the structure used to identify a physical i2c bus along
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* with the access algorithms necessary to access it.
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*/
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struct i2c_adapter {
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const struct i2c_algorithm *algo; /* the algorithm to access the bus */
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void *algo_data;
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void *dw_dev;
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int retries;
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int timeout; /* in jiffies */
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SemaphoreHandle_t xMutex;
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i2c_slave_cb_t slave_cb; /* callback for slave mode */
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int open_count;
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unsigned short flags; /* div., see below */
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unsigned short addr; /* chip address - NOTE: 7bit */
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char name[16];
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};
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static __INLINE int i2c_slave_event(struct i2c_adapter *adap,
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enum i2c_slave_event event, u8 *val)
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{
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return adap->slave_cb(adap, event, val);
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}
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void i2c_init(void);
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int i2c_add_adapter(struct i2c_adapter *adap);
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struct i2c_adapter *i2c_open(const char *i2cdev);
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void i2c_close(struct i2c_adapter *adap);
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int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
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int i2c_slave_register(struct i2c_adapter *adap, u8 addr, i2c_slave_cb_t slave_cb);
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int i2c_slave_unregister(struct i2c_adapter *adap);
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#ifdef __cplusplus
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}
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#endif
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#endif
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