90 lines
3.5 KiB
C
90 lines
3.5 KiB
C
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/*
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* ark_i2s.h
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*
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*/
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#ifndef __I2S_H
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#define __I2S_H
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/*
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* I2S Controller Register and Bit Definitions
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*/
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#define I2S_SACR0 0x00 /* Global Control Register */
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#define I2S_SACR1 0x04 /* Serial Audio I 2 S/MSB-Justified Control Register */
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#define I2S_SASR0 0x0C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
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#define I2S_SAIMR 0x14 /* Serial Audio Interrupt Mask Register */
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#define I2S_SAICR 0x18 /* Serial Audio Interrupt Clear Register */
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#define I2S_SADR 0x80 /* Serial Audio Data Register (TX and RX FIFO access Register). */
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#define SACR0_RFIFIFIRSTBIT (1 << 26) /* rx fifo first bit */
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#define SACR0_TFIFOFIRSTBIT (1 << 25) /* Tx fifo first bit */
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#define SACR0_CHANLOCK (1 << 24) /* Channel lock(left first or right first) */
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#define SACR0_SCBIT (1 << 23) /* */
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#define SACR0_BITS (1 << 22) /* I2S Bit Select(16/32 bits) */
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#define SACR0_SYNCINV (1 << 21) /* SYNC Clock Invert */
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#define SACR0_RFTH_MASK (0x1F << 16)
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#define SACR0_RFTH(x) ((x) << 16) /* Rx FIFO Interrupt or DMA Trigger Threshold */
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#define SACR0_TFTH_MASK (0X1F << 8)
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#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
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#define SACR0_STRF (1 << 7) /* DAC output clk edge select */
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#define SACR0_RDMAEN (1 << 6) /* RX DMA Enable */
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#define SACR0_ENLBF (1 << 5) /* Enable Loopback */
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#define SACR0_RST (1 << 4) /* FIFO, i2s Register Reset */
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#define SACR0_TDMAEN (1 << 3) /* TX DMA Enable */
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#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
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#define SACR0_SYNCD (1 << 1) /* Word Select(sync) Clock Direction */
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#define SACR0_ENB (1 << 0) /* Enable I2S Link */
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#define SACR1_DRPL (1 << 1) /* Disable Replaying Function */
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#define SACR1_DREC (1 << 0) /* Disable Recording Function */
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#define SASR0_RFL(x) ((x) << 16) /* Rx FIFO Level */
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#define SASR0_TFL(x) ((x) << 8) /* Tx FIFO Level */
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#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
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#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
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#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
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#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
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#define SASR0_BSY (1 << 2) /* I2S Busy */
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#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
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#define SASR0_TNF (1 << 0) /* Tx FIFO Not Full */
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#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
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#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
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#define SAICR_RFS (1 << 4) /* Clear Rx FIFO Service Interrupt */
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#define SAICR_TFS (1 << 3) /* Clear Tx FIFO Service Interrupt */
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#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
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#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
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#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
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#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
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struct ark_i2s_cfg {
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int master;
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int rates;
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int channels;
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int bits;
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int lfirst; //0: right channel first; 1:left channel first;
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};
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struct ark_i2s_data {
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unsigned int base;
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unsigned int nco_reg;
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int id;
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int clkid;
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int full_duplex;
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struct ark_i2s_cfg cfg[2];
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struct dma_chan *dma_txch;
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struct dma_chan *dma_rxch;
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SemaphoreHandle_t mutex;
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void *extdata;
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};
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int ark_i2s_init(struct ark_i2s_data *i2s, int flags);
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void ark_i2s_set_volume(struct ark_i2s_data *i2s,int lvol, int rvol);
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int ark_i2s_set_rate(struct ark_i2s_data *i2s, int stream, unsigned int rate);
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int ark_i2s_set_params(struct ark_i2s_data *i2s, int stream, int rates, int channels, int bits);
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int ark_i2s_startup(struct ark_i2s_data *i2s, int stream);
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void ark_i2s_stop(struct ark_i2s_data *i2s, int stream);
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#endif
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