432 lines
15 KiB
C
432 lines
15 KiB
C
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#include "FreeRTOS.h"
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#include "chip.h"
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#include "board.h"
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#define PLL_DIV_MASK 0xFF
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#define PLL_DIV_OFFSET 0
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#define PLL_NO_MASK 0x3
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#define PLL_NO_OFFSET 12
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#define PLL_ENA (1 << 14)
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typedef struct {
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uint32_t clkid;
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uint32_t clktype;
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uint32_t source;
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int clksource[MAX_CLK_SOURCE_NUM];
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int source_index;
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int div;
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uint32_t enable_reg[MAX_CLK_ENABLE_BITS];
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int enable_offset[MAX_CLK_ENABLE_BITS];
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int enable_bits;
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union {
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uint32_t fixed_freq;
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struct {
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int div;
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int mult;
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} fixed_fator_property;
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struct {
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uint32_t cfgreg;
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uint32_t refclkreg;
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uint32_t offset;
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uint32_t mask;
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} pll_property;
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struct {
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uint32_t cfgreg;
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uint32_t analogreg;
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} dds_property;
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struct {
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uint32_t cfgreg;
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int index_offset;
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int index_value;
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uint32_t index_mask;
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int div_offset;
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int div_value;
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uint32_t div_mask;
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int div_mode;
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uint32_t inv_reg;
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int inv_offset;
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uint32_t inv_mask;
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int inv_value;
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} sys_property;
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} u;
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} xClockProperty;
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xClockProperty xClocks[] = {
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{.clkid = CLK_XTAL32K, .clktype = FIXED_CLOCK, .u.fixed_freq = 32768},
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{.clkid = CLK_XTAL24M, .clktype = FIXED_CLOCK, .u.fixed_freq = 24000000},
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{.clkid = CLK_240MHZ, .clktype = FIXED_FACTOR_CLOCK, .clksource = {CLK_XTAL24M},
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.u.fixed_fator_property.div = 1, .u.fixed_fator_property.mult = 10},
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{.clkid = CLK_12MHZ, .clktype = FIXED_FACTOR_CLOCK, .clksource = {CLK_XTAL24M},
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.u.fixed_fator_property.div = 2, .u.fixed_fator_property.mult = 1},
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{.clkid = CLK_6MHZ, .clktype = FIXED_FACTOR_CLOCK, .clksource = {CLK_XTAL24M},
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.u.fixed_fator_property.div = 4, .u.fixed_fator_property.mult = 1},
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{.clkid = CLK_CPUPLL, .clktype = PLL_CLOCK, .clksource = {CLK_6MHZ, CLK_12MHZ},
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.u.pll_property.cfgreg = 0x60000088, .u.pll_property.refclkreg = 0x60000140,
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.u.pll_property.offset = 0, .u.pll_property.mask = 1},
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{.clkid = CLK_SYSPLL, .clktype = PLL_CLOCK, .clksource = {CLK_6MHZ, CLK_12MHZ},
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.u.pll_property.cfgreg = 0x6000008c, .u.pll_property.refclkreg = 0x60000140,
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.u.pll_property.offset = 1, .u.pll_property.mask = 1},
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{.clkid = CLK_DDRPLL, .clktype = PLL_CLOCK, .clksource = {CLK_6MHZ, CLK_12MHZ},
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.u.pll_property.cfgreg = 0x60000090, .u.pll_property.refclkreg = 0x60000140,
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.u.pll_property.offset = 2, .u.pll_property.mask = 1},
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{.clkid = CLK_VPUPLL, .clktype = PLL_CLOCK, .clksource = {CLK_6MHZ, CLK_12MHZ},
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.u.pll_property.cfgreg = 0x60000094, .u.pll_property.refclkreg = 0x60000140,
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.u.pll_property.offset = 3, .u.pll_property.mask = 1},
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{.clkid = CLK_DDR, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M,CLK_DDRPLL},
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.u.sys_property.cfgreg = 0x60000040, .u.sys_property.index_offset = 24,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = -1,
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.u.sys_property.div_offset = 26, .u.sys_property.div_mask = 0x7,
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.u.sys_property.div_value = -1, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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{.clkid = CLK_CPU, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M,CLK_CPUPLL},
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.u.sys_property.cfgreg = 0x60000040, .u.sys_property.index_offset = 0,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = -1,
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.u.sys_property.div_offset = 2, .u.sys_property.div_mask = 0x7,
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.u.sys_property.div_value = -1, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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{.clkid = CLK_AHB, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M,CLK_SYSPLL},
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.u.sys_property.cfgreg = 0x60000040, .u.sys_property.index_offset = 8,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = -1,
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.u.sys_property.div_offset = 10, .u.sys_property.div_mask = 0x7,
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.u.sys_property.div_value = -1, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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{.clkid = CLK_APB, .clktype = SYS_CLOCK, .clksource = {CLK_AHB},
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.u.sys_property.cfgreg = 0x60000040,
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.u.sys_property.div_offset = 16, .u.sys_property.div_mask = 0x3,
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.u.sys_property.div_value = -1, .u.sys_property.div_mode = DIVMODE_DOUBLE,},
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{.clkid = CLK_SPI0, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M, CLK_CPUPLL},
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.enable_reg = {0x60000064, 0x60000064}, .enable_offset = {30, 31}, .enable_bits = 2,
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.u.sys_property.cfgreg = 0x60000064, .u.sys_property.index_offset = 4,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 1,
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.u.sys_property.div_offset = 0, .u.sys_property.div_mask = 0xf,
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.u.sys_property.div_value = 4, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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{.clkid = CLK_SPI1, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M, CLK_CPUPLL},
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.u.sys_property.cfgreg = 0x60000064, .u.sys_property.index_offset = 20,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 1,
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.u.sys_property.div_offset = 16, .u.sys_property.div_mask = 0xf,
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.u.sys_property.div_value = 10, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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#if DEVICE_TYPE_SELECT != EMMC_FLASH
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{.clkid = CLK_SDMMC0, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M, CLK_SYSPLL},
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.enable_reg = {0x60000048, 0x60000050, 0x60000058}, .enable_offset = {0, 12, 15}, .enable_bits = 3,
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.u.sys_property.cfgreg = 0x60000048, .u.sys_property.index_offset = 7,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 0,},
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#else
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{.clkid = CLK_SDMMC0, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M, CLK_SYSPLL},
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.enable_reg = {0x60000048, 0x60000050, 0x60000058}, .enable_offset = {6, 12, 15}, .enable_bits = 3,
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.u.sys_property.cfgreg = 0x60000048, .u.sys_property.index_offset = 7,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 1,
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.u.sys_property.div_offset = 0, .u.sys_property.div_mask = 0x1f,
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.u.sys_property.div_value = 10, .u.sys_property.div_mode = DIVMODE_PONEDOUBLE,},
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#endif
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{.clkid = CLK_LCD, .clktype = SYS_CLOCK, .clksource = {CLK_SYSPLL, CLK_VPUPLL, CLK_XTAL24M, CLK_XTAL24M},
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.enable_reg = {0x60000050, 0x60000058, 0x60000058, 0x60000058}, .enable_offset = {3, 18, 17, 16}, .enable_bits = 4,
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.u.sys_property.cfgreg = 0x6000004c, .u.sys_property.index_offset = 0,
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.u.sys_property.index_mask = 0x3, .u.sys_property.index_value = 0,
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.u.sys_property.div_offset = 3, .u.sys_property.div_mask = 0x1f,
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.u.sys_property.div_value = 11, .u.sys_property.div_mode = DIVMODE_PLUSONE,
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#ifdef LCD_CLK_INVERSE
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.u.sys_property.inv_reg = 0x6000004c, .u.sys_property.inv_offset = 8,
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.u.sys_property.inv_mask = 0x1, .u.sys_property.inv_value = 1,
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#endif
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},
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{.clkid = CLK_TIMER, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M, CLK_CPUPLL},
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.u.sys_property.cfgreg = 0x60000068, .u.sys_property.index_offset = 4,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 0,
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.u.sys_property.div_offset = 0, .u.sys_property.div_mask = 0xf,
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.u.sys_property.div_value = 1, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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{.clkid = CLK_MFC, .clktype = SYS_CLOCK, .clksource = {CLK_SYSPLL, CLK_VPUPLL, CLK_XTAL24M},
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.enable_reg = {0x60000050, 0x60000058}, .enable_offset = {6, 23}, .enable_bits = 2,
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.u.sys_property.cfgreg = 0x60000068, .u.sys_property.index_offset = 8,
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.u.sys_property.index_mask = 0x3, .u.sys_property.index_value = 1,
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.u.sys_property.div_offset = 11, .u.sys_property.div_mask = 0x1f,
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.u.sys_property.div_value = -1, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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{.clkid = CLK_PWM, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M, CLK_240MHZ},
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.enable_reg = {0x60000054, 0x60000058}, .enable_offset = {10, 10}, .enable_bits = 2,
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.u.sys_property.cfgreg = 0x60000044, .u.sys_property.index_offset = 8,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 0,
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.u.sys_property.div_offset = 4, .u.sys_property.div_mask = 0xf,
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.u.sys_property.div_value = 1, .u.sys_property.div_mode = DIVMODE_PLUSONE,},
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{.clkid = CLK_CAN0, .clktype = SYS_CLOCK, .clksource = {CLK_APB},
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.enable_reg = {0x60000054}, .enable_offset = {19}, .enable_bits = 1,
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.u.sys_property.div_value = 1,},
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{.clkid = CLK_CAN1, .clktype = SYS_CLOCK, .clksource = {CLK_APB},
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.enable_reg = {0x60000054}, .enable_offset = {20}, .enable_bits = 1,
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.u.sys_property.div_value = 1,},
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{.clkid = CLK_ADC, .clktype = SYS_CLOCK, .clksource = {CLK_XTAL24M},
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.enable_reg = {0x60000054, 0x60000058}, .enable_offset = {14, 13}, .enable_bits = 2,
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.u.sys_property.cfgreg = 0x60000068, .u.sys_property.div_offset = 16,
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.u.sys_property.div_mask = 0x7fff, .u.sys_property.div_value = 642,
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.u.sys_property.div_mode = DIVMODE_PONEDOUBLE,},
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{.clkid = CLK_I2S, .clktype = SYS_CLOCK, .clksource = {CLK_240MHZ, CLK_SYSPLL},
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.enable_reg = {0x60000054, 0x60000058, 0x60000058}, .enable_offset = {12, 12, 11}, .enable_bits = 3,
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.u.sys_property.cfgreg = 0x60000044, .u.sys_property.index_offset = 16,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 0,
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.u.sys_property.div_value = 1,},
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{.clkid = CLK_I2S1, .clktype = SYS_CLOCK, .clksource = {CLK_240MHZ, CLK_SYSPLL},
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.enable_reg = {0x60000054, 0x60000144, 0x60000144}, .enable_offset = {22, 1, 0}, .enable_bits = 3,
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.u.sys_property.cfgreg = 0x60000140, .u.sys_property.index_offset = 4,
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.u.sys_property.index_mask = 0x1, .u.sys_property.index_value = 0,
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.u.sys_property.div_value = 1,},
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};
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#define CLOCK_NUM (sizeof(xClocks) / sizeof(xClocks[0]))
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static xClockProperty *clk_get(uint32_t clkid)
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{
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int i;
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for (i = 0; i < CLOCK_NUM; i++) {
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if (xClocks[i].clkid == clkid) {
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return &xClocks[i];
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}
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}
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return NULL;
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}
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static uint32_t clk_fixed_get_rate(xClockProperty *clk)
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{
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return clk->u.fixed_freq;
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}
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static uint32_t clk_fixed_factor_get_rate(xClockProperty *clk)
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{
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xClockProperty *parentclk = clk_get(clk->clksource[0]);
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configASSERT(parentclk);
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return clk_fixed_get_rate(parentclk) * clk->u.fixed_fator_property.mult
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/ clk->u.fixed_fator_property.div;
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}
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static uint32_t clk_pll_get_rate(xClockProperty *clk)
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{
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uint32_t parent_rate;
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uint32_t div, no, reg;
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configASSERT(clk);
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parent_rate = ulClkGetRate(clk->clksource[clk->source_index]);
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reg = readl(clk->u.pll_property.cfgreg);
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no = (reg >> PLL_NO_OFFSET) & PLL_NO_MASK;
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div = (reg >> PLL_DIV_OFFSET) & PLL_DIV_MASK;
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return (parent_rate * div) / (1 << no);
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}
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static uint32_t clk_sys_get_rate(xClockProperty *clk)
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{
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uint32_t parent_rate;
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configASSERT(clk);
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configASSERT(clk->div);
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parent_rate = ulClkGetRate(clk->clksource[clk->source_index]);
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return parent_rate / clk->div;
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}
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static void clk_pll_init(xClockProperty *clk)
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{
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configASSERT(clk);
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clk->source_index = (readl(clk->u.pll_property.refclkreg) >> clk->u.pll_property.offset)
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& clk->u.pll_property.mask;
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}
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static int clk_get_div(int div, int divmode)
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{
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switch(divmode) {
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case DIVMODE_NOZERO:
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div = div ? div : 1;
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break;
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case DIVMODE_PLUSONE:
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div = div + 1;
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break;
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case DIVMODE_DOUBLE:
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div *= 2;
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break;
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case DIVMODE_EXPONENT:
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div = 1 << div;
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break;
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case DIVMODE_PONEDOUBLE:
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div = (div + 1) * 2;
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break;
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}
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return div;
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}
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static __INLINE int clk_set_div(int div, int divmode)
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{
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switch(divmode) {
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case DIVMODE_PLUSONE:
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div = div - 1;
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break;
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case DIVMODE_DOUBLE:
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div /= 2;
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break;
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case DIVMODE_EXPONENT:
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div = fls(div) - 1;
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break;
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case DIVMODE_PONEDOUBLE:
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div = div / 2 - 1;
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break;
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}
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return div;
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}
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|
static void clk_sys_set_rate(xClockProperty *clk, uint32_t freq)
|
||
|
|
{
|
||
|
|
int div;
|
||
|
|
uint32_t reg;
|
||
|
|
uint32_t parent_rate;
|
||
|
|
|
||
|
|
configASSERT(clk);
|
||
|
|
|
||
|
|
parent_rate = ulClkGetRate(clk->clksource[clk->source_index]);
|
||
|
|
div = DIV_ROUND_UP(parent_rate, freq);
|
||
|
|
clk->div = div;
|
||
|
|
div = clk_set_div(div, clk->u.sys_property.div_mode);
|
||
|
|
reg = readl(clk->u.sys_property.cfgreg);
|
||
|
|
reg &= ~(clk->u.sys_property.div_mask << clk->u.sys_property.div_offset);
|
||
|
|
reg |= (div & clk->u.sys_property.div_mask) << clk->u.sys_property.div_offset;
|
||
|
|
writel(reg, clk->u.sys_property.cfgreg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void clk_sys_init(xClockProperty *clk)
|
||
|
|
{
|
||
|
|
uint32_t reg;
|
||
|
|
uint32_t val;
|
||
|
|
|
||
|
|
configASSERT(clk);
|
||
|
|
|
||
|
|
if (clk->u.sys_property.index_value >= 0 && clk->u.sys_property.index_mask) {
|
||
|
|
clk->source_index = clk->u.sys_property.index_value;
|
||
|
|
val = clk->u.sys_property.index_value == 3 ? 4 : clk->u.sys_property.index_value;
|
||
|
|
reg = readl(clk->u.sys_property.cfgreg);
|
||
|
|
reg &= ~(clk->u.sys_property.index_mask << clk->u.sys_property.index_offset);
|
||
|
|
reg |= (val & clk->u.sys_property.index_mask) << clk->u.sys_property.index_offset;
|
||
|
|
writel(reg, clk->u.sys_property.cfgreg);
|
||
|
|
} else if (clk->u.sys_property.index_mask) {
|
||
|
|
reg = readl(clk->u.sys_property.cfgreg);
|
||
|
|
val = (reg >> clk->u.sys_property.index_offset) & clk->u.sys_property.index_mask;
|
||
|
|
clk->source_index = val == 4 ? 3 : val;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (clk->u.sys_property.div_value >= 0 && clk->u.sys_property.div_mask) {
|
||
|
|
val = clk_set_div(clk->u.sys_property.div_value, clk->u.sys_property.div_mode);
|
||
|
|
clk->div = clk_get_div(val, clk->u.sys_property.div_mode);
|
||
|
|
reg = readl(clk->u.sys_property.cfgreg);
|
||
|
|
reg &= ~(clk->u.sys_property.div_mask << clk->u.sys_property.div_offset);
|
||
|
|
reg |= (val & clk->u.sys_property.div_mask) << clk->u.sys_property.div_offset;
|
||
|
|
writel(reg, clk->u.sys_property.cfgreg);
|
||
|
|
} else if (clk->u.sys_property.div_mask) {
|
||
|
|
reg = readl(clk->u.sys_property.cfgreg);
|
||
|
|
val = (reg >> clk->u.sys_property.div_offset) & clk->u.sys_property.div_mask;
|
||
|
|
clk->div = clk_get_div(val, clk->u.sys_property.div_mode);
|
||
|
|
} else if (clk->u.sys_property.div_value > 0) {
|
||
|
|
clk->div = clk->u.sys_property.div_value;
|
||
|
|
} else {
|
||
|
|
clk->div = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (clk->u.sys_property.inv_reg) {
|
||
|
|
reg = readl(clk->u.sys_property.inv_reg);
|
||
|
|
reg &= ~(clk->u.sys_property.inv_mask << clk->u.sys_property.inv_offset);
|
||
|
|
reg |= (clk->u.sys_property.inv_value & clk->u.sys_property.inv_mask)
|
||
|
|
<< clk->u.sys_property.inv_offset;
|
||
|
|
writel(reg, clk->u.sys_property.inv_reg);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void clk_sys_enable(xClockProperty *clk)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
configASSERT(clk);
|
||
|
|
|
||
|
|
for (i = 0; i < clk->enable_bits; i++)
|
||
|
|
writel(readl(clk->enable_reg[i]) | (1 << clk->enable_offset[i]),
|
||
|
|
clk->enable_reg[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void clk_sys_disable(xClockProperty *clk)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
configASSERT(clk);
|
||
|
|
|
||
|
|
for (i = 0; i < clk->enable_bits; i++)
|
||
|
|
writel(readl(clk->enable_reg[i]) & ~(1 << clk->enable_offset[i]),
|
||
|
|
clk->enable_reg[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
void vClkInit(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
xClockProperty *clk;
|
||
|
|
|
||
|
|
for (i = 0; i < CLOCK_NUM; i++) {
|
||
|
|
clk = &xClocks[i];
|
||
|
|
if (clk->clktype == PLL_CLOCK) {
|
||
|
|
clk_pll_init(clk);
|
||
|
|
} else if (clk->clktype == SYS_CLOCK) {
|
||
|
|
clk_sys_init(clk);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t ulClkGetRate(uint32_t clkid)
|
||
|
|
{
|
||
|
|
xClockProperty *clk = clk_get(clkid);
|
||
|
|
|
||
|
|
if (clk == NULL)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
switch (clk->clktype) {
|
||
|
|
case FIXED_CLOCK:
|
||
|
|
return clk_fixed_get_rate(clk);
|
||
|
|
case FIXED_FACTOR_CLOCK:
|
||
|
|
return clk_fixed_factor_get_rate(clk);
|
||
|
|
case PLL_CLOCK:
|
||
|
|
return clk_pll_get_rate(clk);
|
||
|
|
case SYS_CLOCK:
|
||
|
|
return clk_sys_get_rate(clk);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void vClkSetRate(uint32_t clkid, uint32_t freq)
|
||
|
|
{
|
||
|
|
xClockProperty *clk = clk_get(clkid);
|
||
|
|
|
||
|
|
if (clk == NULL)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (clk->clktype == SYS_CLOCK)
|
||
|
|
clk_sys_set_rate(clk, freq);
|
||
|
|
}
|
||
|
|
|
||
|
|
void vClkEnable(uint32_t clkid)
|
||
|
|
{
|
||
|
|
xClockProperty *clk = clk_get(clkid);
|
||
|
|
|
||
|
|
if (clk == NULL)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (clk->clktype == SYS_CLOCK)
|
||
|
|
clk_sys_enable(clk);
|
||
|
|
}
|
||
|
|
|
||
|
|
void vClkDisable(uint32_t clkid)
|
||
|
|
{
|
||
|
|
xClockProperty *clk = clk_get(clkid);
|
||
|
|
|
||
|
|
if (clk == NULL)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (clk->clktype == SYS_CLOCK)
|
||
|
|
clk_sys_disable(clk);
|
||
|
|
}
|
||
|
|
|