364 lines
8.6 KiB
C
364 lines
8.6 KiB
C
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2011, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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//-----------------------------------------------------------------------------
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// Reg Reads Writes
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//----------------------------------------------------------------------------
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// 0 ID code Unpredictable
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// 0 cache type Unpredictable
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// 0 TCM status Unpredictable
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// 1 Control Control
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// 2 Translation table base Translation table base
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// 3 Domain access control Domain access control
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// 4 (Reserved)
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// 5 Data fault status Data fault status
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// 5 Instruction fault status Instruction fault status
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// 6 Fault address Fault address
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// 7 cache operations cache operations
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// 8 Unpredictable TLB operations
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// 9 cache lockdown cache lockdown
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// 9 TCM region TCM region
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// 10 TLB lockdown TLB lockdown
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// 11 (Reserved)
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// 12 (Reserved)
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// 13 FCSE PID FCSE PID
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// 13 Context ID Context ID
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// 14 (Reserved)
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// 15 Test configuration Test configuration
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//-----------------------------------------------------------------------------
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/** \page cp15_f CP15 Functions.
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*
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* \section CP15 function Usage
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*
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* Methods to manage the Coprocessor 15. Coprocessor 15, or System Control
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* Coprocessor CP15, is used to configure and control all the items in the
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* list below:
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* <ul>
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* <li> ARM core
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* <li> caches (Icache, Dcache and write buffer)
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* <li> TCM
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* <li> MMU
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* <li> Other system options
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* </ul>
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* \section Usage
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*
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* -# Enable or disable D cache with Enable_D_cache and Disable_D_cache
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* -# Enable or disable I cache with Enable_I_cache and Disable_I_cache
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*
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* Related files:\n
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* \ref cp15.h\n
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* \ref cp15.c.\n
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*/
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/** \file */
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include "chip.h"
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#if defined(__ICCARM__)
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#include <intrinsics.h>
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#endif
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/*----------------------------------------------------------------------------
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* Global functions
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*----------------------------------------------------------------------------*/
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/**
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* \brief Check Instruction cache
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* \return 0 if I_cache disable, 1 if I_cache enable
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*/
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unsigned int CP15_IsIcacheEnabled(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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return ((control & (1 << CP15_I_BIT)) != 0);
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}
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/**
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* \brief Enable Instruction cache
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*/
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void CP15_EnableIcache(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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// Check if cache is disabled
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if ((control & (1 << CP15_I_BIT)) == 0) {
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control |= (1 << CP15_I_BIT);
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CP15_WriteControl(control);
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TRACE_INFO("I cache enabled.\n\r");
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}
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else {
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TRACE_INFO("I cache is already enabled.\n\r");
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}
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}
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/**
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* \brief Disable Instruction cache
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*/
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void CP15_DisableIcache(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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// Check if cache is enabled
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if ((control & (1 << CP15_I_BIT)) != 0) {
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control &= ~(1ul << CP15_I_BIT);
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CP15_WriteControl(control);
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TRACE_INFO("I cache disabled.\n\r");
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}
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else {
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TRACE_INFO("I cache is already disabled.\n\r");
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}
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}
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/**
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* \brief Check MMU
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* \return 0 if MMU disable, 1 if MMU enable
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*/
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unsigned int CP15_IsMMUEnabled(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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return ((control & (1 << CP15_M_BIT)) != 0);
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}
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/**
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* \brief Enable MMU
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*/
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void CP15_EnableMMU(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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// Check if MMU is disabled
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if ((control & (1 << CP15_M_BIT)) == 0) {
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control |= (1 << CP15_M_BIT);
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CP15_WriteControl(control);
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TRACE_INFO("MMU enabled.\n\r");
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}
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else {
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TRACE_INFO("MMU is already enabled.\n\r");
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}
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}
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/**
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* \brief Disable MMU
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*/
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void CP15_DisableMMU(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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// Check if MMU is enabled
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if ((control & (1 << CP15_M_BIT)) != 0) {
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control &= ~(1ul << CP15_M_BIT);
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control &= ~(1ul << CP15_C_BIT);
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CP15_WriteControl(control);
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TRACE_INFO("MMU disabled.\n\r");
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}
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else {
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TRACE_INFO("MMU is already disabled.\n\r");
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}
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}
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/**
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* \brief Check D_cache
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* \return 0 if D_cache disable, 1 if D_cache enable (with MMU of course)
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*/
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unsigned int CP15_IsDcacheEnabled(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0);
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}
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/**
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* \brief Enable Data cache
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*/
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void CP15_EnableDcache(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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if( !CP15_IsMMUEnabled() ) {
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TRACE_ERROR("Do nothing: MMU not enabled\n\r");
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}
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else {
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// Check if cache is disabled
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if ((control & (1 << CP15_C_BIT)) == 0) {
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control |= (1 << CP15_C_BIT);
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CP15_WriteControl(control);
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TRACE_INFO("D cache enabled.\n\r");
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}
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else {
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TRACE_INFO("D cache is already enabled.\n\r");
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}
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}
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}
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/**
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* \brief Disable Data cache
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*/
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void CP15_DisableDcache(void)
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{
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unsigned int control;
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control = CP15_ReadControl();
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// Check if cache is enabled
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if ((control & (1 << CP15_C_BIT)) != 0) {
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control &= ~(1ul << CP15_C_BIT);
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CP15_WriteControl(control);
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TRACE_INFO("D cache disabled.\n\r");
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}
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else {
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TRACE_INFO("D cache is already disabled.\n\r");
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}
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}
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/**
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* \brief Invalidate TLB
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*/
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void CP15_InvalidateTLB(void)
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{
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asm("MCR p15, 0, %0, c8, c3, 0" : : "r"(1));
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asm("DSB");
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}
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/**
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* \brief Clean Data cache
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*/
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void CP15_CacheClean(uint8_t CacheType)
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{
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configASSERT(!CacheType);
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CP15_SelectDCache();
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CP15_CleanDCacheBySetWay();
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asm("DSB");
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}
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/**
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* \brief Invalidate D/Icache
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*/
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void CP15_CacheInvalidate(uint8_t CacheType)
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{
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if(CacheType)
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{
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CP15_SelectICache();
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CP15_InvalidateIcacheInnerSharable();
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asm("DSB");
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asm("ISB");
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}
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else
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{
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CP15_SelectDCache();
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CP15_InvalidateDcacheBySetWay();
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asm("DSB");
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asm("ISB");
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}
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}
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/**
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* \brief Flush(Clean and invalidate) Data cache
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*/
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void CP15_CacheFlush(uint8_t CacheType)
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{
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configASSERT(!CacheType);
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CP15_SelectDCache();
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CP15_CleanInvalidateDCacheBySetWay();
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asm("DSB");
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}
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/**
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* \brief Invalidate Data cache by address
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*/
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void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add)
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{
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CP15_SelectDCache();
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CP15_InvalidateDcacheByMva(S_Add, E_Add);
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}
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/**
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* \brief Clean Data cache by address
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*/
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void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add)
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{
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CP15_SelectDCache();
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CP15_CleanDCacheByMva(S_Add, E_Add);
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}
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/**
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* \brief Flush Data cache by address
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*/
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void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add)
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{
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CP15_SelectDCache();
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CP15_CleanInvalidateDcacheByMva(S_Add, E_Add);
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}
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