266 lines
8.7 KiB
ArmAsm
266 lines
8.7 KiB
ArmAsm
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/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2014, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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/*
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IAR startup file for Arkmicro microcontrollers.
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*/
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION IRQ_STACK:DATA:NOROOT(3)
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SECTION FIQ_STACK:DATA:NOROOT(3)
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SECTION UND_STACK:DATA:NOROOT(3)
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SECTION ABT_STACK:DATA:NOROOT(3)
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SECTION SVC_STACK:DATA:NOROOT(3)
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SECTION CSTACK:DATA:NOROOT(3)
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//------------------------------------------------------------------------------
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// Headers
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Definitions
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//------------------------------------------------------------------------------
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#define AIC 0xFC06E000
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#define AIC_IVR 0x10
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#define AIC_EOICR 0x38
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#define REG_SFR_AICREDIR 0xF8028054
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#define REG_SFR_UID 0xF8028050
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#define AICREDIR_KEY 0x5F67B102
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MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
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#define ARM_MODE_ABT 0x17
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#define ARM_MODE_FIQ 0x11
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#define ARM_MODE_IRQ 0x12
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#define ARM_MODE_SVC 0x13
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#define ARM_MODE_SYS 0x1F
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#define ARM_MODE_UND 0x1B
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#define I_BIT 0x80
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#define F_BIT 0x40
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//------------------------------------------------------------------------------
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// Startup routine
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//------------------------------------------------------------------------------
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/*
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Exception vectors
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*/
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SECTION .intvec:CODE:NOROOT(2)
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PUBLIC resetVector
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EXTERN FreeRTOS_IRQ_Handler
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EXTERN Undefined_C_Handler
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EXTERN FreeRTOS_SWI_Handler
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EXTERN Prefetch_C_Handler
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EXTERN Abort_C_Handler
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PUBLIC FIQ_Handler
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ARM
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__iar_init$$done: ; The interrupt vector is not needed
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; until after copy initialization is done
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resetVector:
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; All default exception handlers (except reset) are
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; defined as weak symbol definitions.
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; If a handler is defined by the application it will take precedence.
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LDR pc, =resetHandler ; Reset
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LDR pc, Undefined_Addr ; Undefined instructions
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LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
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LDR pc, Prefetch_Addr ; Prefetch abort
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LDR pc, Abort_Addr ; Data abort
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B . ; RESERVED
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LDR PC,IRQ_Addr ; 0x18 IRQ
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LDR PC,FIQ_Addr ; 0x1c FIQ
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IRQ_Addr: DCD FreeRTOS_IRQ_Handler
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Undefined_Addr: DCD Undefined_C_Handler
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SWI_Addr: DCD FreeRTOS_SWI_Handler
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Abort_Addr: DCD Abort_C_Handler
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Prefetch_Addr: DCD Prefetch_C_Handler
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FIQ_Addr: DCD FIQ_Handler
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/*
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After a reset, execution starts here, the mode is ARM, supervisor
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with interrupts disabled.
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Initializes the chip and branches to the main() function.
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*/
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SECTION .cstartup:CODE:NOROOT(2)
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PUBLIC resetHandler
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EXTERN LowLevelInit
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EXTERN ?main
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REQUIRE resetVector
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EXTERN CP15_InvalidateBTB
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EXTERN CP15_InvalidateTranslationTable
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EXTERN CP15_InvalidateIcache
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EXTERN CP15_InvalidateDcacheBySetWay
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ARM
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resetHandler:
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MSR CPSR_c, #(ARM_MODE_SVC | F_BIT | I_BIT)
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LDR sp, =SFE(SVC_STACK) ; End of SVC stack
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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;; Set up the normal interrupt stack pointer.
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MSR CPSR_c, #(ARM_MODE_IRQ | F_BIT | I_BIT)
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LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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;; Set up the fast interrupt stack pointer.
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MSR CPSR_c, #(ARM_MODE_FIQ | F_BIT | I_BIT)
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LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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MSR CPSR_c, #(ARM_MODE_ABT | F_BIT | I_BIT)
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LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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MSR CPSR_c, #(ARM_MODE_UND | F_BIT | I_BIT)
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LDR sp, =SFE(UND_STACK) ; End of UND_STACK
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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MSR CPSR_c, #(ARM_MODE_SYS | F_BIT | I_BIT)
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LDR sp, =SFE(CSTACK) ; End of SYS stack
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BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
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MSR CPSR_c, #(ARM_MODE_SVC | F_BIT | I_BIT)
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CPSIE A
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/* Enable VFP */
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/* - Enable access to CP10 and CP11 in CP15.CACR */
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MRC p15, 0, r0, c1, c0, 2
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ORR r0, r0, #0xf00000
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MCR p15, 0, r0, c1, c0, 2
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/* - Enable access to CP10 and CP11 in CP15.NSACR */
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/* - Set FPEXC.EN (B30) */
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#ifdef __ARMVFP__
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MOV r3, #0x40000000
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VMSR FPEXC, r3
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#endif
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// Redirect FIQ to IRQ
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/* LDR r0, =AICREDIR_KEY
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LDR r1, = REG_SFR_UID
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LDR r2, = REG_SFR_AICREDIR
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LDR r3,[r1]
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EORS r0, r0, r3
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ORRS r0, r0, #0x01
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STR r0, [r2] */
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/* Perform low-level initialization of the chip using LowLevelInit() */
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LDR r0, =LowLevelInit
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BLX r0
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MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Regsiter into r0
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TST r0, #0x1 ; Is the MMU enabled?
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BICNE r0, r0, #0x1 ; Clear bit 0
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TST r0, #0x4 ; Is the Dcache enabled?
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BICNE r0, r0, #0x4 ; Clear bit 2
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MCRNE p15, 0, r0, c1, c0, 0 ; Write value back
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DMB
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BL CP15_InvalidateTranslationTable
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BL CP15_InvalidateBTB
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BL CP15_InvalidateIcache
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BL CP15_InvalidateDcacheBySetWay
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DMB
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ISB
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/* Branch to main() */
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LDR r0, =?main
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BLX r0
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/* Loop indefinitely when program is finished */
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loop4:
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B loop4
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;------------------------------------------------------------------------------
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;- Function : FIQ_Handler
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;- Treatments : FIQ Controller Interrupt Handler.
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;- Called Functions : AIC_IVR[interrupt]
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;------------------------------------------------------------------------------
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SAIC DEFINE 0xFC068400
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AIC_FVR DEFINE 0x14
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SECTION .text:CODE:NOROOT(2)
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ARM
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FIQ_Handler:
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/* Save interrupt context on the stack to allow nesting */
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SUB lr, lr, #4
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STMFD sp!, {lr}
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/* MRS lr, SPSR */
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STMFD sp!, {r0}
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/* Write in the IVR to support Protect Mode */
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LDR lr, =SAIC
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LDR r0, [r14, #AIC_IVR]
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STR lr, [r14, #AIC_IVR]
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/* Branch to interrupt handler in Supervisor mode */
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MSR CPSR_c, #ARM_MODE_SVC
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STMFD sp!, {r1-r3, r4, r12, lr}
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MOV r14, pc
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BX r0
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LDMIA sp!, {r1-r3, r4, r12, lr}
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MSR CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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/* Acknowledge interrupt */
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LDR lr, =SAIC
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STR lr, [r14, #AIC_EOICR]
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/* Restore interrupt context and branch back to calling code */
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LDMIA sp!, {r0}
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/* MSR SPSR_cxsf, lr */
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LDMIA sp!, {pc}^
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END
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