From 3b3c63f1f3a74b1a5a5e5cfbc51866ae6accdbaa Mon Sep 17 00:00:00 2001 From: LiJie <1366947981@qq.com> Date: Sat, 17 May 2025 14:22:08 +0800 Subject: [PATCH] =?UTF-8?q?A27R=E7=89=88=E6=9C=AC=E4=BF=AE=E6=94=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- A58-AMTLDR/AMT630Hv100/Exe/AMTLDR.bin | Bin 0 -> 9404 bytes A58-AMTLDR/AMT630Hv100/Exe/AMTLDR.out | Bin 0 -> 86232 bytes A58-AMTLDR/AMT630Hv100/Exe/spildr.bin | Bin 0 -> 8360 bytes A58-AMTLDR/AMT630Hv100/List/AMTLDR.map | 361 + A58-AMTLDR/AMT630Hv100/Obj/AMTLDR.pbd | Bin 0 -> 391984 bytes A58-AMTLDR/AMT630Hv100/Obj/AMTLDR.pbd.browse | Bin 0 -> 391984 bytes A58-AMTLDR/AMT630Hv100/Obj/AMTLDR.pbd.linf | 17 + A58-AMTLDR/AMT630Hv100/Obj/AMTLDR.pbw | 36086 +++ A58-AMTLDR/AMT630Hv100/Obj/Boot.o | Bin 0 -> 4618 bytes A58-AMTLDR/AMT630Hv100/Obj/Entry.o | Bin 0 -> 18417 bytes A58-AMTLDR/AMT630Hv100/Obj/Entry.pbi | Bin 0 -> 79237 bytes A58-AMTLDR/AMT630Hv100/Obj/Entry.pbi.xcl | 329 + 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zS{5+@4*`Bc!z26lNq!vnCW_BiUTIzjF3_f~F zvTB=A$$hhiCHG0o0bRvnO0o&qG}tSjh73i=FjJr8^eo1Pj{{CiO-b=#kW>3+d+AV= zFwHv%iVlCAY@c5;XSOgqMaW>&h3T_}E-whQ0|Oxj%Cju0#Z;Cdh%aDT)~1>MSIpRd E0hV^ghyVZp literal 0 HcmV?d00001 diff --git a/A58-AMTLDR/AMT630Hv100/List/AMTLDR.map b/A58-AMTLDR/AMT630Hv100/List/AMTLDR.map new file mode 100644 index 00000000..5ca4dace --- /dev/null +++ b/A58-AMTLDR/AMT630Hv100/List/AMTLDR.map @@ -0,0 +1,361 @@ +############################################################################### +# +# IAR ELF Linker V8.30.1.114/W32 for ARM 05/Mar/2025 14:11:33 +# Copyright 2007-2018 IAR Systems AB. +# +# Output file = G:\mengxun\A58-AMTLDR\AMT630Hv100\Exe\AMTLDR.out +# Map file = G:\mengxun\A58-AMTLDR\AMT630Hv100\List\AMTLDR.map +# Command line = +# -f C:\Users\13669\AppData\Local\Temp\EWA971.tmp +# (G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\Boot.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\clockcfg.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\cp15.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\cp15_asm_iar.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\crc32.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\diskio.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\Entry.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\exception.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\ff.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\gpio.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\mmu.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\sdmmc.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\SpiBooter.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\SpinandBooter.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\sysinfo.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\timer.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\UartPrint.o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj\wdt.o --no_out_extension -o +# G:\mengxun\A58-AMTLDR\AMT630Hv100\Exe\AMTLDR.out --map +# G:\mengxun\A58-AMTLDR\AMT630Hv100\List\AMTLDR.map --config +# G:\mengxun\A58-AMTLDR\AMTLDR.icf --semihosting --entry +# __iar_program_start --vfe --text_out locale) +# +############################################################################### + +******************************************************************************* +*** RUNTIME MODEL ATTRIBUTES +*** + +CppFlavor = * +__SystemLibrary = DLib +__dlib_version = 6 + + +******************************************************************************* +*** HEAP SELECTION +*** + +The basic heap was selected because no calls to memory allocation +functions were found in the application outside of system library +functions, and there are calls to deallocation functions in the +application. + + +******************************************************************************* +*** PLACEMENT SUMMARY +*** + +"A0": place at 0x30'0000 { ro section .intvec }; +"P1": place in [from 0x30'0080 to 0x30'6fff] { ro }; +define block CSTACK with size = 4K, alignment = 8 { }; +define block SVC_STACK with size = 64, alignment = 8 { }; +define block IRQ_STACK with size = 64, alignment = 8 { }; +define block FIQ_STACK with size = 64, alignment = 8 { }; +define block UND_STACK with size = 64, alignment = 8 { }; +define block ABT_STACK with size = 64, alignment = 8 { }; +define block HEAP with size = 1K, alignment = 8 { }; +"P2": place in [from 0x30'7000 to 0x30'bfff] { + rw, block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + + Section Kind Address Size Object + ------- ---- ------- ---- ------ +"A0": 0x40 + .intvec ro code 0x30'0000 0x40 Boot.o [1] + - 0x30'0040 0x40 + +"P1": 0x243c + .text ro code 0x30'0080 0xd18 SpiBooter.o [1] + .text ro code 0x30'0d98 0x118 gpio.o [1] + .text ro code 0x30'0eb0 0x8c timer.o [1] + .text ro code 0x30'0f3c 0x1e8 UartPrint.o [1] + .text ro code 0x30'1124 0x1a8 I32DivMod.o [3] + .text ro code 0x30'12cc 0x4 IntDivZer.o [3] + .text ro code 0x30'12d0 0x43c Entry.o [1] + .text ro code 0x30'170c 0x40 sysinfo.o [1] + .text ro code 0x30'174c 0x260 clockcfg.o [1] + .text ro code 0x30'19ac 0x40 crc32.o [1] + .rodata const 0x30'19ec 0x400 crc32.o [1] + .text ro code 0x30'1dec 0x170 Boot.o [1] + .rodata const 0x30'1f5c 0x138 SpiBooter.o [1] + .text ro code 0x30'2094 0x78 exception.o [1] + .text ro code 0x30'210c 0x3a zero_init3.o [3] + .text ro code 0x30'2148 0x30 cmain.o [3] + .text ro code 0x30'2178 0x4 low_level_init.o [2] + .text ro code 0x30'217c 0x30 data_init.o [3] + Veneer ro code 0x30'21ac 0x8 - Linker created - + .text ro code 0x30'21b4 0x4 exit.o [2] + .text ro code 0x30'21b8 0x14 exit.o [4] + .text ro code 0x30'21cc 0x10 cexit.o [3] + .rodata const 0x30'21dc 0x28 Entry.o [1] + .rodata const 0x30'2204 0x24 Entry.o [1] + .rodata const 0x30'2228 0x24 SpiBooter.o [1] + .iar.init_table const 0x30'224c 0x10 - Linker created - + .rodata const 0x30'225c 0x1c Entry.o [1] + .rodata const 0x30'2278 0x18 Entry.o [1] + .rodata const 0x30'2290 0x18 Entry.o [1] + .rodata const 0x30'22a8 0x18 Entry.o [1] + .rodata const 0x30'22c0 0x18 Entry.o [1] + .rodata const 0x30'22d8 0x14 Entry.o [1] + .rodata const 0x30'22ec 0x14 Entry.o [1] + .rodata const 0x30'2300 0x14 exception.o [1] + .rodata const 0x30'2314 0x10 exception.o [1] + .rodata const 0x30'2324 0x10 SpiBooter.o [1] + .rodata const 0x30'2334 0xc exception.o [1] + .rodata const 0x30'2340 0xc exception.o [1] + .rodata const 0x30'234c 0xc exception.o [1] + .rodata const 0x30'2358 0xc exception.o [1] + .rodata const 0x30'2364 0xc SpiBooter.o [1] + .rodata const 0x30'2370 0xc SpiBooter.o [1] + .rodata const 0x30'237c 0xc SpiBooter.o [1] + .rodata const 0x30'2388 0xc SpiBooter.o [1] + .rodata const 0x30'2394 0xc SpiBooter.o [1] + .rodata const 0x30'23a0 0xc SpiBooter.o [1] + .rodata const 0x30'23ac 0xc SpiBooter.o [1] + .rodata const 0x30'23b8 0xc SpiBooter.o [1] + .rodata const 0x30'23c4 0xc SpiBooter.o [1] + .rodata const 0x30'23d0 0xc SpiBooter.o [1] + .rodata const 0x30'23dc 0xc SpiBooter.o [1] + .rodata const 0x30'23e8 0xc SpiBooter.o [1] + .rodata const 0x30'23f4 0xc SpiBooter.o [1] + .rodata const 0x30'2400 0xc SpiBooter.o [1] + .rodata const 0x30'240c 0xc SpiBooter.o [1] + .rodata const 0x30'2418 0xc SpiBooter.o [1] + .rodata const 0x30'2424 0xc SpiBooter.o [1] + .rodata const 0x30'2430 0xc SpiBooter.o [1] + .rodata const 0x30'243c 0xc SpiBooter.o [1] + .rodata const 0x30'2448 0xc SpiBooter.o [1] + .rodata const 0x30'2454 0xc SpiBooter.o [1] + .rodata const 0x30'2460 0xc SpiBooter.o [1] + .rodata const 0x30'246c 0xc SpiBooter.o [1] + .rodata const 0x30'2478 0xc SpiBooter.o [1] + .rodata const 0x30'2484 0xc SpiBooter.o [1] + .rodata const 0x30'2490 0x8 SpiBooter.o [1] + .rodata const 0x30'2498 0x8 SpiBooter.o [1] + .rodata const 0x30'24a0 0x8 SpiBooter.o [1] + .rodata const 0x30'24a8 0x8 SpiBooter.o [1] + .rodata const 0x30'24b0 0x8 UartPrint.o [1] + .text ro code 0x30'24b8 0x4 xreturnswi.o [4] + .rodata const 0x30'24bc 0x0 zero_init3.o [3] + - 0x30'24bc 0x243c + +"P2", part 1 of 2: 0x15c + .bss zero 0x30'7000 0x100 SpiBooter.o [1] + .bss zero 0x30'7100 0x58 sysinfo.o [1] + .bss zero 0x30'7158 0x4 SpiBooter.o [1] + - 0x30'715c 0x15c + +"P2", part 2 of 2: 0x1140 + CSTACK 0x30'7160 0x1000 + CSTACK uninit 0x30'7160 0x1000 + SVC_STACK 0x30'8160 0x40 + SVC_STACK uninit 0x30'8160 0x40 + IRQ_STACK 0x30'81a0 0x40 + IRQ_STACK uninit 0x30'81a0 0x40 + FIQ_STACK 0x30'81e0 0x40 + FIQ_STACK uninit 0x30'81e0 0x40 + UND_STACK 0x30'8220 0x40 + UND_STACK uninit 0x30'8220 0x40 + ABT_STACK 0x30'8260 0x40 + ABT_STACK uninit 0x30'8260 0x40 + - 0x30'82a0 0x1140 + +Unused ranges: + + From To Size + ---- -- ---- + 0x30'24bc 0x30'6fff 0x4b44 + 0x30'715c 0x30'715f 0x4 + 0x30'82a0 0x30'bfff 0x3d60 + + +******************************************************************************* +*** INIT TABLE +*** + + Address Size + ------- ---- +Zero (__iar_zero_init3) + 1 destination range, total size 0x15c: + 0x30'7000 0x15c + + + +******************************************************************************* +*** MODULE SUMMARY +*** + + Module ro code ro data rw data + ------ ------- ------- ------- +command line/config: + ------------------------------------------- + Total: + +G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj: [1] + Boot.o 432 + Entry.o 1 084 240 + SpiBooter.o 3 352 696 260 + UartPrint.o 488 8 + clockcfg.o 608 + crc32.o 64 1 024 + exception.o 120 84 + gpio.o 280 + sysinfo.o 64 88 + timer.o 140 + ------------------------------------------- + Total: 6 632 2 052 348 + +dl7Sx_tln.a: [2] + exit.o 4 + low_level_init.o 4 + ------------------------------------------- + Total: 8 + +rt7Sx_tl.a: [3] + I32DivMod.o 424 + IntDivZer.o 4 + cexit.o 16 + cmain.o 48 + data_init.o 48 + zero_init3.o 58 + ------------------------------------------- + Total: 598 + +sh7Sxs_l.a: [4] + exit.o 20 + xreturnswi.o 4 + ------------------------------------------- + Total: 24 + + Gaps 2 + Linker created 8 16 4 416 +----------------------------------------------- + Grand Total: 7 272 2 068 4 764 + + +******************************************************************************* +*** ENTRY LIST +*** + +Entry Address Size Type Object +----- ------- ---- ---- ------ +.iar.init_table$$Base 0x30'224c -- Gb - Linker created - +.iar.init_table$$Limit 0x30'225c -- Gb - Linker created - +?main 0x30'2148 Code Gb cmain.o [3] +ABT_STACK$$Base 0x30'8260 -- Gb - Linker created - +ABT_STACK$$Limit 0x30'82a0 -- Gb - Linker created - +CSTACK$$Base 0x30'7160 -- Gb - Linker created - +CSTACK$$Limit 0x30'8160 -- Gb - Linker created - +FIQ_STACK$$Base 0x30'81e0 -- Gb - Linker created - +FIQ_STACK$$Limit 0x30'8220 -- Gb - Linker created - +FlashBurn 0x30'0d60 0xc Code Gb SpiBooter.o [1] +GPIO_MODREG 0x30'0df8 0x10 Code Lc gpio.o [1] +GPIO_OFFSET 0x30'0db0 0x48 Code Lc gpio.o [1] +GPIO_WDATAREG 0x30'0e08 0xc Code Lc gpio.o [1] +GetSysInfo 0x30'170c 0x8 Code Gb sysinfo.o [1] +HexToChar 0x30'0fb0 0x2c Code Lc UartPrint.o [1] +IRQ_STACK$$Base 0x30'81a0 -- Gb - Linker created - +IRQ_STACK$$Limit 0x30'81e0 -- Gb - Linker created - +InitUart 0x30'0f3c 0x74 Code Gb UartPrint.o [1] +IntToStr 0x30'1040 0x38 Code Gb UartPrint.o [1] +PrintVariableValueHex 0x30'10d0 0x34 Code Gb UartPrint.o [1] +Region$$Table$$Base 0x30'224c -- Gb - Linker created - +Region$$Table$$Limit 0x30'225c -- Gb - Linker created - +SVC_STACK$$Base 0x30'8160 -- Gb - Linker created - +SVC_STACK$$Limit 0x30'81a0 -- Gb - Linker created - +SaveSysInfo 0x30'1714 0x34 Code Gb sysinfo.o [1] +SendUartString 0x30'1078 0x58 Code Gb UartPrint.o [1] +SetCSGpioEnable 0x30'0080 0x28 Code Lc SpiBooter.o [1] +SetCpuPLL 0x30'176c 0x50 Code Gb clockcfg.o [1] +SetDDRPLL 0x30'180c 0x64 Code Gb clockcfg.o [1] +SetGpuclk 0x30'1954 0x1c Code Gb clockcfg.o [1] +SetMfcclk 0x30'1970 0x1c Code Gb clockcfg.o [1] +SetSpiDataMode 0x30'00a8 0x4c Code Lc SpiBooter.o [1] +SetSpiclk 0x30'1938 0x1c Code Gb clockcfg.o [1] +SetSysPLL 0x30'17bc 0x50 Code Gb clockcfg.o [1] +SetVPUPLL 0x30'1870 0x50 Code Gb clockcfg.o [1] +SetXclkAHBclkAPBclk 0x30'18c0 0x78 Code Gb clockcfg.o [1] +ShortToStr 0x30'0fdc 0x64 Code Lc UartPrint.o [1] +SpiDisable4ByteMode 0x30'0220 0x48 Code Lc SpiBooter.o [1] +SpiEmptyRxFIFO 0x30'0114 0x24 Code Lc SpiBooter.o [1] +SpiEnable4ByteMode 0x30'0268 0x48 Code Lc SpiBooter.o [1] +SpiEraseBlock 0x30'086c 0xbc Code Lc SpiBooter.o [1] +SpiEraseSector 0x30'07b0 0xbc Code Lc SpiBooter.o [1] +SpiInit 0x30'061c 0x144 Code Gb SpiBooter.o [1] +SpiNorBurn 0x30'0b4c 0x214 Code Lc SpiBooter.o [1] +SpiNorBurnPage 0x30'0a64 0xb0 Code Lc SpiBooter.o [1] +SpiReadJedecId 0x30'0580 0x9c Code Lc SpiBooter.o [1] +SpiReadPage 0x30'02b0 0x1ec Code Lc SpiBooter.o [1] +SpiReadSta 0x30'01b4 0x6c Code Lc SpiBooter.o [1] +SpiReadSta3 0x30'0138 0x7c Code Lc SpiBooter.o [1] +SpiSelectPad 0x30'049c 0x48 Code Gb SpiBooter.o [1] +SpiWaitIdle 0x30'00f4 0x20 Code Lc SpiBooter.o [1] +SpiWriteEnable 0x30'0760 0x50 Code Lc SpiBooter.o [1] +SpiWritePage 0x30'0928 0x13c Code Lc SpiBooter.o [1] +SpiWriteSysInfo 0x30'0d6c 0x2c Code Gb SpiBooter.o [1] +SwitchTo24MHz 0x30'198c 0x20 Code Gb clockcfg.o [1] +UND_STACK$$Base 0x30'8220 -- Gb - Linker created - +UND_STACK$$Limit 0x30'8260 -- Gb - Linker created - +__aeabi_idiv 0x30'1124 Code Gb I32DivMod.o [3] +__aeabi_idiv0 0x30'12cc Code Gb IntDivZer.o [3] +__aeabi_idivmod 0x30'1124 Code Gb I32DivMod.o [3] +__aeabi_uidiv 0x30'1150 Code Gb I32DivMod.o [3] +__aeabi_uidivmod 0x30'1150 Code Gb I32DivMod.o [3] +__cmain 0x30'2148 Code Gb cmain.o [3] +__exit 0x30'21b9 0x14 Code Gb exit.o [4] +__iar_data_init3 0x30'217d 0x30 Code Gb data_init.o [3] +__iar_program_start 0x30'1dec Code Gb Boot.o [1] +__iar_return_from_swi 0x30'24b8 0x4 Code Gb xreturnswi.o [4] +__iar_zero_init3 0x30'210d 0x3a Code Gb zero_init3.o [3] +__low_level_init 0x30'2179 0x4 Code Gb low_level_init.o [2] +__vector 0x30'0000 Code Gb Boot.o [1] +_call_main 0x30'2160 Code Gb cmain.o [3] +_exit 0x30'21cc Code Gb cexit.o [3] +_main 0x30'2168 Code Gb cmain.o [3] +addr_in_4_byte 0x30'7158 0x4 Data Lc SpiBooter.o [1] +crc32_table 0x30'19ec 0x400 Data Lc crc32.o [1] +data_abort_handler 0x30'20b4 0x10 Code Gb exception.o [1] +ddr3_sdramc_init 0x30'1304 0x19c Code Gb Entry.o [1] +ddr_training_one 0x30'12d0 0x34 Code Gb Entry.o [1] +delay 0x30'174c 0x20 Code Lc clockcfg.o [1] +dwspi_jedec252_reset 0x30'04e4 0x9c Code Lc SpiBooter.o [1] +exit 0x30'21b5 0x4 Code Gb exit.o [2] +fiq_handler 0x30'20d4 0x10 Code Gb exception.o [1] +flash_chip_table 0x30'1f5c 0x138 Data Lc SpiBooter.o [1] +gpio_direction_output 0x30'0e14 0x9c Code Gb gpio.o [1] +gpio_get_regbase 0x30'0d98 0x18 Code Lc gpio.o [1] +irq_handler 0x30'20c4 0x10 Code Gb exception.o [1] +main 0x30'156c 0x11c Code Gb Entry.o [1] +mdelay 0x30'0f28 0x14 Code Gb timer.o [1] +pagecheck 0x30'7000 0x100 Data Lc SpiBooter.o [1] +prefetch_handler 0x30'20a4 0x10 Code Gb exception.o [1] +swi_handler 0x30'20e4 0x10 Code Gb exception.o [1] +sysinfo 0x30'7100 0x58 Data Lc sysinfo.o [1] +timer_init 0x30'0eb0 0x2c Code Gb timer.o [1] +udelay 0x30'0edc 0x4c Code Gb timer.o [1] +undef_handler 0x30'2094 0x10 Code Gb exception.o [1] +updateFromJtag 0x30'14a0 0xcc Code Gb Entry.o [1] +xcrc32 0x30'19ac 0x40 Code Gb crc32.o [1] + + +[1] = G:\mengxun\A58-AMTLDR\AMT630Hv100\Obj +[2] = dl7Sx_tln.a +[3] = rt7Sx_tl.a +[4] = sh7Sxs_l.a + + 7 272 bytes of readonly code memory + 2 068 bytes of readonly data memory + 4 764 bytes of readwrite data memory + +Errors: none +Warnings: none diff --git a/A58-AMTLDR/AMT630Hv100/Obj/AMTLDR.pbd b/A58-AMTLDR/AMT630Hv100/Obj/AMTLDR.pbd new file mode 100644 index 0000000000000000000000000000000000000000..e3d7ba43e8f6b344a8627aebc9d15970bf9029cd GIT binary patch literal 391984 zcmZU+2b@*K`98ky%$YN%-+OoOcD9_|!?J~?2`EJYB?gcf#gfG2YfSuINMelXmY7ed z0@6ef5D-D6gET2pL^{$11f(|sK{_l|{XcWi<*t9dpLx&oGI#DNbEdrS^S+zHQt)4J zDcjPG_bilbm^t1e{GTuP>v|RcyI#xWUH(o0`}I`6r;}C1H@Za`CZFSMbP2ep(^!9A z>X!&5ZKF%Xo@dW{vENe_f1k8xZ9a(JC;C18-t)iFSQYQ*`gKiy-0tTR@Hbk$U>t9g z=*NTCxz4Xd`*8vu$M4rRlY52tB1%c2fAt~*a5ELlP25V{V)A1i1keU&${G0-nXP{0pQfzIFVaFT>}1& z75htdJ2B77wLCuFoNp1}Qa$dkvh>6{&;OM2`D%BaN5HEr&!6M+E+d>;wRB!(z3mX- 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+-D__CODE_PTR_MEMORY_LIST1__()=__CODE_PTR_MEM_HELPER1__(__code, 0 ) +-D__CODE_PTR_MEMORY_LIST2__(_P1)=__CODE_PTR_MEM_HELPER2__(__code, 0 , _P1 ) +-D__CODE_PTR_MEMORY_LIST3__(_P1,_P2)=__CODE_PTR_MEM_HELPER3__(__code, 0 , _P1 , _P2 ) +-D__DATA_PTR_MEMORY_LIST1__()=__DATA_PTR_MEM_HELPER1__(__data, 0 ) +-D__DATA_PTR_MEMORY_LIST2__(_P1)=__DATA_PTR_MEM_HELPER2__(__data, 0 , _P1 ) +-D__DATA_PTR_MEMORY_LIST3__(_P1,_P2)=__DATA_PTR_MEM_HELPER3__(__data, 0 , _P1 , _P2 ) +-D__VAR_MEMORY_LIST1__()=__VAR_MEM_HELPER1__(__data, 0 ) +-D__VAR_MEMORY_LIST2__(_P1)=__VAR_MEM_HELPER2__(__data, 0 , _P1 ) +-D__VAR_MEMORY_LIST3__(_P1,_P2)=__VAR_MEM_HELPER3__(__data, 0 , _P1 , _P2 ) +-D__VARD_MEMORY_LIST1__()=__VARD_MEM_HELPER1__(__data, 0, _ ) +-D__HEAP_MEMORY_LIST1__()=__HEAP_MEM_HELPER1__(__data, 0 ) +-D__HEAP_MEMORY_LIST2__(_P1)=__HEAP_MEM_HELPER2__(__data, 0 , _P1 ) +-D__HEAP_MEMORY_LIST3__(_P1,_P2)=__HEAP_MEM_HELPER3__(__data, 0 , _P1 , _P2 ) +-D__HVAR_MEMORY_LIST1__()=__HVAR_MEM_HELPER1__(__data, 0 ) +-D__HEAPD_MEMORY_LIST1__()=__HEAPD_MEM_HELPER1__(__data, 0, _ ) +-D__HEAPU_MEMORY_LIST1__()=__HEAPU_MEM_HELPER1__(__data, 0 ) +-D__TOPM_DATA_MEMORY_LIST1__()= +-D__TOPM_DATA_MEMORY_LIST2__(_P1)= +-D__TOPM_DATA_MEMORY_LIST3__(_P1,_P2)= +-D__TOPP_DATA_MEMORY_LIST1__()=__TOPP_DATA_MEM_HELPER1__(__data, 0 ) +-D__TOPP_DATA_MEMORY_LIST2__(_P1)=__TOPP_DATA_MEM_HELPER2__(__data, 0 , _P1 ) +-D__TOPP_DATA_MEMORY_LIST3__(_P1,_P2)=__TOPP_DATA_MEM_HELPER3__(__data, 0 , _P1 , _P2 ) +-D__DATA_MEM0_SIZE_TYPE__=unsigned int +-D__DATA_MEM0_INDEX_TYPE__=signed int +-D__iar_fp2bits32(x)=0 +-D__iar_fp2bits64(x)=0 +-D__iar_fpgethi64(x)=0 +-D__iar_atomic_add_fetch(x,y,z)=0 +-D__iar_atomic_sub_fetch(x,y,z)=0 +-D__iar_atomic_load(x,y)=0ULL +-D__iar_atomic_compare_exchange_weak(a,b,c,d,e)=0 diff --git a/A58-AMTLDR/AMTLDR.dep b/A58-AMTLDR/AMTLDR.dep new file mode 100644 index 00000000..a9ca0ddd --- /dev/null +++ b/A58-AMTLDR/AMTLDR.dep @@ -0,0 +1,517 @@ + + + 4 + 3771691642 + + AMT630Hv100 + + $PROJ_DIR$\Src\fs\ff.h + $PROJ_DIR$\Src\fs\ff.c + $PROJ_DIR$\Src\amt630h.h + $PROJ_DIR$\Src\Boot.s + $PROJ_DIR$\Src\fs\diskio.h + $PROJ_DIR$\Src\fs\integer.h + $PROJ_DIR$\Src\fs\diskio.c + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + $PROJ_DIR$\AMT630Hv100\Obj\sysinfo.pbi + $PROJ_DIR$\Src\spi.h + $PROJ_DIR$\AMT630Hv100\Obj\crc32.pbi + $PROJ_DIR$\AMT630Hv100\Obj\cp15.o + $PROJ_DIR$\Src\scsi.h + $PROJ_DIR$\Src\timer.h + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $PROJ_DIR$\Src\crc32.c + $PROJ_DIR$\Src\Entry.c + $PROJ_DIR$\Src\SpiBooter.c + $PROJ_DIR$\Src\sysinfo.c + $PROJ_DIR$\Src\SpinandBooter.c + $PROJ_DIR$\Src\timer.c + $PROJ_DIR$\Src\typedef.h + $PROJ_DIR$\Src\wdt.c + $PROJ_DIR$\AMT630Hv100\Obj\AMTLDR.pbd + $PROJ_DIR$\Src\exception.c + $PROJ_DIR$\Src\BootModeSel.h + $PROJ_DIR$\Src\mmu.c + $PROJ_DIR$\Src\sysinfo.h + $PROJ_DIR$\Src\UartPrint.c + $PROJ_DIR$\Src\cp15_asm_iar.s + $PROJ_DIR$\Src\clockcfg.c + $PROJ_DIR$\Src\list.h + $PROJ_DIR$\Src\sdmmc.c + $PROJ_DIR$\Src\sdmmc.h + $PROJ_DIR$\Src\cp15.c + $PROJ_DIR$\Src\gpio.c + $PROJ_DIR$\Src\crc32.h + $PROJ_DIR$\Src\UartPrint.h + $PROJ_DIR$\AMT630Hv100\Obj\cp15.pbi + $PROJ_DIR$\AMT630Hv100\Obj\timer.pbi + $TOOLKIT_DIR$\lib\dl7Sx_tln.a + $PROJ_DIR$\AMT630Hv100\Obj\ff.o + $PROJ_DIR$\AMT630Hv100\Obj\wdt.pbi + $PROJ_DIR$\AMTLDR.icf + $PROJ_DIR$\AMT630Hv100\Obj\gpio.o + $PROJ_DIR$\Src\cp15.h + $TOOLKIT_DIR$\inc\c\stdint.h + $PROJ_DIR$\AMT630Hv100\Obj\sdmmc.o + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $PROJ_DIR$\AMT630Hv100\Obj\SpinandBooter.pbi + $PROJ_DIR$\AMT630Hv100\Obj\Boot.o + $PROJ_DIR$\AMT630Hv100\Obj\diskio.pbi + $PROJ_DIR$\AMT630Hv100\Obj\clockcfg.pbi + $PROJ_DIR$\AMT630Hv100\Obj\clockcfg.o + $TOOLKIT_DIR$\inc\c\yvals.h + $TOOLKIT_DIR$\inc\c\stdlib.h + $TOOLKIT_DIR$\lib\rt7Sx_tl.a + $PROJ_DIR$\AMT630Hv100\Obj\exception.o + $PROJ_DIR$\AMT630Hv100\Obj\timer.o + $PROJ_DIR$\AMT630Hv100\Obj\ff.pbi + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\AMT630Hv100\Obj\cp15_asm_iar.o + $TOOLKIT_DIR$\inc\c\ysizet.h + $PROJ_DIR$\AMT630Hv100\Exe\AMTLDR.bin + $PROJ_DIR$\AMT630Hv100\Obj\mmu.pbi + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\AMT630Hv100\List\AMTLDR.map + $PROJ_DIR$\AMT630Hv100\Obj\diskio.o + $PROJ_DIR$\AMT630Hv100\Obj\SpiBooter.o + $TOOLKIT_DIR$\inc\c\intrinsics.h + $PROJ_DIR$\AMT630Hv100\Obj\UartPrint.pbi + $TOOLKIT_DIR$\lib\m7Sx_tl.a + $PROJ_DIR$\AMT630Hv100\Obj\crc32.o + $PROJ_DIR$\AMT630Hv100\Obj\Entry.pbi + $PROJ_DIR$\AMT630Hv100\Exe\AMTLDR.out + $PROJ_DIR$\AMT630Hv100\Obj\sdmmc.pbi + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\AMT630Hv100\Obj\Entry.o + $PROJ_DIR$\Src\gpio.h + $PROJ_DIR$\AMT630Hv100\Obj\SpiBooter.pbi + $PROJ_DIR$\AMT630Hv100\Obj\UartPrint.o + $PROJ_DIR$\AMT630Hv100\Obj\mmu.o + $PROJ_DIR$\AMT630Hv100\Obj\exception.pbi + $TOOLKIT_DIR$\lib\sh7Sxs_l.a + $PROJ_DIR$\AMT630Hv100\Obj\wdt.o + $TOOLKIT_DIR$\inc\c\string.h + $PROJ_DIR$\AMT630Hv100\Obj\SpinandBooter.o + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $PROJ_DIR$\AMT630Hv100\Obj\gpio.pbi + $PROJ_DIR$\AMT630Hv100\Obj\sysinfo.o + $TOOLKIT_DIR$\inc\c\stdio.h + $PROJ_DIR$\Src\mmu.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + + + [ROOT_NODE] + + + ILINK + 74 66 + + + + + $PROJ_DIR$\Src\fs\ff.c + + + ICCARM + 41 + + + BICOMP + 59 + + + + + ICCARM + 85 65 54 92 14 60 62 76 0 5 4 + + + BICOMP + 65 76 14 4 62 0 54 60 85 92 5 + + + + + $PROJ_DIR$\Src\Boot.s + + + AARM + 50 + + + + + $PROJ_DIR$\Src\fs\diskio.c + + + ICCARM + 67 + + + BICOMP + 51 + + + + + ICCARM + 4 5 + + + BICOMP + 4 5 + + + + + $PROJ_DIR$\Src\crc32.c + + + ICCARM + 72 + + + BICOMP + 10 + + + + + ICCARM + 90 65 54 92 14 60 62 55 48 + + + BICOMP + 92 54 65 60 62 55 14 90 48 + + + + + $PROJ_DIR$\Src\Entry.c + + + ICCARM + 77 + + + BICOMP + 73 + + + + + ICCARM + 21 2 25 37 13 91 45 46 65 54 92 14 60 27 9 + + + BICOMP + 13 21 92 25 27 54 2 37 91 9 45 46 65 14 60 + + + + + $PROJ_DIR$\Src\SpiBooter.c + + + ICCARM + 68 + + + BICOMP + 79 + + + + + ICCARM + 85 65 54 92 14 60 62 76 21 2 37 13 9 45 46 27 36 78 + + + BICOMP + 36 13 62 60 21 2 45 65 76 14 37 9 27 78 54 92 46 85 + + + + + $PROJ_DIR$\Src\sysinfo.c + + + ICCARM + 89 + + + BICOMP + 8 + + + + + ICCARM + 2 27 36 + + + BICOMP + 36 27 2 + + + + + $PROJ_DIR$\Src\SpinandBooter.c + + + ICCARM + 86 + + + BICOMP + 49 + + + + + ICCARM + 90 65 54 92 14 60 62 85 76 21 2 37 13 9 45 46 27 36 78 + + + BICOMP + 62 27 60 37 65 21 9 78 14 76 85 2 13 45 36 54 92 46 90 + + + + + $PROJ_DIR$\Src\timer.c + + + ICCARM + 58 + + + BICOMP + 39 + + + + + ICCARM + 2 13 21 + + + BICOMP + 21 13 2 + + + + + $PROJ_DIR$\Src\wdt.c + + + ICCARM + 84 + + + BICOMP + 42 + + + + + ICCARM + 2 37 + + + BICOMP + 37 2 + + + + + $PROJ_DIR$\Src\exception.c + + + ICCARM + 57 + + + BICOMP + 82 + + + + + ICCARM + 37 + + + BICOMP + 37 + + + + + $PROJ_DIR$\Src\mmu.c + + + ICCARM + 81 + + + BICOMP + 64 + + + + + ICCARM + 91 45 46 65 54 92 14 60 + + + BICOMP + 45 14 46 65 60 54 92 91 + + + + + $PROJ_DIR$\Src\UartPrint.c + + + ICCARM + 80 + + + BICOMP + 70 + + + + + ICCARM + 2 21 37 + + + BICOMP + 37 21 2 + + + + + $PROJ_DIR$\Src\cp15_asm_iar.s + + + AARM + 61 + + + + + $PROJ_DIR$\Src\clockcfg.c + + + ICCARM + 53 + + + BICOMP + 52 + + + + + ICCARM + 2 + + + BICOMP + 2 + + + + + $PROJ_DIR$\Src\sdmmc.c + + + ICCARM + 47 + + + BICOMP + 75 + + + + + ICCARM + 85 65 54 92 14 60 62 76 21 2 33 37 13 0 5 4 36 27 + + + BICOMP + 36 37 62 60 2 0 65 21 33 13 4 27 76 14 5 85 54 92 + + + + + $PROJ_DIR$\Src\cp15.c + + + ICCARM + 11 + + + BICOMP + 38 + + + + + ICCARM + 45 46 65 54 92 14 60 37 69 7 87 + + + BICOMP + 14 7 65 60 37 69 46 54 92 87 45 + + + + + $PROJ_DIR$\Src\gpio.c + + + ICCARM + 44 + + + BICOMP + 88 + + + + + ICCARM + 2 + + + BICOMP + 2 + + + + + $PROJ_DIR$\AMT630Hv100\Exe\AMTLDR.out + + + ILINK + 66 + + + OBJCOPY + 63 + + + + + ILINK + 43 50 53 11 61 72 67 77 57 41 44 81 47 68 86 89 58 80 84 83 56 71 40 + + + + + diff --git a/A58-AMTLDR/AMTLDR.ewd b/A58-AMTLDR/AMTLDR.ewd new file mode 100644 index 00000000..b7d8d8f7 --- /dev/null +++ b/A58-AMTLDR/AMTLDR.ewd @@ -0,0 +1,1476 @@ + + + 3 + + AMT630Hv100 + + ARM + + 1 + + C-SPY + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/A58-AMTLDR/AMTLDR.ewp b/A58-AMTLDR/AMTLDR.ewp new file mode 100644 index 00000000..93aafc65 --- /dev/null +++ b/A58-AMTLDR/AMTLDR.ewp @@ -0,0 +1,1136 @@ + + + 3 + + AMT630Hv100 + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + $PROJ_DIR$\gen_checksum.exe $PROJ_DIR$\AMT630Hv100\Exe\AMTLDR.bin + + + + ILINK + 0 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Src + + fs + + $PROJ_DIR$\Src\fs\diskio.c + + + $PROJ_DIR$\Src\fs\diskio.h + + + $PROJ_DIR$\Src\fs\ff.c + + + $PROJ_DIR$\Src\fs\ff.h + + + $PROJ_DIR$\Src\fs\integer.h + + + $PROJ_DIR$\Src\fs\sd_if.h + + + + $PROJ_DIR$\Src\amt630h.h + + + $PROJ_DIR$\Src\Boot.s + + + $PROJ_DIR$\Src\BootModeSel.h + + + $PROJ_DIR$\Src\clockcfg.c + + + $PROJ_DIR$\Src\crc32.c + + + $PROJ_DIR$\Src\crc32.h + + + $PROJ_DIR$\Src\Entry.c + + + $PROJ_DIR$\Src\exception.c + + + $PROJ_DIR$\Src\gpio.c + + + $PROJ_DIR$\Src\list.h + + + $PROJ_DIR$\Src\mmu.c + + + $PROJ_DIR$\Src\scsi.h + + + $PROJ_DIR$\Src\sdmmc.c + + + $PROJ_DIR$\Src\sdmmc.h + + + $PROJ_DIR$\Src\spi.h + + + $PROJ_DIR$\Src\SpiBooter.c + + + $PROJ_DIR$\Src\SpinandBooter.c + + + $PROJ_DIR$\Src\sysinfo.c + + + $PROJ_DIR$\Src\sysinfo.h + + + $PROJ_DIR$\Src\timer.c + + + $PROJ_DIR$\Src\timer.h + + + $PROJ_DIR$\Src\typedef.h + + + $PROJ_DIR$\Src\UartPrint.c + + + $PROJ_DIR$\Src\UartPrint.h + + + $PROJ_DIR$\Src\wdt.c + + + + $PROJ_DIR$\Src\cp15.c + + + $PROJ_DIR$\Src\cp15_asm_iar.s + + diff --git a/A58-AMTLDR/AMTLDR.eww b/A58-AMTLDR/AMTLDR.eww new file mode 100644 index 00000000..d8d7443f --- /dev/null +++ b/A58-AMTLDR/AMTLDR.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\AMTLDR.ewp + + + + + diff --git a/A58-AMTLDR/AMTLDR.icf b/A58-AMTLDR/AMTLDR.icf new file mode 100644 index 00000000..0f2506b1 --- /dev/null +++ b/A58-AMTLDR/AMTLDR.icf @@ -0,0 +1,43 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x300000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x300080; +define symbol __ICFEDIT_region_ROM_end__ = 0x306fff; +define symbol __ICFEDIT_region_RAM_start__ = 0x307000; +define symbol __ICFEDIT_region_RAM_end__ = 0x30bfff; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x40; +define symbol __ICFEDIT_size_irqstack__ = 0x40; +define symbol __ICFEDIT_size_fiqstack__ = 0x40; +define symbol __ICFEDIT_size_undstack__ = 0x40; +define symbol __ICFEDIT_size_abtstack__ = 0x40; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; \ No newline at end of file diff --git a/A58-AMTLDR/EMMCLDR.icf b/A58-AMTLDR/EMMCLDR.icf new file mode 100644 index 00000000..79bae08c --- /dev/null +++ b/A58-AMTLDR/EMMCLDR.icf @@ -0,0 +1,43 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x30c000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x30c080; +define symbol __ICFEDIT_region_ROM_end__ = 0x30ffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x310000; +define symbol __ICFEDIT_region_RAM_end__ = 0x313fff; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x40; +define symbol __ICFEDIT_size_irqstack__ = 0x40; +define symbol __ICFEDIT_size_fiqstack__ = 0x40; +define symbol __ICFEDIT_size_undstack__ = 0x40; +define symbol __ICFEDIT_size_abtstack__ = 0x40; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; \ No newline at end of file diff --git a/A58-AMTLDR/Src/Boot.s b/A58-AMTLDR/Src/Boot.s new file mode 100644 index 00000000..97c39796 --- /dev/null +++ b/A58-AMTLDR/Src/Boot.s @@ -0,0 +1,239 @@ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#define __ASSEMBLY__ + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +#define IRAM_BASE 0x300000 +#define SYS_CPU_CTL 0xe4900208 +#define AIC 0xFFFFF000 +#define AIC_IVR 0x10 +#define AIC_EOICR 0x38 + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + +/* + Exception vectors + */ +// SECTION .vectors:CODE:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + PUBLIC __vector + PUBLIC __iar_program_start + + ARM ; Always ARM mode after reset + +__vector: + ldr pc, Reset + DCD 0x424b5244 + //LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + IMPORT undef_handler + IMPORT swi_handler + IMPORT prefetch_handler + IMPORT data_abort_handler + IMPORT irq_handler + IMPORT fiq_handler + +Reset: dc32 __iar_program_start +Undefined_Addr: dc32 undef_handler ;Undefined_Handler +SWI_Addr: dc32 swi_handler ;SWI_Handler +Prefetch_Addr: dc32 prefetch_handler ;ExceptionPAB +Abort_Addr: dc32 data_abort_handler ;ExceptionDAB +Reserved_Addr: dc32 0 ;ExceptionREV +IRQ_Addr: dc32 irq_handler +FIQ_Addr: dc32 fiq_handler + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + +CP_DIS_MASK DEFINE 0xFFFFEFFA + + SECTION .text:CODE:NOROOT(2) + EXTERN ?main + REQUIRE __vector + +__iar_program_start: + b reset_handler +// DCD 0x424b5241 +// DCD 0 +// DCD 0 + +reset_handler: +;================================================================== +; Reset registers +;================================================================== + MOV r2, #0 + MOV r3, #0 + MOV r4, #0 + MOV r5, #0 + MOV r6, #0 + MOV r7, #0 + MOV r8, #0 + MOV r9, #0 + MOV r10, #0 + MOV r11, #0 + MOV r12, #0 + +;================================================================== +; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +; This does not need to be done from a cold reset +;================================================================== + MRC p15, 0, r0, c1, c0, 0 ; Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + ;ORR r0, r0, #(0x1 << 12) ; Set I bit 12 to enable I Cache + BIC r0, r0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 ; Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 ; Write value back to CP15 System Control register + +;================================================================== +; Cache Invalidation code for Cortex-A7 +; NOTE: Neither Caches, nor MMU, nor BTB need post-reset invalidation on Cortex-A7, +; but forcing a cache invalidation, makes the code more portable to other CPUs (e.g. Cortex-A9) +;================================================================== + ; Invalidate L1 Instruction Cache + MRC p15, 1, r0, c0, c0, 1 ; Read Cache Level ID Register (CLIDR) + TST r0, #0x3 ; Harvard Cache? + MOV r0, #0 ; SBZ + MCRNE p15, 0, r0, c7, c5, 0 ; ICIALLU - Invalidate instruction cache and flush branch target cache + + ; Invalidate Data/Unified Caches + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ Finished ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +Loop1 ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT Skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +Loop2 MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +Loop3 ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 ; Invalidate by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE Loop3 + SUBS r7, r7, #1 ; Decrement the Set number + BGE Loop2 +Skip ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT Loop1 + +Finished + +;================================================================== +; Invalidate TLB +;================================================================== + MOV r0, #0 + MCR p15, 0, r0, c8, c7, 0 + +;================================================================== +; Branch Prediction Enable +;================================================================== + ;MOV r1, #0 + ;MRC p15, 0, r1, c1, c0, 0 /* Read Control Register configuration data */ + ;ORR r1, r1, #(0x1 << 11) /* Global BP Enable bit */ + ;MCR p15, 0, r1, c1, c0, 0 /* Write Control Register configuration data */ + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. + mrs r0,cpsr ; Original PSR value + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#SVC_MODE ; Set Supervisor mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#ABT_MODE ; Set Abort mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#UND_MODE ; Set Undefined mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(UND_STACK) ; End of UND_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#FIQ_MODE ; Set FIR mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#IRQ_MODE ; Set IRQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#SYS_MODE ; Set System mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(CSTACK) ; End of CSTACK + + /* Branch to main() */ + LDR r0, =?main + BLX r0 + + /* Loop indefinitely when program is finished */ +loop4: + B loop4 + + + END + \ No newline at end of file diff --git a/A58-AMTLDR/Src/BootModeSel.h b/A58-AMTLDR/Src/BootModeSel.h new file mode 100644 index 00000000..4791a590 --- /dev/null +++ b/A58-AMTLDR/Src/BootModeSel.h @@ -0,0 +1,14 @@ +#ifndef BOOT_MODE_SEL_H__ +#define BOOT_MODE_SEL_H__ + +void bootFromSPI(void); +void bootFromNand(void); +void bootFromUsbHost(); +void bootFromUsbDevice(int highspeed); +void bootFromUart(void); +void bootFromSD(int chipid, int bcheckfile); +void bootFromEMMC(int chipid); +void bootFromSpinand(void); + +#endif + diff --git a/A58-AMTLDR/Src/CommonDef.inc b/A58-AMTLDR/Src/CommonDef.inc new file mode 100644 index 00000000..f4989683 --- /dev/null +++ b/A58-AMTLDR/Src/CommonDef.inc @@ -0,0 +1,61 @@ + //#define VECTOR_ENABLE TRUE + #define VECTOR_ENABLE FALSE + +;Pre-defined run mode constants +USERMODE EQU 0x10 +FIQMODE EQU 0x11 +IRQMODE EQU 0x12 +SVCMODE EQU 0x13 +ABORTMODE EQU 0x17 +UNDEFMODE EQU 0x1b +MODEMASK EQU 0x1f +NOINT EQU 0xc0 + + +;Stacks defination for each run mode +_STACK_BASEADDRESS EQU 0xC0008000 + +UserStackLen EQU 0x10 +SVCStackLen EQU 0x2000 +UndefStackLen EQU 0x10 +AbortStackLen EQU 0x10 +IRQStackLen EQU 0x400 +FIQStackLen EQU 0x10 + +UserStackStart EQU (_STACK_BASEADDRESS) +UndefStackStart EQU (UserStackStart - UserStackLen) +AbortStackStart EQU (UndefStackStart - UndefStackLen) +IRQStackStart EQU (AbortStackStart - AbortStackLen) +FIQStackStart EQU (IRQStackStart - IRQStackLen) +SVCStackStart EQU (FIQStackStart - FIQStackLen) + + +VICL_BASE EQU 0xE0C00000 +VICH_BASE EQU 0xE0B00000 +ENABLE_REG_OFFSET EQU 0x10 +CLR_REG_OFFSET EQU 0x14 +ADDRESS_REG_OFFSET EQU 0xF00 +VICL_RAW_STATUS EQU 0xE0C00008 ;Interrupt raw status low 32 vector +VICH_RAW_STATUS EQU 0xE0B00008 ;Interrupt raw status high 32 vector +VICL_SEL_REG EQU 0xE0C0000C ;Interrupt select reg for low 32 vector +VICH_SEL_REG EQU 0xE0B0000C ;Interrupt select reg for high 32 vector +VICL_ENABLE EQU 0xE0C00010 ;Interrupt Enable control low 32 vector +VICH_ENABLE EQU 0xE0B00010 ;Interrupt Enable control high 32 vector +VICL_CLR EQU 0xE0C00014 ;Interrupt clear control low 32 vector +VICH_CLR EQU 0xE0B00014 ;Interrupt clear control high 32 vector +VICL_ADDR_BASE EQU 0xE0C00100 +VICH_ADDR_BASE EQU 0xE0B00100 +VICL_PROORITY_BASE EQU 0xE0C00200 +VICH_PROORITY_BASE EQU 0xE0B00200 + +;ENABLE_VE EQU 0x01000000 +VICL_ADDRESS EQU 0xE0C00F00 +VICH_ADDRESS EQU 0xE0B00F00 + + +WDT_CTL EQU 0xE4B00000 + +ITCM0_BaseAddress EQU 0xA0000000 ;ITCM0 base : 0xA0000000, Size : 8KB, +ITCM1_BaseAddress EQU 0xA0002000 ;ITCM1 base : 0xA0002000, Size : 8KB, +DTCM0_BaseAddress EQU 0xA0004000 ;DTCM0 base : 0xA0004000, Size : 8KB, +DTCM1_BaseAddress EQU 0xA0006000 ;DTCM1 base : 0xA0006000, Size : 8KB, diff --git a/A58-AMTLDR/Src/Entry.c b/A58-AMTLDR/Src/Entry.c new file mode 100644 index 00000000..a3e016c2 --- /dev/null +++ b/A58-AMTLDR/Src/Entry.c @@ -0,0 +1,477 @@ +/* +********************************************************************** +Copyright (c)2009 Arkmicro Technologies Inc. All Rights Reserved +Filename: boot.c +Version : 1.00 +Date : 2010.06.29 +Author : Donier +Abstract: Ark2116 SoC boot rom code file. +Note : The size the code(*.bin) loaded should never exceed 10K Bytes. +History : From the ark2116 SoC boot rom code file. +*********************************************************************** +*/ +#include "typedef.h" +#include "amt630h.h" +#include "BootModeSel.h" +#include "UartPrint.h" +#include "timer.h" +#include "mmu.h" +#include "sysinfo.h" +#include "spi.h" + +#define PROJECT_FOR_DDR_INIT 0 +#define PROJECT_FOR_SPIFLASH_LOADER 1 +#define PROJECT_FOR_SD_UPDATE 2 +#define PROJECT_FOR_JTAG_UPDATE 3 +#define PROJECT_FOR_EMMC_LOADER 4 +#define PROJECT_FOR_LAUNCH_EMMC 5 + +#define PROJECT_PURPOSE PROJECT_FOR_JTAG_UPDATE + +#if PROJECT_PURPOSE == PROJECT_FOR_EMMC_LOADER || PROJECT_PURPOSE == PROJECT_FOR_LAUNCH_EMMC +#if DEVICE_TYPE_SELECT != EMMC_FLASH +#error "you should select emmc flash device type!" +#endif +#endif + //ok //err//ok //ok //err//ok //ok +#define SYSPLL_CLK 400 //550//600//550//400//500//300//400 +#define CPUPLL_CLK 550 //550//550//550//550//500//550//550 +#define DDRPLL_CLK 600 //700//700//700//600//700//700//700 （RGB屏超过600M低温卡死，lvds屏正常） +#define VPUPLL_CLK 240 //240//240//240//240//240//240//240 + +#define CLK_APB_FREQ (SYSPLL_CLK * 1000000 / 2) +#define OSC_FREQ 24000000 + +#define tref 1560 //(unsigned int)((3900*DDR_CLK)/1000) +#define cas 6 +#define twl 5 +#define tmrd 4 +#define tras 19 //13 //(unsigned int)((45*DDR_CLK)/1000) +#define trc 28 //16 //(unsigned int)((60*DDR_CLK)/1000) +#define trcd 6 //(unsigned int)((15*DDR_CLK)/1000) +#define trfc 45 //37 //(unsigned int)((105*DDR_CLK)/1000) +#define trp 6 //(unsigned int)((15*DDR_CLK)/1000) +#define trrd 5 //(unsigned int)((10*DDR_CLK)/1000) +#define twr 6 //(unsigned int)((15*DDR_CLK)/1000) +#define twtr 4 //(unsigned int)((8*DDR_CLK)/1000) +#define txp 4 +#define txsr 200 +#define tesr 6 +#define tfaw 18 //(unsigned int)((45*DDR_CLK)/1000) + +extern void SetSysPLL(unsigned int freq); +extern void SetCpuPLL(unsigned int freq); +extern void SetDDRPLL(unsigned int freq); +extern void SetVPUPLL(unsigned int freq); +extern void SetXclkAHBclkAPBclk(void); +extern void SetSpiclk(void); +extern void SetGpuclk(void); +extern void SetMfcclk(void); +extern void SwitchTo24MHz(void); +extern void updateFromSD(int chipid); +extern void FlashBurn(void *buf, unsigned int offset, unsigned int size); +extern int wdt_init(unsigned int clk_freq); +extern int EmmcInit(int chipid); +extern void launchEMMC(int chipid); +extern int EmmcBurn(void *buf, unsigned int offset, unsigned int size, int show_progress); + +static void delay(volatile UINT32 count ) +{ + while(count--); +} + +void ddr_rd_clk_config() +{ + unsigned int i; + rSYS_DDRCTL1_CFG = 0x01; //reset pll + delay(1000); + rSYS_DDRCTL1_CFG = 0x00; //enable pll + delay(100000); + i = 0x01 << 1 | 200 << 8; + rSYS_DDRCTL1_CFG = i; + delay(100000); +} + +void ddr_training_one(void) +{ + int value = 0; + + rSYS_DDRCTL_CFG = (1<<15); +// value = (0x1c<<0) |(0x1c<<8)|(0x30<<16); +// value = (0x1c<<0) |(0x1c<<8)|(0x18<<16); fail 25 +// value = (0x1c<<0) |(0x1c<<8)|(0x20<<16); 25 ok +// value = (0x1c<<0) |(0x1c<<8)|(0x28<<16); 25 ok +// value = (0x1c<<0) |(0x1c<<8)|(0x30<<16); +// value = (0x1c<<0) |(0x1c<<8)|(0x26<<16); //4 ok +// value = (0x1c<<0) |(0x1c<<8)|(0x20<<16); //1 ok +// value = (0x1c<<0) |(0x1c<<8)|(0x30<<16); //4 ok 0514 + value = (0x1c<<0) |(0x1c<<8)|(0x33<<16); //4 ok +// value = (0x1c<<0) |(0x1c<<8)|(0x3b<<16); //4 ok + + rSYS_DDRCTL1_CFG =value; + rSYS_DDRCTL2_CFG =value; +} + +#if 0 +#define DDR_TOTAL 0x10000 +int DDR3_RW_Test(void) +{ + + unsigned int i=0; + unsigned int data_char; + + for (i=0; iapp_checksum = header->checksum; + sysinfo->stepldr_offset = STEPLDRA_OFFSET; + sysinfo->stepldr_size = STEPLDR_MAX_SIZE; + sysinfo->update_status = UPDATE_STATUS_END; + sysinfo->image_offset = IMAGE_OFFSET; + sysinfo->loader_offset = LOADER_OFFSET; + sysinfo->loader_size = LOADER_MAX_SIZE; + +#if DEVICE_TYPE_SELECT != EMMC_FLASH + SendUartString("burn loader start... \r\n"); + FlashBurn((void*)loader_addr, LOADER_OFFSET, LOADER_MAX_SIZE); + SendUartString("burn loader end. \r\n"); + + SendUartString("burn stepldr start... \r\n"); + FlashBurn((void*)stepldr_addr, STEPLDRA_OFFSET, STEPLDR_MAX_SIZE); + SendUartString("burn stepldr end. \r\n"); + + SendUartString("burn app start... \r\n"); + FlashBurn((void*)app_addr, IMAGE_OFFSET, header->size); + SendUartString("burn app end. \r\n"); +#else + EmmcInit(0); + + SendUartString("burn launch start... \r\n"); + FlashBurn((void*)launch_addr, LOADER_OFFSET, LOADER_MAX_SIZE); + SendUartString("burn launch end. \r\n"); + + SendUartString("burn loader start... \r\n"); + EmmcBurn((void*)loader_addr, LOADER_OFFSET, LOADER_MAX_SIZE, 0); + SendUartString("burn loader end. \r\n"); + + SendUartString("burn stepldr start... \r\n"); + EmmcBurn((void*)stepldr_addr, STEPLDRA_OFFSET, STEPLDR_MAX_SIZE, 0); + SendUartString("burn stepldr end. \r\n"); + + SendUartString("burn app start... \r\n"); + EmmcBurn((void*)app_addr, IMAGE_OFFSET, header->size, 0); + SendUartString("burn app end. \r\n"); +#endif + + SaveSysInfo(sysinfo); + + SendUartString("Update is finished. Please reset. \r\n"); + while(1); +} + +void main(void) +{ + unsigned int val; + + //set all io drive to 4ma(default 8ma). + rSYS_IO_DRIVER00=0x55555555; + rSYS_IO_DRIVER01=0x55555555; + rSYS_IO_DRIVER02=0x55555555; + rSYS_IO_DRIVER03=0x55555555; + rSYS_IO_DRIVER04=0x55555555; + rSYS_IO_DRIVER05=0x55555555; + rSYS_IO_DRIVER06=0x55555555; + +#if PROJECT_PURPOSE == PROJECT_FOR_LAUNCH_EMMC + timer_init(); + InitUart(115200); + SendUartString("\nARK AMT630Hv100 launch emmc from norflash\r\n"); + wdt_init(OSC_FREQ); + launchEMMC(0); +#endif + + SwitchTo24MHz(); + timer_init(); + InitUart(115200); + SendUartString("\nARK AMT630Hv100 AMTLDR 0906_700M\n"); +/* + val = rSYS_ANA1_CFG; + val |= (1 << 4)|(5 << 1); + rSYS_ANA1_CFG = val; + udelay(300); + val = rSYS_ANA1_CFG; + val &= ~(0x1 <<5); + rSYS_ANA1_CFG = val; +*/ +#if 1 //低电压2.8V复位 + rSYS_ANA1_CFG |= (1 << 4)|(5 << 1); + udelay(300); + rSYS_ANA1_CFG |= (1 << 5); + udelay(100); +#else //低电压2.5V复位 + rSYS_ANA1_CFG |= (1 << 4)|(0 << 1); + udelay(3000); + rSYS_ANA1_CFG |= (1 << 5); + udelay(1000); +#endif + val = rSYS_ANA2_CFG; + val = (0x3F <<6)|(1 << 2)|(1 << 0); + rSYS_ANA2_CFG = val; + + SetSysPLL(SYSPLL_CLK); + SetCpuPLL(CPUPLL_CLK); + SetDDRPLL(DDRPLL_CLK); + SetVPUPLL(VPUPLL_CLK); + udelay(500); + + SetXclkAHBclkAPBclk(); + SetSpiclk(); + SetGpuclk(); + SetMfcclk(); + mdelay(50); //50 + +#if PROJECT_PURPOSE == PROJECT_FOR_SPIFLASH_LOADER || PROJECT_PURPOSE == PROJECT_FOR_EMMC_LOADER + wdt_init(CLK_APB_FREQ); +#endif + + ddr3_sdramc_init(); + mdelay(50); //80//100 + SendUartString("\nDDR init over2!!_m50\n"); + SpiInit(); +#ifdef MMU_ENABLE + MMU_Init(); +#endif + +#if PROJECT_PURPOSE == PROJECT_FOR_DDR_INIT + while(1); +#elif PROJECT_PURPOSE == PROJECT_FOR_SPIFLASH_LOADER + bootFromSPI(); +#elif PROJECT_PURPOSE == PROJECT_FOR_SD_UPDATE + SetDefaultSysInfo(); + SaveSysInfo(0); + updateFromSD(0); + bootFromSPI(); +#elif PROJECT_PURPOSE == PROJECT_FOR_JTAG_UPDATE + updateFromJtag(); +#elif PROJECT_PURPOSE == PROJECT_FOR_EMMC_LOADER + bootFromEMMC(0); +#endif +} diff --git a/A58-AMTLDR/Src/SpiBooter.c b/A58-AMTLDR/Src/SpiBooter.c new file mode 100644 index 00000000..2588968b --- /dev/null +++ b/A58-AMTLDR/Src/SpiBooter.c @@ -0,0 +1,747 @@ +#include +#include "typedef.h" +#include "amt630h.h" +#include "UartPrint.h" +#include "timer.h" +#include "spi.h" +#include "cp15.h" +#include "sysinfo.h" +#include "crc32.h" +#include "gpio.h" + + +#if DEVICE_TYPE_SELECT == SPI_NOR_FLASH || DEVICE_TYPE_SELECT == EMMC_FLASH +#define SPI_CS_GPIO 32 + +#define SPI_RXFIFO_FULL (1<<4) +#define SPI_RXFIFO_NOTEMPTY (1<<3) +#define SPI_TXFIFO_EMPTY (1<<2) +#define SPI_TXFIFO_NOTFULL (1<<1) +#define SPIFLASH_BUSY (1<<0) + +/* SFUD support manufacturer JEDEC ID */ +#define SFUD_MF_ID_CYPRESS 0x01 +#define SFUD_MF_ID_FUJITSU 0x04 +#define SFUD_MF_ID_EON 0x1C +#define SFUD_MF_ID_ATMEL 0x1F +#define SFUD_MF_ID_MICRON 0x20 +#define SFUD_MF_ID_AMIC 0x37 +#define SFUD_MF_ID_SANYO 0x62 +#define SFUD_MF_ID_INTEL 0x89 +#define SFUD_MF_ID_ESMT 0x8C +#define SFUD_MF_ID_FUDAN 0xA1 +#define SFUD_MF_ID_HYUNDAI 0xAD +#define SFUD_MF_ID_SST 0xBF +#define SFUD_MF_ID_MICRONIX 0xC2 +#define SFUD_MF_ID_GIGADEVICE 0xC8 +#define SFUD_MF_ID_ISSI 0xD5 +#define SFUD_MF_ID_WINBOND 0xEF + +static void SpiWriteEnable(void); + +/* flash chip information */ +typedef struct { + char *name; /**< flash chip name */ + uint8_t mf_id; /**< manufacturer ID */ + uint8_t type_id; /**< memory type ID */ + uint8_t capacity_id; /**< capacity ID */ + uint32_t capacity; /**< flash capacity (bytes) */ +} flash_chip; + +static const flash_chip flash_chip_table[] = +{ + {"W25Q40BV", SFUD_MF_ID_WINBOND, 0x40, 0x13, 512L*1024L}, + {"W25Q16BV", SFUD_MF_ID_WINBOND, 0x40, 0x15, 2L*1024L*1024L}, + {"W25Q32BV", SFUD_MF_ID_WINBOND, 0x40, 0x16, 4L*1024L*1024L}, + {"W25Q64CV", SFUD_MF_ID_WINBOND, 0x40, 0x17, 8L*1024L*1024L}, + {"W25Q64DW", SFUD_MF_ID_WINBOND, 0x60, 0x17, 8L*1024L*1024L}, + {"W25Q128BV", SFUD_MF_ID_WINBOND, 0x40, 0x18, 16L*1024L*1024L}, + {"W25Q256FV", SFUD_MF_ID_WINBOND, 0x40, 0x19, 32L*1024L*1024L}, + {"W25H256JV", SFUD_MF_ID_WINBOND, 0x90, 0x19, 32L*1024L*1024L}, + {"W25Q512JVFM", SFUD_MF_ID_WINBOND, 0x70, 0x20, 64L*1024L*1024L}, + {"SST25VF080B", SFUD_MF_ID_SST, 0x25, 0x8E, 1L*1024L*1024L}, + {"SST25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2L*1024L*1024L}, + {"EN25Q32B", SFUD_MF_ID_EON, 0x30, 0x16, 4L*1024L*1024L}, + {"GD25Q64B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x17, 8L*1024L*1024L}, + {"GD25Q16B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x15, 2L*1024L*1024L}, + {"GD25Q32C", SFUD_MF_ID_GIGADEVICE, 0x40, 0x16, 4L*1024L*1024L}, + {"S25FL216K", SFUD_MF_ID_CYPRESS, 0x40, 0x15, 2L*1024L*1024L}, + {"S25FL032P", SFUD_MF_ID_CYPRESS, 0x02, 0x15, 4L*1024L*1024L}, + {"A25L080", SFUD_MF_ID_AMIC, 0x30, 0x14, 1L*1024L*1024L}, + {"F25L004", SFUD_MF_ID_ESMT, 0x20, 0x13, 512L*1024L}, + {"PCT25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2L*1024L*1024L}, + {"IS25LP128F", SFUD_MF_ID_ISSI, 0x60, 0x18, 16L*1024L*1024L}, + {"MX25L6433F", SFUD_MF_ID_MICRONIX, 0x20, 0x17, 8L*1024L*1024L}, + {"MX25L12845G", SFUD_MF_ID_MICRONIX, 0x20, 0x18, 16L*1024L*1024L}, + {"MX25L25645G", SFUD_MF_ID_MICRONIX, 0x20, 0x19, 32L*1024L*1024L}, + {"W25Q512JVFM", SFUD_MF_ID_WINBOND, 0x70, 0x20, 64L*1024L*1024L}, + {"GD25B512ME", SFUD_MF_ID_GIGADEVICE, 0x47, 0x1A, 64L*1024L*1024L}, +}; + +static int addr_in_4_byte = 0; + +static void SetCSGpioEnable(int enable) +{ + gpio_direction_output(SPI_CS_GPIO, !enable); +} + +static void SetSpiDataMode(unsigned int bitMode) +{ + unsigned int val = 0; + + (void)val; + while((rSPI_SR & SPI_BUSY)); + rSPI_SSIENR = 0; + val = rSPI_CTLR0; + val &=~(0x1f<<16); + val |=((bitMode-1)<<16); + rSPI_CTLR0 = val; + rSPI_SSIENR = 1; +} + +static void SpiWaitIdle(void) +{ + while(rSPI_SR & SPIFLASH_BUSY); + udelay(2); +} + +static void SpiEmptyRxFIFO(void) +{ + INT32 data = 0; + + (void)data; + + while(rSPI_SR & SPI_RXFIFO_NOTEMPTY) + data = rSPI_DR; +} + +/* static void SpiWriteSta2(uint8_t status) +{ + SpiWriteEnable(); + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_WRITE_STATUS2; + rSPI_DR = status; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static UINT8 SpiReadSta2(void) +{ + UINT8 status; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_READ_STATUS2; + rSPI_DR = 0; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + PrintVariableValueHex("status s2 :", status); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + return status; +} */ + +static UINT8 SpiReadSta3(void) +{ + UINT8 status; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_READ_STATUS3; + rSPI_DR = 0; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + PrintVariableValueHex("status s3 :", status); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + return status; +} + +static UINT8 SpiReadSta(void) +{ + UINT8 status; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_READ_STATUS; + rSPI_DR = 0; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + //PrintVariableValueHex("status:", status); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + return status; +} + +static void SpiDisable4ByteMode(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_DISABLE_4BYTE_MODE; + while(!(rSPI_SR & SPI_TXFIFO_EMPTY)); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiEnable4ByteMode(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_ENABLE_4BYTE_MODE; + while(!(rSPI_SR & SPI_TXFIFO_EMPTY)); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiReadPage(UINT32 pagenum, UINT32 *buf) +{ + UINT32 addr; + UINT32 val = 0; + INT32 i, j; + UINT8 tmpaddr[4]; + UINT8 *data = (UINT8*)buf; + + (void)val; + + addr = pagenum*BYTESPERPAGE; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiEmptyRxFIFO(); + SetCSGpioEnable(1); + + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADDR_READ_DATA; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + for (i = 0; i < 5; i++) { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val = rSPI_DR; + } + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_READ_DATA; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val = rSPI_DR; + } + + if (addr_in_4_byte) { + for (i = 0; i < 4; i++) { + for (j = 0; j < WORDSPERPAGE; j++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = 0; + } + for (j = 0; j < WORDSPERPAGE; j++) { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + *data++ = rSPI_DR; + } + } + } else { + for (i = 0; i < WORDSPERPAGE; i++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = 0; + } + for(i = 0; i < WORDSPERPAGE; i++) { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + *buf++ = rSPI_DR; + } + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + if (addr_in_4_byte) + SetSpiDataMode(32); +} + +void SpiSelectPad() +{ + UINT32 val; + val = rSYS_PAD_CTRL02; + val &= ~0xfff; + val |= (0x1<<10)|(0x1 << 8)|(0x1 << 6)|(0x1 << 4)| (0x1 << 2); + rSYS_PAD_CTRL02 = val; + + val = rSYS_SSP_CLK_CFG; + val &= ~((0x1<<31)|(0x1<<30)); + val |= (0x1<<31)|(0x1<<30); + rSYS_SSP_CLK_CFG = val; + + //cs inactive first + SetCSGpioEnable(0); +} + +void Reset(void) +{ + SetSpiDataMode(8); + rSPI_DR = 0x66; + while((SpiReadSta() & SPI_BUSY)); +// while(!(SpiReadSta() & SPIFLASH_WRITEENABLE)); + rSPI_DR = 0x99; + while((SpiReadSta() & SPI_BUSY)); +// while(!(SpiReadSta() & SPIFLASH_WRITEENABLE)); + + SetSpiDataMode(32); +} + +#define SPI0_CS0_GPIO 32 +#define SPI0_IO0_GPIO 34 +static void dwspi_jedec252_reset(void) +{ + int i; + int si = 0; + UINT32 val; + + val = rSYS_PAD_CTRL02; + val &= ~((3 << 4) | 3); + rSYS_PAD_CTRL02 = val; + + gpio_direction_output(SPI0_CS0_GPIO, 1); + gpio_direction_output(SPI0_IO0_GPIO, 1); + udelay(300); + + for (i = 0; i < 4; i++) { + gpio_direction_output(SPI0_CS0_GPIO, 0); + gpio_direction_output(SPI0_IO0_GPIO, si); + si = !si; + udelay(300); + gpio_direction_output(SPI0_CS0_GPIO, 1); + udelay(300); + } +} + +static void SpiReadDeviceId(UINT8 *mfid, UINT8 *devid) +{ + UINT8 val[6]; + int i; + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_MF_DEVICE_ID; + rSPI_DR = 0; + rSPI_DR = 0; + rSPI_DR = 0; + rSPI_DR = 0; + rSPI_DR = 0; + for (i = 0; i < 6; i++) + { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val[i] = rSPI_DR; + } + *mfid = val[4]; + *devid = val[5]; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiReadJedecId(UINT8 *mfid, UINT8 *memid, UINT8 *capid) +{ + UINT8 val[4]; + int i; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_READ_JEDEC_ID; + rSPI_DR = 0; + rSPI_DR = 0; + rSPI_DR = 0; + + for (i = 0; i < 4; i++) + { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val[i] = rSPI_DR; + } + *mfid = val[1]; + *memid = val[2]; + *capid = val[3]; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +void SpiReadId(void) +{ + UINT8 mfid,devid,memid,capid; + + SpiReadDeviceId(&mfid,&devid); + SpiReadJedecId(&mfid,&memid,&capid); + PrintVariableValueHex("ManufacturerID: ", mfid); + PrintVariableValueHex("DeviceID: ", devid); + PrintVariableValueHex("Memory Type ID: ", memid); + PrintVariableValueHex("Capacity ID: ", capid); +} + +int SpiInit(void) +{ + uint8_t mfid, typeid, capid; + unsigned int val; + int i; + + dwspi_jedec252_reset(); + SpiSelectPad(); + + val = rSYS_SOFT_RST; + val &= ~(0x1<<8); + rSYS_SOFT_RST = val; + udelay(10); + val |= (0x1<<8); + rSYS_SOFT_RST = val; + + rSPI_SSIENR = 0; + rSPI_CTLR0 = 0; + rSPI_CTLR0 |=(0<<21)|(0x1f<<16)|(0x0<<12)|(0x0<<8)|(0x0<<4); + //rSPI_CTLR1 = 63; + rSPI_BAUDR = 4;//42;//16;//2; + rSPI_SER = 1; + rSPI_IMR = 0; + rSPI_SSIENR = 1; + +// Reset(); + SpiReadJedecId(&mfid, &typeid, &capid); + for (i = 0; i < sizeof(flash_chip_table) / sizeof(flash_chip); i++) { + if ((flash_chip_table[i].mf_id == mfid) + && (flash_chip_table[i].type_id == typeid) + && (flash_chip_table[i].capacity_id == capid)) { + if (flash_chip_table[i].capacity > 0x1000000) { + PrintVariableValueHex("i is %x : ", i); + addr_in_4_byte = 1; + SpiEnable4ByteMode(); + } + break; + } + } + + if (!addr_in_4_byte) + SpiDisable4ByteMode(); + +#ifdef SPI0_QSPI_MODE + uint8_t status = SpiReadSta2(); + status |= SPI_QE; + SpiWriteSta2(status); +#endif + + SpiReadSta3(); + + udelay(10000); + + return 0; +} + +#define SPI_READ_MAXLEN BYTESPERPAGE + +static void SpiLoadStepldr(void (*readfunc)(UINT32, UINT32 *)) +{ + unsigned int i = 0; + UINT32 *buf = (UINT32*)STEPLDR_ENTRY; + UINT32 offset; + UINT32 size; + UINT32 nPageCount; + UINT32 nPageStart; + + if (ReadSysInfo()) { + SendUartString("read sysinfo fail, try to load stepldr part a.\n"); + offset = STEPLDRA_OFFSET; + size = STEPLDR_MAX_SIZE; + } else { + SysInfo *sysinfo = GetSysInfo(); + offset = sysinfo->stepldr_offset; + size = sysinfo->stepldr_size; + } + + PrintVariableValueHex("stepldr offset: ", offset); + + nPageCount = (size + BYTESPERPAGE - 1) / BYTESPERPAGE; + nPageStart = offset / BYTESPERPAGE; + for(i = nPageStart; i < nPageStart + nPageCount; i++) + { + readfunc(i, buf); + buf += BYTESPERPAGE/4; + } + +#ifdef MMU_ENABLE + CP15_clean_dcache_for_dma(STEPLDR_ENTRY, STEPLDR_ENTRY + size); +#endif +} + +static void SpiWriteEnable(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_WRITE_ENABLE; + SpiWaitIdle(); + SetCSGpioEnable(0); + while((SpiReadSta() & SPI_BUSY)); + while(!(SpiReadSta() & SPIFLASH_WRITEENABLE)); + SetSpiDataMode(32); +} + +static void SpiEraseSector(UINT32 sectorNum) +{ + UINT32 addr; + UINT8 tmpaddr[4]; + + addr = BYTESPERSECTOR*sectorNum; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiWriteEnable(); + SetCSGpioEnable(1); + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADD_SECTOR_ERASE; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_SECTOR_ERASE; + } + SpiWaitIdle(); + SetCSGpioEnable(0); + while((SpiReadSta() & SPIFLASH_WRITEENABLE)); +} + +static void SpiEraseBlock(UINT32 blockNum) +{ + UINT32 addr; + UINT8 tmpaddr[4]; + + addr = BYTESPERBLOCK*blockNum; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiWriteEnable(); + SetCSGpioEnable(1); + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADD_BLOCK_ERASE; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_BLOCK_ERASE; + } + SpiWaitIdle(); + SetCSGpioEnable(0); + + while((SpiReadSta() & SPIFLASH_WRITEENABLE)); +} + +static void SpiWritePage(UINT32 pagenum, UINT32 *buf) +{ + UINT32 addr; + UINT32 val = 0;; + INT32 i; + UINT8 tmpaddr[4]; + UINT8 *data = (UINT8*)buf; + + (void)val; + + addr = pagenum*BYTESPERPAGE; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiWriteEnable(); + SetCSGpioEnable(1); + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADD_PAGE_PROGRAM; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_PAGE_PROGRAM; + } + + if (addr_in_4_byte) { + for (i = 0; i < BYTESPERPAGE; i++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = *data++; + } + } else { + for (i = 0; i < WORDSPERPAGE; i++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = *buf++; + } + } + SpiWaitIdle(); + SetCSGpioEnable(0); + while(SpiReadSta() & SPI_BUSY); +} + +void bootFromSPI(void) +{ + void (*funPtr)(void); + + SpiLoadStepldr(SpiReadPage); + + funPtr = (void (*)(void))STEPLDR_ENTRY; + funPtr(); +} + +static unsigned int pagecheck[WORDSPERPAGE]; +/* offset is at least align to SECOTR_SIZE */ +static int SpiNorBurnPage(int pagenum, unsigned int *buf) +{ + int timeout = 3; + unsigned int *tmp = (unsigned int *)buf; + int i; + +retry: + SpiWritePage(pagenum, buf); + SpiReadPage(pagenum, pagecheck); + for (i = 0; i < WORDSPERPAGE; i++) { + if (tmp[i] != pagecheck[i]) { + if (timeout-- > 0) { + PrintVariableValueHex("write: ", tmp[i]); + PrintVariableValueHex("read: ", pagecheck[i]); + SendUartString("burn check data fail, retry...\r\n"); + goto retry; + } else { + SendUartString("burn error!\r\n"); + return -1; + } + } + } + + return 0; +} + + +/* offset is at least align to SECOTR_SIZE */ +static int SpiNorBurn(void *buf, unsigned int offset, unsigned int size) +{ + int i, j; + int secstart, secnum; + int blkstart, blknum; + int pagestart, pageburned; + int remain = size; + unsigned int *pbuf = (unsigned int *)buf; + + pagestart = offset / BYTESPERPAGE; + pageburned = 0; + + while (remain > 0) { + unsigned int tmp = offset & (BYTESPERBLOCK - 1); + if (tmp) { + tmp = (BYTESPERBLOCK - tmp) / BYTESPERSECTOR; + secnum = (remain + BYTESPERSECTOR - 1) / BYTESPERSECTOR; + secnum = min(tmp, secnum); + secstart = offset / BYTESPERSECTOR; + for (i = 0; i < secnum; i++) { + SpiEraseSector(secstart + i); + for (j = 0; j < PAGESPERSECTORS; j++) { + if (SpiNorBurnPage(pagestart + j, pbuf)) + return -1; + pbuf += WORDSPERPAGE; + pageburned++; + remain -= BYTESPERPAGE; + if (remain <= 0) goto finish; + } + pagestart += PAGESPERSECTORS; + } + offset += secnum * BYTESPERSECTOR; + } else { + blkstart = offset / BYTESPERBLOCK; + blknum = remain / BYTESPERBLOCK; + for (i = 0; i < blknum; i++) { + SpiEraseBlock(blkstart + i); + for (j = 0; j < PAGESPERSECTORS * SECTORSPERBLOCK; j++) { + if (SpiNorBurnPage(pagestart + j, pbuf)) + return -1; + pbuf += WORDSPERPAGE; + pageburned++; + remain -= BYTESPERPAGE; + if (remain <= 0) goto finish; + } + pagestart += PAGESPERSECTORS * SECTORSPERBLOCK; + } + offset += blknum * BYTESPERBLOCK; + if (remain > 0) { + secstart = offset / BYTESPERSECTOR; + secnum = (remain + BYTESPERSECTOR - 1) / BYTESPERSECTOR; + for (i = 0; i < secnum; i++) { + SpiEraseSector(secstart + i); + for (j = 0; j < PAGESPERSECTORS; j++) { + if (SpiNorBurnPage(pagestart + j, pbuf)) + return -1; + pbuf += WORDSPERPAGE; + pageburned++; + remain -= BYTESPERPAGE; + if (remain <= 0) goto finish; + } + pagestart += PAGESPERSECTORS; + } + offset += secnum * BYTESPERSECTOR; + } + } + } +finish: + return 0; +} + +int FlashBurn(void *buf, unsigned int offset, unsigned int size) +{ + return SpiNorBurn(buf, offset, size); +} + +int SpiReadSysInfo(SysInfo *info) +{ + int pagestart; + UINT32 checksum; + UINT32 calc_checksum; + UINT8 data[512]; + + pagestart = SYSINFOA_OFFSET / BYTESPERPAGE; + SpiReadPage(pagestart, (UINT32 *)data); + + checksum = *(UINT32*)((UINT32)data + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)data, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, data, sizeof(SysInfo)); + return 0; + } + + pagestart = SYSINFOB_OFFSET / BYTESPERPAGE; + SpiReadPage(pagestart, (UINT32 *)data); + + checksum = *(UINT32*)((UINT32)data + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)data, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, data, sizeof(SysInfo)); + return 0; + } + + return -1; +} + +void SpiWriteSysInfo(SysInfo *info) +{ + SpiNorBurn(info, SYSINFOB_OFFSET, sizeof(SysInfo)); + SpiNorBurn(info, SYSINFOA_OFFSET, sizeof(SysInfo)); +} +#endif diff --git a/A58-AMTLDR/Src/SpinandBooter.c b/A58-AMTLDR/Src/SpinandBooter.c new file mode 100644 index 00000000..a0a04384 --- /dev/null +++ b/A58-AMTLDR/Src/SpinandBooter.c @@ -0,0 +1,1393 @@ +#include +#include +#include "typedef.h" +#include "amt630h.h" +#include "UartPrint.h" +#include "timer.h" +#include "spi.h" +#include "cp15.h" +#include "sysinfo.h" +#include "crc32.h" +#include "gpio.h" + +#if DEVICE_TYPE_SELECT == SPI_NAND_FLASH +/* SPI commands */ +#define SPI_RXFIFO_ENABLE (1<<8) +#define SPI_TRANS_COMPLETE (1<<7) +#define SPI_RXFIFO_OVER (1<<6) + +#define SPI_TXFIFO_FULL (1<<2) +#define SPI_TXFIFO_REQ (1<<1) + +#define SPI_RXFIFO_FULL (1<<4) +#define SPI_RXFIFO_NOTEMPTY (1<<3) +#define SPI_TXFIFO_EMPTY (1<<2) +#define SPI_TXFIFO_NOTFULL (1<<1) +#define SPI_BUSY (1<<0) + +#define SPI0_CS0_GPIO 32 +#define SPI0_IO0_GPIO 34 +#define SPI_CS_GPIO SPI0_CS0_GPIO + + +/* SPI NAND commands */ +#define SPI_NAND_WRITE_ENABLE 0x06 +#define SPI_NAND_WRITE_DISABLE 0x04 +#define SPI_NAND_GET_FEATURE 0x0f +#define SPI_NAND_SET_FEATURE 0x1f +#define SPI_NAND_PAGE_READ 0x13 +#define SPI_NAND_READ_CACHE 0x03 +#define SPI_NAND_FAST_READ_CACHE 0x0b +#define SPI_NAND_READ_CACHE_X2 0x3b +#define SPI_NAND_READ_CACHE_X4 0x6b +#define SPI_NAND_READ_CACHE_DUAL_IO 0xbb +#define SPI_NAND_READ_CACHE_QUAD_IO 0xeb +#define SPI_NAND_READ_ID 0x9f +#define SPI_NAND_PROGRAM_LOAD 0x02 +#define SPI_NAND_PROGRAM_LOAD4 0x32 +#define SPI_NAND_PROGRAM_EXEC 0x10 +#define SPI_NAND_PROGRAM_LOAD_RANDOM 0x84 +#define SPI_NAND_PROGRAM_LOAD_RANDOM4 0xc4 +#define SPI_NAND_BLOCK_ERASE 0xd8 +#define SPI_NAND_RESET 0xff + +/* Registers common to all devices */ +#define SPI_NAND_LOCK_REG 0xa0 +#define SPI_NAND_PROT_UNLOCK_ALL 0x0 + +#define SPI_NAND_FEATURE_REG 0xb0 +#define SPI_NAND_ECC_EN (1 << 4) +#define SPI_NAND_QUAD_EN (1 << 0) + +#define SPI_NAND_STATUS_REG 0xc0 +#define SPI_NAND_STATUS_REG_ECC_MASK 0x3 +#define SPI_NAND_STATUS_REG_ECC_SHIFT 4 +#define SPI_NAND_STATUS_REG_PROG_FAIL (1 << 3) +#define SPI_NAND_STATUS_REG_ERASE_FAIL (1 << 2) +#define SPI_NAND_STATUS_REG_WREN (1 << 1) +#define SPI_NAND_STATUS_REG_BUSY (1 << 0) + +#define SPI_NAND_ECC_UNCORR 0x2 + +/* */ +#define MAX_SNF_BUF_SIZE 32 +#define MAX_SPARE_SIZE 64 +#define MAX_PAGE_SIZE 2048 +#define MAX_BLK_SIZE 2048 + +#define SNF_MAX_BLOCK_COUNT 2048 +#define SNF_REPLACE_BLK_PERCENT 2 //default: 2% +#define SNF_BBT_BLK_COUNT 4 +#define SNF_BBT_HEADER_SIZE 32 +#define SNF_BBT_HEADER_MASK "SNF BAD BLOCK TABLE" //<32 bytes. + + +enum { + SNF_OK, + SNF_ERR, + SNF_TIMEOUT, + SNF_BAD_BLK, +}; + +enum { + SNF_BLK_BAD = 0, + SNF_BLK_USED, + SNF_BLK_GOOD = 0xFF +}; + +typedef struct _snf_blk_node { + u8 status; + u16 replace; //replace bad block. +} snf_blk_node; + +typedef struct _snf_bbt { + u8 header_mask[SNF_BBT_HEADER_SIZE]; + snf_blk_node node[SNF_MAX_BLOCK_COUNT]; + u32 bad_blocks; + u32 reserved[8]; + u32 bbt_crc; +} snf_bbt; + +typedef struct spi_nand_plane_select +{ + /* plane select is used for block select */ + u32 rpb; //read page(from nand array to cache) bit. + u32 rcb; //read cache(from page cache to app buffer) bit. + u32 plb; //program load(write data to cache) bit. + u32 peb; //program excute(flush cache to nand array) bit. +} snf_ps; + +typedef struct spi_nand_cfg_tag +{ + char Name[MAX_SNF_BUF_SIZE]; + u8 MID; + u8 DID0; + u8 DID1; + u8 BBMType; + u32 BytePerPage; + u32 PagePerBlk; + u32 TotalBlk; + u32 SprSize; + int PsArrayIndex; +} spi_nand_cfg; + +typedef struct _snf_chip_info +{ + u8 Name[MAX_SNF_BUF_SIZE]; + u8 MID; + u8 DID0; + u8 DID1; + u8 BBMType; + u32 BytePerPage; + u32 BytePerBlk; + u32 TotalBlk; + u32 SprSize; + u32 FtlSprSize; + u32 PsArrayIndex; + // + u32 AvailableBlks; + u32 Capacity; + u32 AvailableCapacity; + u32 PagePerBlk; + u32 BbtBlkOffset; + u32 ReplaceBlks; + snf_bbt bbt; + snf_ps *ps; +} snf_chip_info; + +static int SpiNandFindAReplaceBlock(snf_chip_info *chip, u32 *block); +static int SpiNandUpdateBbt(void); +static int SpiNandCheckReplaceBlockValid(u32 block); + + +/* PlaneSelect bit array */ +static snf_ps g_SnfPsArray[] = { + [0] = {6, 12, 12, 6}, /* DS35Q2GA */ +}; +static spi_nand_cfg g_SnfChipCfgArray[] = +{ + // name, MID, DID0, DID1, BBM, BytePerPage, PagePerBlk, TotalBlkCnt, SpareSize, PlaneSelect + { "DS35Q1GA", 0xE5, 0x71, 0x00, 2, 2048, 64, 1024, 64, -1/* not use */}, + { "DS35Q2GA", 0xE5, 0x72, 0x00, 2, 2048, 64, 2048, 64, 0}, + { "GD5F2GM7", 0xc8, 0x92, 0x00, 2, 2048, 64, 2048, 64, -1}, +}; +static snf_chip_info g_snf = {0}; +static unsigned int pagebuf[MAX_PAGE_SIZE/4]; + +static void UInt2str(u32 number, char *str) +{ + int i=0, j; + int temp; + char buf[20]; + + do { + temp = number % 10; + buf[i] = temp + 48; + i++; + number = number / 10; + } while (number != 0); + + buf[i]='\0'; + + for (j=0; jrpb);//set plane select bit. + } + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_PAGE_READ; + rSPI_DR = (page >> 16) & 0xFF; + rSPI_DR = (page >> 8) & 0xFF; + rSPI_DR = page & 0xFF; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +void SpiNandStorePage(u32 page) +{ + if (g_snf.ps) { + int block = page / g_snf.PagePerBlk; + if (block % 2) + page |= (1 << g_snf.ps->peb); + } + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_PROGRAM_EXEC; + rSPI_DR = (page >> 16) & 0xFF; + rSPI_DR = (page >> 8) & 0xFF; + rSPI_DR = page & 0xFF; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +int SpiNandReadCache(u32 page, u32 offset, int length, u8 *read_buf) +{ + int i; + u8 val = 0; + u32 addr = (offset & 0xFFF); + + (void)val; + + if (g_snf.ps) { + int block = page / g_snf.PagePerBlk; + if (block % 2) + addr |= (1 << g_snf.ps->rcb); + } + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_READ_CACHE; + rSPI_DR = (addr >> 8) & 0xFF; + rSPI_DR = addr & 0xFF; + rSPI_DR = 0x0; //dummy byte. + + for (i = 0; i < 4; i++) + { + while (!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val = rSPI_DR; + } + + for (i = 0; i < length; i++) + { + rSPI_DR = 0; + while (!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + read_buf[i] = rSPI_DR; + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + return SNF_OK; +} + +static int SpiNandReadPageSpare(u32 page, char *buf) +{ + int status; + int ecc_status; + int page_size = g_snf.BytePerPage; + int spare_size = g_snf.SprSize; + + SpiNandLoadPage(page); + status = SpiNandWaitTillReady(); + if (status < 0) + return status; + + ecc_status = (status >> SPI_NAND_STATUS_REG_ECC_SHIFT) & SPI_NAND_STATUS_REG_ECC_MASK; + if (ecc_status == SPI_NAND_ECC_UNCORR) + { + PrintVariableValueHex("SpiNandReadPageSpare ECC error, status:", status); + SNF_Print("pagenum:", __func__, page); + return -SNF_BAD_BLK; + } + return SpiNandReadCache(page, page_size, spare_size, (u8 *)buf); +} + +static int SpiNandStoreCache(u32 page, u32 offset, int length, u8 *write_buf) +{ + int i; + u32 addr = (offset & 0xFFF); + + if (g_snf.ps) { + int block = page / g_snf.PagePerBlk; + if (block % 2) + addr |= (1 << g_snf.ps->plb); //set read cache plane select bit. + } + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_PROGRAM_LOAD; + rSPI_DR = (addr >> 8) & 0xFF; + rSPI_DR = addr & 0xFF; + + for (i = 0; i < length; i++) + { + while (!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = write_buf[i]; + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + + return SNF_OK; +} + +static int SpiNandEraseBlock(int block) +{ + u32 page_offset; + int status; + int timeout = 0; + +retry: + SpiNandWriteEnable(); + SetSpiDataMode(8); + SetCSGpioEnable(1); + page_offset = block * g_snf.PagePerBlk; + rSPI_DR = SPI_NAND_BLOCK_ERASE; + rSPI_DR = (page_offset >> 16) & 0xff; + rSPI_DR = (page_offset >> 8) & 0xff; + rSPI_DR = page_offset & 0xff; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + + status = SpiNandWaitTillReady(); + if (status < 0) { + if (timeout++ < 3) + goto retry; + SNF_Print("block erase timeout, block:", __func__, block); + return status; + } + + if (status & SPI_NAND_STATUS_REG_ERASE_FAIL) { + /*find a new bad block. */ + SNF_Print("block erase failed, block:", __func__, block); + return -SNF_BAD_BLK; + } + + return SNF_OK; +} + +/* read a few bytes in one page */ +static int SpiNandReadBytesInPage(u32 page, u32 offset, u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + int status; + int ecc_status; + + SpiNandLoadPage(page); + status = SpiNandWaitTillReady(); + if (status < 0) { + SNF_Print2("timeout, block:", "page", __func__, page / chip->PagePerBlk, page % chip->PagePerBlk); + return status; + } + + ecc_status = (status >> SPI_NAND_STATUS_REG_ECC_SHIFT) & SPI_NAND_STATUS_REG_ECC_MASK; + if (ecc_status == SPI_NAND_ECC_UNCORR) //ECC error meains bad block. + { + SNF_Print2("ECC error blk:", "page:", __func__, page / chip->PagePerBlk, page % chip->PagePerBlk); + return -SNF_ERR;//-SNF_BAD_BLK; + } + return SpiNandReadCache(page, offset, size, data); +} + +static int SpiNandReadOnePage(u32 page, u8 *data) +{ + return SpiNandReadBytesInPage(page, 0, data, g_snf.BytePerPage); +} + +/* write a few bytes in one page */ +static int SpiNandWriteBytesInPage(u32 page, u32 offset, u8 *data, u32 size) +{ + int timeout = 0; + int ret; + +retry: + SpiNandWriteEnable(); + SpiNandStoreCache(page, offset, size, data); + SpiNandStorePage(page); + ret = SpiNandWaitTillReady(); + if (ret < 0) { + if (timeout++ < 3) + goto retry; + } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) { + return -SNF_BAD_BLK; + } + + return ret; +} + +static int SpiNandWriteOnePage(u32 page, u8 *data) +{ + return SpiNandWriteBytesInPage(page, 0, data, g_snf.BytePerPage); +} + +static int SpiNandReadPhysicalBlock(u32 block , u32 offset_in_block, u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + u8 *pdata = data; + u32 currpage, BytePerPage; + u32 offset_in_page; + u32 read_size; + int remain = size; + int ret; + + BytePerPage = chip->BytePerPage; + currpage = block * chip->PagePerBlk + offset_in_block / BytePerPage; + offset_in_page = offset_in_block % BytePerPage; + + while (remain > 0) { + read_size = ((BytePerPage - offset_in_page) >= remain) ? remain : (BytePerPage - offset_in_page); + ret = SpiNandReadBytesInPage(currpage, offset_in_page, pdata, read_size); + if (ret != SNF_OK) { + SNF_Print2("read page falied, page:", "block:", __func__, currpage, block); + break; + } + + if (offset_in_page) + offset_in_page = 0; + + currpage++; + remain -= read_size; + pdata += read_size; + } + + return ret; +} + +static int SpiNandReadInBlock(u32 block , u32 offset_in_block, u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + u32 blk = block; + int ret; + + //bad block check and replace. + if (chip->bbt.node[block].status == SNF_BLK_BAD) { + blk = chip->bbt.node[block].replace; + ret = SpiNandCheckReplaceBlockValid(blk); + if ((ret == SNF_OK) && (chip->bbt.node[blk].status != SNF_BLK_BAD)) { + //find replace block. + if (chip->bbt.node[blk].status != SNF_BLK_USED) { + SNF_Print2("block:", "replace blk:", __func__, block, blk); + chip->bbt.node[blk].status = SNF_BLK_USED; + } + } else { + SNF_Print2("bad block:", "invalid replace blk:", __func__, block, blk); + return -SNF_BAD_BLK; + } + } + + return SpiNandReadPhysicalBlock(blk, offset_in_block, data, size); +} + +static int SpiNandReadData(u32 addr, void *data, int size) +{ + snf_chip_info *chip = &g_snf; + u8 *pdata; + u32 read_size, bytePerBlk; + u32 currblk,offset_in_block; + int remain; + int ret = SNF_OK; + + pdata = (u8 *)data; + remain = size; + bytePerBlk = chip->BytePerBlk; + currblk = addr / bytePerBlk; + offset_in_block = addr % bytePerBlk; + + //area check valid. + if ((addr + size) > chip->AvailableCapacity) { + SNF_PrintString("burn out of boundry.\n", __func__); + return -SNF_ERR; + } + + while (remain > 0) { + //read block. + read_size = ((bytePerBlk - offset_in_block) >= remain) ? remain : (bytePerBlk - offset_in_block); + ret = SpiNandReadInBlock(currblk, offset_in_block, pdata, read_size); + if (ret != SNF_OK) { + SNF_Print("SpiNandReadInBlock failed, block:", __func__, currblk); + break; + } + + if (offset_in_block) + offset_in_block = 0; + + currblk++; + pdata += read_size; + remain -= read_size; + if (remain < 0) { + ret = -SNF_ERR; + SNF_PrintString("Invalid remain.\n", __func__); + break; + } + } + + return ret; +} + +/* offset is at least align to SECOTR_SIZE */ +static int SpiNandBurnPage(int page, u8 *buf) +{ + int ret; + + ret = SpiNandWriteOnePage(page, buf); + if (ret == SNF_OK) { + u32 *tmp = (u32 *)buf; + int wordPerPage = g_snf.BytePerPage / 4; + int i; + + ret = SpiNandReadOnePage(page, (u8 *)pagebuf); + if (ret == SNF_OK) { + for (i = 0; i < wordPerPage; i++) { + if (tmp[i] != pagebuf[i]) { + SNF_Print("burn error, pos:", __func__, i); + PrintVariableValueHex("write:", tmp[i]); + PrintVariableValueHex("read:", pagebuf[i]); + return -SNF_ERR; + } + } + } else { + SNF_Print("read page failed, page:", __func__, page); + return -SNF_ERR; //read page should not create a bad block. + } + } else { + SNF_Print("SpiNandWriteOnePage failed, page:", __func__, page); + return ret; + } + + return SNF_OK; +} + +static int SpiNandBurnBlock(u32 block, u32 offset_in_block, const u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + u8 *buf = (u8 *)data; + u32 left_size = size; + u8 pageBuf[MAX_PAGE_SIZE]; + u32 byte_per_page; + u32 start_page; + u32 whole_page_num; + u32 result; + u32 i; + + byte_per_page = chip->BytePerPage; + start_page = block * chip->PagePerBlk + offset_in_block / byte_per_page; + + if (offset_in_block % byte_per_page) { + SNF_PrintString("offset is not align with page.\n", __func__); + return -SNF_ERR; + } + + if (left_size > 0) { + whole_page_num = left_size / byte_per_page; + for (i=0; i 0) { + memset(pageBuf + left_size, 0xff, MAX_PAGE_SIZE - left_size); + memcpy(pageBuf, buf, left_size); + result = SpiNandBurnPage(start_page, pageBuf); + if (result != SNF_OK) { + SNF_Print2("Burn page failed, page:", "result:", __func__, start_page, result); + return result; + } + } + + return result; +} + +static int SpiNandEraseWriteInBlock(u32 block, u32 offset_in_block, void *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + int ret; + u32 blk = block; + u32 bbtUpdate = 0; + + //bad block check and replace. + if (chip->bbt.node[block].status == SNF_BLK_BAD) { + blk = chip->bbt.node[block].replace; + ret = SpiNandCheckReplaceBlockValid(blk); + if ((ret == SNF_OK) && (chip->bbt.node[blk].status != SNF_BLK_BAD)) { + //find replace block. + if (chip->bbt.node[blk].status != SNF_BLK_USED) { + SNF_Print2("block:", "replace blk:", __func__, block, blk); + chip->bbt.node[blk].status = SNF_BLK_USED; + } + } else { +retry: + //find a new replace block. + ret = SpiNandFindAReplaceBlock(chip, &blk); + if (ret != SNF_OK) { + SNF_PrintString("SpiNandFindAReplaceBlock failed, no replace block.\n", __func__); + goto exit; + } + + SNF_Print2("block:","find a new replace blk:", __func__, block, blk); + chip->bbt.node[block].replace = blk; + bbtUpdate = 1; + } + } + + if (offset_in_block == 0) { + ret = SpiNandEraseBlock(blk);//phy block + if (ret != SNF_OK) { + SNF_Print("SpiNandEraseBlock failed, mask bad block and try to find a replace block, blk:", __func__, blk); + chip->bbt.node[blk].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbtUpdate = 1; + goto retry; + } + } + + ret = SpiNandBurnBlock(blk, offset_in_block, data, size);//phy block + if (ret != SNF_OK) { + if ((ret == -SNF_BAD_BLK) && (offset_in_block == 0)) { + SNF_Print("SpiNandWriteData failed, try to find replace block, blk:", __func__, blk); + chip->bbt.node[blk].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbtUpdate = 1; + goto retry; + } else { + SNF_Print("SpiNandWriteData failed, blk:", __func__, blk); + } + } + +exit: + if (bbtUpdate) + SpiNandUpdateBbt(); + + return ret; +} + +static int SpiNandCheckReplaceBlockValid(u32 block) +{ + snf_chip_info *chip = &g_snf; + + if ((block >= chip->AvailableBlks) && (block < chip->BbtBlkOffset)) { + return SNF_OK; + } + + return -SNF_ERR; +} + +static int SpiNandCheckPhysicalBadBlock(u32 blknum) +{ + int page = blknum * g_snf.PagePerBlk; + int bbm = g_snf.BBMType; + char spareBuf[MAX_SPARE_SIZE] = {0}; + int ret; + + ret = SpiNandReadPageSpare(page, spareBuf); + if (ret != SNF_OK) { + SNF_Print("SpiNandReadPageSpare page0 failed, ret:", __func__, ret); + goto exit; + } + + if (spareBuf[0] == 0xFF) { + if(bbm == 2) { + ret = SpiNandReadPageSpare(page+1, spareBuf); + if (ret != SNF_OK) { + SNF_Print("SpiNandReadPageSpare page1 failed, ret:", __func__, ret); + goto exit; + } + if (spareBuf[0] == 0xFF) { + //SNF_Print("good block:", __func__, blknum); + return SNF_OK; + } else { + SNF_Print("bad block:", __func__, blknum); + } + } + } + +exit: + SNF_Print("bad block:", __func__, blknum); + + return -SNF_BAD_BLK; +} + +static int SpiNandFindAReplaceBlock(snf_chip_info *chip, u32 *block) +{ + int i; + + u32 replace_blk_start = chip->AvailableBlks; + u32 replace_blk_stop = chip->AvailableBlks + chip->ReplaceBlks; + + for (i=replace_blk_stop-1; i>=replace_blk_start; i--) { + if (chip->bbt.node[i].status == SNF_BLK_GOOD) { + *block = i; + chip->bbt.node[i].status = SNF_BLK_USED; + return SNF_OK; + } + } + + SNF_PrintString("there are no valid replace blocks.\n", __func__); + + return -SNF_ERR; +} + +static int SpiNandWriteBbt(u8 *buf , u32 size) +{ + snf_chip_info *chip = &g_snf; + int curr_block; + int i, ret; + int bbt_bad_blocks = 0; + int write_block_num = 0; + + for(i=0; iBbtBlkOffset + i; + + if(write_block_num >= 2) { + break; + } + + if(chip->bbt.node[curr_block].status == SNF_BLK_BAD) { + bbt_bad_blocks++; + continue; + } + + ret = SpiNandEraseBlock(curr_block); + if (ret != SNF_OK) { + SNF_Print2("erase block failed, block: ", "ret:", __func__, curr_block, ret); + if (ret == -SNF_BAD_BLK) { + chip->bbt.node[curr_block].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbt_bad_blocks++; + continue; + } + break; + } + + ret = SpiNandBurnBlock(curr_block, 0, buf, size); + if (ret != SNF_OK) { + SNF_Print2("burn block failed, block: ", "ret:", __func__, curr_block, ret); + if (ret == -SNF_BAD_BLK) { + chip->bbt.node[curr_block].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbt_bad_blocks++; + continue; + } + break; + } + + write_block_num++; + } + + if (bbt_bad_blocks) { + SNF_Print("%s, bbt has bad blcok: ", __func__, bbt_bad_blocks); + } + + return ret; +} + +static int SpiNandReadBbt(u8* buf, u32 size) +{ + snf_chip_info *chip = &g_snf; + u32 crc_size; + u32 checksum; + int curr_block; + int ret, i; + + crc_size = size - SNF_BBT_HEADER_SIZE - sizeof(chip->bbt.bbt_crc); + + for(i=0; iBbtBlkOffset + i; + ret = SpiNandReadPhysicalBlock(curr_block, 0, buf, size); + if (ret != SNF_OK) { + SNF_Print("SpiNandReadPhysicalBlock failed, block:", __func__, curr_block); + continue; + } + + if (memcmp(chip->bbt.header_mask, SNF_BBT_HEADER_MASK, sizeof(SNF_BBT_HEADER_MASK))) { + SNF_Print("Not fond BBT header, block:", __func__, curr_block); + ret = -SNF_ERR; + continue; + } + + checksum = xcrc32(buf + SNF_BBT_HEADER_SIZE, crc_size, 0xFFFFFFFF); + + if (chip->bbt.bbt_crc != checksum) { + SNF_Print("BBT information is abnormal, block:", __func__, curr_block); + ret = -SNF_ERR; + continue; + } + + break; + } + + return ret; +} + +static int SpiNandUpdateBbt(void) +{ + snf_chip_info *chip = &g_snf; + int ret = SNF_OK; + u32 bbt_size, crc_size; + u8 *pbuf; + + pbuf = (u8 *)&chip->bbt; + bbt_size = sizeof(snf_bbt); + crc_size = bbt_size - SNF_BBT_HEADER_SIZE - sizeof(chip->bbt.bbt_crc); + + chip->bbt.bbt_crc = xcrc32(pbuf + SNF_BBT_HEADER_SIZE, crc_size, 0xFFFFFFFF); + + ret = SpiNandWriteBbt(pbuf, bbt_size); + if (ret != SNF_OK) { + SNF_Print("write bbt failed, ret:", __func__, ret); + } + + return ret; +} + +static int SpiNandBbtInit(void) +{ + snf_chip_info *chip = &g_snf; + int ret = 0; + u32 bbt_size; + u8 *pbuf; + int i; + + pbuf = (u8 *)&chip->bbt; + bbt_size = sizeof(snf_bbt); + + ret = SpiNandReadBbt(pbuf, bbt_size); + if (ret != SNF_OK) { + memset(&chip->bbt, 0, bbt_size); + SNF_PrintString("Create a new BBT.\n", __func__); + for (i=0; iTotalBlk; i++) { + ret = SpiNandCheckPhysicalBadBlock(i); + if (ret == SNF_OK) { + chip->bbt.node[i].status = SNF_BLK_GOOD; + } else { + chip->bbt.node[i].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + } + chip->bbt.node[i].replace = 0; + } + + memcpy(chip->bbt.header_mask, SNF_BBT_HEADER_MASK, sizeof(SNF_BBT_HEADER_MASK)); + SpiNandUpdateBbt(); + ret = SNF_OK; + } + + return ret; +} + +static int SpiNandSetAttribute(snf_chip_info *chip) +{ + spi_nand_cfg *cfg = g_SnfChipCfgArray; + int fond = 0; + int i; + + if (!chip) { + SNF_PrintString("SpiNandSetAttribute: Invalid chip.\n", __func__); + return -SNF_ERR; + } + + for (i=0; iMID == cfg[i].MID) && (chip->DID0 == cfg[i].DID0)) { + fond = 1; + break; + } + } + + if (fond) { + memcpy(chip->Name, cfg[i].Name, MAX_SNF_BUF_SIZE); + chip->BBMType = cfg[i].BBMType; + chip->BytePerPage = cfg[i].BytePerPage; + chip->PagePerBlk = cfg[i].PagePerBlk; + chip->BytePerBlk = chip->BytePerPage * chip->PagePerBlk; + chip->TotalBlk = cfg[i].TotalBlk; + chip->SprSize = cfg[i].SprSize; + chip->FtlSprSize = 24; //reserved. + chip->Capacity = chip->BytePerBlk * chip->TotalBlk; + chip->ReplaceBlks = chip->TotalBlk * SNF_REPLACE_BLK_PERCENT / 100; + chip->AvailableBlks = chip->TotalBlk - chip->ReplaceBlks - SNF_BBT_BLK_COUNT; + chip->AvailableCapacity = chip->AvailableBlks * chip->BytePerBlk; + chip->BbtBlkOffset = chip->TotalBlk - SNF_BBT_BLK_COUNT; + if ((cfg[i].PsArrayIndex < 0) || (cfg[i].PsArrayIndex >= sizeof(g_SnfPsArray)/sizeof(g_SnfPsArray[0]))) { + chip->ps = NULL; + } else { + chip->ps = &g_SnfPsArray[cfg[i].PsArrayIndex]; + } + } else { + SNF_PrintString("Not find spi nand flash.\n", __func__); + return -SNF_ERR; + } + + if (chip->BytePerPage > MAX_PAGE_SIZE) { + SNF_Print("Invalid MAX_PAGE_SIZE:", __func__, MAX_PAGE_SIZE); + return -SNF_ERR; + } + if (chip->SprSize > MAX_SPARE_SIZE) { + SNF_Print("Invalid MAX_SPARE_SIZE:", __func__, MAX_SPARE_SIZE); + return -SNF_ERR; + } + if (chip->TotalBlk > MAX_BLK_SIZE) { + SNF_Print("Invalid MAX_BLK_SIZE:", __func__, MAX_BLK_SIZE); + return -SNF_ERR; + } + + return SNF_OK; +} + +int SpiInit(void) +{ + snf_chip_info *snf = &g_snf; + int ret; + + memset(snf, 0, sizeof(snf_chip_info)); + + /* spi controler init */ + SpiInitialize(); + + /* spi nand init */ + SpinandSoftreset(); + SpiNandWaitTillReady(); + SpiNandReadId(); + ret = SpiNandSetAttribute(snf); + if (ret != SNF_OK) { + SNF_PrintString("Not find spi nand flash.\n", __func__); + return ret; + } + + SpiNandWriteReg(SPI_NAND_LOCK_REG, SPI_NAND_PROT_UNLOCK_ALL); + SpiNandEnableECC(); + SpiNandDisableQuad(); + //SpiNandWriteEnable(); + ret = SpiNandBbtInit(); + if (ret != SNF_OK) + SNF_PrintString("SpiNandLoderBbt failed.\n", __func__); + + return ret; +} + +static void SpiLoadStepldr(void) +{ + UINT32 *buf = (UINT32*)STEPLDR_ENTRY; + UINT32 offset; + UINT32 size; + int ret; + int count = 3; + +retry: + if (ReadSysInfo()) { + SNF_PrintString("read sysinfo fail, try to load stepldr part A.\n", __func__); + offset = STEPLDRA_OFFSET; + size = STEPLDR_MAX_SIZE; + } else { + SysInfo *sysinfo = GetSysInfo(); + offset = sysinfo->stepldr_offset; + size = sysinfo->stepldr_size; + } + + PrintVariableValueHex("stepldr offset", offset); + + ret = SpiNandReadData(offset, buf, size); + if (ret != SNF_OK) { + if (--count) { + goto retry; + } else { + SNF_PrintString("SpiNandReadData failed.\n", __func__); + } + } + +#ifdef MMU_ENABLE + CP15_clean_dcache_for_dma(STEPLDR_ENTRY, STEPLDR_ENTRY + size); +#endif +} + +void bootFromSPI(void) +{ + void (*funPtr)(void); + + SpiLoadStepldr(); + + funPtr = (void (*)(void))STEPLDR_ENTRY; + funPtr(); +} + +/* offset is at least align to PAGE_SIZE */ +static int SpiNandBurn(void *buf, u32 offset, u32 size) +{ + snf_chip_info *chip = &g_snf; + u32 currblk, burn_size; + u32 bytePerBlk; + u32 offset_in_block; + int remain; + int ret = SNF_OK; + u8 *pbuf; + + pbuf = (u8 *)buf; + remain = size; + bytePerBlk = chip->BytePerBlk; + currblk = offset / bytePerBlk; + offset_in_block = offset % bytePerBlk; + + //area check valid. + if ((offset + size) > chip->AvailableCapacity) { + SNF_PrintString("burn out of boundry.\n", __func__); + return -SNF_ERR; + } + + //offset check align + if (offset % chip->BytePerPage) { + SNF_PrintString("offset is not align with page.\n", __func__); + return -SNF_ERR; + } + + while (remain > 0) { + burn_size = ((bytePerBlk - offset_in_block) >= remain) ? remain : (bytePerBlk - offset_in_block); + ret = SpiNandEraseWriteInBlock(currblk, offset_in_block, pbuf, burn_size);//logic block + if (ret != SNF_OK) { + SNF_Print("erase write block failed, block: ", __func__, currblk); + break; + } + + if (offset_in_block) + offset_in_block = 0; + + currblk++; + pbuf += burn_size; + remain -= burn_size; + if (remain < 0) { + ret = -SNF_ERR; + SNF_PrintString("Invalid remain.\n", __func__); + break; + } + } + + SpiNandWriteDisable(); + + return ret; +} + +int FlashBurn(void *buf, u32 offset, u32 size) +{ + return SpiNandBurn(buf, offset, size); +} + +int SpiReadSysInfo(SysInfo *info) +{ + u32 checksum; + u32 calc_checksum; + u8 data[MAX_PAGE_SIZE]; + int ret; + + ret = SpiNandReadData(SYSINFOA_OFFSET, data, sizeof(SysInfo)); + if (ret != SNF_OK) { + SNF_Print("SYSINFOA_OFFSET read failed, ret:", __func__, ret); + } + + checksum = *(u32*)((u32)data + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)data, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, data, sizeof(SysInfo)); + return 0; + } + + ret = SpiNandReadData(SYSINFOB_OFFSET, data, sizeof(SysInfo)); + if (ret != SNF_OK) { + SNF_Print("SYSINFOB_OFFSET read failed, ret:", __func__, ret); + } + + checksum = *(u32*)((u32)data + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)data, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, data, sizeof(SysInfo)); + return 0; + } + + return -1; +} + +void SpiWriteSysInfo(SysInfo *info) +{ + SpiNandBurn(info, SYSINFOB_OFFSET, sizeof(SysInfo)); + SpiNandBurn(info, SYSINFOA_OFFSET, sizeof(SysInfo)); +} +#endif diff --git a/A58-AMTLDR/Src/UartPrint.c b/A58-AMTLDR/Src/UartPrint.c new file mode 100644 index 00000000..8571ced9 --- /dev/null +++ b/A58-AMTLDR/Src/UartPrint.c @@ -0,0 +1,113 @@ +#include "amt630h.h" +#include "typedef.h" +#include "UartPrint.h" + +void InitUart(unsigned int baud) +{ + unsigned int Baud_Rate_Divisor; + unsigned int val; + + //select pad + val = rSYS_PAD_CTRL02; + val &= ~(0xF<<12); + val |=(0x1<<14)|(0x1<<12); + rSYS_PAD_CTRL02 = val; + + Baud_Rate_Divisor = ((CLK_24MHZ<<3) + baud)/(baud<<1); + rUART_IBRD = Baud_Rate_Divisor >> 6; + rUART_FBRD = Baud_Rate_Divisor & 0x3f; + + rUART_LCR_H = 0x70;//data len:8 bit,parity checking disable + rUART_IFLS = 0x19; + rUART_CR = 0x301; +} + +static char HexToChar(unsigned char value) +{ + value &= 0x0f; + + if ( value < 10 ) + return(0x30 + value); + else + return(0x60 + value - 9); +} + + +static void ShortToStr(unsigned short value, char *str) +{ + str[0] = HexToChar(value >> 12); + str[1] = HexToChar((value >> 8) & 0x0f); + str[2] = HexToChar((value >> 4) & 0x0f); + str[3] = HexToChar(value & 0x0f); + str[4] = 0; +} + +void IntToStr(unsigned int value, char *str) +{ + ShortToStr(value >> 16, str); + ShortToStr(value & 0xffff, str + 4); + str[8] = 0; +} + +void SendUartString(char * buf) +{ + int i = 0; + while ( buf[i] != 0) + { + while ( !(rUART_FR & 0x20) ) + { + rUART_DR = buf[i++]; + if ( buf[i] == 0 ) + return; + } + while ( (rUART_FR & 0x20)); + } +} + +void SendUartChar(char ch) +{ + while ( (rUART_FR & 0x20) ); + rUART_DR = ch; +} + + +void PrintVariableValueHex(char * variable, unsigned int value) +{ + char buf[10]; + + SendUartString(variable); + SendUartString(": 0x"); + IntToStr(value, buf); + SendUartString(buf); + SendUartString("\r\n"); +} + +void SendUartWord(unsigned int data) +{ + char buf[10]; + + SendUartString("0x"); + IntToStr(data, buf); + SendUartString(buf); + SendUartString("\r\n"); +} +void uart_puts(const UINT8*buf) +{ + INT32 i = 0; + while ( buf[i] != 0) + { + while( !(rUART_FR & 0x20) ) + { + if ( buf[i] == '\n' ) + { + rUART_DR = '\r'; + while( (rUART_FR & 0x20) ); + } + + rUART_DR = buf[i++]; + if ( buf[i] == 0 ) + return; + } + while( (rUART_FR & 0x20) ); + } +} diff --git a/A58-AMTLDR/Src/UartPrint.h b/A58-AMTLDR/Src/UartPrint.h new file mode 100644 index 00000000..6eb21d45 --- /dev/null +++ b/A58-AMTLDR/Src/UartPrint.h @@ -0,0 +1,12 @@ +#ifndef UART_PRINT_H__ +#define UART_PRINT_H__ + +void InitUart(unsigned int baud); +void SendUartString(char * buf); +void SendUartChar(char ch); +void PrintVariableValueHex(char * variable, unsigned int value); +void SendUartWord(unsigned int data); +void IntToStr(unsigned int value, char *str); + +#endif + diff --git a/A58-AMTLDR/Src/amt630h.h b/A58-AMTLDR/Src/amt630h.h new file mode 100644 index 00000000..b30ff64e --- /dev/null +++ b/A58-AMTLDR/Src/amt630h.h @@ -0,0 +1,478 @@ +/*********************************************************************** +Copyright (c)2020 Arkmicro Technologies Inc. All Rights Reserved +Filename: amt630h.h +Version : 1.0 +Date : 2020.04.08 +Author : Sim. Huang +History : +************************************************************************/ + +#ifndef _AMT630H_H_ +#define _AMT630H_H_ + +#define VECTOR_ENABLE 0 //if you want to change this value, please + //change the Assemble logic valuable VECTOR_ENABLE //in file Boot.s +#define CLK_24MHZ 24000000 +#define CLK_12MHZ 12000000 + + +#define SPINOR_BOOTER_SD 0 +#define BOOT_FROM_USB 1 +#define SPINAND_BOOTER_SD 2 +#define BOOT_FROM_SPI 3 + +#define SPI_NOR_FLASH 0 +#define SPI_NAND_FLASH 1 +#define EMMC_FLASH 2 +#define DEVICE_TYPE_SELECT SPI_NOR_FLASH + +/* register base address */ + +#define SDHC0_BASE 0x70400000 +#define USB_BASE 0x70300000//0x700C0000 +#define SSI1_BASE 0x60200000//0x48002000 +#define SSI0_BASE 0x60100000 +#define GPIO_BASE 0x60900000//0x40409000 +#define SYS_BASE 0x60000000//0x40408000 +#define TIMER_BASE 0x60a00000//0x40405000 +#define WDT_BASE 0x60c00000//0x40404000 +#define RTC_BASE 0x61000000//0x40406000 +#define UART0_BASE 0x60500000//0x4040B000 + +//uart +#define UART_BASE UART0_BASE +#define rUART_DR *((volatile unsigned int *)(UART_BASE + 0x00)) +#define rUART_RSR *((volatile unsigned int *)(UART_BASE + 0x04)) +#define rUART_FR *((volatile unsigned int *)(UART_BASE + 0x18)) +#define rUART_ILPR *((volatile unsigned int *)(UART_BASE + 0x20)) +#define rUART_IBRD *((volatile unsigned int *)(UART_BASE + 0x24)) +#define rUART_FBRD *((volatile unsigned int *)(UART_BASE + 0x28)) +#define rUART_LCR_H *((volatile unsigned int *)(UART_BASE + 0x2C)) +#define rUART_CR *((volatile unsigned int *)(UART_BASE + 0x30)) +#define rUART_IFLS *((volatile unsigned int *)(UART_BASE + 0x34)) +#define rUART_IMSC *((volatile unsigned int *)(UART_BASE + 0x38)) +#define rUART_RIS *((volatile unsigned int *)(UART_BASE + 0x3C)) +#define rUART_MIS *((volatile unsigned int *)(UART_BASE + 0x40)) +#define rUART_ICR *((volatile unsigned int *)(UART_BASE + 0x44)) +#define rUART_DMACR *((volatile unsigned int *)(UART_BASE + 0x48)) + + +/*************************************************************** + AHB slave interface registers definition +****************************************************************/ +/* AHB system */ +#define rSYS_BOOT_SAMPLE *((volatile unsigned int *)(SYS_BASE+0x0)) +#define rSYS_BUS_CLK_SEL *((volatile unsigned int *)(SYS_BASE+0x40)) +#define rSYS_PLLRFCK_CTL *((volatile unsigned int *)(SYS_BASE+0x44)) +#define rSYS_SDMMC_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x48)) +#define rSYS_VOU_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x4c)) +#define rSYS_PER_CLK_EN *((volatile unsigned int *)(SYS_BASE+0x50)) +#define rSYS_LCD_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x54)) +#define rSYS_SD_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x58)) +#define rSYS_SOFT_RST *((volatile unsigned int *)(SYS_BASE+0x5c)) +#define rSYS_SOFT1_RST *((volatile unsigned int *)(SYS_BASE+0x60)) +#define rSYS_SSP_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x64)) +#define rSYS_TIMER_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x68)) +#define rSYS_I2S_NCO_CFG *((volatile unsigned int *)(SYS_BASE+0x6c)) + +#define rSYS_BUS_CLK1_SEL *((volatile unsigned int *)(SYS_BASE+0x140)) +#define rSYS_PER_CLK1_EN *((volatile unsigned int *)(SYS_BASE+0x144)) +#define rSYS_I2S1_NCO_CFG *((volatile unsigned int *)(SYS_BASE+0x148)) + +#define rSYS_DDRCTL_CFG *((volatile unsigned int *)(SYS_BASE+0x70)) +#define rSYS_DDRCTL1_CFG *((volatile unsigned int *)(SYS_BASE+0x74)) +#define rSYS_DDRCTL2_CFG *((volatile unsigned int *)(SYS_BASE+0xb0)) +#define rSYS_DDRCTL3_CFG *((volatile unsigned int *)(SYS_BASE+0xb4)) +#define rSYS_PERCTL_CFG *((volatile unsigned int *)(SYS_BASE+0x78)) +#define rSYS_TIMER1_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x7c)) +#define rSYS_ANA_CFG *((volatile unsigned int *)(SYS_BASE+0x80)) +#define rSYS_ANA1_CFG *((volatile unsigned int *)(SYS_BASE+0x84)) +#define rSYS_CPUPLL_CFG *((volatile unsigned int *)(SYS_BASE+0x88)) +#define rSYS_SYSPLL_CFG *((volatile unsigned int *)(SYS_BASE+0x8c)) +#define rSYS_DDRPLL_CFG *((volatile unsigned int *)(SYS_BASE+0x90)) +#define rSYS_VPUPLL_CFG *((volatile unsigned int *)(SYS_BASE+0x94)) +#define rSYS_ANA2_CFG *((volatile unsigned int *)(SYS_BASE+0x98)) +#define rSYS_ANA3_CFG *((volatile unsigned int *)(SYS_BASE+0x9c)) +#define rSYS_ANA4_CFG *((volatile unsigned int *)(SYS_BASE+0xa0)) + + + +#define rSYS_PAD_CTRL00 *((volatile unsigned int *)(SYS_BASE+0x30*4)) +#define rSYS_PAD_CTRL01 *((volatile unsigned int *)(SYS_BASE+0x31*4)) +#define rSYS_PAD_CTRL02 *((volatile unsigned int *)(SYS_BASE+0x32*4)) +#define rSYS_PAD_CTRL03 *((volatile unsigned int *)(SYS_BASE+0x33*4)) +#define rSYS_PAD_CTRL04 *((volatile unsigned int *)(SYS_BASE+0x34*4)) +#define rSYS_PAD_CTRL05 *((volatile unsigned int *)(SYS_BASE+0xD4)) +#define rSYS_PAD_CTRL06 *((volatile unsigned int *)(SYS_BASE+0x36*4)) +#define rSYS_PAD_CTRL07 *((volatile unsigned int *)(SYS_BASE+0x37*4)) +#define rSYS_PAD_CTRL08 *((volatile unsigned int *)(SYS_BASE+0x120)) + + + +#define rSYS_IO_DRIVER00 *((volatile unsigned int *)(SYS_BASE+0x38*4)) +#define rSYS_IO_DRIVER01 *((volatile unsigned int *)(SYS_BASE+0x39*4)) +#define rSYS_IO_DRIVER02 *((volatile unsigned int *)(SYS_BASE+0x3A*4)) +#define rSYS_IO_DRIVER03 *((volatile unsigned int *)(SYS_BASE+0x3B*4)) +#define rSYS_IO_DRIVER04 *((volatile unsigned int *)(SYS_BASE+0x3C*4)) +#define rSYS_IO_DRIVER05 *((volatile unsigned int *)(SYS_BASE+0x3D*4)) +#define rSYS_IO_DRIVER06 *((volatile unsigned int *)(SYS_BASE+0x3E*4)) +#define rSYS_IO_DRIVER07 *((volatile unsigned int *)(SYS_BASE+0x3F*4)) + +#define rSYS_IO_UP00 *((volatile unsigned int *)(SYS_BASE+0x40*4)) +#define rSYS_IO_UP01 *((volatile unsigned int *)(SYS_BASE+0x41*4)) +#define rSYS_IO_UP02 *((volatile unsigned int *)(SYS_BASE+0x42*4)) +#define rSYS_IO_UP03 *((volatile unsigned int *)(SYS_BASE+0x43*4)) +#define rSYS_IO_UP04 *((volatile unsigned int *)(SYS_BASE+0x44*4)) +#define rSYS_IO_UP05 *((volatile unsigned int *)(SYS_BASE+0x45*4)) +#define rSYS_IO_UP06 *((volatile unsigned int *)(SYS_BASE+0x46*4)) +#define rSYS_IO_UP07 *((volatile unsigned int *)(SYS_BASE+0x47*4)) + +/* Timer */ +#define rTIMER0_LOAD_COUNT (*(volatile unsigned int *)(TIMER_BASE + 0x00)) +#define rTIMER0_CURRENT_VALUE (*(volatile unsigned int *)(TIMER_BASE + 0x04)) +#define rTIMER0_CONTROL (*(volatile unsigned int *)(TIMER_BASE + 0x08)) +#define rTIMER0_EOI (*(volatile unsigned int *)(TIMER_BASE + 0x0C)) +#define rTIMER0_INT_STATUS (*(volatile unsigned int *)(TIMER_BASE + 0x10)) + +/* WDT */ +#define rWDT_CR (*(volatile unsigned int *)(WDT_BASE + 0x00)) +#define rWDT_PSR (*(volatile unsigned int *)(WDT_BASE + 0x04)) +#define rWDT_LDR (*(volatile unsigned int *)(WDT_BASE + 0x08)) +#define rWDT_VLR (*(volatile unsigned int *)(WDT_BASE + 0x0C)) +#define rWDT_ISR (*(volatile unsigned int *)(WDT_BASE + 0x10)) +#define rWDT_RCR (*(volatile unsigned int *)(WDT_BASE + 0x14)) +#define rWDT_TMR (*(volatile unsigned int *)(WDT_BASE + 0x18)) +#define rWDT_TCR (*(volatile unsigned int *)(WDT_BASE + 0x1C)) + +/* RTC */ +#define rRTC_CTL (*(volatile unsigned int *)(RTC_BASE + 0x00)) /*control register*/ +#define rRTC_ANAWEN (*(volatile unsigned int *)(RTC_BASE + 0x04)) /*analog block write enable register*/ +#define rRTC_ANACTL (*(volatile unsigned int *)(RTC_BASE + 0x08)) /*analog block control register*/ +#define rRTC_IM (*(volatile unsigned int *)(RTC_BASE + 0x0C)) /*interrupt mode register*/ +#define rRTC_STA (*(volatile unsigned int *)(RTC_BASE + 0x10)) /*rtc status register*/ +#define rRTC_ALMDAT (*(volatile unsigned int *)(RTC_BASE + 0x14)) /*alarm data register*/ +#define rRTC_DONT (*(volatile unsigned int *)(RTC_BASE + 0x18)) /*delay on timer register*/ +#define rRTC_RAM (*(volatile unsigned int *)(RTC_BASE + 0x1C)) /*ram bit register*/ +#define rRTC_CNTL (*(volatile unsigned int *)(RTC_BASE + 0x20)) /*rtc counter register*/ +#define rRTC_CNTH (*(volatile unsigned int *)(RTC_BASE + 0x24)) /*rtc sec counter register*/ + +/* UART0 */ +#define rUART0_DR (*(volatile unsigned int *)(UART0_BASE + 0x00)) +#define rUART0_RSR (*(volatile unsigned int *)(UART0_BASE + 0x04)) +#define rUART0_FR (*(volatile unsigned int *)(UART0_BASE + 0x18)) +#define rUART0_ILPR (*(volatile unsigned int *)(UART0_BASE + 0x20)) +#define rUART0_IBRD (*(volatile unsigned int *)(UART0_BASE + 0x24)) +#define rUART0_FBRD (*(volatile unsigned int *)(UART0_BASE + 0x28)) +#define rUART0_LCR_H (*(volatile unsigned int *)(UART0_BASE + 0x2C)) +#define rUART0_CR (*(volatile unsigned int *)(UART0_BASE + 0x30)) +#define rUART0_IFLS (*(volatile unsigned int *)(UART0_BASE + 0x34)) +#define rUART0_IMSC (*(volatile unsigned int *)(UART0_BASE + 0x38)) +#define rUART0_RIS (*(volatile unsigned int *)(UART0_BASE + 0x3C)) +#define rUART0_MIS (*(volatile unsigned int *)(UART0_BASE + 0x40)) +#define rUART0_ICR (*(volatile unsigned int *)(UART0_BASE + 0x44)) +#define rUART0_DMACR (*(volatile unsigned int *)(UART0_BASE + 0x48)) + + +/* SSI */ +#define rSPI_CONTROLREG (*(volatile unsigned int *)(SSI1_BASE + 0x08)) +#define rSPI_CONFIGREG (*(volatile unsigned int *)(SSI1_BASE + 0x0C)) +#define rSPI_INTREG (*(volatile unsigned int *)(SSI1_BASE + 0x10)) +#define rSPI_DMAREG (*(volatile unsigned int *)(SSI1_BASE + 0x14)) +#define rSPI_STATUSREG (*(volatile unsigned int *)(SSI1_BASE + 0x18)) +#define rSPI_PERIODREG (*(volatile unsigned int *)(SSI1_BASE + 0x1C)) +#define rSPI_TESTREG (*(volatile unsigned int *)(SSI1_BASE + 0x20)) +#define rSPI_MSGREG (*(volatile unsigned int *)(SSI1_BASE + 0x40)) +#define rSPI_RXDATA (*(volatile unsigned int *)(SSI1_BASE + 0x50)) +#define rSPI_TXDATA (*(volatile unsigned int *)(SSI1_BASE + 0x460)) +#define rSPI_TXFIFO (SSI_BASE + 0x460) +#define rSPI_RXFIFO (SSI_BASE + 0x50) + +/* SSI0 */ +#define rSPI_CTLR0 (*(volatile unsigned int *)(SSI0_BASE + 0x00)) +#define rSPI_CTLR1 (*(volatile unsigned int *)(SSI0_BASE + 0x04)) +#define rSPI_SSIENR (*(volatile unsigned int *)(SSI0_BASE + 0x08)) +#define rSPI_MWCR (*(volatile unsigned int *)(SSI0_BASE + 0x0c)) +#define rSPI_SER (*(volatile unsigned int *)(SSI0_BASE + 0x10)) +#define rSPI_BAUDR (*(volatile unsigned int *)(SSI0_BASE + 0x14)) +#define rSPI_TXFTLR (*(volatile unsigned int *)(SSI0_BASE + 0x18)) +#define rSPI_RXFTLR (*(volatile unsigned int *)(SSI0_BASE + 0x1C)) +#define rSPI_TXFLR (*(volatile unsigned int *)(SSI0_BASE + 0x20)) +#define rSPI_RXFLR (*(volatile unsigned int *)(SSI0_BASE + 0x24)) +#define rSPI_SR (*(volatile unsigned int *)(SSI0_BASE + 0x28)) +#define rSPI_IMR (*(volatile unsigned int *)(SSI0_BASE + 0x2C)) +#define rSPI_ISR (*(volatile unsigned int *)(SSI0_BASE + 0x30)) +#define rSPI_RISR (*(volatile unsigned int *)(SSI0_BASE + 0x34)) +#define rSPI_TXOICR (*(volatile unsigned int *)(SSI0_BASE + 0x38)) +#define rSPI_RXOICR (*(volatile unsigned int *)(SSI0_BASE + 0x3C)) +#define rSPI_RXUICR (*(volatile unsigned int *)(SSI0_BASE + 0x40)) +#define rSPI_MSTICR (*(volatile unsigned int *)(SSI0_BASE + 0x44)) +#define rSPI_ICR (*(volatile unsigned int *)(SSI0_BASE + 0x48)) +#define rSPI_DMACR (*(volatile unsigned int *)(SSI0_BASE + 0x4C)) +#define rSPI_DMATDLR (*(volatile unsigned int *)(SSI0_BASE + 0x50)) +#define rSPI_DMARDLR (*(volatile unsigned int *)(SSI0_BASE + 0x54)) +#define rSPI_IDR (*(volatile unsigned int *)(SSI0_BASE + 0x58)) +#define rSPI_SSI_COMP_VERSION (*(volatile unsigned int *)(SSI0_BASE + 0x5C)) +#define rSPI_DR (*(volatile unsigned int *)(SSI0_BASE + 0x60)) +#define SPI_DR (SSI0_BASE + 0x60) + +#define rSPI_RX_SAMPLE_DLY (*(volatile unsigned int *)(SSI0_BASE + 0xf0)) +#define rSPI_SPI_CTRLR0 (*(volatile unsigned int *)(SSI0_BASE + 0xf4)) +//#define rSPI_RSVD_1 (*(volatile unsigned int *)(SSI0_BASE + 0xf8)) +//#define rSPI_RSVD_1 (*(volatile unsigned int *)(SSI0_BASE + 0xfC)) + + + +/* GPIO */ +#define rGPIO_PA_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x00)) +#define rGPIO_PA_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x04)) +#define rGPIO_PA_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x08)) +#define rGPIO_PA_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x0C)) +#define rGPIO_PA_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x10)) + +#define rGPIO_PB_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x20)) +#define rGPIO_PB_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x24)) +#define rGPIO_PB_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x28)) +#define rGPIO_PB_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x2C)) +#define rGPIO_PB_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x30)) + +#define rGPIO_PC_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x40)) +#define rGPIO_PC_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x44)) +#define rGPIO_PC_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x48)) +#define rGPIO_PC_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x4C)) +#define rGPIO_PC_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x50)) + +#define rGPIO_PD_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x60)) +#define rGPIO_PD_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x64)) +#define rGPIO_PD_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x68)) +#define rGPIO_PD_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x6C)) +#define rGPIO_PD_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x70)) + + +//DDR Reg + + +#define DDR2_BASE 0x71300000 + +#define MEM_STA_REG (*(volatile unsigned int *)(DDR2_BASE + 0x00)) +#define MEM_CMD_REG (*(volatile unsigned int *)(DDR2_BASE + 0x04)) +#define DIR_CMD_REG (*(volatile unsigned int *)(DDR2_BASE + 0x08)) +#define MEM_CFG_REG (*(volatile unsigned int *)(DDR2_BASE + 0x0C)) +#define REF_PRD_REG (*(volatile unsigned int *)(DDR2_BASE + 0x10)) +#define TCAS_REG (*(volatile unsigned int *)(DDR2_BASE + 0x14)) +#define TWL_REG (*(volatile unsigned int *)(DDR2_BASE + 0x18)) +#define TMRD_REG (*(volatile unsigned int *)(DDR2_BASE + 0x1C)) +#define TRAS_REG (*(volatile unsigned int *)(DDR2_BASE + 0x20)) +#define TRC_REG (*(volatile unsigned int *)(DDR2_BASE + 0x24)) +#define TRCD_REG (*(volatile unsigned int *)(DDR2_BASE + 0x28)) +#define TRFC_REG (*(volatile unsigned int *)(DDR2_BASE + 0x2C)) +#define TRP_REG (*(volatile unsigned int *)(DDR2_BASE + 0x30)) +#define TRRD_REG (*(volatile unsigned int *)(DDR2_BASE + 0x34)) +#define TWR_REG (*(volatile unsigned int *)(DDR2_BASE + 0x38)) +#define TWTR_REG (*(volatile unsigned int *)(DDR2_BASE + 0x3C)) +#define TXP_REG (*(volatile unsigned int *)(DDR2_BASE + 0x40)) +#define TXSR_REG (*(volatile unsigned int *)(DDR2_BASE + 0x44)) +#define TESR_REG (*(volatile unsigned int *)(DDR2_BASE + 0x48)) +#define MEM_CFG2_REG (*(volatile unsigned int *)(DDR2_BASE + 0x4C)) +#define MEM_CFG3_REG (*(volatile unsigned int *)(DDR2_BASE + 0x50)) +#define TFAW_REG (*(volatile unsigned int *)(DDR2_BASE + 0x54)) +#define READ_DELAY_REG (*(volatile unsigned int *)(DDR2_BASE + 0x58)) +#define CHIP_CFG_REG (*(volatile unsigned int *)(DDR2_BASE + 0x200)) +#define FEA_CTL_REG (*(volatile unsigned int *)(DDR2_BASE + 0x30C)) + + +//#define MMU_ENABLE + +#if DEVICE_TYPE_SELECT == SPI_NAND_FLASH +#define LOADER_OFFSET 0x0 +#define LOADER_MAX_SIZE 0x4000 + +#define STEPLDRA_OFFSET 0x20000 +#define STEPLDRB_OFFSET 0x40000 +#define STEPLDR_MAX_SIZE 0x14000 + +#define SYSINFOA_OFFSET 0x60000 +#define SYSINFOB_OFFSET 0x80000 +#define SYSINFO_MAX_SIZE 0x1000 + +#define IMAGE_OFFSET 0xa0000 +#define IMAGE_READ_SIZE 0x20000 + +#define LOADER_FILE_NAME "spildr.bin" +#define STEPLDR_FILE_NAME "stepldr.bin" +#define APP_FILE_NAME "update.bin" + +#elif DEVICE_TYPE_SELECT == SPI_NOR_FLASH +#define LOADER_OFFSET 0x0 +#define LOADER_MAX_SIZE 0x4000 + +#define STEPLDRA_OFFSET 0x4000 +#define STEPLDRB_OFFSET 0x20000 +#define STEPLDR_MAX_SIZE 0x14000 + +#define SYSINFOA_OFFSET 0x3c000 +#define SYSINFOB_OFFSET 0x3e000 +#define SYSINFO_MAX_SIZE 0x1000 + +#define IMAGE_OFFSET 0x40000 +#define IMAGE_MAX_SIZE 0xf00000 + +#define LOADER_FILE_NAME "spildr.bin" +#define STEPLDR_FILE_NAME "stepldr.bin" +#define APP_FILE_NAME "update.bin" + +#elif DEVICE_TYPE_SELECT == EMMC_FLASH +/********************************************************************************************** +emmc·ÖÇøÇé¿ö +(0-------0x200000-------0x400000------0x500000---0xA00000-----0x40000000-----0x80000000-----end +|------------|--------------|--------------|---------|-------------|----------- --|-----------| +| | | | | | | | +| EMMCLDR | stepldr | SYSINFO | log | app1 | app2 | ota | +|____________|______________|______________|_________|_____________|______________|___________| + +**********************************************************************************************/ +#define LOADER_OFFSET 0x0 +#define LOADERB_OFFSET 0x100000 +#define LOADER_MAX_SIZE 0x4000 + +#define STEPLDRA_OFFSET 0x200000 +#define STEPLDRB_OFFSET 0x300000 +#define STEPLDR_MAX_SIZE 0x14000 + +#define SYSINFOA_OFFSET 0x400000 +#define SYSINFOB_OFFSET 0x500000 +#define SYSINFO_MAX_SIZE 0x1000 + +#define IMAGE_OFFSET 0xA00000 +#define IMAGEB_OFFSET 0x40000000 +#define IMAGE_MAX_SIZE 0xf00000 +#define IMAGE_READ_SIZE 0x80000 + +#define LOADER_FILE_NAME "emmcldr.bin" +#define STEPLDR_FILE_NAME "stepldr.bin" +#define APP_FILE_NAME "update.bin" + +#endif + + +#define IMAGE_ENTRY 0x30c000 +#define STEPLDR_ENTRY 0x20f00000 +#define IMAGE_FLAG 0x424b5244 +#define CheckImageValid (*((volatile unsigned int *)(IMAGE_ENTRY+4)) == IMAGE_FLAG) + +typedef struct { + unsigned int magic; + unsigned int offset; + unsigned int size; +} UpFileInfo; + +typedef struct { + unsigned int magic; + unsigned int filenum; + unsigned int size; + unsigned int checksum; + unsigned int reserved1; + unsigned int reserved2; + UpFileInfo files[]; +} UpFileHeader; + +#define ENOENT 2 /* No such file or directory */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define ENOMEM 12 /* Out of memory */ +#define ENODEV 19 /* No such device */ +#define EINVAL 22 /* Invalid argument */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ + + +#define min(x,y) ((x) < (y) ? x : y) +#define max(x,y) ((x) > (y) ? x : y) + + +#define min3(x, y, z) min(min(x, y), z) +#define max3(x, y, z) max(max(x, y), z) + +#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +#define ALIGN(x,a) __ALIGN_MASK((x),(uintptr_t)(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + + +#define ARCH_DMA_MINALIGN 32//64 +#define USB_DMA_MINALIGN ARCH_DMA_MINALIGN +//typedef unsigned long uintptr_t; + +#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) +#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) +#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ + char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ + + (align - 1)]; \ + \ + type *name = (type *)ALIGN((uintptr_t)__##name, align) +#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) +#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) +#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ + ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + + +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} +/* +static void writeb(unsigned char val, void *ptr) +{ + *(volatile unsigned char*)ptr = val; +} + +static unsigned char readb(void *ptr) +{ + return *(volatile unsigned char*)ptr; +} + +static void writew(unsigned short val, void *ptr) +{ + *(volatile unsigned short*)ptr = val; +} + +static unsigned short readw(void *ptr) +{ + return *(volatile unsigned short*)ptr; +} +*/ +#define reg32_read(addr) *((volatile unsigned int *)(addr)) +#define reg32_write(addr,val) *((volatile unsigned int *)(addr)) = (val) +#define readl(a) reg32_read(a) +#define writel(v, a) reg32_write(a, v) + +#endif // _AMT630H_H_ diff --git a/A58-AMTLDR/Src/clockcfg.c b/A58-AMTLDR/Src/clockcfg.c new file mode 100644 index 00000000..9d3d9983 --- /dev/null +++ b/A58-AMTLDR/Src/clockcfg.c @@ -0,0 +1,124 @@ +#include "amt630h.h" + +static void delay(volatile int count ) +{ + while(count--); +} + +void SetCpuPLL(unsigned int freq_mhz) +{ + rSYS_CPUPLL_CFG &= ~(1<<14); + delay(10); + + rSYS_BUS_CLK1_SEL |= (1<< 0); + rSYS_CPUPLL_CFG = (freq_mhz/6)|(0x1C<<8)|(1<<14)|(1<<15); +} + +void SetSysPLL(unsigned int freq_mhz) +{ + rSYS_SYSPLL_CFG &= ~(1<<14); + delay(10); + + rSYS_BUS_CLK1_SEL |= (1<< 1); + rSYS_SYSPLL_CFG = (freq_mhz/6)|(0x1C<<8)|(1<<14)|(1<<15); +} + +void SetDDRPLL(unsigned int freq_mhz) +{ + rSYS_DDRPLL_CFG &= ~(1<<14); + delay(10); + + rSYS_BUS_CLK1_SEL |= (1<< 2); +// rSYS_DDRPLL_CFG = (freq_mhz/6)|(0x1C<<8)|(1<<14)|(1<<15); + rSYS_DDRPLL_CFG = (freq_mhz/6)|(0x1C<<8)|(1<<15); + +// rSYS_DDRPLL_CFG = (freq_mhz/12)|(0x0C<<8)|(1<<14)|(1<<15); + + delay(100); + rSYS_DDRPLL_CFG |= (1<< 14); +} + +void SetVPUPLL(unsigned int freq_mhz) +{ + rSYS_VPUPLL_CFG &= ~(1<<14); + delay(10); + + rSYS_BUS_CLK1_SEL |= (1<< 3); + rSYS_VPUPLL_CFG = (freq_mhz/6)|(0x1C<<8)|(1<<14)|(1<<15); +} + +void SetXclkAHBclkAPBclk(void) +{ + unsigned int val; + unsigned int hclk2x_div; + unsigned int apbclk_div; + unsigned int main_hclk_sel; + unsigned int main_hclk2x_sel; + unsigned int cpuclk_div; + unsigned int main_cpuclk_sel; + unsigned int ddrclk2x_div; + unsigned int main_ddrclk2x_sel; + + main_cpuclk_sel = 1; + cpuclk_div = 0; + main_hclk2x_sel = 1; + hclk2x_div = 0; + main_hclk_sel = 1; + apbclk_div = 1; + ddrclk2x_div = 0; + main_ddrclk2x_sel = 1; +#if 0 + val = rSYS_BUS_CLK_SEL; + val &=~(0xFFFFFFFF); + val |= (main_cpuclk_sel<< 0) |(cpuclk_div << 2) | (main_hclk2x_sel << 8) | (hclk2x_div << 7) | (main_hclk_sel << 11) | (apbclk_div << 16); + + rSYS_BUS_CLK_SEL = val; +#endif + + val = rSYS_BUS_CLK_SEL; + val &=~(0xFFFFFFFF); + val |= (main_cpuclk_sel<< 0) |(cpuclk_div << 2); + rSYS_BUS_CLK_SEL = val; + delay(2000); + + val = rSYS_BUS_CLK_SEL; + val |= (main_hclk2x_sel << 8) | (hclk2x_div << 10) | (main_hclk_sel << 15) | (apbclk_div << 16) | (main_ddrclk2x_sel << 24) | (ddrclk2x_div << 26); + rSYS_BUS_CLK_SEL = val; + delay(2000); + +} +void SetSpiclk(void) +{ + unsigned int val; + val = rSYS_SSP_CLK_CFG; + val &=~(0x1F); + val |= (1<< 4) |(4 << 0); + rSYS_SSP_CLK_CFG = val; +} + +void SetGpuclk(void) +{ + unsigned int val; + val = rSYS_TIMER1_CLK_CFG; + val &=~(0xfF); + val |= (0<< 3) |(1<< 0); //00:syspll_clk, 01:cpupll_clk + rSYS_TIMER1_CLK_CFG = val; +} + +void SetMfcclk(void) +{ + unsigned int val; + val = rSYS_TIMER_CLK_CFG; + val &=~(0xfF<<8); + val |= (0x00<< 11) |(0x1<< 8); + rSYS_TIMER_CLK_CFG = val; +} + + + +void SwitchTo24MHz(void) +{ + rSYS_BUS_CLK_SEL = 0; + + delay(10); +} diff --git a/A58-AMTLDR/Src/cp15.c b/A58-AMTLDR/Src/cp15.c new file mode 100644 index 00000000..384c685f --- /dev/null +++ b/A58-AMTLDR/Src/cp15.c @@ -0,0 +1,365 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Reg Reads Writes +//---------------------------------------------------------------------------- +// 0 ID code Unpredictable +// 0 cache type Unpredictable +// 0 TCM status Unpredictable +// 1 Control Control +// 2 Translation table base Translation table base +// 3 Domain access control Domain access control +// 4 (Reserved) +// 5 Data fault status Data fault status +// 5 Instruction fault status Instruction fault status +// 6 Fault address Fault address +// 7 cache operations cache operations +// 8 Unpredictable TLB operations +// 9 cache lockdown cache lockdown +// 9 TCM region TCM region +// 10 TLB lockdown TLB lockdown +// 11 (Reserved) +// 12 (Reserved) +// 13 FCSE PID FCSE PID +// 13 Context ID Context ID +// 14 (Reserved) +// 15 Test configuration Test configuration +//----------------------------------------------------------------------------- + + +/** \page cp15_f CP15 Functions. + * + * \section CP15 function Usage + * + * Methods to manage the Coprocessor 15. Coprocessor 15, or System Control + * Coprocessor CP15, is used to configure and control all the items in the + * list below: + *

    + *
  • ARM core + *
  • caches (Icache, Dcache and write buffer) + *
  • TCM + *
  • MMU + *
  • Other system options + *
+ * \section Usage + * + * -# Enable or disable D cache with Enable_D_cache and Disable_D_cache + * -# Enable or disable I cache with Enable_I_cache and Disable_I_cache + * + * Related files:\n + * \ref cp15.h\n + * \ref cp15.c.\n + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "cp15.h" +#include "UartPrint.h" + +#if defined(__ICCARM__) + #include +#endif +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Check Instruction cache + * \return 0 if I_cache disable, 1 if I_cache enable + */ +unsigned int CP15_IsIcacheEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & (1 << CP15_I_BIT)) != 0); +} + + +/** + * \brief Enable Instruction cache + */ +void CP15_EnableIcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is disabled + if ((control & (1 << CP15_I_BIT)) == 0) { + + control |= (1 << CP15_I_BIT); + CP15_WriteControl(control); + SendUartString("I cache enabled.\n\r"); + } + else { + + SendUartString("I cache is already enabled.\n\r"); + } +} + + +/** + * \brief Disable Instruction cache + */ +void CP15_DisableIcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is enabled + if ((control & (1 << CP15_I_BIT)) != 0) { + + control &= ~(1ul << CP15_I_BIT); + CP15_WriteControl(control); + SendUartString("I cache disabled.\n\r"); + } + else { + + SendUartString("I cache is already disabled.\n\r"); + } +} + +/** + * \brief Check MMU + * \return 0 if MMU disable, 1 if MMU enable + */ +unsigned int CP15_IsMMUEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & (1 << CP15_M_BIT)) != 0); +} + + +/** + * \brief Enable MMU + */ +void CP15_EnableMMU(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if MMU is disabled + if ((control & (1 << CP15_M_BIT)) == 0) { + + control |= (1 << CP15_M_BIT); + CP15_WriteControl(control); + SendUartString("MMU enabled.\n\r"); + } + else { + + SendUartString("MMU is already enabled.\n\r"); + } +} + + +/** + * \brief Disable MMU + */ +void CP15_DisableMMU(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if MMU is enabled + if ((control & (1 << CP15_M_BIT)) != 0) { + + control &= ~(1ul << CP15_M_BIT); + control &= ~(1ul << CP15_C_BIT); + CP15_WriteControl(control); + SendUartString("MMU disabled.\n\r"); + } + else { + + SendUartString("MMU is already disabled.\n\r"); + } +} + + +/** + * \brief Check D_cache + * \return 0 if D_cache disable, 1 if D_cache enable (with MMU of course) + */ +unsigned int CP15_IsDcacheEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0); +} + +/** + * \brief Enable Data cache + */ +void CP15_EnableDcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + if( !CP15_IsMMUEnabled() ) { + SendUartString("Do nothing: MMU not enabled\r\n"); + } + else { + // Check if cache is disabled + if ((control & (1 << CP15_C_BIT)) == 0) { + + control |= (1 << CP15_C_BIT); + CP15_WriteControl(control); + SendUartString("D cache enabled.\r\n"); + } + else { + + SendUartString("D cache is already enabled.\r\n"); + } + } +} + +/** + * \brief Disable Data cache + */ +void CP15_DisableDcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is enabled + if ((control & (1 << CP15_C_BIT)) != 0) { + + control &= ~(1ul << CP15_C_BIT); + CP15_WriteControl(control); + SendUartString("D cache disabled.\n\r"); + } + else { + + SendUartString("D cache is already disabled.\n\r"); + } +} + +/** + * \brief Invalidate TLB + */ +void CP15_InvalidateTLB(void) +{ + asm("MCR p15, 0, %0, c8, c3, 0" : : "r"(1)); + asm("DSB"); +} + + +/** + * \brief Clean Data cache + */ +void CP15_CacheClean(uint8_t CacheType) +{ + //assert(!CacheType); + CP15_SelectDCache(); + + CP15_CleanDCacheBySetWay(); + asm("DSB"); + +} + +/** + * \brief Invalidate D/Icache + */ +void CP15_CacheInvalidate(uint8_t CacheType) +{ + if(CacheType) + { + CP15_SelectICache(); + CP15_InvalidateIcacheInnerSharable(); + asm("DSB"); + asm("ISB"); + } + else + { + CP15_SelectDCache(); + CP15_InvalidateDcacheBySetWay(); + asm("DSB"); + asm("ISB"); + } + + +} + +/** + * \brief Flush(Clean and invalidate) Data cache + */ +void CP15_CacheFlush(uint8_t CacheType) +{ + //assert(!CacheType); + + CP15_SelectDCache(); + CP15_CleanInvalidateDCacheBySetWay(); + + asm("DSB"); + +} + +/** + * \brief Invalidate Data cache by address + */ +void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add) +{ + + CP15_SelectDCache(); + CP15_InvalidateDcacheByMva(S_Add, E_Add); +} + +/** + * \brief Clean Data cache by address + */ +void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add) +{ + + CP15_SelectDCache(); + CP15_CleanDCacheByMva(S_Add, E_Add); +} + +/** + * \brief Flush Data cache by address + */ + +void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add) +{ + + CP15_SelectDCache(); + CP15_CleanInvalidateDcacheByMva(S_Add, E_Add); +} diff --git a/A58-AMTLDR/Src/cp15.h b/A58-AMTLDR/Src/cp15.h new file mode 100644 index 00000000..3141ad6f --- /dev/null +++ b/A58-AMTLDR/Src/cp15.h @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _CP15_H +#define _CP15_H + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define CP15_L4_BIT 15 // Determines if the T bit is set when load instructions + // change the PC: + // 0 = loads to PC set the T bit + // 1 = loads to PC do not set T bit + +#define CP15_RR_BIT 14 // RR bit Replacement strategy for Icache and Dcache: + // 0 = Random replacement + // 1 = Round-robin replacement. + +#define CP15_V_BIT 13 // V bit Location of exception vectors: + // 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C + // 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C + +#define CP15_I_BIT 12 // I bit Icache enable/disable: + // 0 = Icache disabled + // 1 = Icache enabled + +#define CP15_R_BIT 9 // R bit ROM protection + +#define CP15_S_BIT 8 // S bit System protection + +#define CP15_B_BIT 7 // B bit Endianness: + // 0 = Little-endian operation + // 1 = Big-endian operation. + +#define CP15_C_BIT 2 // C bit Dcache enable/disable: + // 0 = cache disabled + // 1 = cache enabled + +#define CP15_A_BIT 1 // A bit Alignment fault enable/disable: + // 0 = Data address alignment fault checking disabled + // 1 = Data address alignment fault checking enabled + +#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled. + // 0 = disabled + // 1 = enabled + +/** No access Any access generates a domain fault. */ +#define CP15_DOMAIN_NO_ACCESS 0x00 +/** Client Accesses are checked against the access permission bits in the section or page descriptor. */ +#define CP15_DOMAIN_CLIENT_ACCESS 0x01 +/** Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated. */ +#define CP15_DOMAIN_MANAGER_ACCESS 0x03 + + +#define CP15_ICache 1 +#define CP15_DCache 0 + +#define CP15_PMCNTENSET_ENABLE 31 +#define CP15_PMCR_DIVIDER 3 +#define CP15_PMCR_RESET 2 +#define CP15_PMCR_ENABLE 0 + + +/*------------------------------------------------------------------------------ */ +/* Exported functions */ +/*------------------------------------------------------------------------------ */ +extern unsigned int CP15_ReadID(void); +extern unsigned int CP15_ReadControl(void); +extern void CP15_ExclusiveCache(void); +extern void CP15_NonExclusiveCache(void); +extern void CP15_ISB(void); +extern void CP15_DSB(void); +extern void CP15_DMB(void); +extern void CP15_SelectDCache(void); +extern void CP15_SelectICache(void); +extern void CP15_WriteControl(unsigned int value); +extern void CP15_WriteTTB(unsigned int value); +extern void CP15_WriteDomainAccessControl(unsigned int value); + +extern void CP15_InvalidateIcacheInnerSharable(void); +extern void CP15_InvalidateBTBinnerSharable(void); +extern void CP15_InvalidateIcache(void); +extern void CP15_InvalidateIcacheByMva(void); +extern void CP15_InvalidateBTB(void); +extern void CP15_InvalidateBTBbyMva(uint32_t VA_Addr); + +extern void CP15_InvalidateDcacheBySetWay(void); +extern void CP15_CleanDCacheBySetWay(void); +extern void CP15_CleanInvalidateDCacheBySetWay(void); + +extern void CP15_InvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr ); +extern void CP15_CleanDCacheByMva(uint32_t startAddr, uint32_t endAddr ); +extern void CP15_CleanInvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr ); + +extern void CP15_CleanDCacheUMva(void); +extern void CP15_InvalidateTranslationTable(void); + +extern void CP15_coherent_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_invalidate_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_clean_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_flush_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_flush_kern_dcache_for_dma (uint32_t startAddr, uint32_t size ); + + + +/*------------------------------------------------------------------------------ */ +/* Exported functions from CP15.c */ +/*------------------------------------------------------------------------------ */ + +/** MMU (Status/Enable/Disable) */ +extern unsigned int CP15_IsMMUEnabled(void); +extern void CP15_EnableMMU(void); +extern void CP15_DisableMMU(void); + +/** I cache (Status/Enable/Disable) */ +extern unsigned int CP15_IsIcacheEnabled(void); +extern void CP15_EnableIcache(void); +extern void CP15_DisableIcache(void); + +/** D cache (Status/Enable/Disable) */ +extern unsigned int CP15_IsDcacheEnabled(void); +extern void CP15_EnableDcache(void); +extern void CP15_DisableDcache(void); + + +extern void CP15_InvalidateTLB(void); + + +extern void CP15_CacheClean(uint8_t CacheType); +extern void CP15_CacheInvalidate(uint8_t CacheType); +extern void CP15_CacheFlush(uint8_t CacheType); +extern void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add); +extern void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add); +extern void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add); + +#endif // #ifndef _CP15_H + diff --git a/A58-AMTLDR/Src/cp15_asm_iar.s b/A58-AMTLDR/Src/cp15_asm_iar.s new file mode 100644 index 00000000..efcafc33 --- /dev/null +++ b/A58-AMTLDR/Src/cp15_asm_iar.s @@ -0,0 +1,728 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA, + * OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + + +/** + * \addtogroup cp15_cache Cache Operations + * + * \section Usage + * + * They are performed as MCR instructions and only operate on a level 1 cache associated with + * ATM v7 processor. + * The supported operations are: + *
    + *
  • Any of these operations can be applied to + * -# any data cache + * -# any unified cache. + *
  • Invalidate by MVA + * Performs an invalidate of a data or unified cache line based on the address it contains. + *
  • Invalidate by set/way + * Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
  • Clean by MVA + * Performs a clean of a data or unified cache line based on the address it contains. + *
  • Clean by set/way + * Performs a clean of a data or unified cache line based on its location in the cache hierarchy. + *
  • Clean and Invalidate by MVA + * Performs a clean and invalidate of a data or unified cache line based on the address it contains. + *
  • Clean and Invalidate by set/way + * Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
+ * + * Related files:\n + * \ref cp15.h\n + * \ref cp15_arm_iar.s \n + */ + + + MODULE ?cp15 + + //// Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(2) + SECTION CSTACK:DATA:NOROOT(3) + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#define __ASSEMBLY__ + + +/*---------------------------------------------------------------------------- + * Functions to access CP15 coprocessor register + *----------------------------------------------------------------------------*/ + PUBLIC CP15_ReadID + PUBLIC CP15_ExclusiveCache + PUBLIC CP15_NonExclusiveCache + PUBLIC CP15_ISB + PUBLIC CP15_DSB + PUBLIC CP15_DMB + PUBLIC CP15_SelectICache + PUBLIC CP15_SelectDCache + PUBLIC CP15_ReadControl + PUBLIC CP15_WriteControl + PUBLIC CP15_WriteDomainAccessControl + PUBLIC CP15_WriteTTB + PUBLIC CP15_InvalidateIcacheInnerSharable + PUBLIC CP15_InvalidateBTBinnerSharable + PUBLIC CP15_InvalidateIcache + PUBLIC CP15_InvalidateIcacheByMva + PUBLIC CP15_InvalidateBTB + PUBLIC CP15_InvalidateBTBbyMva + + PUBLIC CP15_InvalidateDcacheBySetWay + PUBLIC CP15_CleanDCacheBySetWay + PUBLIC CP15_CleanInvalidateDCacheBySetWay + + PUBLIC CP15_InvalidateDcacheByMva + PUBLIC CP15_CleanDCacheByMva + PUBLIC CP15_CleanDCacheUMva + PUBLIC CP15_CleanInvalidateDcacheByMva + PUBLIC CP15_InvalidateTranslationTable + + PUBLIC CP15_coherent_dcache_for_dma + PUBLIC CP15_invalidate_dcache_for_dma + PUBLIC CP15_clean_dcache_for_dma + PUBLIC CP15_flush_dcache_for_dma + PUBLIC CP15_flush_kern_dcache_for_dma + +/** + * \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers. + * Reading from this register returns the device ID, the cache type, or the TCM status + * depending on the value of Opcode_2 used. + */ + SECTION .CP15_ReadID:DATA:NOROOT(2) + PUBLIC CP15_ReadID +CP15_ReadID: + mov r0, #0 + mrc p15, 0, r0, c0, c0, 0 + bx lr + + +/** + * \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_ISB:DATA:NOROOT(2) + PUBLIC CP15_ISB +CP15_ISB: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 4 + nop + bx lr + +/** + * \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_DSB:DATA:NOROOT(2) + PUBLIC CP15_DSB +CP15_DSB: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + nop + bx lr + +/** + * \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_DMB:DATA:NOROOT(2) + PUBLIC CP15_DMB +CP15_DMB: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 5 + nop + bx lr + +/** + * \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_ExclusiveCache:DATA:NOROOT(2) + PUBLIC CP15_ExclusiveCache +CP15_ExclusiveCache: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR + orr r0, r0, #0x00000080 + mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR + nop + bx lr + + +/** + * \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_NonExclusiveCache:DATA:NOROOT(2) + PUBLIC CP15_NonExclusiveCache +CP15_NonExclusiveCache: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR + bic r0, r0, #0x00000080 + mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR + nop + bx lr + +/** + * \brief Register c1 accesses the CSSELR Register, to select ICache + */ + SECTION .CP15_SelectICache:DATA:NOROOT(2) + PUBLIC CP15_SelectICache +CP15_SelectICache: + mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR + orr r0, r0, #0x1 ; Change 0th bit to ICache + mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR + nop + bx lr + +/** + * \brief Register c1 accesses the CSSELR Register, to select DCache + */ + SECTION .CP15_SelectDCache:DATA:NOROOT(2) + PUBLIC CP15_SelectDCache +CP15_SelectDCache: + mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR + and r0, r0, #0xFFFFFFFE ; Change 0th bit to ICache + mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR + nop + bx lr + + + +/** + * \brief Register c1 is the Control Register for the ARM926EJ-S processor. + * This register specifies the configuration used to enable and disable the + * caches and MMU. It is recommended that you access this register using a + * read-modify-write sequence + */ + SECTION .CP15_ReadControl:CODE:NOROOT(2) + PUBLIC CP15_ReadControl +CP15_ReadControl: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 0 + bx lr + + SECTION .CP15_WriteControl:CODE:NOROOT(2) + PUBLIC CP15_WriteControl +CP15_WriteControl: + mcr p15, 0, r0, c1, c0, 0 + dsb + isb + bx lr + + SECTION .CP15_WriteDomainAccessControl:CODE:NOROOT(2) + PUBLIC CP15_WriteDomainAccessControl +CP15_WriteDomainAccessControl: + mcr p15, 0, r0, c3, c0, 0 + dsb + isb + bx lr + +/** + * \brief ARMv7A architecture supports two translation tables + * Configure translation table base (TTB) control register cp15,c2 + * to a value of all zeros, indicates we are using TTB register 0. + * write the address of our page table base to TTB register 0. + */ + SECTION .CP15_WriteTTB:CODE:NOROOT(2) + PUBLIC CP15_WriteTTB +CP15_WriteTTB: + mcr p15, 0, r0, c2, c0, 0 + dsb + isb + bx lr + +/** + * \brief Invalidate I cache predictor array inner Sharable + */ + SECTION .CP15_InvalidateIcacheInnerSharable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcacheInnerSharable +CP15_InvalidateIcacheInnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 0 + bx lr + +/** + * \brief Invalidate entire branch predictor array inner Sharable + */ + SECTION .CP15_InvalidateBTBinnerSharable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateBTBinnerSharable +CP15_InvalidateBTBinnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 + bx lr + +/** + * \brief Invalidate all instruction caches to PoU, also flushes branch target cache + */ + SECTION .CP15_InvalidateIcache:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcache +CP15_InvalidateIcache: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + isb + bx lr + +/** + * \brief Invalidate instruction caches by VA to PoU + */ + SECTION .CP15_InvalidateIcacheByMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcacheByMva +CP15_InvalidateIcacheByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 1 + bx lr + +/** + * \brief Invalidate entire branch predictor array + */ + SECTION .CP15_InvalidateBTB:CODE:NOROOT(2) + PUBLIC CP15_InvalidateBTB +CP15_InvalidateBTB: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 + dsb + isb + bx lr + +/** + * \brief Invalidate branch predictor array entry by MVA + */ + SECTION .CP15_InvalidateBTBbyMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateBTBbyMva +CP15_InvalidateBTBbyMva: + mcr p15, 0, r0, c7, c5, 7 + bx lr + +/*********************************************************** +* +* ===Data Cache related maintenance functions=== +* +**************************************************************/ + + +// ===Data Cache maintenance by SetWay === + +/** + * \brief Invalidate entire data cache by set/way + */ + SECTION .CP15_InvalidateDcacheBySetWay:CODE:NOROOT(2) + PUBLIC CP15_InvalidateDcacheBySetWay +CP15_InvalidateDcacheBySetWay: + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ inv_finish ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +inv_cache_level_loop + ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT inv_skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +inv_set_loop + MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +inv_way_loop + ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 ; Invalidate by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE inv_way_loop + SUBS r7, r7, #1 ; Decrement the Set number + BGE inv_set_loop +inv_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT inv_cache_level_loop +inv_finish + NOP + BX lr + +/** + * \brief Clean entire data cache by set/way + */ + SECTION .CP15_CleanDCacheBySetWay:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheBySetWay +CP15_CleanDCacheBySetWay: + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ clean_finish ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +clean_cache_level_loop + ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT clean_skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_set_loop + MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +clean_way_loop + ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c10, 2 ; Clean by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE clean_way_loop + SUBS r7, r7, #1 ; Decrement the Set number + BGE clean_set_loop +clean_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_cache_level_loop +clean_finish + NOP + BX lr + +/** + * \brief Clean and Invalidate entire data cache by set/way + */ + SECTION .CP15_CleanInvalidateDCacheBySetWay:CODE:NOROOT(2) + PUBLIC CP15_CleanInvalidateDCacheBySetWay +CP15_CleanInvalidateDCacheBySetWay: + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ clinv_finish ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +clinv_cache_level_loop + ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT clean_skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clinv_set_loop + MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +clinv_way_loop + ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c14, 2 ; Clean and Invalidate by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE clean_way_loop + SUBS r7, r7, #1 ; Decrement the Set number + BGE clean_set_loop +clinv_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_cache_level_loop +clinv_finish + NOP + BX lr + + + +// ===Data Cache maintenance by VA === + + +/** + * \brief Invalidate data cache by VA to Poc + */ + SECTION .CP15_InvalidateDcacheByMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateDcacheByMva +CP15_InvalidateDcacheByMva: + mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes + mov r3, r0 +inv_loop + mcr p15, 0, r0, c7, c6, 1 + add r3, r3, r2 + cmp r3, r1 + bls inv_loop + bx lr + + +/** + * \brief Clean data cache by MVA + */ + SECTION .CP15_CleanDCacheByMva:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheByMva +CP15_CleanDCacheByMva: + mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes + mov r3, r0 +clean_loop + mcr p15, 0, r0, c7, c10, 1 + add r3, r3, r2 + cmp r3, r1 + bls clean_loop + bx lr + +/** + * \brief Clean unified cache by MVA + */ + SECTION .CP15_CleanDCacheUMva:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheUMva +CP15_CleanDCacheUMva: + mov r0, #0 + mcr p15, 0, r0, c7, c11, 1 + bx lr + +/** + * \brief Clean and invalidate data cache by VA to PoC + */ + SECTION .CP15_CleanInvalidateDcacheByMva:CODE:NOROOT(2) + PUBLIC CP15_CleanInvalidateDcacheByMva +CP15_CleanInvalidateDcacheByMva: + mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes + mov r3, r0 +clinv_loop + mcr p15, 0, r0, c7, c14, 1 + add r3, r3, r2 + cmp r3, r1 + bls clinv_loop + bx lr + + +/** + * \brief Invalidate translation table + */ + SECTION .CP15_InvalidateTranslationTable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateTranslationTable +CP15_InvalidateTranslationTable: + mov r0, #0 + mcr p15, 0, r0, c8, c3, 0 + dsb + isb + mcr p15, 0, r0, c8, c7, 0 + dsb + isb + bx lr + +/** + * \brief flush translation table + */ + SECTION .CP15_FlushTranslationTable:CODE:NOROOT(2) + PUBLIC CP15_FlushTranslationTable +CP15_FlushTranslationTable: + mov r0, #0 + mcr p15, 0, r0, c8, c3, 0 + dsb + isb + bx lr + + +/** + * \brief Ensure that the I and D caches are coherent within specified + * region. This is typically used when code has been written to + * a memory region, and will be executed. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_coherent_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_coherent_dcache_for_dma +CP15_coherent_dcache_for_dma: +// dcache_line_size r2, r3 + + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r12, r0, r3 +loop1: + mcr p15, 0, r12, c7, c11, 1 // clean D line to the point of unification + add r12, r12, r2 + cmp r12, r1 + blo loop1 + dsb + +// .macro icache_line_size, reg, tmp + mrc p15, 0, r3, c0, c0, 1 // read ctr + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r12, r0, r3 +loop2: + mcr p15, 0, r12, c7, c5, 1 // invalidate I line + add r12, r12, r2 + cmp r12, r1 + blo loop2 + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 //invalidate BTB Inner Shareable + mcr p15, 0, r0, c7, c5, 6 // invalidate BTB + dsb + isb + bx lr + + +/** + * \brief Invalidate the data cache within the specified region; we will + * be performing a DMA operation in this region and we want to + * purge old data in the cache. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_invalidate_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_invalidate_dcache_for_dma +CP15_invalidate_dcache_for_dma: + +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + tst r0, r3 + bic r0, r0, r3 + + mcrne p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line + + tst r1, r3 + bic r1, r1, r3 + mcrne p15, 0, r1, c7, c14, 1 // clean & invalidate D / U line +loop3: + mcr p15, 0, r0, c7, c6, 1 // invalidate D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop3 + dsb + bx lr + + +/** + * \brief Clean the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_clean_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_clean_dcache_for_dma +CP15_clean_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r0, r0, r3 +loop4: + mcr p15, 0, r0, c7, c10, 1 // clean D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop4 + dsb + bx lr + + +/** + * \brief Flush the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_flush_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_flush_dcache_for_dma +CP15_flush_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + sub r3, r2, #1 + bic r0, r0, r3 +loop5: + mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop5 + dsb + bx lr + + +/** + * \brief CP15_flush_kern_dcache_for_dma + * Ensure that the data held in the page kaddr is written back to the page in question. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_flush_kern_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_flush_kern_dcache_for_dma +CP15_flush_kern_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 + + mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D line / unified line + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb + bx lr + END + diff --git a/A58-AMTLDR/Src/crc32.c b/A58-AMTLDR/Src/crc32.c new file mode 100644 index 00000000..de4c3b21 --- /dev/null +++ b/A58-AMTLDR/Src/crc32.c @@ -0,0 +1,82 @@ +#include +#include + +static const unsigned int crc32_table[] = +{ + 0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, + 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, + 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, + 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, + 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, + 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, + 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, + 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd, + 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, + 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, + 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, + 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d, + 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, + 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95, + 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, + 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, + 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, + 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072, + 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, + 0x018aeb13, 0x054bf6a4, 0x0808d07d, 0x0cc9cdca, + 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, + 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, + 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, + 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba, + 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, + 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692, + 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, + 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, + 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, + 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, + 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, + 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a, + 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, + 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, + 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, + 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53, + 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, + 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b, + 0x0315d626, 0x07d4cb91, 0x0a97ed48, 0x0e56f0ff, + 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, + 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, + 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b, + 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, + 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3, + 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, + 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, + 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, + 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3, + 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, + 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, + 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, + 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, + 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, + 0x029f3d35, 0x065e2082, 0x0b1d065b, 0x0fdc1bec, + 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, + 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, + 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, + 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, + 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, + 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, + 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, + 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c, + 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, + 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4 +}; + +unsigned int +xcrc32(const unsigned char *buf, int len, unsigned int init) +{ + unsigned int crc = init; + while (len--) + { + crc = (crc << 8) ^ crc32_table[((crc >> 24) ^ *buf) & 255]; + buf++; + } + return crc; +} diff --git a/A58-AMTLDR/Src/crc32.h b/A58-AMTLDR/Src/crc32.h new file mode 100644 index 00000000..2312956a --- /dev/null +++ b/A58-AMTLDR/Src/crc32.h @@ -0,0 +1,7 @@ +#ifndef _CRC32_H +#define _CRC32_H + +unsigned int +xcrc32(const unsigned char *buf, int len, unsigned int init); + +#endif \ No newline at end of file diff --git a/A58-AMTLDR/Src/exception.c b/A58-AMTLDR/Src/exception.c new file mode 100644 index 00000000..ba6b1791 --- /dev/null +++ b/A58-AMTLDR/Src/exception.c @@ -0,0 +1,38 @@ +#include "UartPrint.h" + +void undef_handler() +{ + SendUartString("\r\nUndef EXC"); + while(1); +} + +void prefetch_handler() +{ + SendUartString("\r\nPrefetch EXC"); + while(1); +} + +void data_abort_handler() +{ + SendUartString("\r\nData abort EXC"); + while(1); +} + +void irq_handler() +{ + SendUartString("\r\nIRQ EXC"); + while(1); +} + +void fiq_handler() +{ + SendUartString("\r\nFIQ EXC"); + while(1); +} + +void swi_handler() +{ + SendUartString("\r\nSWI EXC"); + while(1); +} + diff --git a/A58-AMTLDR/Src/fs/diskio.c b/A58-AMTLDR/Src/fs/diskio.c new file mode 100644 index 00000000..4f4d0265 --- /dev/null +++ b/A58-AMTLDR/Src/fs/diskio.c @@ -0,0 +1,243 @@ +/*-----------------------------------------------------------------------*/ +/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */ +/*-----------------------------------------------------------------------*/ +/* This is a stub disk I/O module that acts as front end of the existing */ +/* disk I/O modules and attach it to FatFs module with common interface. */ +/*-----------------------------------------------------------------------*/ + +#include "diskio.h" + +//#include + +//#include "sdfmd.h" +//#include +//#include + +//extern DWORD SDInitialize(void); +//extern DWORD WriteSector(PBYTE pData, DWORD dwStartSector, DWORD dwNumber); +//extern DWORD ReadSector(PBYTE pData, DWORD dwStartSector, DWORD dwNumber); +//extern void Delay(UINT32 count); + + + +extern void lcd_printstr(char* str); +#define printf lcd_printstr +/*-----------------------------------------------------------------------*/ +/* Correspondence between physical drive number and physical drive. */ +/* Note that Tiny-FatFs supports only single drive and always */ +/* accesses drive number 0. */ + +/*-----------------------------------------------------------------------*/ +/* Inidialize a Drive */ +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + DSTATUS stat; + int result; + + switch (drv) { + /*case ATA : + result = ATA_disk_initialize(); + // translate the reslut code here + + return stat;*/ + + case SDMMC : + result = MMC_disk_initialize(); + // translate the reslut code here + if(result < 0) + stat = STA_NOINIT; + else + stat = 0; + return stat; +#if 0 + case USB : + result = USB_disk_initialize(); + // translate the reslut code here + if(result < 0) + stat = STA_NOINIT; + else + stat = 0; + + return stat; +#endif + } + return STA_NOINIT; + +} + + + +/*-----------------------------------------------------------------------*/ +/* Return Disk Status */ + +DSTATUS disk_status ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + //drv = drv; + return 0; +#if 0 + + DSTATUS stat; + int result; + + + switch (drv) { + case ATA : + result = ATA_disk_status(); + // translate the reslut code here + + return stat; + + case SDMMC : + result = MMC_disk_status(); + // translate the reslut code here + + return stat; +#if 0 + case USB : + result = USB_disk_status(); + // translate the reslut code here + + return stat; +#endif + } + return STA_NOINIT; +#endif +} + + + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ + +DRESULT disk_read ( + BYTE drv, /* Physical drive nmuber (0..) */ + BYTE *buff, /* Data buffer to store read data */ + DWORD sector, /* Sector address (LBA) */ + BYTE count /* Number of sectors to read (1..255) */ +) +{ + DRESULT res; + int result; + + switch (drv) { + /*case ATA : + result = ATA_disk_read(buff, sector, count); + // translate the reslut code here + + return res;*/ + + case SDMMC : + result = MMC_disk_read(buff, sector, count); + // translate the reslut code here + if(result < 0) + res = RES_ERROR; + else + res = RES_OK; + return res; +#if 0 + case USB : + result = USB_disk_read(buff, sector, count); + // translate the reslut code here + if(result < 0) + res = RES_ERROR; + else + res = RES_OK; + return res; +#endif + } + + return RES_PARERR; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ + +#if _READONLY == 0 +DRESULT disk_write ( + BYTE drv, /* Physical drive nmuber (0..) */ + const BYTE *buff, /* Data to be written */ + DWORD sector, /* Sector address (LBA) */ + BYTE count /* Number of sectors to write (1..255) */ +) +{ + DRESULT res; + int result; + + switch (drv) { + case ATA : + result = ATA_disk_write(buff, sector, count); + // translate the reslut code here + + return res; + + case SDMMC : + result = MMC_disk_write(buff, sector, count); + // translate the reslut code here + + return res; +#if 0 + case USB : + result = USB_disk_write(buff, sector, count); + // translate the reslut code here + + return res; +#endif + } + return RES_PARERR; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0..) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + int result; + + switch (drv) { + /*case ATA : + // pre-process here + + result = ATA_disk_ioctl(ctrl, buff); + // post-process here + + return res;*/ + + case SDMMC : + // pre-process here + + result = MMC_disk_ioctl(ctrl, buff); + // post-process here + if(result < 0) + res = RES_PARERR; + else + res = RES_OK; + return res; + + /*case USB : + // pre-process here + + result = USB_disk_ioctl(ctrl, buff); + if(result < 0) + res = RES_PARERR; + else + res = RES_OK; + + return res;*/ + } + return RES_PARERR; +} + diff --git a/A58-AMTLDR/Src/fs/diskio.h b/A58-AMTLDR/Src/fs/diskio.h new file mode 100644 index 00000000..3b839b4e --- /dev/null +++ b/A58-AMTLDR/Src/fs/diskio.h @@ -0,0 +1,86 @@ +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file R0.06 (C)ChaN, 2007 +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO +#define _DISKIO + +#define _READONLY 1 /* 1: Read-only mode */ +#define _USE_IOCTL 1 + +#include "integer.h" + + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + +DSTATUS disk_initialize (BYTE); +DSTATUS disk_status (BYTE); +DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); +#if _READONLY == 0 +DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); +#endif +DRESULT disk_ioctl (BYTE, BYTE, void*); +void disk_timerproc (void); + + + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl() */ + +/* Generic command */ +#define CTRL_SYNC 0 /* Mandatory for read/write configuration */ +#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ +#define GET_SECTOR_SIZE 2 +#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ +#define CTRL_POWER 4 +#define CTRL_LOCK 5 +#define CTRL_EJECT 6 +/* MMC/SDC command */ +#define MMC_GET_TYPE 10 +#define MMC_GET_CSD 11 +#define MMC_GET_CID 12 +#define MMC_GET_OCR 13 +#define MMC_GET_SDSTAT 14 +/* ATA/CF command */ +#define ATA_GET_REV 20 +#define ATA_GET_MODEL 21 +#define ATA_GET_SN 22 + +#define SDMMC 0 +#define USB 1 +#define ATA 2 + +int MMC_disk_initialize(void); + +int MMC_disk_read(void *buff, DWORD sector, BYTE count); + +int MMC_disk_ioctl(BYTE ctrl, void *buff); + +int USB_disk_initialize(void); + +int USB_disk_read(void *buff, DWORD sector, BYTE count); + +int USB_disk_ioctl(BYTE ctrl, void *buff); + +#endif diff --git a/A58-AMTLDR/Src/fs/ff.c b/A58-AMTLDR/Src/fs/ff.c new file mode 100644 index 00000000..fbe8008b --- /dev/null +++ b/A58-AMTLDR/Src/fs/ff.c @@ -0,0 +1,2057 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.06 (C)ChaN, 2008 +/-----------------------------------------------------------------------------/ +/ The FatFs module is an experimenal project to implement FAT file system to +/ cheap microcontrollers. This is a free software and is opened for education, +/ research and development under license policy of following trems. +/ +/ Copyright (C) 2008, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is no warranty. +/ * You can use, modify and/or redistribute it for personal, non-profit or +/ commercial use without restriction under your responsibility. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) patition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algolithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a plysical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close +/ without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same +/ or following cluster. +/---------------------------------------------------------------------------*/ + +#include +#include "ff.h" /* FatFs declarations */ +#include "diskio.h" /* Include file for user provided disk functions */ + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ +DWORD get_fattime(void) +{ + return 0x12345678; +} + +static +FATFS *FatFs[_DRIVES]; /* Pointer to the file system objects (logical drives) */ +static +WORD fsid; /* File system mount ID */ + +FATFS g_fs; + +/*-----------------------------------------------------------------------*/ +/* Change window offset */ +/*-----------------------------------------------------------------------*/ + +static +BOOL move_window ( /* TRUE: successful, FALSE: failed */ + FATFS *fs, /* File system object */ + DWORD sector /* Sector number to make apperance in the fs->win[] */ +) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + + wsect = fs->winsect; + if (wsect != sector) { /* Changed current window */ +#if !_FS_READONLY + BYTE n; + if (fs->winflag) { /* Write back dirty window if needed */ + if (disk_write(fs->drive, fs->win, wsect, 1) != RES_OK) + return FALSE; + fs->winflag = 0; + if (wsect < (fs->fatbase + fs->sects_fat)) { /* In FAT area */ + for (n = fs->n_fats; n >= 2; n--) { /* Refrect the change to FAT copy */ + wsect += fs->sects_fat; + disk_write(fs->drive, fs->win, wsect, 1); + } + } + } +#endif + if (sector) { + if (disk_read(fs->drive, fs->win, sector, 1) != RES_OK) + return FALSE; + fs->winsect = sector; + } + } + return TRUE; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Clean-up cached data */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +FRESULT sync ( /* FR_OK: successful, FR_RW_ERROR: failed */ + FATFS *fs /* File system object */ +) +{ + fs->winflag = 1; + if (!move_window(fs, 0)) return FR_RW_ERROR; +#if _USE_FSINFO + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { + fs->winsect = 0; + memset(fs->win, 0, 512); + ST_WORD(&fs->win[BS_55AA], 0xAA55); + ST_DWORD(&fs->win[FSI_LeadSig], 0x41615252); + ST_DWORD(&fs->win[FSI_StrucSig], 0x61417272); + ST_DWORD(&fs->win[FSI_Free_Count], fs->free_clust); + ST_DWORD(&fs->win[FSI_Nxt_Free], fs->last_clust); + disk_write(fs->drive, fs->win, fs->fsi_sector, 1); + fs->fsi_flag = 0; + } +#endif + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drive, CTRL_SYNC, NULL) != RES_OK) + return FR_RW_ERROR; + return FR_OK; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Get a cluster status */ +/*-----------------------------------------------------------------------*/ + +static +DWORD get_cluster ( /* 0,>=2: successful, 1: failed */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to get the link information */ +) +{ + WORD wc, bc; + DWORD fatsect; + + + if (clust >= 2 && clust < fs->max_clust) { /* Is it a valid cluster#? */ + fatsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = (WORD)clust * 3 / 2; + if (!move_window(fs, fatsect + (bc / SS(fs)))) break; + wc = fs->win[bc & (SS(fs) - 1)]; bc++; + if (!move_window(fs, fatsect + (bc / SS(fs)))) break; + wc |= (WORD)fs->win[bc & (SS(fs) - 1)] << 8; + return (clust & 1) ? (wc >> 4) : (wc & 0xFFF); + + case FS_FAT16 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 2)))) break; + return LD_WORD(&fs->win[((WORD)clust * 2) & (SS(fs) - 1)]); + + case FS_FAT32 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 4)))) break; + return LD_DWORD(&fs->win[((WORD)clust * 4) & (SS(fs) - 1)]) & 0x0FFFFFFF; + } + } + + return 1; /* Out of cluster range, or an error occured */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change a cluster status */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +BOOL put_cluster ( /* TRUE: successful, FALSE: failed */ + FATFS *fs, /* File system object */ + DWORD clust, /* Cluster# to change (must be 2 to fs->max_clust-1) */ + DWORD val /* New value to mark the cluster */ +) +{ + WORD bc; + BYTE *p; + DWORD fatsect; + + + fatsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = (WORD)clust * 3 / 2; + if (!move_window(fs, fatsect + (bc / SS(fs)))) return FALSE; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clust & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->winflag = 1; + if (!move_window(fs, fatsect + (bc / SS(fs)))) return FALSE; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clust & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 2)))) return FALSE; + ST_WORD(&fs->win[((WORD)clust * 2) & (SS(fs) - 1)], (WORD)val); + break; + + case FS_FAT32 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 4)))) return FALSE; + ST_DWORD(&fs->win[((WORD)clust * 4) & (SS(fs) - 1)], val); + break; + + default : + return FALSE; + } + fs->winflag = 1; + return TRUE; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +BOOL remove_chain ( /* TRUE: successful, FALSE: failed */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to remove chain from */ +) +{ + DWORD nxt; + + + while (clust >= 2 && clust < fs->max_clust) { + nxt = get_cluster(fs, clust); + if (nxt == 1) return FALSE; + if (!put_cluster(fs, clust, 0)) return FALSE; + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust++; +#if _USE_FSINFO + fs->fsi_flag = 1; +#endif + } + clust = nxt; + } + return TRUE; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Stretch or create a cluster chain */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +DWORD create_chain ( /* 0: No free cluster, 1: Error, >=2: New cluster number */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to stretch, 0 means create new */ +) +{ + DWORD cstat, ncl, scl, mcl = fs->max_clust; + + + if (clust == 0) { /* Create new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (scl == 0 || scl >= mcl) scl = 1; + } + else { /* Stretch existing chain */ + cstat = get_cluster(fs, clust); /* Check the cluster status */ + if (cstat < 2) return 1; /* It is an invalid cluster */ + if (cstat < mcl) return cstat; /* It is already followed by next cluster */ + scl = clust; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= mcl) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free custer */ + } + cstat = get_cluster(fs, ncl); /* Get the cluster status */ + if (cstat == 0) break; /* Found a free cluster */ + if (cstat == 1) return 1; /* Any error occured */ + if (ncl == scl) return 0; /* No free custer */ + } + + if (!put_cluster(fs, ncl, 0x0FFFFFFF)) return 1; /* Mark the new cluster "in use" */ + if (clust != 0 && !put_cluster(fs, clust, ncl)) return 1; /* Link it to previous one if needed */ + + fs->last_clust = ncl; /* Update fsinfo */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; +#if _USE_FSINFO + fs->fsi_flag = 1; +#endif + } + + return ncl; /* Return new cluster number */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + +static +DWORD clust2sect ( /* !=0: sector number, 0: failed - invalid cluster# */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to be converted */ +) +{ + clust -= 2; + if (clust >= (fs->max_clust - 2)) return 0; /* Invalid cluster# */ + return clust * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Move directory pointer to next */ +/*-----------------------------------------------------------------------*/ + +static +BOOL next_dir_entry ( /* TRUE: successful, FALSE: could not move next */ + DIR *dj /* Pointer to directory object */ +) +{ + DWORD clust; + WORD idx; + + + idx = dj->index + 1; + if ((idx & ((SS(dj->fs) - 1) / 32)) == 0) { /* Table sector changed? */ + dj->sect++; /* Next sector */ + if (dj->clust == 0) { /* In static table */ + if (idx >= dj->fs->n_rootdir) return FALSE; /* Reached to end of table */ + } else { /* In dynamic table */ + if (((idx / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ + clust = get_cluster(dj->fs, dj->clust); /* Get next cluster */ + if (clust < 2 || clust >= dj->fs->max_clust) /* Reached to end of table */ + return FALSE; + dj->clust = clust; /* Initialize for new cluster */ + dj->sect = clust2sect(dj->fs, clust); + } + } + } + dj->index = idx; /* Lower several bits of dj->index indicates offset in dj->sect */ + return TRUE; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file status from directory entry */ +/*-----------------------------------------------------------------------*/ + +#if _FS_MINIMIZE <= 1 +static +void get_fileinfo ( /* No return code */ + FILINFO *finfo, /* Ptr to store the file information */ + const BYTE *dir /* Ptr to the directory entry */ +) +{ + BYTE n, c, a; + char *p; + + + p = &finfo->fname[0]; + a = _USE_NTFLAG ? dir[DIR_NTres] : 0; /* NT flag */ + for (n = 0; n < 8; n++) { /* Convert file name (body) */ + c = dir[n]; + if (c == ' ') break; + if (c == 0x05) c = 0xE5; + if (a & 0x08 && c >= 'A' && c <= 'Z') c += 0x20; + *p++ = c; + } + if (dir[8] != ' ') { /* Convert file name (extension) */ + *p++ = '.'; + for (n = 8; n < 11; n++) { + c = dir[n]; + if (c == ' ') break; + if (a & 0x10 && c >= 'A' && c <= 'Z') c += 0x20; + *p++ = c; + } + } + *p = '\0'; + + finfo->fattrib = dir[DIR_Attr]; /* Attribute */ + finfo->fsize = LD_DWORD(&dir[DIR_FileSize]); /* Size */ + finfo->fdate = LD_WORD(&dir[DIR_WrtDate]); /* Date */ + finfo->ftime = LD_WORD(&dir[DIR_WrtTime]); /* Time */ +} +#endif /* _FS_MINIMIZE <= 1 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a paragraph and create the name in format of directory entry */ +/*-----------------------------------------------------------------------*/ + +static +char make_dirfile ( /* 1: error - detected an invalid format, '\0'or'/': next character */ + const char **path, /* Pointer to the file path pointer */ + char *dirname /* Pointer to directory name buffer {Name(8), Ext(3), NT flag(1)} */ +) +{ + BYTE n, t, c, a, b; + + + memset(dirname, ' ', 8+3); /* Fill buffer with spaces */ + a = 0; b = 0x18; /* NT flag */ + n = 0; t = 8; + for (;;) { + c = *(*path)++; + if (c == '\0' || c == '/') { /* Reached to end of str or directory separator */ + if (n == 0) break; + dirname[11] = _USE_NTFLAG ? (a & b) : 0; + return c; + } + if (c <= ' ' || c == 0x7F) break; /* Reject invisible chars */ + if (c == '.') { + if (!(a & 1) && n >= 1 && n <= 8) { /* Enter extension part */ + n = 8; t = 11; continue; + } + break; + } + if (_USE_SJIS && + ((c >= 0x81 && c <= 0x9F) || /* Accept S-JIS code */ + (c >= 0xE0 && c <= 0xFC))) { + if (n == 0 && c == 0xE5) /* Change heading \xE5 to \x05 */ + c = 0x05; + a ^= 0x01; goto md_l2; + } + if (c == '"') break; /* Reject " */ + if (c <= ')') goto md_l1; /* Accept ! # $ % & ' ( ) */ + if (c <= ',') break; /* Reject * + , */ + if (c <= '9') goto md_l1; /* Accept - 0-9 */ + if (c <= '?') break; /* Reject : ; < = > ? */ + if (!(a & 1)) { /* These checks are not applied to S-JIS 2nd byte */ + if (c == '|') break; /* Reject | */ + if (c >= '[' && c <= ']') break;/* Reject [ \ ] */ + if (_USE_NTFLAG && c >= 'A' && c <= 'Z') + (t == 8) ? (b &= 0xF7) : (b &= 0xEF); + if (c >= 'a' && c <= 'z') { /* Convert to upper case */ + c -= 0x20; + if (_USE_NTFLAG) (t == 8) ? (a |= 0x08) : (a |= 0x10); + } + } + md_l1: + a &= 0xFE; + md_l2: + if (n >= t) break; + dirname[n++] = c; + } + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Trace a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT trace_path ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Pointer to directory object to return last directory */ + char *fn, /* Pointer to last segment name to return {file(8),ext(3),attr(1)} */ + const char *path, /* Full-path string to trace a file or directory */ + BYTE **dir /* Pointer to pointer to found entry to retutn */ +) +{ + DWORD clust; + char ds; + BYTE *dptr = NULL; + FATFS *fs = dj->fs; + + + /* Initialize directory object */ + clust = fs->dirbase; + if (fs->fs_type == FS_FAT32) { + dj->clust = dj->sclust = clust; + dj->sect = clust2sect(fs, clust); + } else { + dj->clust = dj->sclust = 0; + dj->sect = clust; + } + dj->index = 0; + + if (*path == '\0') { /* Null path means the root directory */ + *dir = NULL; return FR_OK; + } + + for (;;) { + ds = make_dirfile(&path, fn); /* Get a paragraph into fn[] */ + if (ds == 1) return FR_INVALID_NAME; + for (;;) { + if (!move_window(fs, dj->sect)) return FR_RW_ERROR; + dptr = &fs->win[(dj->index & ((SS(fs) - 1) / 32)) * 32]; /* Pointer to the directory entry */ + if (dptr[DIR_Name] == 0) /* Has it reached to end of dir? */ + return !ds ? FR_NO_FILE : FR_NO_PATH; + if (dptr[DIR_Name] != 0xE5 /* Matched? */ + && !(dptr[DIR_Attr] & AM_VOL) + && !memcmp(&dptr[DIR_Name], fn, 8+3) ) break; + if (!next_dir_entry(dj)) /* Next directory pointer */ + return !ds ? FR_NO_FILE : FR_NO_PATH; + } + if (!ds) { *dir = dptr; return FR_OK; } /* Matched with end of path */ + if (!(dptr[DIR_Attr] & AM_DIR)) return FR_NO_PATH; /* Cannot trace because it is a file */ + clust = ((DWORD)LD_WORD(&dptr[DIR_FstClusHI]) << 16) | LD_WORD(&dptr[DIR_FstClusLO]); /* Get cluster# of the directory */ + dj->clust = dj->sclust = clust; /* Restart scanning at the new directory */ + dj->sect = clust2sect(fs, clust); + dj->index = 2; + } +} + + + + +/*-----------------------------------------------------------------------*/ +/* Reserve a directory entry */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +FRESULT reserve_direntry ( /* FR_OK: successful, FR_DENIED: no free entry, FR_RW_ERROR: a disk error occured */ + DIR *dj, /* Target directory to create new entry */ + BYTE **dir /* Pointer to pointer to created entry to retutn */ +) +{ + DWORD clust, sector; + BYTE c, n, *dptr; + FATFS *fs = dj->fs; + + + /* Re-initialize directory object */ + clust = dj->sclust; + if (clust != 0) { /* Dyanmic directory table */ + dj->clust = clust; + dj->sect = clust2sect(fs, clust); + } else { /* Static directory table */ + dj->sect = fs->dirbase; + } + dj->index = 0; + + do { + if (!move_window(fs, dj->sect)) return FR_RW_ERROR; + dptr = &fs->win[(dj->index & ((SS(dj->fs) - 1) / 32)) * 32]; /* Pointer to the directory entry */ + c = dptr[DIR_Name]; + if (c == 0 || c == 0xE5) { /* Found an empty entry */ + *dir = dptr; return FR_OK; + } + } while (next_dir_entry(dj)); /* Next directory pointer */ + /* Reached to end of the directory table */ + + /* Abort when it is a static table or could not stretch dynamic table */ + if (clust == 0 || !(clust = create_chain(fs, dj->clust))) return FR_DENIED; + if (clust == 1 || !move_window(fs, 0)) return FR_RW_ERROR; + + /* Cleanup the expanded table */ + fs->winsect = sector = clust2sect(fs, clust); + memset(fs->win, 0, SS(fs)); + for (n = fs->csize; n; n--) { + if (disk_write(fs->drive, fs->win, sector, 1) != RES_OK) + return FR_RW_ERROR; + sector++; + } + fs->winflag = 1; + *dir = fs->win; + + return FR_OK; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Load boot record and check if it is an FAT boot record */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record or error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + if (disk_read(fs->drive, fs->win, sect, 1) != RES_OK) /* Load boot record */ + return 2; + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if (!memcmp(&fs->win[BS_FilSysType], "FAT", 3)) /* Check FAT signature */ + return 0; + if (!memcmp(&fs->win[BS_FilSysType32], "FAT32", 5) && !(fs->win[BPB_ExtFlags] & 0x80)) + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Make sure that the file system is valid */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT auto_mount ( /* FR_OK(0): successful, !=0: any error occured */ + const char **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ +) +{ + BYTE drv, fmt, *tbl; + DSTATUS stat; + DWORD bootsect, fatsize, totalsect, maxclust; + const char *p = *path; + FATFS *fs; + + + /* Get drive number from the path name */ + while (*p == ' ') p++; /* Strip leading spaces */ + drv = p[0] - '0'; /* Is there a drive number? */ + if (drv <= 9 && p[1] == ':') + p += 2; /* Found a drive number, get and strip it */ + else + drv = 0; /* No drive number is given, use drive number 0 as default */ + if (*p == '/') p++; /* Strip heading slash */ + *path = p; /* Return pointer to the path name */ + + /* Check if the drive number is valid or not */ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; /* Is the drive number valid? */ + *rfs = fs = FatFs[drv]; /* Returen pointer to the corresponding file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object registered? */ + + if (fs->fs_type) { /* If the logical drive has been mounted */ + stat = disk_status(fs->drive); + if (!(stat & STA_NOINIT)) { /* and physical drive is kept initialized (has not been changed), */ +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + return FR_OK; /* The file system object is valid */ + } + } + + /* The logical drive must be re-mounted. Following code attempts to mount the logical drive */ + + memset(fs, 0, sizeof(FATFS)); /* Clean-up the file system object */ + fs->drive = LD2PD(drv); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drive); /* Initialize low level disk I/O layer */ + if (stat & STA_NOINIT) /* Check if the drive is ready */ + return FR_NOT_READY; +#if S_MAX_SIZ > 512 /* Get disk sector size if needed */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > S_MAX_SIZ) + return FR_NO_FILESYSTEM; +#endif +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + /* Search FAT partition on the drive */ + fmt = check_fs(fs, bootsect = 0); /* Check sector 0 as an SFD format */ +#if 0 + if (fmt == 1) { /* Not an FAT boot record, it may be patitioned */ + /* Check a partition listed in top of the partition table */ + tbl = &fs->win[MBR_Table + LD2PT(drv) * 16]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bootsect); /* Check the partition */ + } + } +#else +// if (fmt == 1) + { + int i; + /* Check a first fat partition listed in partition table */ + for(i = 0; i < 4; i++) { + tbl = &fs->win[MBR_Table + i * 16]; /* Partition table */ + if (tbl[4] == 0x01 || tbl[4] == 0x04 || tbl[4] == 0x06 || tbl[4] == 0x0B || + tbl[4] == 0x0C || tbl[4] == 0x0E) { /* Is the FAT partition? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bootsect); /* Check the partition */ + break; + } + } + } +#endif + if (fmt || LD_WORD(&fs->win[BPB_BytsPerSec]) != SS(fs)) /* No valid FAT patition is found */ + return FR_NO_FILESYSTEM; + + /* Initialize the file system object */ + fatsize = LD_WORD(&fs->win[BPB_FATSz16]); /* Number of sectors per FAT */ + if (!fatsize) fatsize = LD_DWORD(&fs->win[BPB_FATSz32]); + fs->sects_fat = fatsize; + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + fatsize *= fs->n_fats; /* (Number of sectors in FAT area) */ + fs->fatbase = bootsect + LD_WORD(&fs->win[BPB_RsvdSecCnt]); /* FAT start sector (lba) */ + fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + fs->n_rootdir = LD_WORD(&fs->win[BPB_RootEntCnt]); /* Nmuber of root directory entries */ + totalsect = LD_WORD(&fs->win[BPB_TotSec16]); /* Number of sectors on the file system */ + if (!totalsect) totalsect = LD_DWORD(&fs->win[BPB_TotSec32]); + fs->max_clust = maxclust = (totalsect /* max_clust = Last cluster# + 1 */ + - LD_WORD(&fs->win[BPB_RsvdSecCnt]) - fatsize - fs->n_rootdir / (SS(fs)/32) + ) / fs->csize + 2; + + fmt = FS_FAT12; /* Determine the FAT sub type */ + if (maxclust >= 0xFF7) fmt = FS_FAT16; + if (maxclust >= 0xFFF7) fmt = FS_FAT32; + + if (fmt == FS_FAT32) + fs->dirbase = LD_DWORD(&fs->win[BPB_RootClus]); /* Root directory start cluster */ + else + fs->dirbase = fs->fatbase + fatsize; /* Root directory start sector (lba) */ + fs->database = fs->fatbase + fatsize + fs->n_rootdir / (SS(fs)/32); /* Data start sector (lba) */ + +#if !_FS_READONLY + /* Initialize allocation information */ + fs->free_clust = 0xFFFFFFFF; +#if _USE_FSINFO + /* Get fsinfo if needed */ + if (fmt == FS_FAT32) { + fs->fsi_sector = bootsect + LD_WORD(&fs->win[BPB_FSInfo]); + if (disk_read(fs->drive, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(&fs->win[BS_55AA]) == 0xAA55 && + LD_DWORD(&fs->win[FSI_LeadSig]) == 0x41615252 && + LD_DWORD(&fs->win[FSI_StrucSig]) == 0x61417272) { + fs->last_clust = LD_DWORD(&fs->win[FSI_Nxt_Free]); + fs->free_clust = LD_DWORD(&fs->win[FSI_Free_Count]); + } + } +#endif +#endif + + fs->fs_type = fmt; /* FAT syb-type */ + fs->id = ++fsid; /* File system mount ID */ + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/dir object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + const FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ +) +{ + if (!fs || !fs->fs_type || fs->id != id) + return FR_INVALID_OBJECT; + if (disk_status(fs->drive) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Locical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + BYTE drv, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ +) +{ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + + if (FatFs[drv]) FatFs[drv]->fs_type = 0; /* Clear old object */ + + FatFs[drv] = fs; /* Register and clear new object */ + if (fs) fs->fs_type = 0; + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL *fp, /* Pointer to the blank file object */ + const char *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + fp->fs = NULL; /* Clear file object */ +#if !_FS_READONLY + mode &= (FA_READ|FA_WRITE|FA_CREATE_ALWAYS|FA_OPEN_ALWAYS|FA_CREATE_NEW); + res = auto_mount(&path, &dj.fs, (BYTE)(mode & (FA_WRITE|FA_CREATE_ALWAYS|FA_OPEN_ALWAYS|FA_CREATE_NEW))); +#else + mode &= FA_READ; + res = auto_mount(&path, &dj.fs, 0); +#endif + if (res != FR_OK) return res; + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + +#if !_FS_READONLY + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS|FA_OPEN_ALWAYS|FA_CREATE_NEW)) { + DWORD ps, rs; + if (res != FR_OK) { /* No file, create new */ + if (res != FR_NO_FILE) return res; + res = reserve_direntry(&dj, &dir); + if (res != FR_OK) return res; + memset(dir, 0, 32); /* Initialize the new entry with open name */ + memcpy(&dir[DIR_Name], fn, 8+3); + dir[DIR_NTres] = fn[11]; + mode |= FA_CREATE_ALWAYS; + } + else { /* Any object is already existing */ + if (mode & FA_CREATE_NEW) /* Cannot create new */ + return FR_EXIST; + if (!dir || (dir[DIR_Attr] & (AM_RDO|AM_DIR))) /* Cannot overwrite it (R/O or DIR) */ + return FR_DENIED; + if (mode & FA_CREATE_ALWAYS) { /* Resize it to zero if needed */ + rs = ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); /* Get start cluster */ + ST_WORD(&dir[DIR_FstClusHI], 0); /* cluster = 0 */ + ST_WORD(&dir[DIR_FstClusLO], 0); + ST_DWORD(&dir[DIR_FileSize], 0); /* size = 0 */ + dj.fs->winflag = 1; + ps = dj.fs->winsect; /* Remove the cluster chain */ + if (!remove_chain(dj.fs, rs) || !move_window(dj.fs, ps)) + return FR_RW_ERROR; + dj.fs->last_clust = rs - 1; /* Reuse the cluster hole */ + } + } + if (mode & FA_CREATE_ALWAYS) { + dir[DIR_Attr] = 0; /* Reset attribute */ + ps = get_fattime(); + ST_DWORD(&dir[DIR_CrtTime], ps); /* Created time */ + dj.fs->winflag = 1; + mode |= FA__WRITTEN; /* Set file changed flag */ + } + } + /* Open an existing file */ + else { +#endif /* !_FS_READONLY */ + if (res != FR_OK) return res; /* Trace failed */ + if (!dir || (dir[DIR_Attr] & AM_DIR)) /* It is a directory */ + return FR_NO_FILE; +#if !_FS_READONLY + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + return FR_DENIED; + } + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dir; +#endif + fp->flag = mode; /* File access mode */ + fp->org_clust = /* File start cluster */ + ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); + fp->fsize = LD_DWORD(&dir[DIR_FileSize]); /* File size */ + fp->fptr = 0; fp->csect = 255; /* File pointer */ + fp->curr_sect = 0; + fp->fs = dj.fs; fp->id = dj.fs->id; /* Owner file system object of the file */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL *fp, /* Pointer to the file object */ + void *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clust, sect, remain; + UINT rcnt, cc; + BYTE *rbuff = buff; + + + *br = 0; + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; /* Check error flag */ + if (!(fp->flag & FA_READ)) return FR_DENIED; /* Check access mode */ + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data transferred */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + clust = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_cluster(fp->fs, fp->curr_clust); + if (clust < 2 || clust >= fp->fs->max_clust) goto fr_error; + fp->curr_clust = clust; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust) + fp->csect; /* Get current sector */ + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_read(fp->fs->drive, rbuff, sect, (BYTE)cc) != RES_OK) + goto fr_error; + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } + if (sect != fp->curr_sect) { /* Is window offset changed? */ +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write back file I/O buffer if needed */ + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + goto fr_error; + fp->flag &= (BYTE)~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drive, fp->buffer, sect, 1) != RES_OK) /* Fill file I/O buffer with file data */ + goto fr_error; + fp->curr_sect = sect; + } + fp->csect++; /* Next sector address in the cluster */ + } + rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector from file I/O buffer */ + if (rcnt > btr) rcnt = btr; + memcpy(rbuff, &fp->buffer[fp->fptr % SS(fp->fs)], rcnt); + } + + return FR_OK; + +fr_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL *fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clust, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + + + *bw = 0; + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; /* Check error flag */ + if (!(fp->flag & FA_WRITE)) return FR_DENIED; /* Check access mode */ + if (fp->fsize + btw < fp->fsize) return FR_OK; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data transferred */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clust = fp->org_clust; /* Follow from the origin */ + if (clust == 0) /* When there is no cluster chain, */ + fp->org_clust = clust = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ + clust = create_chain(fp->fs, fp->curr_clust); /* Trace or streach cluster chain */ + } + if (clust == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clust == 1 || clust >= fp->fs->max_clust) goto fw_error; + fp->curr_clust = clust; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust) + fp->csect; /* Get current sector */ + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_write(fp->fs->drive, wbuff, sect, (BYTE)cc) != RES_OK) + goto fw_error; + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } + if (sect != fp->curr_sect) { /* Is window offset changed? */ + if (fp->flag & FA__DIRTY) { /* Write back file I/O buffer if needed */ + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + goto fw_error; + fp->flag &= (BYTE)~FA__DIRTY; + } + if (fp->fptr < fp->fsize && /* Fill file I/O buffer with file data */ + disk_read(fp->fs->drive, fp->buffer, sect, 1) != RES_OK) + goto fw_error; + fp->curr_sect = sect; + } + fp->csect++; /* Next sector address in the cluster */ + } + wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; + memcpy(&fp->buffer[fp->fptr % SS(fp->fs)], wbuff, wcnt); + fp->flag |= FA__DIRTY; + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file changed flag */ + return FR_OK; + +fw_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the file object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ + /* Write back data buffer if needed */ + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + return FR_RW_ERROR; + fp->flag &= (BYTE)~FA__DIRTY; + } + /* Update the directory entry */ + if (!move_window(fp->fs, fp->dir_sect)) + return FR_RW_ERROR; + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(&dir[DIR_FileSize], fp->fsize); /* Update file size */ + ST_WORD(&dir[DIR_FstClusLO], fp->org_clust); /* Update start cluster */ + ST_WORD(&dir[DIR_FstClusHI], fp->org_clust >> 16); + tim = get_fattime(); /* Updated time */ + ST_DWORD(&dir[DIR_WrtTime], tim); + fp->flag &= (BYTE)~FA__WRITTEN; + res = sync(fp->fs); + } + } + return res; +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + + +#if !_FS_READONLY + res = f_sync(fp); +#else + res = validate(fp->fs, fp->id); +#endif + if (res == FR_OK) fp->fs = NULL; + return res; +} + + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL *fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + DWORD clust, csize, nsect, ifptr; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = 0; fp->csect = 255; + nsect = 0; + if (ofs > 0) { + csize = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / csize >= (ifptr - 1) / csize) {/* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(csize - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clust = fp->curr_clust; + } else { /* When seek to back cluster, */ + clust = fp->org_clust; /* start from the first cluster */ +#if !_FS_READONLY + if (clust == 0) { /* If no cluster chain, create a new chain */ + clust = create_chain(fp->fs, 0); + if (clust == 1) goto fk_error; + fp->org_clust = clust; + } +#endif + fp->curr_clust = clust; + } + if (clust != 0) { + while (ofs > csize) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clust = create_chain(fp->fs, clust); /* Force streached if in write mode */ + if (clust == 0) { /* When disk gets full, clip file size */ + ofs = csize; break; + } + } else +#endif + clust = get_cluster(fp->fs, clust); /* Follow cluster chain if not in write mode */ + if (clust < 2 || clust >= fp->fs->max_clust) goto fk_error; + fp->curr_clust = clust; + fp->fptr += csize; + ofs -= csize; + } + fp->fptr += ofs; + fp->csect = (BYTE)(ofs / SS(fp->fs)); /* Sector offset in the cluster */ + if (ofs & (SS(fp->fs) - 1)) { + nsect = clust2sect(fp->fs, clust) + fp->csect; /* Current sector */ + fp->csect++; + } + } + } + if (nsect && nsect != fp->curr_sect) { +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty buffer if needed */ + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + goto fk_error; + fp->flag &= (BYTE)~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drive, fp->buffer, nsect, 1) != RES_OK) + goto fk_error; + fp->curr_sect = nsect; + } + +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set changed flag if the file was extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + + return FR_OK; + +fk_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a directroy object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR *dj, /* Pointer to directory object to create */ + const char *path /* Pointer to the directory path */ +) +{ + FRESULT res; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj->fs, 0); + if (res == FR_OK) { + res = trace_path(dj, fn, path, &dir); /* Trace the directory path */ + if (res == FR_OK) { /* Trace completed */ + if (dir) { /* It is not the root dir */ + if (dir[DIR_Attr] & AM_DIR) { /* The entry is a directory */ + dj->clust = ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); + dj->sect = clust2sect(dj->fs, dj->clust); + dj->index = 2; + } else { /* The entry is not a directory */ + res = FR_NO_FILE; + } + } + dj->id = dj->fs->id; + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entry in Sequense */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR *dj, /* Pointer to the directory object */ + FILINFO *finfo /* Pointer to file information to return */ +) +{ + BYTE *dir, c, res; + + + res = validate(dj->fs, dj->id); /* Check validity of the object */ + if (res != FR_OK) return (FRESULT)res; + + finfo->fname[0] = 0; + while (dj->sect) { + if (!move_window(dj->fs, dj->sect)) + return FR_RW_ERROR; + dir = &dj->fs->win[(dj->index & ((SS(dj->fs) - 1) >> 5)) * 32]; /* pointer to the directory entry */ + c = dir[DIR_Name]; + if (c == 0) break; /* Has it reached to end of dir? */ + if (c != 0xE5 && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ + get_fileinfo(finfo, dir); + if (!next_dir_entry(dj)) dj->sect = 0; /* Next entry */ + if (finfo->fname[0]) break; /* Found valid entry */ + } + + return FR_OK; +} + + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const char *path, /* Pointer to the file path */ + FILINFO *finfo /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 0); + if (res == FR_OK) { + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) { /* Trace completed */ + if (dir) /* Found an object */ + get_fileinfo(finfo, dir); + else /* It is root dir */ + res = FR_INVALID_NAME; + } + } + + return res; +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; /* Check error flag */ + if (!(fp->flag & FA_WRITE)) return FR_DENIED; /* Check access mode */ + + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + if (!remove_chain(fp->fs, fp->org_clust)) goto ft_error; + fp->org_clust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_cluster(fp->fs, fp->curr_clust); + if (ncl < 2) goto ft_error; + if (ncl < fp->fs->max_clust) { + if (!put_cluster(fp->fs, fp->curr_clust, 0x0FFFFFFF)) goto ft_error; + if (!remove_chain(fp->fs, ncl)) goto ft_error; + } + } + } + + return FR_OK; + +ft_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const char *drv, /* Pointer to the logical drive number (root dir) */ + DWORD *nclust, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ +) +{ + FRESULT res; + DWORD n, clust, sect; + BYTE fat, f, *p; + + + /* Get drive number */ + res = auto_mount(&drv, fatfs, 0); + if (res != FR_OK) return res; + + /* If number of free cluster is valid, return it without cluster scan. */ + if ((*fatfs)->free_clust <= (*fatfs)->max_clust - 2) { + *nclust = (*fatfs)->free_clust; + return FR_OK; + } + + /* Get number of free clusters */ + fat = (*fatfs)->fs_type; + n = 0; + if (fat == FS_FAT12) { + clust = 2; + do { + if ((WORD)get_cluster(*fatfs, clust) == 0) n++; + } while (++clust < (*fatfs)->max_clust); + } else { + clust = (*fatfs)->max_clust; + sect = (*fatfs)->fatbase; + f = 0; p = 0; + do { + if (!f) { + if (!move_window(*fatfs, sect++)) return FR_RW_ERROR; + p = (*fatfs)->win; + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; f += 1; + } else { + if (LD_DWORD(p) == 0) n++; + p += 4; f += 2; + } + } while (--clust); + } + (*fatfs)->free_clust = n; +#if _USE_FSINFO + if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; +#endif + + *nclust = n; + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const char *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, *sdir; + DWORD dclust, dsect; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 1); + if (res != FR_OK) return res; + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res != FR_OK) return res; /* Trace failed */ + if (!dir) return FR_INVALID_NAME; /* It is the root directory */ + if (dir[DIR_Attr] & AM_RDO) return FR_DENIED; /* It is a R/O object */ + dsect = dj.fs->winsect; + dclust = ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); + + if (dir[DIR_Attr] & AM_DIR) { /* It is a sub-directory */ + dj.clust = dclust; /* Check if the sub-dir is empty or not */ + dj.sect = clust2sect(dj.fs, dclust); + dj.index = 2; + do { + if (!move_window(dj.fs, dj.sect)) return FR_RW_ERROR; + sdir = &dj.fs->win[(dj.index & ((SS(dj.fs) - 1) >> 5)) * 32]; + if (sdir[DIR_Name] == 0) break; + if (sdir[DIR_Name] != 0xE5 && !(sdir[DIR_Attr] & AM_VOL)) + return FR_DENIED; /* The directory is not empty */ + } while (next_dir_entry(&dj)); + } + + if (!move_window(dj.fs, dsect)) return FR_RW_ERROR; /* Mark the directory entry 'deleted' */ + dir[DIR_Name] = 0xE5; + dj.fs->winflag = 1; + if (!remove_chain(dj.fs, dclust)) return FR_RW_ERROR; /* Remove the cluster chain */ + + return sync(dj.fs); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const char *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, *fw, n; + char fn[8+3+1]; + DWORD sect, dsect, dclust, pclust, tim; + + + res = auto_mount(&path, &dj.fs, 1); + if (res != FR_OK) return res; + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) return FR_EXIST; /* Any file or directory is already existing */ + if (res != FR_NO_FILE) return res; + + res = reserve_direntry(&dj, &dir); /* Reserve a directory entry */ + if (res != FR_OK) return res; + sect = dj.fs->winsect; + dclust = create_chain(dj.fs, 0); /* Allocate a cluster for new directory table */ + if (dclust == 1) return FR_RW_ERROR; + dsect = clust2sect(dj.fs, dclust); + if (!dsect) return FR_DENIED; + if (!move_window(dj.fs, dsect)) return FR_RW_ERROR; + + fw = dj.fs->win; + memset(fw, 0, SS(dj.fs)); /* Clear the new directory table */ + for (n = 1; n < dj.fs->csize; n++) { + if (disk_write(dj.fs->drive, fw, ++dsect, 1) != RES_OK) + return FR_RW_ERROR; + } + memset(&fw[DIR_Name], ' ', 8+3); /* Create "." entry */ + fw[DIR_Name] = '.'; + fw[DIR_Attr] = AM_DIR; + tim = get_fattime(); + ST_DWORD(&fw[DIR_WrtTime], tim); + memcpy(&fw[32], &fw[0], 32); fw[33] = '.'; /* Create ".." entry */ + ST_WORD(&fw[ DIR_FstClusLO], dclust); + ST_WORD(&fw[ DIR_FstClusHI], dclust >> 16); + pclust = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pclust == dj.fs->dirbase) pclust = 0; + ST_WORD(&fw[32+DIR_FstClusLO], pclust); + ST_WORD(&fw[32+DIR_FstClusHI], pclust >> 16); + dj.fs->winflag = 1; + + if (!move_window(dj.fs, sect)) return FR_RW_ERROR; + memset(&dir[0], 0, 32); /* Initialize the new entry */ + memcpy(&dir[DIR_Name], fn, 8+3); /* Name */ + dir[DIR_NTres] = fn[11]; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(&dir[DIR_WrtTime], tim); /* Crated time */ + ST_WORD(&dir[DIR_FstClusLO], dclust); /* Table start cluster */ + ST_WORD(&dir[DIR_FstClusHI], dclust >> 16); + + return sync(dj.fs); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change File Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const char *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 1); + if (res == FR_OK) { + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) { /* Trace completed */ + if (!dir) { + res = FR_INVALID_NAME; /* Root directory */ + } else { + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + res = sync(dj.fs); + } + } + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const char *path, /* Pointer to the file/directory name */ + const FILINFO *finfo /* Pointer to the timestamp to be set */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 1); + if (res == FR_OK) { + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) { /* Trace completed */ + if (!dir) { + res = FR_INVALID_NAME; /* Root directory */ + } else { + ST_WORD(&dir[DIR_WrtTime], finfo->ftime); + ST_WORD(&dir[DIR_WrtDate], finfo->fdate); + res = sync(dj.fs); + } + } + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const char *path_old, /* Pointer to the old name */ + const char *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR dj; + DWORD sect_old; + BYTE *dir_old, *dir_new, direntry[32-11]; + char fn[8+3+1]; + + + res = auto_mount(&path_old, &dj.fs, 1); + if (res != FR_OK) return res; + + res = trace_path(&dj, fn, path_old, &dir_old); /* Check old object */ + if (res != FR_OK) return res; /* The old object is not found */ + if (!dir_old) return FR_NO_FILE; + sect_old = dj.fs->winsect; /* Save the object information */ + memcpy(direntry, &dir_old[DIR_Attr], 32-11); + + res = trace_path(&dj, fn, path_new, &dir_new); /* Check new object */ + if (res == FR_OK) return FR_EXIST; /* The new object name is already existing */ + if (res != FR_NO_FILE) return res; /* Is there no old name? */ + res = reserve_direntry(&dj, &dir_new); /* Reserve a directory entry */ + if (res != FR_OK) return res; + + memcpy(&dir_new[DIR_Attr], direntry, 32-11); /* Create new entry */ + memcpy(&dir_new[DIR_Name], fn, 8+3); + dir_new[DIR_NTres] = fn[11]; + dj.fs->winflag = 1; + + if (!move_window(dj.fs, sect_old)) return FR_RW_ERROR; /* Delete old entry */ + dir_old[DIR_Name] = 0xE5; + + return sync(dj.fs); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Multiple of 32 and <= 2048 */ +#define N_FATS 1 /* 1 or 2 */ +#define MAX_SECTOR 64000000UL /* Maximum partition size */ +#define MIN_SECTOR 2000UL /* Minimum partition size */ + + + +FRESULT f_mkfs ( + BYTE drv, /* Logical drive number */ + BYTE partition, /* Partitioning rule 0:FDISK, 1:SFD */ + WORD allocsize /* Allocation unit size [bytes] */ +) +{ + BYTE fmt, m, *tbl; + DWORD b_part, b_fat, b_dir, b_data; /* Area offset (LBA) */ + DWORD n_part, n_rsv, n_fat, n_dir; /* Area size */ + DWORD n_clust, n; + FATFS *fs; + DSTATUS stat; + + + /* Check validity of the parameters */ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + if (partition >= 2) return FR_MKFS_ABORTED; + for (n = 512; n <= 32768U && n != allocsize; n <<= 1); + if (n != allocsize) return FR_MKFS_ABORTED; + + /* Check mounted drive and clear work area */ + fs = FatFs[drv]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + drv = LD2PD(drv); + + /* Get disk statics */ + stat = disk_initialize(drv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_part) != RES_OK || n_part < MIN_SECTOR) + return FR_MKFS_ABORTED; + if (n_part > MAX_SECTOR) n_part = MAX_SECTOR; + b_part = (!partition) ? 63 : 0; /* Boot sector */ + n_part -= b_part; +#if S_MAX_SIZ > 512 /* Check disk sector size */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK + || SS(fs) > S_MAX_SIZ + || SS(fs) > allocsize) + return FR_MKFS_ABORTED; +#endif + allocsize /= SS(fs); /* Number of sectors per cluster */ + + /* Pre-compute number of clusters and FAT type */ + n_clust = n_part / allocsize; + fmt = FS_FAT12; + if (n_clust >= 0xFF5) fmt = FS_FAT16; + if (n_clust >= 0xFFF5) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + switch (fmt) { + case FS_FAT12: + n_fat = ((n_clust * 3 + 1) / 2 + 3 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + case FS_FAT16: + n_fat = ((n_clust * 2) + 4 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + default: + n_fat = ((n_clust * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 33 - partition; + n_dir = 0; + } + b_fat = b_part + n_rsv; /* FATs start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory start sector */ + b_data = b_dir + n_dir; /* Data start sector */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK) return FR_MKFS_ABORTED; + n = (b_data + n - 1) & ~(n - 1); + n_fat += (n - b_data) / N_FATS; + /* b_dir and b_data are no longer used below */ + + /* Determine number of cluster and final check of validity of the FAT type */ + n_clust = (n_part - n_rsv - n_fat * N_FATS - n_dir) / allocsize; + if ( (fmt == FS_FAT16 && n_clust < 0xFF5) + || (fmt == FS_FAT32 && n_clust < 0xFFF5)) + return FR_MKFS_ABORTED; + + /* Create partition table if needed */ + if (!partition) { + DWORD n_disk = b_part + n_part; + + tbl = &fs->win[MBR_Table]; + ST_DWORD(&tbl[0], 0x00010180); /* Partition start in CHS */ + if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */ + n_disk = n_disk / 63 / 255; + tbl[7] = (BYTE)n_disk; + tbl[6] = (BYTE)((n_disk >> 2) | 63); + } else { + ST_WORD(&tbl[6], 0xFFFF); + } + tbl[5] = 254; + if (fmt != FS_FAT32) /* System ID */ + tbl[4] = (n_part < 0x10000) ? 0x04 : 0x06; + else + tbl[4] = 0x0c; + ST_DWORD(&tbl[8], 63); /* Partition start in LBA */ + ST_DWORD(&tbl[12], n_part); /* Partition size in LBA */ + ST_WORD(&tbl[64], 0xAA55); /* Signature */ + if (disk_write(drv, fs->win, 0, 1) != RES_OK) + return FR_RW_ERROR; + } + + /* Create boot record */ + tbl = fs->win; /* Clear buffer */ + memset(tbl, 0, SS(fs)); + ST_DWORD(&tbl[BS_jmpBoot], 0x90FEEB); /* Boot code (jmp $, nop) */ + ST_WORD(&tbl[BPB_BytsPerSec], SS(fs)); /* Sector size */ + tbl[BPB_SecPerClus] = (BYTE)allocsize; /* Sectors per cluster */ + ST_WORD(&tbl[BPB_RsvdSecCnt], n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + ST_WORD(&tbl[BPB_RootEntCnt], SS(fs) / 32 * n_dir); /* Number of rootdir entries */ + if (n_part < 0x10000) { /* Number of total sectors */ + ST_WORD(&tbl[BPB_TotSec16], n_part); + } else { + ST_DWORD(&tbl[BPB_TotSec32], n_part); + } + tbl[BPB_Media] = 0xF8; /* Media descripter */ + ST_WORD(&tbl[BPB_SecPerTrk], 63); /* Number of sectors per track */ + ST_WORD(&tbl[BPB_NumHeads], 255); /* Number of heads */ + ST_DWORD(&tbl[BPB_HiddSec], b_part); /* Hidden sectors */ + n = get_fattime(); /* Use current time as a VSN */ + if (fmt != FS_FAT32) { + ST_DWORD(&tbl[BS_VolID], n); /* Volume serial number */ + ST_WORD(&tbl[BPB_FATSz16], n_fat); /* Number of secters per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + memcpy(&tbl[BS_VolLab], "NO NAME FAT ", 19); /* Volume lavel, FAT signature */ + } else { + ST_DWORD(&tbl[BS_VolID32], n); /* Volume serial number */ + ST_DWORD(&tbl[BPB_FATSz32], n_fat); /* Number of secters per FAT */ + ST_DWORD(&tbl[BPB_RootClus], 2); /* Root directory cluster (2) */ + ST_WORD(&tbl[BPB_FSInfo], 1); /* FSInfo record (bs+1) */ + ST_WORD(&tbl[BPB_BkBootSec], 6); /* Backup boot record (bs+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + memcpy(&tbl[BS_VolLab32], "NO NAME FAT32 ", 19); /* Volume lavel, FAT signature */ + } + ST_WORD(&tbl[BS_55AA], 0xAA55); /* Signature */ + if (disk_write(drv, tbl, b_part+0, 1) != RES_OK) + return FR_RW_ERROR; + if (fmt == FS_FAT32) + disk_write(drv, tbl, b_part+6, 1); + + /* Initialize FAT area */ + for (m = 0; m < N_FATS; m++) { + memset(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + if (fmt != FS_FAT32) { + n = (fmt == FS_FAT12) ? 0x00FFFFF8 : 0xFFFFFFF8; + ST_DWORD(&tbl[0], n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + ST_DWORD(&tbl[0], 0xFFFFFFF8); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(&tbl[4], 0xFFFFFFFF); + ST_DWORD(&tbl[8], 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ + } + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_RW_ERROR; + memset(tbl, 0, SS(fs)); /* Following FAT entries are filled by zero */ + for (n = 1; n < n_fat; n++) { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_RW_ERROR; + } + } + + /* Initialize Root directory */ + m = (BYTE)((fmt == FS_FAT32) ? allocsize : n_dir); + do { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_RW_ERROR; + } while (--m); + + /* Create FSInfo record if needed */ + if (fmt == FS_FAT32) { + ST_WORD(&tbl[BS_55AA], 0xAA55); + ST_DWORD(&tbl[FSI_LeadSig], 0x41615252); + ST_DWORD(&tbl[FSI_StrucSig], 0x61417272); + ST_DWORD(&tbl[FSI_Free_Count], n_clust - 1); + ST_DWORD(&tbl[FSI_Nxt_Free], 0xFFFFFFFF); + disk_write(drv, tbl, b_part+1, 1); + disk_write(drv, tbl, b_part+7, 1); + } + + return (disk_ioctl(drv, CTRL_SYNC, NULL) == RES_OK) ? FR_OK : FR_RW_ERROR; +} + +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC >= 1 +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ +char* fgets ( + char* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer */ + FIL* fil /* Pointer to the file object */ +) +{ + int i = 0; + char *p = buff; + UINT rc; + + + while (i < len - 1) { /* Read bytes until buffer gets filled */ + f_read(fil, p, 1, &rc); + if (rc != 1) break; /* Break when no data to read */ +#if _USE_STRFUNC >= 2 + if (*p == '\r') continue; /* Strip '\r' */ +#endif + i++; + if (*p++ == '\n') break; /* Break when reached end of line */ + } + *p = 0; + return i ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ +int fputc ( + int chr, /* A character to be output */ + FIL* fil /* Ponter to the file object */ +) +{ + UINT bw; + char c; + + +#if _USE_STRFUNC >= 2 + if (chr == '\n') fputc ('\r', fil); /* LF -> CRLF conversion */ +#endif + if (!fil) { /* Special value may be used to switch the destination to any other device */ + /* put_console(chr); */ + return chr; + } + c = (char)chr; + f_write(fil, &c, 1, &bw); /* Write a byte to the file */ + return bw ? chr : EOF; /* Return the resulut */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ +int fputs ( + const char* str, /* Pointer to the string to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + int n; + + + for (n = 0; *str; str++, n++) { + if (fputc(*str, fil) == EOF) return EOF; + } + return n; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ +int fprintf ( + FIL* fil, /* Pointer to the file object */ + const char* str, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + UCHAR c, f, r; + ULONG val; + char s[16]; + int i, w, res, cc; + + + va_start(arp, str); + + for (cc = res = 0; cc != EOF; res += cc) { + c = *str++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape cahracter */ + cc = fputc(c, fil); + if (cc != EOF) cc = 1; + continue; + } + w = f = 0; + c = *str++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *str++; + } + while (c >= '0' && c <= '9') { /* Precision */ + w = w * 10 + (c - '0'); + c = *str++; + } + if (c == 'l') { /* Prefix: Size is long int */ + f |= 2; c = *str++; + } + if (c == 's') { /* Type is string */ + cc = fputs(va_arg(arp, char*), fil); + continue; + } + if (c == 'c') { /* Type is character */ + cc = fputc(va_arg(arp, char), fil); + if (cc != EOF) cc = 1; + continue; + } + r = 0; + if (c == 'd') r = 10; /* Type is signed decimal */ + if (c == 'u') r = 10; /* Type is unsigned decimal */ + if (c == 'X') r = 16; /* Type is unsigned hexdecimal */ + if (r == 0) break; /* Unknown type */ + if (f & 2) { /* Get the value */ + val = (ULONG)va_arg(arp, long); + } else { + val = (c == 'd') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int); + } + /* Put numeral string */ + if (c == 'd') { + if (val >= 0x80000000) { + val = 0 - val; + f |= 4; + } + } + i = sizeof(s) - 1; s[i] = 0; + do { + c = (UCHAR)(val % r + '0'); + if (c > '9') c += 7; + s[--i] = c; + val /= r; + } while (i && val); + if (i && (f & 4)) s[--i] = '-'; + w = sizeof(s) - 1 - w; + while (i && i > w) s[--i] = (f & 1) ? '0' : ' '; + cc = fputs(&s[i], fil); + } + + va_end(arp); + return (cc == EOF) ? cc : res; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC >= 1*/ diff --git a/A58-AMTLDR/Src/fs/ff.h b/A58-AMTLDR/Src/fs/ff.h new file mode 100644 index 00000000..9b5720c5 --- /dev/null +++ b/A58-AMTLDR/Src/fs/ff.h @@ -0,0 +1,343 @@ +/*--------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.06 (C)ChaN, 2008 +/---------------------------------------------------------------------------/ +/ FatFs module is an experimenal project to implement FAT file system to +/ cheap microcontrollers. This is a free software and is opened for education, +/ research and development under license policy of following trems. +/ +/ Copyright (C) 2008, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is no warranty. +/ * You can use, modify and/or redistribute it for personal, non-profit or +/ commercial use without any restriction under your responsibility. +/ * Redistributions of source code must retain the above copyright notice. +/ +/---------------------------------------------------------------------------*/ + +#ifndef _FATFS +#define _FATFS + +#define _MCU_ENDIAN 2 +/* The _MCU_ENDIAN defines which access method is used to the FAT structure. +/ 1: Enable word access. +/ 2: Disable word access and use byte-by-byte access instead. +/ When the architectural byte order of the MCU is big-endian and/or address +/ miss-aligned access results incorrect behavior, the _MCU_ENDIAN must be set to 2. +/ If it is not the case, it can also be set to 1 for good code efficiency. */ + +#define _FS_READONLY 1 +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + +#define _FS_MINIMIZE 3 +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename are removed. +/ 2: f_opendir and f_readdir are removed in addition to level 1. +/ 3: f_lseek is removed in addition to level 2. */ + +#define _USE_STRFUNC 0 +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + +#define _USE_MKFS 0 +/* When _USE_MKFS is set to 1 and _FS_READONLY is set to 0, f_mkfs function is +/ enabled. */ + +#define _DRIVES 2 +/* Number of logical drives to be used. This affects the size of internal table. */ + +#define _MULTI_PARTITION 0 +/* When _MULTI_PARTITION is set to 0, each logical drive is bound to same +/ physical drive number and can mount only 1st primaly partition. When it is +/ set to 1, each logical drive can mount a partition listed in Drives[]. */ + +#define _USE_FSINFO 1 +/* To enable FSInfo support on FAT32 volume, set _USE_FSINFO to 1. */ + +#define _USE_SJIS 1 +/* When _USE_SJIS is set to 1, Shift-JIS code transparency is enabled, otherwise +/ only US-ASCII(7bit) code can be accepted as file/directory name. */ + +#define _USE_NTFLAG 1 +/* When _USE_NTFLAG is set to 1, upper/lower case of the file name is preserved. +/ Note that the files are always accessed in case insensitive. */ + + +#include "integer.h" + + + +/* Definitions corresponds to multiple sector size (not tested) */ +#define S_MAX_SIZ 512U /* Do not change */ +#if S_MAX_SIZ > 512U +#define SS(fs) ((fs)->s_size) +#else +#define SS(fs) 512U +#endif + + +/* File system object structure */ +typedef struct _FATFS { + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries */ + DWORD winsect; /* Current sector appearing in the win[] */ + DWORD sects_fat; /* Sectors per fat */ + DWORD max_clust; /* Maximum cluster# + 1 */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (cluster# for FAT32) */ + DWORD database; /* Data start sector */ +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ +#if _USE_FSINFO + DWORD fsi_sector; /* fsinfo sector */ + BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + BYTE pad2; +#endif +#else + BYTE pad3; + BYTE pad2; +#endif + BYTE fs_type; /* FAT sub type */ + BYTE csize; /* Number of sectors per cluster */ +#if S_MAX_SIZ > 512U + WORD s_size; /* Sector size */ +#endif + BYTE n_fats; /* Number of FAT copies */ + BYTE drive; /* Physical drive number */ + BYTE winflag; /* win[] dirty flag (1:must be written back) */ + BYTE pad1; + BYTE win[S_MAX_SIZ]; /* Disk access window for Directory/FAT */ +} FATFS; + + +/* Directory object structure */ +typedef struct _DIR { + WORD id; /* Owner file system mount ID */ + WORD index; /* Current index */ + FATFS* fs; /* Pointer to the owner file system object */ + DWORD sclust; /* Start cluster */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ +} DIR; + + +/* File object structure */ +typedef struct _FIL { + WORD id; /* Owner file system mount ID */ + BYTE flag; /* File status flags */ + BYTE csect; /* Sector address in the cluster */ + FATFS* fs; /* Pointer to the owner file system object */ + DWORD fptr; /* File R/W pointer */ + DWORD fsize; /* File size */ + DWORD org_clust; /* File start cluster */ + DWORD curr_clust; /* Current cluster */ + DWORD curr_sect; /* Current sector */ +#if _FS_READONLY == 0 + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Ponter to the directory entry in the window */ +#endif + BYTE buffer[S_MAX_SIZ]; /* File R/W buffer */ +} FIL; + + +/* File status structure */ +typedef struct _FILINFO { + DWORD fsize; /* Size */ + WORD fdate; /* Date */ + WORD ftime; /* Time */ + BYTE fattrib; /* Attribute */ + char fname[8+1+3+1]; /* Name (8.3 format) */ +} FILINFO; + + + +/* Definitions corresponds to multi partition */ + +#if _MULTI_PARTITION != 0 /* Multiple partition cfg */ + +typedef struct _PARTITION { + BYTE pd; /* Physical drive # (0-255) */ + BYTE pt; /* Partition # (0-3) */ +} PARTITION; +extern +const PARTITION Drives[]; /* Logical drive# to physical location conversion table */ +#define LD2PD(drv) (Drives[drv].pd) /* Get physical drive# */ +#define LD2PT(drv) (Drives[drv].pt) /* Get partition# */ + +#else /* Single partition cfg */ + +#define LD2PD(drv) (drv) /* Physical drive# is equal to logical drive# */ +#define LD2PT(drv) 0 /* Always mounts the 1st partition */ + +#endif + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* 0 */ + FR_NOT_READY, /* 1 */ + FR_NO_FILE, /* 2 */ + FR_NO_PATH, /* 3 */ + FR_INVALID_NAME, /* 4 */ + FR_INVALID_DRIVE, /* 5 */ + FR_DENIED, /* 6 */ + FR_EXIST, /* 7 */ + FR_RW_ERROR, /* 8 */ + FR_WRITE_PROTECTED, /* 9 */ + FR_NOT_ENABLED, /* 10 */ + FR_NO_FILESYSTEM, /* 11 */ + FR_INVALID_OBJECT, /* 12 */ + FR_MKFS_ABORTED /* 13 */ +} FRESULT; + + + +/*-----------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ +FRESULT f_open (FIL*, const char*, BYTE); /* Open or create a file */ +FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */ +FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */ +FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ +FRESULT f_close (FIL*); /* Close an open file object */ +FRESULT f_opendir (DIR*, const char*); /* Open an existing directory */ +FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ +FRESULT f_stat (const char*, FILINFO*); /* Get file status */ +FRESULT f_getfree (const char*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ +FRESULT f_truncate (FIL*); /* Truncate file */ +FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ +FRESULT f_unlink (const char*); /* Delete an existing file or directory */ +FRESULT f_mkdir (const char*); /* Create a new directory */ +FRESULT f_chmod (const char*, BYTE, BYTE); /* Change file/dir attriburte */ +FRESULT f_utime (const char*, const FILINFO*); /* Change file/dir timestamp */ +FRESULT f_rename (const char*, const char*); /* Rename/Move a file or directory */ +FRESULT f_mkfs (BYTE, BYTE, WORD); /* Create a file system on the drive */ +#if _USE_STRFUNC +#define feof(fp) ((fp)->fptr == (fp)->fsize) +#define EOF -1 +int fputc (int, FIL*); /* Put a character to the file */ +int fputs (const char*, FIL*); /* Put a string to the file */ +int fprintf (FIL*, const char*, ...); /* Put a formatted string to the file */ +char* fgets (char*, int, FIL*); /* Get a string from the file */ +#endif + +/* User defined function to give a current time to fatfs module */ + +DWORD get_fattime (void); /* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */ + /* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */ + + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 +#if _FS_READONLY == 0 +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif +#define FA__ERROR 0x80 + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ + + + +/* Offset of FAT structure members */ + +#define BS_jmpBoot 0 +#define BS_OEMName 3 +#define BPB_BytsPerSec 11 +#define BPB_SecPerClus 13 +#define BPB_RsvdSecCnt 14 +#define BPB_NumFATs 16 +#define BPB_RootEntCnt 17 +#define BPB_TotSec16 19 +#define BPB_Media 21 +#define BPB_FATSz16 22 +#define BPB_SecPerTrk 24 +#define BPB_NumHeads 26 +#define BPB_HiddSec 28 +#define BPB_TotSec32 32 +#define BS_55AA 510 + +#define BS_DrvNum 36 +#define BS_BootSig 38 +#define BS_VolID 39 +#define BS_VolLab 43 +#define BS_FilSysType 54 + +#define BPB_FATSz32 36 +#define BPB_ExtFlags 40 +#define BPB_FSVer 42 +#define BPB_RootClus 44 +#define BPB_FSInfo 48 +#define BPB_BkBootSec 50 +#define BS_DrvNum32 64 +#define BS_BootSig32 66 +#define BS_VolID32 67 +#define BS_VolLab32 71 +#define BS_FilSysType32 82 + +#define FSI_LeadSig 0 +#define FSI_StrucSig 484 +#define FSI_Free_Count 488 +#define FSI_Nxt_Free 492 + +#define MBR_Table 446 + +#define DIR_Name 0 +#define DIR_Attr 11 +#define DIR_NTres 12 +#define DIR_CrtTime 14 +#define DIR_CrtDate 16 +#define DIR_FstClusHI 20 +#define DIR_WrtTime 22 +#define DIR_WrtDate 24 +#define DIR_FstClusLO 26 +#define DIR_FileSize 28 + + + +/* Multi-byte word access macros */ + +#if _MCU_ENDIAN==1 /* Use word access */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#elif _MCU_ENDIAN==2 /* Use byte-by-byte access */ +#define LD_WORD(ptr) (WORD)(((WORD)*(volatile BYTE*)((ptr)+1)<<8)|(WORD)*(volatile BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*(volatile BYTE*)((ptr)+3)<<24)|((DWORD)*(volatile BYTE*)((ptr)+2)<<16)|((WORD)*(volatile BYTE*)((ptr)+1)<<8)|*(volatile BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(volatile BYTE*)(ptr)=(BYTE)(val); *(volatile BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(volatile BYTE*)(ptr)=(BYTE)(val); *(volatile BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(volatile BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(volatile BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24) +#else +#error Do not forget to set _MCU_ENDIAN properly! +#endif + +extern FATFS g_fs; + +#endif /* _FATFS */ diff --git a/A58-AMTLDR/Src/fs/integer.h b/A58-AMTLDR/Src/fs/integer.h new file mode 100644 index 00000000..66285de1 --- /dev/null +++ b/A58-AMTLDR/Src/fs/integer.h @@ -0,0 +1,33 @@ +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _INTEGER + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef signed char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +/* Boolean type */ +#undef FALSE +#undef TRUE + +typedef enum { FALSE = 0, TRUE } BOOL; + +#define _INTEGER +#endif diff --git a/A58-AMTLDR/Src/fs/sd_if.h b/A58-AMTLDR/Src/fs/sd_if.h new file mode 100644 index 00000000..e2abd88b --- /dev/null +++ b/A58-AMTLDR/Src/fs/sd_if.h @@ -0,0 +1,10 @@ +#ifndef SD_IF_H__ +#define SD_IF_H__ + +int MMC_disk_initialize(); + +int MMC_disk_read(void *buff, DWORD sector, BYTE count); + +int MMC_disk_ioctl(BYTE ctrl, void *buff); + +#endif diff --git a/A58-AMTLDR/Src/gpio.c b/A58-AMTLDR/Src/gpio.c new file mode 100644 index 00000000..652a875c --- /dev/null +++ b/A58-AMTLDR/Src/gpio.c @@ -0,0 +1,88 @@ +#include "amt630h.h" + +#define GPIO_SWPORTA_DR 0x00 +#define GPIO_SWPORTA_DDR 0x04 +#define GPIO_SWPORTA_CTL 0x08 +#define GPIO_SWPORTA_INTEN 0x30 +#define GPIO_SWPORTA_INTMASK 0x34 +#define GPIO_SWPORTA_INTTYPE_LEVEL 0x38 +#define GPIO_SWPORTA_INT_POLARITY 0x3c +#define GPIO_SWPORTA_INTSTATUS 0x40 +#define GPIO_SWPORTA_RAW_INTSTATUS 0x44 +#define GPIO_SWPORTA_DEBOUNCE 0x48 +#define GPIO_SWPORTA_EOI 0x4c +#define GPIO_SWPORTA_EXT_PORTA 0x50 +#define GPIO_SWPORTA_EXT_PORTB 0x54 +#define GPIO_SWPORTA_EXT_PORTC 0x58 +#define GPIO_SWPORTA_EXT_PORTD 0x5c +#define GPIO_SWPORTA_LS_SYNC 0x60 +#define GPIO_SWPORTA_ID_CODE 0x64 +#define GPIO_SWPORTA_INT_BOTHEDGE 0x68 +#define GPIO_SWPORTA_VER_ID_CODE 0x6C +#define GPIO_SWPORTA_CONFIG_REG2 0x70 +#define GPIO_SWPORTA_CONFIG_REG1 0x74 + +#define GPIO_NUM 128 + +static unsigned int gpio_get_regbase(int gpio) +{ + int gpiox = (gpio >> 5) & 0x3; + + return GPIO_BASE + 0x80 * gpiox; +} + +static int GPIO_OFFSET(unsigned gpio) +{ + if (gpio == 96) + return 2; + else if (gpio == 97) + return 0; + else if (gpio == 98) + return 3; + else if (gpio == 99) + return 1; + else + return gpio & 0x1F; +} + +static void *GPIO_MODREG(unsigned gpio) +{ + return (void*)(gpio_get_regbase(gpio) + GPIO_SWPORTA_DDR); +} + +static void *GPIO_WDATAREG(unsigned gpio) +{ + return (void*)(gpio_get_regbase(gpio) + GPIO_SWPORTA_DR); +} + +static void *GPIO_RDATAREG(unsigned gpio) +{ + return (void*)(gpio_get_regbase(gpio) + GPIO_SWPORTA_EXT_PORTA); +} + +void gpio_direction_output(unsigned gpio, int value) +{ + writel(readl(GPIO_MODREG(gpio)) | (1 << GPIO_OFFSET(gpio)), GPIO_MODREG(gpio)); + if (value) + writel(readl(GPIO_WDATAREG(gpio)) | (1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); + else + writel(readl(GPIO_WDATAREG(gpio)) & ~(1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); +} + +void gpio_direction_input(unsigned gpio) +{ + writel(readl(GPIO_MODREG(gpio)) & ~(1 << GPIO_OFFSET(gpio)), GPIO_MODREG(gpio)); +} + +void gpio_set_value(unsigned gpio, int value) +{ + if (value) + writel(readl(GPIO_WDATAREG(gpio)) | (1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); + else + writel(readl(GPIO_WDATAREG(gpio)) & ~(1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); +} + +int gpio_get_value(unsigned gpio) +{ + return !!(readl(GPIO_RDATAREG(gpio)) & (1 << GPIO_OFFSET(gpio))); +} diff --git a/A58-AMTLDR/Src/gpio.h b/A58-AMTLDR/Src/gpio.h new file mode 100644 index 00000000..6a9e2391 --- /dev/null +++ b/A58-AMTLDR/Src/gpio.h @@ -0,0 +1,23 @@ +#ifndef _GPIO_H +#define _GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +void gpio_request(unsigned gpio); + +void gpio_direction_output(unsigned gpio, int value); + +void gpio_direction_input(unsigned gpio); + +void gpio_set_value(unsigned gpio, int value); + +int gpio_get_value(unsigned gpio); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/A58-AMTLDR/Src/list.h b/A58-AMTLDR/Src/list.h new file mode 100644 index 00000000..c507766b --- /dev/null +++ b/A58-AMTLDR/Src/list.h @@ -0,0 +1,685 @@ +#ifndef _LINUX_LIST_H +#define _LINUX_LIST_H + +#define LIST_POISON1 ((void *) 0x0) +#define LIST_POISON2 ((void *) 0x0) + +#ifndef ARCH_HAS_PREFETCH +#define ARCH_HAS_PREFETCH +static inline void prefetch(const void *x) {;} +#endif + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head *prev, struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, the entry is + * in an undefined state. + */ +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = LIST_POISON1; + entry->prev = LIST_POISON2; +} + +/** + * list_replace - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +static inline void list_replace(struct list_head *old, + struct list_head *new) +{ + new->next = old->next; + new->next->prev = new; + new->prev = old->prev; + new->prev->next = new; +} + +static inline void list_replace_init(struct list_head *old, + struct list_head *new) +{ + list_replace(old, new); + INIT_LIST_HEAD(old); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add_tail(list, head); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +static inline int list_is_last(const struct list_head *list, + const struct list_head *head) +{ + return list->next == head; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(const struct list_head *head) +{ + return head->next == head; +} + +/** + * list_empty_careful - tests whether a list is empty and not being modified + * @head: the list to test + * + * Description: + * tests whether a list is empty _and_ checks that no other CPU might be + * in the process of modifying either member (next or prev) + * + * NOTE: using list_empty_careful() without synchronization + * can only be safe if the only activity that can happen + * to the list entry is list_del_init(). Eg. it cannot be used + * if another CPU could re-list_add() it. + */ +static inline int list_empty_careful(const struct list_head *head) +{ + struct list_head *next = head->next; + return (next == head) && (next == head->prev); +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +static inline int list_is_singular(const struct list_head *head) +{ + return !list_empty(head) && (head->next == head->prev); +} + +static inline void __list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + struct list_head *new_first = entry->next; + list->next = head->next; + list->next->prev = list; + list->prev = entry; + entry->next = list; + head->next = new_first; + new_first->prev = head; +} + +/** + * list_cut_position - cut a list into two + * @list: a new list to add all removed entries + * @head: a list with entries + * @entry: an entry within head, could be the head itself + * and if so we won't cut the list + * + * This helper moves the initial part of @head, up to and + * including @entry, from @head to @list. You should + * pass on @entry an element you know is on @head. @list + * should be an empty list or a list you do not care about + * losing its data. + * + */ +static inline void list_cut_position(struct list_head *list, + struct list_head *head, struct list_head *entry) +{ + if (list_empty(head)) + return; + if (list_is_singular(head) && + (head->next != entry && head != entry)) + return; + if (entry == head) + INIT_LIST_HEAD(list); + else + __list_cut_position(list, head, entry); +} + +static inline void __list_splice(const struct list_head *list, + struct list_head *prev, + struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + first->prev = prev; + prev->next = first; + + last->next = next; + next->prev = last; +} + +/** + * list_splice - join two lists, this is designed for stacks + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(const struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head, head->next); +} + +/** + * list_splice_tail - join two lists, each list being a queue + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice_tail(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head->prev, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head, head->next); + INIT_LIST_HEAD(list); + } +} + +/** + * list_splice_tail_init - join two lists and reinitialise the emptied list + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * Each of the lists is a queue. + * The list at @list is reinitialised + */ +static inline void list_splice_tail_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + container_of(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +/** + * list_last_entry - get the last element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_last_entry(ptr, type, member) \ + list_entry((ptr)->prev, type, member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next; prefetch(pos->next), pos != (head); \ + pos = pos->next) + +/** + * __list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * This variant differs from list_for_each() in that it's the + * simplest possible list iteration code, no prefetching is done. + * Use this for code that knows the list to be very short (empty + * or 1 entry) most of the time. + */ +#define __list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ + pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; \ + prefetch(pos->prev), pos != (head); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_reverse(pos, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member); \ + prefetch(pos->member.prev), &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_struct within the struct. + * + * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** + * list_for_each_entry_continue - continue iteration over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Continue to iterate over list of given type, continuing after + * the current position. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member); \ + prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ + prefetch(pos->member.prev), &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_for_each_entry_from - iterate over list of given type from the current point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing from current position. + */ +#define list_for_each_entry_from(pos, head, member) \ + for (; prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_continue + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_from + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type from current point, safe against + * removal of list entry. + */ +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_reverse + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define list_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member), \ + n = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.prev, typeof(*n), member)) + +/* + * Double linked lists with a single pointer list head. + * Mostly useful for hash tables where the two pointer list head is + * too wasteful. + * You lose the ability to access the tail in O(1). + */ + +struct hlist_head { + struct hlist_node *first; +}; + +struct hlist_node { + struct hlist_node *next, **pprev; +}; + +#define HLIST_HEAD_INIT { .first = NULL } +#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } +#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) +static inline void INIT_HLIST_NODE(struct hlist_node *h) +{ + h->next = NULL; + h->pprev = NULL; +} + +static inline int hlist_unhashed(const struct hlist_node *h) +{ + return !h->pprev; +} + +static inline int hlist_empty(const struct hlist_head *h) +{ + return !h->first; +} + +static inline void __hlist_del(struct hlist_node *n) +{ + struct hlist_node *next = n->next; + struct hlist_node **pprev = n->pprev; + *pprev = next; + if (next) + next->pprev = pprev; +} + +static inline void hlist_del(struct hlist_node *n) +{ + __hlist_del(n); + n->next = LIST_POISON1; + n->pprev = LIST_POISON2; +} + +static inline void hlist_del_init(struct hlist_node *n) +{ + if (!hlist_unhashed(n)) { + __hlist_del(n); + INIT_HLIST_NODE(n); + } +} + +static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) +{ + struct hlist_node *first = h->first; + n->next = first; + if (first) + first->pprev = &n->next; + h->first = n; + n->pprev = &h->first; +} + +/* next must be != NULL */ +static inline void hlist_add_before(struct hlist_node *n, + struct hlist_node *next) +{ + n->pprev = next->pprev; + n->next = next; + next->pprev = &n->next; + *(n->pprev) = n; +} + +static inline void hlist_add_after(struct hlist_node *n, + struct hlist_node *next) +{ + next->next = n->next; + n->next = next; + next->pprev = &n->next; + + if(next->next) + next->next->pprev = &next->next; +} + +#define hlist_entry(ptr, type, member) container_of(ptr,type,member) + +#define hlist_for_each(pos, head) \ + for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \ + pos = pos->next) + +#define hlist_for_each_safe(pos, n, head) \ + for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ + pos = n) + +/** + * hlist_for_each_entry - iterate over list of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry(tpos, pos, head, member) \ + for (pos = (head)->first; \ + pos && ({ prefetch(pos->next); 1;}) && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_continue - iterate over a hlist continuing after current point + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_continue(tpos, pos, member) \ + for (pos = (pos)->next; \ + pos && ({ prefetch(pos->next); 1;}) && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_from - iterate over a hlist continuing from current point + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_from(tpos, pos, member) \ + for (; pos && ({ prefetch(pos->next); 1;}) && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = pos->next) + +/** + * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @n: another &struct hlist_node to use as temporary storage + * @head: the head for your list. + * @member: the name of the hlist_node within the struct. + */ +#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ + for (pos = (head)->first; \ + pos && ({ n = pos->next; 1; }) && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ + pos = n) + +#endif diff --git a/A58-AMTLDR/Src/mmu.c b/A58-AMTLDR/Src/mmu.c new file mode 100644 index 00000000..802a1637 --- /dev/null +++ b/A58-AMTLDR/Src/mmu.c @@ -0,0 +1,98 @@ +#include "mmu.h" + +//#pragma data_alignment=16384 +//__no_init unsigned int mmu_tlb_table[4096]; + +//#define _MMUTT_STARTADDRESS ((unsigned int)mmu_tlb_table) +#define _MMUTT_STARTADDRESS ((unsigned int)0x30c000) + + +/** + * \brief Initializes MMU. + * \param pTB Address of the translation table. + */ +void MMU_Initialize(unsigned int *pTB) +{ + unsigned int index; + unsigned int addr; + + /* Reset table entries */ + for (index = 0; index < 4096; index++) + pTB[index] = 0; + + /* interrupt vector address (after remap) 0x0000_0000 */ + pTB[0x000] = (0x200 << 20)| // Physical Address + // ( 1 << 12)| // TEX[0] + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => YES + ( 0 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* SRAM address (after remap) 0x0030_0000 */ + pTB[0x003] = (0x003 << 20)| // Physical Address + ( 1 << 18)| // 16MB Supersection + ( 3 << 10)| // Access in supervisor mode (AP) + ( 1 << 12)| // TEX[0] + ( 0 << 5)| // Domain 0x0, Supersection only support domain 0 + ( 0 << 4)| // (XN) + ( 1 << 3)| // C bit : cachable => YES + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* DDRAM address (after remap) 0x2000_0000 */ + for(addr = 0x200; addr < 0x220; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 1 << 18)| // 16MB Supersection + ( 3 << 10)| // Access in supervisor mode (AP) + ( 1 << 12)| // TEX[0] + ( 0 << 5)| // Domain 0x0, Supersection only support domain 0 + ( 0 << 4)| // (XN) + ( 1 << 3)| // C bit : cachable => YES + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* DDRAM non-cache address (after remap) 0x3000_0000 */ + for(addr = 0x300; addr < 0x320; addr++) + pTB[addr] = ((addr - 0x100) << 20)| // Physical Address + ( 1 << 18)| // 16MB Supersection + ( 3 << 10)| // Access in supervisor mode (AP) + ( 1 << 12)| // TEX[0] + ( 0 << 5)| // Domain 0x0, Supersection only support domain 0 + ( 0 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => YES + ( 0 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + // periph address 0x60000000 ~ 0x80000000 + for(addr = 0x600; addr < 0x800; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + CP15_WriteTTB((unsigned int)pTB); + /* Program the domain access register */ + CP15_WriteDomainAccessControl(0xC0000003); // only domain 0 & 15: access are not checked +} + +void MMU_Init(void) +{ + if(CP15_IsIcacheEnabled()) + CP15_DisableIcache(); + if(CP15_IsDcacheEnabled()) + CP15_DisableDcache(); + + if(CP15_IsMMUEnabled()) + CP15_DisableMMU(); + + MMU_Initialize((unsigned int*)_MMUTT_STARTADDRESS); + + CP15_EnableMMU(); + CP15_EnableIcache(); + CP15_EnableDcache(); +} diff --git a/A58-AMTLDR/Src/mmu.h b/A58-AMTLDR/Src/mmu.h new file mode 100644 index 00000000..230c45ba --- /dev/null +++ b/A58-AMTLDR/Src/mmu.h @@ -0,0 +1,21 @@ +#ifndef _MMU_ +#define _MMU_ +#include "cp15.h" +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void MMU_Init(void); +extern void dma_flush_range(unsigned int ulStart, unsigned int ulEnd); +extern void dma_inv_range (unsigned int ulStart, unsigned int ulEnd); +extern void dma_clean_range(unsigned int ulStart, unsigned int ulEnd); +extern unsigned int vaddr_to_page_addr (unsigned int addr); +extern unsigned int page_addr_to_vaddr (unsigned int addr); + + + +#endif /* #ifndef _MMU_ */ + diff --git a/A58-AMTLDR/Src/scsi.h b/A58-AMTLDR/Src/scsi.h new file mode 100644 index 00000000..a4f6f259 --- /dev/null +++ b/A58-AMTLDR/Src/scsi.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + */ + #ifndef _SCSI_H + #define _SCSI_H + +struct scsi_cmd { + unsigned char cmd[16]; /* command */ + /* for request sense */ + #pragma pack(ARCH_DMA_MINALIGN) + unsigned char sense_buf[64]; + unsigned char status; /* SCSI Status */ + unsigned char target; /* Target ID */ + unsigned char lun; /* Target LUN */ + unsigned char cmdlen; /* command len */ + unsigned long datalen; /* Total data length */ + unsigned char * pdata; /* pointer to data */ + unsigned char msgout[12]; /* Messge out buffer (NOT USED) */ + unsigned char msgin[12]; /* Message in buffer */ + unsigned char sensecmdlen; /* Sense command len */ + unsigned long sensedatalen; /* Sense data len */ + unsigned char sensecmd[6]; /* Sense command */ + unsigned long contr_stat; /* Controller Status */ + unsigned long trans_bytes; /* tranfered bytes */ + + unsigned int priv; +}; + +/*----------------------------------------------------------- +** +** SCSI constants. +** +**----------------------------------------------------------- +*/ + +/* +** Messages +*/ + +#define M_COMPLETE (0x00) +#define M_EXTENDED (0x01) +#define M_SAVE_DP (0x02) +#define M_RESTORE_DP (0x03) +#define M_DISCONNECT (0x04) +#define M_ID_ERROR (0x05) +#define M_ABORT (0x06) +#define M_REJECT (0x07) +#define M_NOOP (0x08) +#define M_PARITY (0x09) +#define M_LCOMPLETE (0x0a) +#define M_FCOMPLETE (0x0b) +#define M_RESET (0x0c) +#define M_ABORT_TAG (0x0d) +#define M_CLEAR_QUEUE (0x0e) +#define M_INIT_REC (0x0f) +#define M_REL_REC (0x10) +#define M_TERMINATE (0x11) +#define M_SIMPLE_TAG (0x20) +#define M_HEAD_TAG (0x21) +#define M_ORDERED_TAG (0x22) +#define M_IGN_RESIDUE (0x23) +#define M_IDENTIFY (0x80) + +#define M_X_MODIFY_DP (0x00) +#define M_X_SYNC_REQ (0x01) +#define M_X_WIDE_REQ (0x03) +#define M_X_PPR_REQ (0x04) + + +/* +** Status +*/ + +#define S_GOOD (0x00) +#define S_CHECK_COND (0x02) +#define S_COND_MET (0x04) +#define S_BUSY (0x08) +#define S_INT (0x10) +#define S_INT_COND_MET (0x14) +#define S_CONFLICT (0x18) +#define S_TERMINATED (0x20) +#define S_QUEUE_FULL (0x28) +#define S_ILLEGAL (0xff) +#define S_SENSE (0x80) + +/* + * Sense_keys + */ + +#define SENSE_NO_SENSE 0x0 +#define SENSE_RECOVERED_ERROR 0x1 +#define SENSE_NOT_READY 0x2 +#define SENSE_MEDIUM_ERROR 0x3 +#define SENSE_HARDWARE_ERROR 0x4 +#define SENSE_ILLEGAL_REQUEST 0x5 +#define SENSE_UNIT_ATTENTION 0x6 +#define SENSE_DATA_PROTECT 0x7 +#define SENSE_BLANK_CHECK 0x8 +#define SENSE_VENDOR_SPECIFIC 0x9 +#define SENSE_COPY_ABORTED 0xA +#define SENSE_ABORTED_COMMAND 0xB +#define SENSE_VOLUME_OVERFLOW 0xD +#define SENSE_MISCOMPARE 0xE + + +#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_COPY 0x18 /* Copy (O) */ +#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */ +#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */ +#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */ +#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */ +#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */ +#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */ +#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */ +#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */ +#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */ +#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */ +#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */ +#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */ +/*************************************************************************** + * %%% Commands Unique to Direct Access Devices %%% + ***************************************************************************/ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */ +#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */ +#define SCSI_PREFETCH 0x34 /* Prefetch (O) */ +#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */ +#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */ +#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */ +#define SCSI_READ16 0x48 +#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */ +#define SCSI_RD_CAPAC10 SCSI_RD_CAPAC /* Read Capacity (10) */ +#define SCSI_RD_CAPAC16 0x9e /* Read Capacity (16) */ +#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */ +#define SCSI_READ_LONG 0x3E /* Read Long (O) */ +#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */ +#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */ +#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */ +#define SCSI_REZERO 0x01 /* Rezero Unit (O) */ +#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */ +#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */ +#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */ +#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */ +#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */ +#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */ +#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */ +#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */ +#define SCSI_VERIFY 0x2F /* Verify (O) */ +#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */ +#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */ +#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */ +#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */ +#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */ + +/** + * struct scsi_platdata - stores information about SCSI controller + * + * @base: Controller base address + * @max_lun: Maximum number of logical units + * @max_id: Maximum number of target ids + */ +struct scsi_platdata { + unsigned long base; + unsigned long max_lun; + unsigned long max_id; +}; + +#if 0 +/* Operations for SCSI */ +struct scsi_ops { + /** + * exec() - execute a command + * + * @dev: SCSI bus + * @cmd: Command to execute + * @return 0 if OK, -ve on error + */ + int (*exec)(struct udevice *dev, struct scsi_cmd *cmd); + + /** + * bus_reset() - reset the bus + * + * @dev: SCSI bus to reset + * @return 0 if OK, -ve on error + */ + int (*bus_reset)(struct udevice *dev); +}; + +#define scsi_get_ops(dev) ((struct scsi_ops *)(dev)->driver->ops) + +extern struct scsi_ops scsi_ops; + +/** + * scsi_exec() - execute a command + * + * @dev: SCSI bus + * @cmd: Command to execute + * @return 0 if OK, -ve on error + */ +int scsi_exec(struct udevice *dev, struct scsi_cmd *cmd); + +/** + * scsi_bus_reset() - reset the bus + * + * @dev: SCSI bus to reset + * @return 0 if OK, -ve on error + */ +int scsi_bus_reset(struct udevice *dev); + +/** + * scsi_scan() - Scan all SCSI controllers for available devices + * + * @vebose: true to show information about each device found + */ +int scsi_scan(bool verbose); + +/** + * scsi_scan_dev() - scan a SCSI bus and create devices + * + * @dev: SCSI bus + * @verbose: true to show information about each device found + */ +int scsi_scan_dev(struct udevice *dev, bool verbose); +#endif + +void scsi_low_level_init(int busdevfunc); +void scsi_init(void); + +#define SCSI_IDENTIFY 0xC0 /* not used */ + +/* Hardware errors */ +#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */ +#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */ +#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */ +#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */ + +#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */ + +#endif /* _SCSI_H */ diff --git a/A58-AMTLDR/Src/sdmmc.c b/A58-AMTLDR/Src/sdmmc.c new file mode 100644 index 00000000..d257d7eb --- /dev/null +++ b/A58-AMTLDR/Src/sdmmc.c @@ -0,0 +1,1735 @@ +/* +********************************************************************** +Copyright (c)2007 Arkmicro Technologies Inc. All Rights Reserved +Filename: sdmmc.c +Version : 1.0 +Date : 2015.12.01 +Abstract: ark1680 soc sd driver +History : +*********************************************************************** +*/ +#include +#include "typedef.h" +#include "amt630h.h" +#include "sdmmc.h" +#include "UartPrint.h" +#include "timer.h" +#include "fs/ff.h" +#include "fs/diskio.h" +#include "crc32.h" +#include "sysinfo.h" + +#define SDMMC_BUS_CLK CLK_24MHZ + +#define INIT_CLOCK 400000 +#define SD_TRUE 1 +#define SD_FAULSE 0 +#define TIMEOUT_SD 10000 + + +#if SD_DEBUG +#define DEBUG_MSG(fmt, ...) printf(fmt, __VA_ARGS__) +#else +#define DEBUG_MSG(fmt, ...) +#endif + +static UINT32 lg_ulChip; +static UINT32 SDHC_Controls[1] = {SDHC0_BASE}; +static UINT32 mmc_voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; +#define READ_INT32(r) *((volatile UINT32 *)(r)) +#define WRITE_INT32(r,d) (*((volatile UINT32 *)(r)) = d) + +#define SDHC_REG_READ32(c,r)\ + (READ_INT32(SDHC_Controls[(c)] + (r))) +#define SDHC_REG_WRITE32(c,r,v)\ + (WRITE_INT32(SDHC_Controls[(c)] + (r),(v))) + +#define SDMMC_CTRL 0x00 +#define SDMMC_PWREN 0x04 +#define SDMMC_CLKDIV 0x08 +#define SDMMC_CLKSRC 0x0C +#define SDMMC_CLKENA 0x10 +#define SDMMC_TMOUT 0x14 +#define SDMMC_CTYPE 0x18 +#define SDMMC_BLKSIZ 0x1C +#define SDMMC_BYTCNT 0x20 +#define SDMMC_INTMASK 0x24 +#define SDMMC_CMDARG 0x28 +#define SDMMC_CMD 0x2C +#define SDMMC_RESP0 0x30 +#define SDMMC_RESP1 0x34 +#define SDMMC_RESP2 0x38 +#define SDMMC_RESP3 0x3C +#define SDMMC_MINTSTS 0x40 +#define SDMMC_RINTSTS 0x44 +#define SDMMC_STATUS 0x48 +#define SDMMC_FIFOTH 0x4C +#define SDMMC_CDETECT 0x50 +#define SDMMC_WRTPRT 0x54 +#define SDMMC_GPIO 0x58 +#define SDMMC_TCBCNT 0x5C +#define SDMMC_TBBCNT 0x60 +#define SDMMC_DEBNCE 0x64 +#define SDMMC_USRID 0x68 +#define SDMMC_VERID 0x6C +#define SDMMC_HCON 0x70 +#define SDMMC_UHS_REG 0x74 +#define SDMMC_BMOD 0x80 +#define SDMMC_PLDMND 0x84 +#define SDMMC_DBADDR 0x88 +#define SDMMC_IDSTS 0x8C +#define SDMMC_IDINTEN 0x90 +#define SDMMC_DATA 0x200 +#define SDMMC_FIFO (SDHC_Controls[lg_ulChip] + 0x200) + +/* Interrupt Mask register */ +#define SDMMC_INTMSK_ALL 0xffffffff +#define SDMMC_INTMSK_RE (1 << 1) +#define SDMMC_INTMSK_CDONE (1 << 2) +#define SDMMC_INTMSK_DTO (1 << 3) +#define SDMMC_INTMSK_TXDR (1 << 4) +#define SDMMC_INTMSK_RXDR (1 << 5) +#define SDMMC_INTMSK_DCRC (1 << 7) +#define SDMMC_INTMSK_RTO (1 << 8) +#define SDMMC_INTMSK_DRTO (1 << 9) +#define SDMMC_INTMSK_HTO (1 << 10) +#define SDMMC_INTMSK_FRUN (1 << 11) +#define SDMMC_INTMSK_HLE (1 << 12) +#define SDMMC_INTMSK_SBE (1 << 13) +#define SDMMC_INTMSK_ACD (1 << 14) +#define SDMMC_INTMSK_EBE (1 << 15) + +/* Raw interrupt Regsiter */ +#define SDMMC_DATA_ERR (SDMMC_INTMSK_EBE | SDMMC_INTMSK_SBE | SDMMC_INTMSK_HLE |\ + SDMMC_INTMSK_FRUN | SDMMC_INTMSK_EBE | SDMMC_INTMSK_DCRC) +#define SDMMC_DATA_TOUT (SDMMC_INTMSK_HTO | SDMMC_INTMSK_DRTO) + +/* CTRL register */ +#define SDMMC_CTRL_RESET (1 << 0) +#define SDMMC_CTRL_FIFO_RESET (1 << 1) +#define SDMMC_CTRL_DMA_RESET (1 << 2) +#define SDMMC_DMA_EN (1 << 5) +#define SDMMC_CTRL_SEND_AS_CCSD (1 << 10) +#define SDMMC_IDMAC_EN (1 << 25) +#define SDMMC_RESET_ALL (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |\ + SDMMC_CTRL_DMA_RESET) + +/* CMD register */ +#define SDMMC_CMD_RESP_EXP (1 << 6) +#define SDMMC_CMD_RESP_LENGTH (1 << 7) +#define SDMMC_CMD_CHECK_CRC (1 << 8) +#define SDMMC_CMD_DATA_EXP (1 << 9) +#define SDMMC_CMD_RW (1 << 10) +#define SDMMC_CMD_SEND_STOP (1 << 12) +#define SDMMC_CMD_ABORT_STOP (1 << 14) +#define SDMMC_CMD_PRV_DAT_WAIT (1 << 13) +#define SDMMC_CMD_UPD_CLK (1 << 21) +#define SDMMC_CMD_USE_HOLD_REG (1 << 29) +#define SDMMC_CMD_START (1UL << 31) + +/* CLKENA register */ +#define SDMMC_CLKEN_ENABLE (1 << 0) +#define SDMMC_CLKEN_LOW_PWR (1 << 16) + +/* Card-type registe */ +#define SDMMC_CTYPE_1BIT 0 +#define SDMMC_CTYPE_4BIT (1 << 0) +#define SDMMC_CTYPE_8BIT (1 << 16) + +/* Status Register */ +#define SDMMC_BUSY (1 << 9) +#define SDMMC_FIFO_MASK 0x1fff +#define SDMMC_FIFO_SHIFT 17 + +/* FIFOTH Register */ +#define MSIZE(x) ((x) << 28) +#define RX_WMARK(x) ((x) << 16) +#define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) + +#define fifo_tran_over() do{}while (!(SDHC_REG_READ32(lg_ulChip,SDMMC_STATUS) & 0x00000004)) +#define confi_fifo_full() do{}while (!(SDHC_REG_READ32(lg_ulChip,SDMMC_STATUS) & 0x00000008)) +//#define confi_fifo_unempty() do{}while ((rSTATUS & 0x00000004)) + +/* frequency bases */ +/* divided by 10 to be nice to platforms without floating point */ +static const int fbase[] = { + 10000, + 100000, + 1000000, + 10000000, +}; + +/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice + * to platforms without floating point. + */ +static const UINT8 multipliers[] = { + 0, /* reserved */ + 10, + 12, + 13, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 70, + 80, +}; + +//extern volatile FS_CARD SDCard; + +static UINT32 fifoth_val; +static UINT32 sd_ocr; +static UINT32 sd_cid[4]; +static UINT32 sd_csd[4]; +static UINT32 sd_rca; +static UINT32 read_bl_len; +static UINT32 write_bl_len; +static UINT32 erase_grp_size; +static UINT64 capacity_user; + +typedef enum {MMC, SD}CARDTYPE; +static CARDTYPE CardType = SD; // 1 sd card, 0 means MMC +static enum {Ver0, Ver1, Ver2} Spec = Ver1; +static enum {Standard, High} Capacity = Standard; +//static INT8 *sd_spec[3]={"1.0 & 1.01", "1.1", "2.0"}; +//static INT8 *mmc_spec[5]={"1.0-1.2", "1.4", "2.0-2.2","3.1-3.2-3.31","4.x"}; +//static UINT8 SD_SPEC; +//static UINT8 MMC_SPEC; + +static UINT32 g_MatchSdVcc = 1; + +#define SDMMC_SECTOR_SIZE 512 + +static void select_sd_pad(UINT32 ulChip) +{ + UINT32 val; + UINT32 regval; + val = rSYS_BOOT_SAMPLE; + val = (val>>2)&0x1; + + if(val == 1) + { /*sd0 128pin*/ + regval = rSYS_PAD_CTRL01; + regval &= ~((0x3<<12)|(0x3<<10)|(0x3<<8)|(0x3<<6)|(0x3<<4)|(0x3<<2)|(0x3<<0)); + regval |= ((0x1<<12)|(0x1<<10)|(0x1<<8)|(0x1<<6)|(0x1<<4)|(0x1<<2)|(0x1<<0)); + rSYS_PAD_CTRL01 = regval; + regval = rSYS_PAD_CTRL07; + regval &= ~((0x1<<26)|(0x1<<25)|(0x1<<24)|(0x1<<2)|(0x1<<1)|(0x1<<0)); + rSYS_PAD_CTRL07 = regval; + } + else + { + /*sd0 96pin*/ + regval = rSYS_PAD_CTRL01; + regval &= ~((0x3<<20)|(0x3<<18)|(0x3<<16)|(0x3<<14)); + regval |= ((0x3<<20)|(0x3<<18)|(0x3<<16)|(0x3<<14)); + rSYS_PAD_CTRL01 = regval; + + regval = rSYS_PAD_CTRL02; + regval &= ~((0x3<<28)|(0x3<<26)|(0x3<<24)); + regval |= ((0x2<<28)|(0x2<<26)|(0x2<<24)); + rSYS_PAD_CTRL02 = regval; + + regval = rSYS_PAD_CTRL07; + regval &= ~((0x1<<31)|(0x1<<26)|(0x1<<25)|(0x1<<24)); + regval |= (0x1<<31)|(0x1<<26)|(0x1<<25)|(0x1<<24); + rSYS_PAD_CTRL07 = regval; + + } +// rSYS_SDMMC_CLK_CFG |= (1<<6); +} + +static int sdmmc_wait_reset(UINT32 value) +{ + unsigned long timeout = 1000; + UINT32 ctrl; + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CTRL, value); + + while (timeout--) { + ctrl = SDHC_REG_READ32(lg_ulChip, SDMMC_CTRL); + if (!(ctrl & SDMMC_RESET_ALL)) + return -1; + } + return 0; +} + +static int sdmmc_data_transfer(struct mmc_data *data) +{ + int ret = 0; + UINT32 timeout = 240000; + UINT32 mask, size, i, len = 0; + UINT32 *buf = NULL; + ULONG start = get_timer(0); + UINT32 fifo_depth = (((fifoth_val & RX_WMARK_MASK) >> + RX_WMARK_SHIFT) + 1) * 2; + + size = data->blocksize * data->blocks / 4; + if (data->flags == MMC_DATA_READ) + buf = (unsigned int *)data->dest; + else + buf = (unsigned int *)data->src; + + for (;;) { + mask = SDHC_REG_READ32(lg_ulChip, SDMMC_RINTSTS); + /* Error during data transfer. */ + if (mask & (SDMMC_DATA_ERR | SDMMC_DATA_TOUT)) { + DEBUG_MSG("%s: DATA ERROR!\n", __func__); + ret = -1; + break; + } + + if (size) { + len = 0; + if (data->flags == MMC_DATA_READ && + (mask & SDMMC_INTMSK_RXDR)) { + while (size) { + len = SDHC_REG_READ32(lg_ulChip, SDMMC_STATUS); + len = (len >> SDMMC_FIFO_SHIFT) & + SDMMC_FIFO_MASK; + len = min(size, len); + for (i = 0; i < len; i++) + *buf++ = SDHC_REG_READ32(lg_ulChip, SDMMC_DATA); + size = size > len ? (size - len) : 0; + } + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, + SDMMC_INTMSK_RXDR); + } else if (data->flags == MMC_DATA_WRITE && + (mask & SDMMC_INTMSK_TXDR)) { + while (size) { + len = SDHC_REG_READ32(lg_ulChip, SDMMC_STATUS); + len = fifo_depth - ((len >> + SDMMC_FIFO_SHIFT) & + SDMMC_FIFO_MASK); + len = min(size, len); + for (i = 0; i < len; i++) + SDHC_REG_WRITE32(lg_ulChip, SDMMC_DATA, + *buf++); + size = size > len ? (size - len) : 0; + } + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, + SDMMC_INTMSK_TXDR); + } + } + + /* Data arrived correctly. */ + if (mask & SDMMC_INTMSK_DTO) { + ret = 0; + break; + } + + /* Check for timeout. */ + if (get_timer(start) > timeout) { + DEBUG_MSG("%s: Timeout waiting for data!\n", + __func__); + ret = -1; + break; + } + } + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, mask); + + return ret; +} + +static int sdmmc_set_transfer_mode(struct mmc_data *data) +{ + unsigned long mode; + + mode = SDMMC_CMD_DATA_EXP; + if (data->flags & MMC_DATA_WRITE) + mode |= SDMMC_CMD_RW; + + return mode; +} + +static int mmc_send_cmd(struct mmc_cmd *cmd, struct mmc_data *data) +{ + int ret = 0, flags = 0, i; + unsigned int timeout = 500; + UINT32 retry = 100000; + UINT32 mask; + ULONG start = get_timer(0); + + while (SDHC_REG_READ32(lg_ulChip, SDMMC_STATUS) & SDMMC_BUSY) { + if (get_timer(start) > timeout) { + DEBUG_MSG("%s: Timeout on data busy\n", __func__); + return SDMMC_RW_CMDTIMEROUT; + } + } + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, SDMMC_INTMSK_ALL); + + if (data) { + SDHC_REG_WRITE32(lg_ulChip, SDMMC_BLKSIZ, data->blocksize); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_BYTCNT, + data->blocksize * data->blocks); + sdmmc_wait_reset(SDMMC_CTRL_FIFO_RESET); + } + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMDARG, cmd->cmdarg); + + if (data) + flags = sdmmc_set_transfer_mode(data); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -1; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + flags |= SDMMC_CMD_ABORT_STOP; + else + flags |= SDMMC_CMD_PRV_DAT_WAIT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + flags |= SDMMC_CMD_RESP_EXP; + if (cmd->resp_type & MMC_RSP_136) + flags |= SDMMC_CMD_RESP_LENGTH; + } + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= SDMMC_CMD_CHECK_CRC; + + flags |= (cmd->cmdidx | SDMMC_CMD_START | SDMMC_CMD_USE_HOLD_REG); + + DEBUG_MSG("Sending CMD%d\n",cmd->cmdidx); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMD, flags); + + for (i = 0; i < retry; i++) { + mask = SDHC_REG_READ32(lg_ulChip, SDMMC_RINTSTS); + if (mask & SDMMC_INTMSK_CDONE) { + if (!data) + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, mask); + break; + } + } + + if (i == retry) { + DEBUG_MSG("%s: Timeout.\n", __func__); + return SDMMC_RW_CMDTIMEROUT; + } + + if (mask & SDMMC_INTMSK_RTO) { + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + DEBUG_MSG("%s: Response Timeout.\n", __func__); + return SDMMC_RW_CMDTIMEROUT; + } else if (mask & SDMMC_INTMSK_RE) { + DEBUG_MSG("%s: Response Error.\n", __func__); + return -1; + } + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP3); + cmd->response[1] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP2); + cmd->response[2] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP1); + cmd->response[3] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP0); + } else { + cmd->response[0] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP0); + } + } + + if (data) { + ret = sdmmc_data_transfer(data); + } + + udelay(100); + + return ret; +} + +/* static void GetCardInfo(INT32 *CID, CARDTYPE ct) +{ + UINT16 Year; + UINT8 Month; + UINT8 CardName[7]; + UINT8 RevisionN; + UINT8 RevisionM; + + if(ct== MMC) + { + Month = (UINT8)((CID[0]&0x0000f000)>>12); + Year = (unsigned long)((CID[0]&0x00000f00)>>8)+1997; + RevisionN = (UINT8)((CID[1]&0x00f00000)>>20); + RevisionM = (UINT8)((CID[1]&0x000f0000)>>16); + CardName[0] = (UINT8)(CID[3]&0x000000ff); + CardName[1] = (UINT8)((CID[2]&0xff000000)>>24); + CardName[2] = (UINT8)((CID[2]&0x00ff0000)>>16); + CardName[3] = (UINT8)((CID[2]&0x0000ff00)>>8); + CardName[4] = (UINT8)(CID[2]&0x000000ff); + CardName[5] = (UINT8)((CID[1]&0xff000000)>>24); + CardName[6] = '\0'; + DEBUG_MSG("Product Name : %s\n", CardName); + DEBUG_MSG("Product revision : %d.%d\n", RevisionN, RevisionM); + DEBUG_MSG("Manufacturing date %d-%d\n", Month, Year); + } + else + { + Month = (UINT8)((CID[0]&0x00000f00)>>8); + Year = (unsigned long)((CID[0]&0x000ff000)>>12)+2000; + RevisionN = (UINT8)((CID[1]&0xf0000000)>>28); + RevisionM = (UINT8)((CID[1]&0x0f00000)>>24); + CardName[0] = (UINT8)(CID[3]&0x000000ff); + CardName[1] = (UINT8)((CID[2]&0xff000000)>>24); + CardName[2] = (UINT8)((CID[2]&0x00ff0000)>>16); + CardName[3] = (UINT8)((CID[2]&0x0000ff00)>>8); + CardName[4] = (UINT8)(CID[2]&0x000000ff); + CardName[5] = '\0'; + DEBUG_MSG("Product Name : %s\n", CardName); + DEBUG_MSG("Product revision : %d.%d\n", RevisionN, RevisionM); + DEBUG_MSG("Manufacturing date %d-%d\n", Month, Year); + } +} */ + +/* static UINT8 GetSD_SPEC(UINT32 *scr) +{ + UINT8 ss; + ss=(UINT8)(scr[0]&0x0000000f); + + return ss; +} + +static UINT8 GetMMC_SPEC(void) +{ + UINT8 ss; + ss = (sd_csd[3]>>26)&0x0000000f; + + return ss; +} */ + +INT32 data_tran_over(void) +{ + INT32 count_sd = 0; + INT32 tt; + + do + { + count_sd++; + if(count_sd > TIMEOUT_SD) + return -1; + + //tt = rSDMMC_RINTSTS; //Command done + tt = SDHC_REG_READ32(lg_ulChip, SDMMC_RINTSTS); + }while (!(tt & 0x00000008)); + + if((tt&0xBFC2) != 0) + { + DEBUG_MSG("This rSDMMC_RINTSTS = 0x%x\n", tt); + + + //rSDMMC_RINTSTS = 0x0000ffff; + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, 0x0000ffff); + return -1; + } + //rSDMMC_RINTSTS = 0x0000ffff; + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, 0x0000ffff); + + return 0; // 0 means successful +} + +static INT32 mmc_go_idle(void) +{ + struct mmc_cmd cmd; + int err; + + udelay(1000); + + cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_NONE; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + udelay(2000); + + return 0; +} + +static int mmc_set_blocklen(int len) +{ + struct mmc_cmd cmd; + int err; + + cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = len; + + err = mmc_send_cmd(&cmd, NULL); + + return err; +} + + +static int sd_select_bus_width(int w) +{ + int err; + struct mmc_cmd cmd; + + if ((w != 4) && (w != 1)) + return -1; + + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = sd_rca << 16; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; + cmd.resp_type = MMC_RSP_R1; + if (w == 4) + cmd.cmdarg = 2; + else if (w == 1) + cmd.cmdarg = 0; + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + return 0; +} + +/* static UINT8 get_width(UINT32 *scr) +{ + if((scr[0]&0x00000f00) == 0x00000500) + return 4; + else + return 1; +} */ + +static int sdmmc_setup_bus(UINT32 freq) +{ + UINT32 div, status; + int timeout = 10000; + unsigned long sclk = SDMMC_BUS_CLK; + + div = sclk / freq; + if (sclk % freq && sclk > freq) + div += 1; + + div = (sclk != freq) ? DIV_ROUND_UP(div, 2) : 0; + +#if 0 + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); +#endif + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKENA, 0); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKSRC, 0); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKDIV, div); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMD, SDMMC_CMD_PRV_DAT_WAIT | + SDMMC_CMD_UPD_CLK | SDMMC_CMD_START); + + do { + status = SDHC_REG_READ32(lg_ulChip, SDMMC_CMD); + if (timeout-- < 0) { + DEBUG_MSG("%s: Timeout!\n", __func__); + return -1; + } + } while (status & SDMMC_CMD_START); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKENA, SDMMC_CLKEN_ENABLE | + SDMMC_CLKEN_LOW_PWR); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMD, SDMMC_CMD_PRV_DAT_WAIT | + SDMMC_CMD_UPD_CLK | SDMMC_CMD_START); + + timeout = 10000; + do { + status = SDHC_REG_READ32(lg_ulChip, SDMMC_CMD); + if (timeout-- < 0) { + DEBUG_MSG("%s: Timeout!\n", __func__); + return -1; + } + } while (status & SDMMC_CMD_START); + + return 0; +} + +static int sdmmc_hw_init() +{ + UINT32 fifo_size; + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_PWREN, 1); + + if (!sdmmc_wait_reset(SDMMC_RESET_ALL)) { + DEBUG_MSG("%s[%d] Fail-reset!!\n", __func__, __LINE__); + return -1; + } + + /* Enumerate at 400KHz */ + sdmmc_setup_bus(INIT_CLOCK); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, 0xFFFFFFFF); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_INTMASK, 0); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_TMOUT, 0xFFFFFFFF); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_IDINTEN, 0); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_BMOD, 1); + + fifo_size = SDHC_REG_READ32(lg_ulChip, SDMMC_FIFOTH); + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | + TX_WMARK(fifo_size / 2); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_FIFOTH, fifoth_val); + + return 0; +} + +static int mmc_send_if_cond() +{ + struct mmc_cmd cmd; + int err; + + cmd.cmdidx = SD_CMD_SEND_IF_COND; + /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ + cmd.cmdarg = (1 << 8) | 0xaa; + cmd.resp_type = MMC_RSP_R7; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + if ((cmd.response[0] & 0xff) != 0xaa) + return -1; + else + Spec = Ver2; + + return 0; +} + +static int sd_send_op_cond() +{ + int timeout = 1000; + int err; + struct mmc_cmd cmd; + + while (1) { + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + + /* + * Most cards do not answer if some reserved bits + * in the ocr are set. However, Some controller + * can set bit 7 (reserved for low voltages), but + * how to manage low voltages SD card is not yet + * specified. + */ + cmd.cmdarg = mmc_voltages & 0xff8000; + + if (Spec == Ver2) + cmd.cmdarg |= OCR_HCS; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + if (cmd.response[0] & OCR_BUSY) + break; + + if (timeout-- <= 0) + return -1; + + udelay(1000); + } + + sd_ocr = cmd.response[0]; + if ((sd_ocr & OCR_HCS) == OCR_HCS) + Capacity = High; + sd_rca = 0; + + return 0; +} + +static int mmc_send_op_cond_iter(int use_arg) +{ + struct mmc_cmd cmd; + int err; + + cmd.cmdidx = MMC_CMD_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + cmd.cmdarg = 0; + if (use_arg) + cmd.cmdarg = OCR_HCS | + (mmc_voltages & + (sd_ocr & OCR_VOLTAGE_MASK)) | + (sd_ocr & OCR_ACCESS_MODE); + + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + sd_ocr = cmd.response[0]; + return 0; +} + +static int mmc_send_op_cond() +{ + int err, i; + + /* Some cards seem to need this */ + mmc_go_idle(); + + /* Asking to the card its capabilities */ + for (i = 0; i < 2; i++) { + err = mmc_send_op_cond_iter(i != 0); + if (err) + return err; + + /* exit if not busy (flag seems to be inverted) */ + if (sd_ocr & OCR_BUSY) + break; + } + + return 0; +} + +static int mmc_complete_op_cond() +{ + int timeout = 1000; + ULONG start; + int err; + + if (!(sd_ocr & OCR_BUSY)) { + /* Some cards seem to need this */ + mmc_go_idle(); + + start = get_timer(0); + while (1) { + err = mmc_send_op_cond_iter(1); + if (err) + return err; + if (sd_ocr & OCR_BUSY) + break; + if (get_timer(start) > timeout) + return -1; + udelay(100); + } + } + + if ((sd_ocr & OCR_HCS) == OCR_HCS); + Capacity = High; + sd_rca = 1; + + return 0; +} + +int mmc_send_status(int timeout) +{ + struct mmc_cmd cmd; + int err, retries = 5; + + cmd.cmdidx = MMC_CMD_SEND_STATUS; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = sd_rca << 16; + + while (1) { + err = mmc_send_cmd(&cmd, NULL); + if (!err) { + if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && + (cmd.response[0] & MMC_STATUS_CURR_STATE) != + MMC_STATE_PRG) + break; + + if (cmd.response[0] & MMC_STATUS_MASK) { + return -1; + } + } else if (--retries < 0) + return err; + + if (timeout-- <= 0) + break; + + udelay(1000); + } + + if (timeout <= 0) { + return -1; + } + + return 0; +} + +int mmc_switch(UINT8 set, UINT8 index, UINT8 value) +{ + struct mmc_cmd cmd; + int timeout = 1000; + int retries = 3; + int ret; + + cmd.cmdidx = MMC_CMD_SWITCH; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | + (index << 16) | + (value << 8); + + while (retries > 0) { + ret = mmc_send_cmd(&cmd, NULL); + + /* Waiting for the ready status */ + if (!ret) { + ret = mmc_send_status(timeout); + return ret; + } + + retries--; + } + + return ret; +} + +static int mmc_startup() +{ + int err; + UINT mult, freq; + UINT64 cmult, csize; + struct mmc_cmd cmd; + + /* Put the Card in Identify Mode */ + cmd.cmdidx = MMC_CMD_ALL_SEND_CID; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = 0; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + memcpy(sd_cid, cmd.response, 16); + + /* + * For MMC cards, set the Relative Address. + * For SD cards, get the Relatvie Address. + * This also puts the cards into Standby State + */ + cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; + cmd.cmdarg = sd_rca << 16; + cmd.resp_type = MMC_RSP_R6; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + if (CardType == SD) + sd_rca = (cmd.response[0] >> 16) & 0xffff; + + /* Get the Card-Specific Data */ + cmd.cmdidx = MMC_CMD_SEND_CSD; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = sd_rca << 16; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + sd_csd[0] = cmd.response[0]; + sd_csd[1] = cmd.response[1]; + sd_csd[2] = cmd.response[2]; + sd_csd[3] = cmd.response[3]; + + /* divide frequency by 10, since the mults are 10x bigger */ + freq = fbase[(cmd.response[0] & 0x7)]; + mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; + read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); + + if (CardType == SD) + write_bl_len = read_bl_len; + else//emmc + write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); + + if (Capacity == High) { + csize = (sd_csd[1] & 0x3f) << 16 + | (sd_csd[2] & 0xffff0000) >> 16; + cmult = 8; + } else { + csize = (sd_csd[1] & 0x3ff) << 2 + | (sd_csd[2] & 0xc0000000) >> 30; + cmult = (sd_csd[2] & 0x00038000) >> 15; + } + capacity_user = (csize + 1) << (cmult + 2); + capacity_user *= read_bl_len; + if (read_bl_len > MMC_MAX_BLOCK_LEN) + read_bl_len = MMC_MAX_BLOCK_LEN; + + if (write_bl_len > MMC_MAX_BLOCK_LEN) + write_bl_len = MMC_MAX_BLOCK_LEN; + + erase_grp_size = 0x400; + + /* Select the card, and put it into Transfer Mode */ + cmd.cmdidx = MMC_CMD_SELECT_CARD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = sd_rca << 16; + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + mmc_set_blocklen(read_bl_len); + sdmmc_setup_bus(freq * mult); + if (CardType == SD) + { + err = sd_select_bus_width(4); + SDHC_REG_WRITE32(0, SDMMC_CTYPE, 0x00000001); + } + else + err = mmc_switch(EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_1); + if (err) + return err; + + return 0; +} + +INT32 sd_mmc_card_identify(void) +{ + INT32 ret; + INT32 op_cond_pending = 0; + + CardType = SD; + Capacity = Standard; //need to re_initialize in case of MMC card + + sdmmc_hw_init(); + + // set the controller 1bit mode + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CTYPE, 0x00000000); + + if (mmc_go_idle()) + return -1; + + /* Test for SD version 2 */ + mmc_send_if_cond(); + + if (g_MatchSdVcc) + ret = sd_send_op_cond(); + else + ret = SDMMC_RW_CMDTIMEROUT; + + if (ret == SDMMC_RW_CMDTIMEROUT) + { + /* If the command timed out, we check for an MMC card */ + ret = mmc_send_op_cond(); + if (ret) { + DEBUG_MSG("Card did not respond to voltage select!\n"); + return -1; + } + CardType = MMC; + op_cond_pending = 1; + } + + if (op_cond_pending) + mmc_complete_op_cond(); + + return 0; +} + +static int mmc_read_blocks(void *dst, ULONG start, ULONG blkcnt) +{ + struct mmc_cmd cmd; + struct mmc_data data; + + if (blkcnt > 1) + cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; + + if (Capacity == High) + cmd.cmdarg = start; + else + cmd.cmdarg = start * read_bl_len; + + cmd.resp_type = MMC_RSP_R1; + + data.dest = dst; + data.blocks = blkcnt; + data.blocksize = read_bl_len; + data.flags = MMC_DATA_READ; + + if (mmc_send_cmd(&cmd, &data)) + return 0; + + if (blkcnt > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + if (mmc_send_cmd(&cmd, NULL)) { + return 0; + } + } + + return blkcnt; +} + +static INT32 SD_Identify(UINT32 Unit) +{ + INT32 ret; + + ret = sd_mmc_card_identify(); + +// if(ret) +// DEBUG_MSG("SD_Identify fails\n"); + + return ret; +} + +INT32 SD_Init(UINT32 Unit) +{ + INT32 ret; + + ret = mmc_startup(); + + return ret; +} + +INT32 SD_ReadSector(UINT32 Unit,ULONG Sector,UINT8 *pBuffer, ULONG Count) +{ + INT32 ret; + + ret = mmc_read_blocks((UINT32 *)pBuffer, Sector, Count); + + return ret; +} + +INT32 InitSDMMCCard() +{ + INT32 result = -1; + + if (!SD_Identify(lg_ulChip)) + { + SendUartString("SDMMC card successfully\n"); + if (!SD_Init(lg_ulChip)) + { + result = 0; + } + } + else + { + SendUartString("SDMMC card identify failed\n"); + } + + return result; +} + +int IsCardExist(void) +{ + return !(SDHC_REG_READ32(lg_ulChip, SDMMC_CDETECT) & 0x1); +} + +#ifdef CHECK_FISRT_FILE +static BYTE *g_rBuffer = g_fs.win; + +static INT32 check_fatfs(UINT8 *buf) +{ + if (!memcmp(&buf[BS_FilSysType], "FAT", 3)) /* Check FAT signature */ + return 0; + if (!memcmp(&buf[BS_FilSysType32], "FAT32", 5) && !(buf[BPB_ExtFlags] & 0x80)) + return 0; + + return 1; +} + +static INT32 check_loaderfile(void) +{ + BYTE fmt, *tbl; + DWORD bootsect = 0, fatsize, fatbase, totalsect, csize, n_rootdir, maxclust, dirbase; + INT i; + + if (mmc_read_blocks((UINT32 *)g_rBuffer, 0, 1) != 1) + return 1; + + fmt = check_fatfs(g_rBuffer); +#if 0 + if (fmt == 1) { /* Not an FAT boot record, it may be patitioned */ + /* Check a partition listed in top of the partition table */ + tbl = &g_rBuffer[MBR_Table]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + if (mmc_read_blocks((UINT32 *)g_rBuffer, bootsect, 1) != 1) + return 1; + fmt = check_fatfs(g_rBuffer); /* Check the partition */ + } + } +#else + /* Check a first fat partition listed in partition table */ + for(i = 0; i < 4; i++) { + tbl = &g_rBuffer[MBR_Table + i * 16]; /* Partition table */ + if (tbl[4] == 0x01 || tbl[4] == 0x04 || tbl[4] == 0x06 || tbl[4] == 0x0B || + tbl[4] == 0x0C || tbl[4] == 0x0E) { /* Is the FAT partition? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + if (mmc_read_blocks((UINT32 *)g_rBuffer, bootsect, 1) != 1) + return 1; + fmt = check_fatfs(g_rBuffer); /* Check the partition */ + break; + } + } +#endif + if (fmt || LD_WORD(&g_rBuffer[BPB_BytsPerSec]) != 512) /* No valid FAT patition is found */ + { + SendUartString("Not found fatfs.\r\n"); + return 2; + } + + /* Initialize the file system object */ + fatsize = LD_WORD(&g_rBuffer[BPB_FATSz16]); /* Number of sectors per FAT */ + if (!fatsize) fatsize = LD_DWORD(&g_rBuffer[BPB_FATSz32]); + fatsize *= g_rBuffer[BPB_NumFATs]; /* (Number of sectors in FAT area) */ + fatbase = bootsect + LD_WORD(&g_rBuffer[BPB_RsvdSecCnt]); /* FAT start sector (lba) */ + csize = g_rBuffer[BPB_SecPerClus]; /* Number of sectors per cluster */ + n_rootdir = LD_WORD(&g_rBuffer[BPB_RootEntCnt]); /* Nmuber of root directory entries */ + totalsect = LD_WORD(&g_rBuffer[BPB_TotSec16]); /* Number of sectors on the file system */ + if (!totalsect) totalsect = LD_DWORD(&g_rBuffer[BPB_TotSec32]); + maxclust = (totalsect /* max_clust = Last cluster# + 1 */ + - LD_WORD(&g_rBuffer[BPB_RsvdSecCnt]) - fatsize - n_rootdir / (512/32) + ) / csize + 2; + + fmt = FS_FAT12; /* Determine the FAT sub type */ + if (maxclust >= 0xFF7) fmt = FS_FAT16; + if (maxclust >= 0xFFF7) fmt = FS_FAT32; + + dirbase = fatbase + fatsize; /* Root directory start sector (lba) */ + + if (fmt == FS_FAT32) + { + DWORD clust = LD_DWORD(&g_rBuffer[BPB_RootClus]); + if(clust <= maxclust) + dirbase += csize * (clust - 2); /* Root directory start cluster */ + } + + if (mmc_read_blocks((UINT32 *)g_rBuffer, dirbase, 1) != 1) + return 1; + + //оʱһļλڵڶĿ¼ + if (!memcmp(&g_rBuffer[0], "ARKSDLDRBIN", 11) || + !memcmp(&g_rBuffer[32], "ARKSDLDRBIN", 11) + ) + { + return 0; + } + //Win10¸ʽԶһSystem Volume InformationĿ¼ + else if (!memcmp(&g_rBuffer[64], "SYSTEM~1 ", 11)) + { + if (!memcmp(&g_rBuffer[96], "ARKSDLDRBIN", 11) || + !memcmp(&g_rBuffer[128], "ARKSDLDRBIN", 11)) + return 0; + } + //о + else if (!memcmp(&g_rBuffer[96], "SYSTEM~1 ", 11)) + { + if (!memcmp(&g_rBuffer[128], "ARKSDLDRBIN", 11) || + !memcmp(&g_rBuffer[160], "ARKSDLDRBIN", 11)) + return 0; + } + else + { + SendUartString("Not found ARKSDLDR.bin.\r\n"); + return 3; + } + + return -1; +} +#endif + +void updateFromSD(int chipid) +{ + FRESULT fret; + FIL fp = {0}; + UINT32 size; + void (*funPtr)(void); + + lg_ulChip = chipid; + g_MatchSdVcc = 1; + select_sd_pad(lg_ulChip); + + if(!IsCardExist()) + { + SendUartString("Card is not in the slot.\r\n"); + return; + } + else + { + if(InitSDMMCCard()) + { + SendUartString("InitSDMMCCard fail.\r\n"); + return; + } + } + fret = f_mount(MMC, &g_fs); + if(fret == FR_OK) + SendUartString("Mount file ok\r\n"); + else + { + SendUartString("Mount file fail\r\n"); + return; + } + + SendUartString("load stepldr... \r\n"); + fret = f_open(&fp, STEPLDR_FILE_NAME, FA_OPEN_EXISTING | FA_READ); + if(fret != FR_OK) + { + SendUartString("Open file fail\r\n"); + return; + } + fret = f_read(&fp, (void *)STEPLDR_ENTRY, STEPLDR_MAX_SIZE, &size); + if(fret != FR_OK) + { + SendUartString("Read file fail\r\n"); + return; + } + f_close(&fp); + + funPtr = (void (*)(void))STEPLDR_ENTRY; + funPtr(); +} + +// for fatfs's sd interface +static unsigned long sdmmc_disk_size; +#define SECOTR_SIZE 512 + +int MMC_disk_initialize() +{ + UINT64 secotrs; + + /* if(InitSDMMCCard() < 0) + { + SendUartString("disk mount fail!\r\n"); + return -1; + } + else + SendUartString("disk mount success!\r\n"); */ + + secotrs = capacity_user / SECOTR_SIZE; + if(secotrs == -1) return -1; + //֧4G + if(secotrs * SECOTR_SIZE > (unsigned int)-1 ) + secotrs = ((unsigned int)-1)/SECOTR_SIZE; + sdmmc_disk_size = secotrs * SECOTR_SIZE; + + return 0; +} +static ulong mmc_erase_t(ulong start, lbaint_t blkcnt) +{ + struct mmc_cmd cmd; + ulong end; + int err, start_cmd, end_cmd; + + if (Capacity == High) { + end = start + blkcnt - 1; + } else { + end = (start + blkcnt - 1) * write_bl_len; + start *= write_bl_len; + } + + if (0) { + start_cmd = SD_CMD_ERASE_WR_BLK_START; + end_cmd = SD_CMD_ERASE_WR_BLK_END; + } else { + start_cmd = MMC_CMD_ERASE_GROUP_START; + end_cmd = MMC_CMD_ERASE_GROUP_END; + } + + cmd.cmdidx = start_cmd; + cmd.cmdarg = start; + cmd.resp_type = MMC_RSP_R1; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = end_cmd; + cmd.cmdarg = end; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = MMC_CMD_ERASE; + cmd.cmdarg = MMC_ERASE_ARG; + cmd.resp_type = MMC_RSP_R1b; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + goto err_out; + + return 0; + +err_out: + SendUartString("mmc erase failed\n"); + return err; +} + +ulong mmc_berase( lbaint_t start, lbaint_t blkcnt) +{ + int err = 0; + lbaint_t blk = 0, blk_r = 0; + int timeout = 1000; + + while (blk < blkcnt) { + if (0/*IS_SD(mmc) && mmc->ssr.au*/) { + ; + //blk_r = ((blkcnt - blk) > mmc->ssr.au) ? + // mmc->ssr.au : (blkcnt - blk); + } else { + blk_r = ((blkcnt - blk) > erase_grp_size) ? + erase_grp_size : (blkcnt - blk); + } + err = mmc_erase_t(start + blk, blk_r); + if (err) + break; + + blk += blk_r; + + /* Waiting for the ready status */ + if (mmc_send_status(timeout)) + return 0; + } + + return blk; +} + +static ulong mmc_write_blocks(lbaint_t start, + lbaint_t blkcnt, const void *src) +{ + struct mmc_cmd cmd; + struct mmc_data data; + int timeout = 1000; + +/* if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) { + printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", + start + blkcnt, mmc_get_blk_desc(mmc)->lba); + return 0; + }*/ + + if (blkcnt == 0) + return 0; + else if (blkcnt == 1) + cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; + + if (Capacity == High) + cmd.cmdarg = start; + else + cmd.cmdarg = start * write_bl_len; + + cmd.resp_type = MMC_RSP_R1; + + data.src = src; + data.blocks = blkcnt; + data.blocksize = write_bl_len; + data.flags = MMC_DATA_WRITE; + + if (mmc_send_cmd(&cmd, &data)) { + SendUartString("mmc write failed\n"); + return 0; + } + + /* SPI multiblock writes terminate using a special + * token, not a STOP_TRANSMISSION request. + */ + if (blkcnt > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + if (mmc_send_cmd(&cmd, NULL)) { + SendUartString("mmc fail to send stop cmd\n"); + return 0; + } + } + + /* Waiting for the ready status */ + if (mmc_send_status(timeout)) + return 0; + + return blkcnt; +} + +ulong mmc_bwrite(lbaint_t start, lbaint_t blkcnt, + const void *src) +{ + lbaint_t cur, blocks_todo = blkcnt; + unsigned char *buf = (unsigned char*)src; + + + if (mmc_set_blocklen(read_bl_len)) + return 0; + + do { + cur = (blocks_todo > CONFIG_SYS_MMC_MAX_BLK_COUNT) ? + CONFIG_SYS_MMC_MAX_BLK_COUNT : blocks_todo; + if (mmc_write_blocks(start, cur, buf) != cur) + return 0; + blocks_todo -= cur; + start += cur; + buf += cur * write_bl_len; + } while (blocks_todo > 0); + + return blkcnt; +} +unsigned int mmc_write(void *buf, unsigned int offset, unsigned int size/*, int show_progress*/) +{ + int blkstart, blkcnt; + unsigned int *pbuf = (unsigned int *)buf; + + if(offset%write_bl_len) + blkstart = offset/write_bl_len + 1; + else + blkstart = offset/write_bl_len; + +// blkstart = offset;//offset/write_bl_len; + + if(size%write_bl_len) + blkcnt = (size/write_bl_len) +1; + else + blkcnt = size/write_bl_len; + + mmc_bwrite(blkstart,blkcnt, pbuf); + +// if (show_progress) +// update_progress_set(100); + + return 0; +} + +ulong mmc_bread(lbaint_t start, lbaint_t blkcnt, void *dst) +{ + lbaint_t cur, blocks_todo = blkcnt; + unsigned char *buf = (unsigned char*)dst; + + if (blkcnt == 0) + return 0; + + if (mmc_set_blocklen(read_bl_len)) { + SendUartString("mmc_bread: Failed to set blocklen\n"); + return 0; + } + + do { + cur = (blocks_todo > CONFIG_SYS_MMC_MAX_BLK_COUNT) ? + CONFIG_SYS_MMC_MAX_BLK_COUNT : blocks_todo; + + if (mmc_read_blocks(buf, start, cur) != cur) { + SendUartString("mmc_bread: Failed to read blocks\n"); + return 0; + } + blocks_todo -= cur; + start += cur; + buf += cur * read_bl_len; + } while (blocks_todo > 0); + + return blkcnt; +} + +unsigned int mmc_read(void *buf, unsigned int offset, unsigned int size) +{ + int blkstart, blkcnt; + unsigned int inoffset = 0; + unsigned int readsize = 0; + + blkstart = offset/read_bl_len; + inoffset = offset - blkstart*read_bl_len; + readsize = size + inoffset; + if(readsize%read_bl_len) + blkcnt = (readsize/read_bl_len) +1; + else + blkcnt = readsize/read_bl_len; + mmc_bread(blkstart, blkcnt, buf); + + return 0; +} + +int EmmcInit(int chipid) +{ + lg_ulChip = chipid; + g_MatchSdVcc = 0; + + select_sd_pad(lg_ulChip); + + if(InitSDMMCCard()) + { + SendUartString("InitSDMMCCard fail.\r\n"); + return -1; + } + + return 0; +} + +int EmmcBurn(void *buf, unsigned int offset, unsigned int size, int show_progress) +{ + int blkstart, blkcnt; + unsigned int *pbuf = (unsigned int *)buf; + + if(offset%write_bl_len) + blkstart = offset/write_bl_len + 1; + else + blkstart = offset/write_bl_len; + + +// blkstart = offset;//offset/write_bl_len; + + if(size%write_bl_len) + blkcnt = (size/write_bl_len) +1; + else + blkcnt = size/write_bl_len; + + mmc_berase(blkstart,blkcnt); + mmc_bwrite(blkstart,blkcnt, pbuf); + +// if (show_progress) +// update_progress_set(100); + + return 0; +} + +void EmmcWriteSysInfo(SysInfo *info) +{ + EmmcBurn(info, SYSINFOB_OFFSET, sizeof(SysInfo), 0); + EmmcBurn(info, SYSINFOA_OFFSET, sizeof(SysInfo), 0); +} + +int EmmcReadSysInfo(SysInfo *info) +{ + int startoffset; + UINT32 checksum; + UINT32 calc_checksum; + unsigned char data[512]; + + startoffset = SYSINFOA_OFFSET; + mmc_read(data, startoffset, sizeof(SysInfo)); + checksum = *(UINT32*)((UINT32)data + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)data, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, data, sizeof(SysInfo)); + return 0; + } + + startoffset = SYSINFOB_OFFSET; + mmc_read(data, startoffset, sizeof(SysInfo)); + checksum = *(UINT32*)((UINT32)data + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)data, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, data, sizeof(SysInfo)); + return 0; + } + + return -1; +} + +int MMC_disk_read(void *buff, DWORD sector, BYTE count) +{ + return SD_ReadSector(0, sector, buff, count); +} + +int MMC_disk_ioctl(BYTE ctrl, void *buff) +{ + switch(ctrl) + { + case CTRL_SYNC: + break; + case GET_SECTOR_COUNT: + *(DWORD*)buff = sdmmc_disk_size / SECOTR_SIZE; + break; + case GET_BLOCK_SIZE: + *(DWORD*)buff = 1; + break; + default: + return -1; + } + return 0; +} + +void bootFromEMMC(int chipid) +{ + void (*funPtr)(); + INT32 nSectorCount; + UINT32 blksart = 0 ; + SysInfo *pSysInfo = NULL; + + EmmcInit(chipid); + + if (ReadSysInfo()) { + SendUartString("read sysinfo fail, use default.\r\n"); + SetDefaultSysInfo(); + } + pSysInfo = GetSysInfo(); + + PrintVariableValueHex("stepldr_offset", pSysInfo->stepldr_offset); + blksart = pSysInfo->stepldr_offset / 512; + nSectorCount = DIV_ROUND_UP(STEPLDR_MAX_SIZE, SDMMC_SECTOR_SIZE); + if (mmc_read_blocks((UINT32 *)STEPLDR_ENTRY, blksart, nSectorCount) != nSectorCount) + { + SendUartString("EMMC Read fail.\r\n"); + //return; + } + + SendUartString("Load STEP !!!\r\n"); + funPtr = (void (*)(void))STEPLDR_ENTRY; + funPtr(); + + return; +} + +void launchEMMC(int chipid) +{ + void (*funPtr)(); + INT32 nSectorCount; + SysInfo *pSysInfo = NULL; + + EmmcInit(chipid); + + if (ReadSysInfo()) { + SendUartString("read sysinfo fail, use default.\r\n"); + SetDefaultSysInfo(); + } + pSysInfo = GetSysInfo(); + + PrintVariableValueHex("loader_offset", pSysInfo->loader_offset); + nSectorCount = DIV_ROUND_UP(LOADER_MAX_SIZE, SDMMC_SECTOR_SIZE); + if (mmc_read_blocks((UINT32 *)IMAGE_ENTRY, pSysInfo->loader_offset / 512, nSectorCount) != nSectorCount) + { + SendUartString("EMMC Read fail.\r\n"); + //return; + } + + if((CheckImageValid)) + { + funPtr = (void (*)(void))IMAGE_ENTRY; + funPtr(); + } + else + SendUartString("invalid Image\n"); + + while(1); +} diff --git a/A58-AMTLDR/Src/sdmmc.h b/A58-AMTLDR/Src/sdmmc.h new file mode 100644 index 00000000..16c0fa48 --- /dev/null +++ b/A58-AMTLDR/Src/sdmmc.h @@ -0,0 +1,297 @@ +/* +********************************************************************** +Copyright (c)2007 Arkmicro Technologies Inc. All Rights Reserved +Filename: sdmmc.h +Version : 1.1 +Date : 2008.01.08 +Author : wx(Modify by Salem) +Abstract: ark1610 soc sd driver +History : +*********************************************************************** +*/ +#ifndef SDMMC_H +#define SDMMC_H + + +#define SD_DEBUG 0 + + +typedef unsigned long ulong; +typedef ulong lbaint_t; + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 + + +#define SDMMC_RW_SUCCES 0 +#define SDMMC_RW_TIMEOUT -1 +#define SDMMC_RW_DMAREAD_FAIL -2 +#define SDMMC_RW_DMAWRITE_FAIL -3 +#define SDMMC_RW_CMDTIMEROUT -4 + + +#define PWREN_ON 0x00000000 //turn on all card power +#define PWREN_OFF 0xFFFFFFFF //turn off all card power +#define CLK_CLKEN 0x0000ffff // +#define CLK_CLKDIS 0x00000000 // disable clk +#define CLK_DIV_INITIAL 0x00000010 //initial choose frequency +#define CLK_DIV_NORMAL 0x00000000 //data transfers clk frequency +#define CLK_SRC 0x00000000 // +#define CMD_CHANG_CLK 0x80202000 //chang clk +#define CMD_INITIAL_CLK 0x80008000 //initial clk before work +#define CMD0_GO_IDLE 0x80000000 //go idle +#define CMD1_MATCH_VCC 0x80000041 //turn on for match vcc +#define CMD2_CID 0x800001c2 //initial card get CID +#define CMD3_RCA 0x80000143 //comfire RCA to card +#define CMD6_SWTICH 0x80000346 //switch function +#define CMD7_SELECT_CARD 0x80000147 //select card +#define CMD8_SPEC 0x80000048 //confire specfic +#define CMD9_CSD 0x800001c9 //get CSD +#define CMD10_CID 0x800001ca //get CID at transfers +#define CMD12_STOP_STEARM 0x8000004c //stop block transfers +#define CMD13_STATUS_CARD 0x8000014D //get card status +#define CMD15_INACTIVE 0x8000000F //make card to inactive +#define CMD16_SET_BLOCKLEN 0x80000150 //set card block length +#define CMD17_READ_SINGLE 0x80000351 //single block read +#define CMD18_READ_MUL 0x80001352 //multipe block read +#define CMD23_PRE_ERASE 0x80000157 //pre erase for write +#define CMD24_WRITE_SINGLE 0x80000758 //single block write +#define CMD25_WRITE_MUL 0x80000759 //multipe block write +#define CMD27_PROG_CSD 0x8000065b //programme csd +#define CMD28_SET_PROTECT 0x8000015c //set protect +#define CMD29_CLR_PROTECT 0x8000015d //clearn protect +#define CMD30_SEND_WRITE 0x8000025e //get the status about protect +#define CMD32_ERASESD_START 0x80000160 //set start erase SD card address +#define CMD33_ERASESD_END 0x80000161 //set end erase SD card address +#define CMD38_ERASE 0x80000166 //confirm erase +#define CMD41_MATCH_VCC 0x80000169 //FOR SD +#define CMD55_APP 0x80000177 //APP CMD +#define ACMD6_WID 0x80000146 //set bus width +#define ACMD13_GET_STATUS 0x8000024d //get status 512 bit +#define ACMD42_DISCON_DATA3 0x8000016a //make data3 disconnect +#define ACMD51_GET_CSR 0x80000273 //get card csr +//=======================MMC set bus========================== +#define CMD6_SWITH 0x80000446 //set bus width +//================================================ + +#define MMC_ERASE_ARG 0x00000000 + + +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SWITCH 6 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_EXT_CSD 8 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_SEND_TUNING_BLOCK 19 +#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21 +#define MMC_CMD_SET_BLOCK_COUNT 23 +#define MMC_CMD_WRITE_SINGLE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_ERASE_GROUP_START 35 +#define MMC_CMD_ERASE_GROUP_END 36 +#define MMC_CMD_ERASE 38 +#define MMC_CMD_APP_CMD 55 +#define MMC_CMD_SPI_READ_OCR 58 +#define MMC_CMD_SPI_CRC_ON_OFF 59 +#define MMC_CMD_RES_MAN 62 + +#define MMC_CMD62_ARG1 0xefac62ec +#define MMC_CMD62_ARG2 0xcbaea7 + + +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH_FUNC 6 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_SWITCH_UHS18V 11 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_SD_STATUS 13 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ + MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + +#define OCR_BUSY 0x80000000 +#define OCR_HCS 0x40000000 +#define OCR_S18R 0x1000000 +#define OCR_VOLTAGE_MASK 0x007FFF80 +#define OCR_ACCESS_MODE 0x60000000 + +#define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_SWITCH_ERROR (1 << 7) +#define MMC_STATUS_RDY_FOR_DATA (1 << 8) +#define MMC_STATUS_CURR_STATE (0xf << 9) +#define MMC_STATUS_ERROR (1 << 19) + +#define MMC_STATE_PRG (7 << 9) + +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte + addressed by index which are + 1 in value field */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte + addressed by index, which are + 1 in value field */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ + +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SWITCH 1 + +/* + * EXT_CSD fields + */ +#define EXT_CSD_ENH_START_ADDR 136 /* R/W */ +#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ +#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ +#define EXT_CSD_PARTITION_SETTING 155 /* R/W */ +#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ +#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ +#define EXT_CSD_WR_REL_PARAM 166 /* R */ +#define EXT_CSD_WR_REL_SET 167 /* R/W */ +#define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_BOOT_BUS_WIDTH 177 +#define EXT_CSD_PART_CONF 179 /* R/W */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ + +/* + * EXT_CSD field definitions + */ + +#define EXT_CSD_CMD_SET_NORMAL (1 << 0) +#define EXT_CSD_CMD_SET_SECURE (1 << 1) +#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) + +#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) + +#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ + /* SDR mode @1.8V I/O */ +#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ + /* SDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ + EXT_CSD_CARD_TYPE_HS200_1_2V) + +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ +#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ +#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ + +#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ +#define EXT_CSD_TIMING_HS 1 /* HS */ +#define EXT_CSD_TIMING_HS200 2 /* HS200 */ + +#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) +#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) +#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) +#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) + +#define EXT_CSD_BOOT_ACK(x) (x << 6) +#define EXT_CSD_BOOT_PART_NUM(x) (x << 3) +#define EXT_CSD_PARTITION_ACCESS(x) (x << 0) + +#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) +#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) +#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) + +#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) + +#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) + +#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ +#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ + +#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ + +#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ +#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ + + +#define MMC_DATA_READ 1 +#define MMC_DATA_WRITE 2 + +/* Maximum block size for MMC */ +#define MMC_MAX_BLOCK_LEN 512 + +struct mmc_cmd { + USHORT cmdidx; + UINT resp_type; + UINT cmdarg; + UINT response[4]; +}; + +struct mmc_data { + union { + char *dest; + const char *src; /* src buffers don't get written to */ + }; + UINT flags; + UINT blocks; + UINT blocksize; +}; + +#endif + diff --git a/A58-AMTLDR/Src/spi.h b/A58-AMTLDR/Src/spi.h new file mode 100644 index 00000000..840df0ff --- /dev/null +++ b/A58-AMTLDR/Src/spi.h @@ -0,0 +1,75 @@ +#ifndef __SPI_H__ +#define __SPI_H__ + +#define MAX_WAIT_LOOP_COUNT 100000 + +#define SPI_WRITE_ENABLE 0x06 +#define SPI_WRITE_DISABLE 0x04 +#define SPI_READ_STATUS 0x05 +#define SPI_READ_STATUS2 0x35 +#define SPI_READ_STATUS3 0x15 +#define SPI_WRITE_STATUS 0x01 +#define SPI_WRITE_STATUS2 0x31 +#define SPI_READ_DATA 0x03 + +#define SPI_4BYTEADDR_READ_DATA 0x13 + +#define SPI_FAST_READ 0x0B +#define SPI_PAGE_PROGRAM 0x02 +#define SPI_4BYTEADD_PAGE_PROGRAM 0x12 +#define SPI_SECTOR_ERASE 0x20 +#define SPI_4BYTEADD_SECTOR_ERASE 0x21 +#define SPI_SECTOR_ERASE_1 0xD7 +#define SPI_BLOCK_ERASE 0xD8 +#define SPI_4BYTEADD_BLOCK_ERASE 0xDC +#define SPI_BLOCK_ERASE_1 0x52 +#define SPI_CHIP_ERASE 0xC7 +#define SPI_CHIP_ERASE_1 0x60 +#define SPI_POWER_DOWN 0xB9 +#define SPI_READ_JEDEC_ID 0x9F +#define SPI_READ_ID_1 0xAB +#define SPI_MF_DEVICE_ID 0x90 +#define SPI_MF_DEVICE_ID_1 0x15 +#define SPI_READ_ELECTRON_SIGN 0xAB + +#define SPI_MF_WINBOND 0xEF +#define SPI_MF_EON 0x1C +#define SPI_MF_AMIC 0x37 +#define SPI_MF_ATMEL 0x1F +#define SPI_MF_SST 0xBF +#define SPI_MF_MXIC 0xC2 + +#define SPI_ENABLE_4BYTE_MODE 0xB7 +#define SPI_DISABLE_4BYTE_MODE 0xE9 +#define SPI_QUAD_IO_READ_DATA 0xEB + + +#define SPI_BUSY (1<<0) +#define SPIFLASH_WRITEENABLE (1<<1) + +#define SPI_QE (1 << 1) + +#define SPI_WRITE_DMA +#define SPI_READ_DMA + +#define WORDSPERPAGE 64 +#define BYTESPERPAGE 256 +#define PAGESPERSECTORS 16 +#define SECTORSPERBLOCK 16 +#define BLOCKSPERFLASH 64 + + +#define BYTESPERBLOCK (BYTESPERPAGE*PAGESPERSECTORS*SECTORSPERBLOCK) +#define BYTESPERSECTOR (BYTESPERPAGE*PAGESPERSECTORS) + + +#define PAGES_PER_BLOCK 64 +#define BYTES_PER_PAGE 2048 + +void SpiSelectPad(void); +int SpiInit(void); +void SpiBurnLoad(void); +void SpiReadId(void); + +#endif + diff --git a/A58-AMTLDR/Src/sysinfo.c b/A58-AMTLDR/Src/sysinfo.c new file mode 100644 index 00000000..c9e5e471 --- /dev/null +++ b/A58-AMTLDR/Src/sysinfo.c @@ -0,0 +1,51 @@ +#include "amt630h.h" +#include "sysinfo.h" +#include "crc32.h" + +extern int SpiReadSysInfo(SysInfo *info); +extern void SpiWriteSysInfo(SysInfo *info); +extern int EmmcReadSysInfo(SysInfo *info); +extern void EmmcWriteSysInfo(SysInfo *info); + +static SysInfo sysinfo = {0}; + +SysInfo *GetSysInfo(void) +{ + return &sysinfo; +} + +void SetDefaultSysInfo(void) +{ +#if DEVICE_TYPE_SELECT != EMMC_FLASH + sysinfo.update_media_type = UPDATE_MEDIA_SD; +#else + sysinfo.update_media_type = UPDATE_MEDIA_USB; + sysinfo.loader_offset = LOADER_OFFSET; + sysinfo.loader_size = LOADER_MAX_SIZE; +#endif + sysinfo.image_offset = IMAGE_OFFSET; + sysinfo.update_status = UPDATE_STATUS_START; + sysinfo.stepldr_offset = STEPLDRB_OFFSET; + sysinfo.stepldr_size = STEPLDR_MAX_SIZE; +} + +int ReadSysInfo(void) +{ +#if DEVICE_TYPE_SELECT != EMMC_FLASH + return SpiReadSysInfo(&sysinfo); +#else + return EmmcReadSysInfo(&sysinfo); +#endif +} + +void SaveSysInfo(SysInfo *info) +{ + if (!info) + info = &sysinfo; + info->checksum = xcrc32((unsigned char*)info, sizeof(SysInfo) - 4, 0xffffffff); +#if DEVICE_TYPE_SELECT != EMMC_FLASH + SpiWriteSysInfo(info); +#else + EmmcWriteSysInfo(info); +#endif +} \ No newline at end of file diff --git a/A58-AMTLDR/Src/sysinfo.h b/A58-AMTLDR/Src/sysinfo.h new file mode 100644 index 00000000..d53b22b8 --- /dev/null +++ b/A58-AMTLDR/Src/sysinfo.h @@ -0,0 +1,32 @@ +#ifndef _SYSINFO_H_ +#define _SYSINFO_H_ + +#define UPDATE_MEDIA_SD 0 +#define UPDATE_MEDIA_USB 1 +#define UPDATE_MEDIA_UART 2 + +#define UPDATE_STATUS_START 0 +#define UPDATE_STATUS_END 1 + +typedef struct { + unsigned int app_checksum; + unsigned int stepldr_offset; + unsigned int stepldr_size; + unsigned int update_media_type; + unsigned int update_status; + unsigned int app_size; + unsigned int image_offset; + unsigned int loader_offset; + unsigned int loader_size; + unsigned int reserved[10]; + unsigned int upgrade_flag; + unsigned int upgrade_appsize; + unsigned int checksum; +} SysInfo; + +SysInfo *GetSysInfo(void); +void SetDefaultSysInfo(void); +int ReadSysInfo(void); +void SaveSysInfo(SysInfo *info); + +#endif \ No newline at end of file diff --git a/A58-AMTLDR/Src/timer.c b/A58-AMTLDR/Src/timer.c new file mode 100644 index 00000000..326f6b93 --- /dev/null +++ b/A58-AMTLDR/Src/timer.c @@ -0,0 +1,78 @@ +#include "amt630h.h" +#include "timer.h" + +#define APBTMR_CONTROL_ENABLE (1 << 0) +/* 1: periodic, 0:free running. */ +#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1) +#define APBTMR_CONTROL_INT_DISABLE (1 << 2) + +#define TIMER_CLK CLK_24MHZ +#define TIMER_PERIOD 1000000 +#define TIMER_LOAD_VAL 0xffffffff + +static unsigned long timestamp; +static unsigned long lastdec; + +void timer_init(void) +{ + rTIMER0_CONTROL = 0; + rTIMER0_LOAD_COUNT = TIMER_LOAD_VAL; + /* No timer interrupt */ + rTIMER0_CONTROL = APBTMR_CONTROL_INT_DISABLE | + APBTMR_CONTROL_MODE_PERIODIC | APBTMR_CONTROL_ENABLE; +} + +void udelay(unsigned long usec) +{ + long tmo = usec * (TIMER_CLK / TIMER_PERIOD); + unsigned long last = rTIMER0_CURRENT_VALUE; + unsigned long now; + + while (tmo > 0) { + now = rTIMER0_CURRENT_VALUE; + if (last >= now) + tmo -= last - now; + else + tmo -= last + (TIMER_LOAD_VAL - now); + last = now; + } +} + +void mdelay(unsigned long msec) +{ + udelay(1000*msec); +} + +#if 0 +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = rTIMER0_CURRENT_VALUE; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} +#endif + +ULONG get_timer_masked (void) +{ + unsigned long now = rTIMER0_CURRENT_VALUE; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + (TIMER_LOAD_VAL - now); + } + lastdec = now; + + return timestamp / DIV_ROUND_UP(TIMER_CLK, TIMER_PERIOD) / 1000; +} + +ULONG get_timer(ULONG base) +{ + return get_timer_masked () - base; +} \ No newline at end of file diff --git a/A58-AMTLDR/Src/timer.h b/A58-AMTLDR/Src/timer.h new file mode 100644 index 00000000..39c8cbef --- /dev/null +++ b/A58-AMTLDR/Src/timer.h @@ -0,0 +1,12 @@ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "typedef.h" + +extern void timer_init(void); +//extern void reset_timer_masked (void); +extern void udelay(unsigned long usec); +extern void mdelay(unsigned long msec); +extern ULONG get_timer(ULONG base); + +#endif diff --git a/A58-AMTLDR/Src/typedef.h b/A58-AMTLDR/Src/typedef.h new file mode 100644 index 00000000..422ab66f --- /dev/null +++ b/A58-AMTLDR/Src/typedef.h @@ -0,0 +1,128 @@ +#ifndef TYPEDEF_HEAD_H__ +#define TYPEDEF_HEAD_H__ + +#ifndef _INTEGER + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef signed char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +#define _INTEGER +#endif + + +typedef char INT8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef unsigned short HWORD; +typedef signed int INT32; +typedef unsigned int UINT32; +typedef unsigned long COLORREF; +typedef unsigned long long UINT64; + +typedef void VOID; +typedef void * P_VOID; + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; + +typedef int bool; + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; + +#define true 1 +#define false 0 + +#if 0 +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ + +#define ENOSYS 38 /* Invalid system call number */ + +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ +#endif + +#define EAGAIN 11 /* Try again */ +#define ETIMEDOUT 110 /* Connection timed out */ + + +typedef struct { + char Present; //1 - card is in the socket + char Changed; //1 - card changed(card is in socket) + unsigned int SecNum; // the whole setctor number +} FS_CARD; + +#endif diff --git a/A58-AMTLDR/Src/wdt.c b/A58-AMTLDR/Src/wdt.c new file mode 100644 index 00000000..f29cf178 --- /dev/null +++ b/A58-AMTLDR/Src/wdt.c @@ -0,0 +1,137 @@ +#include "amt630h.h" +#include "UartPrint.h" + +#define WTCON 0x00 +#define WTPSR 0x04 +#define WTCNT 0x08 +#define WTCLRINT 0x10 +#define WTRCR 0x14 + +#define WTCNT_MAXCNT 0xffff +#define WTCON_MAXDIV 0x80 + +#define WTCON_ENABLE (1 << 0) +#define WTCON_RSTEN (1 << 1) +#define WTCON_INTEN (1 << 2) + +#define WTCON_DIV16 (0 << 4) +#define WTCON_DIV32 (1 << 4) +#define WTCON_DIV64 (2 << 4) +#define WTCON_DIV128 (3 << 4) +#define WTCON_DIVMASK (0x3 << 4) + +#define WTCON_PRESCALE_MAX 0x10000 + +#define WATCHDOG_DEFAULT_TIME (3) + +static int wdt_timeout = WATCHDOG_DEFAULT_TIME; +static int soft_noboot = 0; /* 1: not reboot when watchdog timer expired */ +static int wdt_count; + +static inline unsigned int wdt_max_timeout(unsigned int clk_freq) +{ + return WTCNT_MAXCNT / (clk_freq / WTCON_PRESCALE_MAX + / WTCON_MAXDIV); +} + +int wdt_set_heartbeat(unsigned int timeout, unsigned int clk_freq) +{ + unsigned int count; + unsigned int divisor = 1; + + if (timeout < 1 || timeout > wdt_max_timeout(clk_freq)) + return -EINVAL; + + clk_freq = DIV_ROUND_UP(clk_freq, 128); + count = timeout * clk_freq; + + /* TRACE_DEBUG("Heartbeat: count=%d, timeout=%d, freq=%lu\n", + count, timeout, freq); */ + + /* if the count is bigger than the watchdog register, + then work out what we need to do (and if) we can + actually make this value + */ + + if (count >= 0x10000) { + divisor = DIV_ROUND_UP(count, 0xffff); + + if (divisor > WTCON_PRESCALE_MAX) { + SendUartString("timeout too big\n"); + return -EINVAL; + } + } + + /* TRACE_DEBUG("Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", + timeout, divisor, count, DIV_ROUND_UP(count, divisor)); */ + + count = DIV_ROUND_UP(count, divisor); + wdt_count = count; + + /* update the pre-scaler */ + writel(divisor - 1, WDT_BASE + WTPSR); + + writel(count, WDT_BASE + WTCNT); + + wdt_timeout = timeout; + + return 0; +} + +void wdt_stop(void) +{ + unsigned long wtcon; + + wtcon = readl(WDT_BASE + WTCON); + wtcon &= ~(WTCON_ENABLE | WTCON_RSTEN); + writel(wtcon, WDT_BASE + WTCON); +} + +void wdt_start(void) +{ + unsigned long wtcon; + + wdt_stop(); + + wtcon = readl(WDT_BASE + WTCON); + wtcon &= ~WTCON_DIVMASK; + wtcon |= WTCON_ENABLE | WTCON_DIV128; + if (soft_noboot) { + wtcon |= WTCON_INTEN; + wtcon &= ~WTCON_RSTEN; + } else { + wtcon &= ~WTCON_INTEN; + wtcon |= WTCON_RSTEN; + } + + /* TRACE_DEBUG("Starting watchdog: count=0x%08x, wtcon=%08lx\n", + wdt_count, wtcon); */ + + writel(wdt_count, WDT_BASE + WTCNT); + writel(wtcon, WDT_BASE + WTCON); +} + +int wdt_init(unsigned int clk_freq) +{ + int ret; + + wdt_stop(); + + ret = wdt_set_heartbeat(wdt_timeout, clk_freq); + if (ret) { + SendUartString("failed to set timeout value\n"); + } + + wdt_start(); + + return 0; +} + +void wdt_cpu_reboot(void) +{ + SendUartString("cpu reboot...\n"); + soft_noboot = 0; + wdt_count = 300; + wdt_start(); + while(1); +} diff --git a/A58-AMTLDR/gen_checksum.exe b/A58-AMTLDR/gen_checksum.exe new file mode 100644 index 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index 00000000..b0fb9f13 --- /dev/null +++ b/A58-STEPLDR/Debug/List/stepldr.map @@ -0,0 +1,1060 @@ +############################################################################### +# +# IAR ELF Linker V8.30.1.114/W32 for ARM 08/May/2025 17:50:04 +# Copyright 2007-2018 IAR Systems AB. +# +# Output file = +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Exe\stepldr.out +# Map file = +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\List\stepldr.map +# Command line = +# -f C:\Users\13669\AppData\Local\Temp\EW716D.tmp +# (G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\aic.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\ark_dwc2.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\Boot.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\core.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\core_intr.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\cp15.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\cp15_asm_iar.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\crc32.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\diskio.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\Entry.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\exception.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\ff.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\gpio.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\hcd.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\hcd_intr.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\hcd_queue.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\heap_4.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\i2c-gpio.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\i2c.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\lcd.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\list.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\mipi.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\mmu.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\os_adapt.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\params.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\pinctrl.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\platform.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\pxp.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\sdmmc.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\SpiBooter.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\SpinandBooter.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\sysctl.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\sysinfo.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\timer.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\uart.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\update.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\usb.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\usb_massstorage.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\usb_os_adapter.o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj\wdt.o +# --no_out_extension -o +# G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Exe\stepldr.out +# --redirect _Printf=_PrintfFullNoMb --redirect _Scanf=_ScanfFullNoMb +# --map G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\List\stepldr.map +# --config G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\stepldr.icf +# --semihosting --entry __iar_program_start --vfe --text_out locale) +# +############################################################################### + +******************************************************************************* +*** RUNTIME MODEL ATTRIBUTES +*** + +CppFlavor = * +__SystemLibrary = DLib +__dlib_version = 6 + + +******************************************************************************* +*** HEAP SELECTION +*** + +The basic heap was selected because no calls to memory allocation +functions were found in the application outside of system library +functions, and there are calls to deallocation functions in the +application. + + +******************************************************************************* +*** PLACEMENT SUMMARY +*** + +"A0": place at 0x20f0'0000 { ro section .intvec }; +"P1": place in [from 0x20f0'0080 to 0x20f1'ffff] { ro }; +define block CSTACK with size = 4K, alignment = 8 { }; +define block SVC_STACK with size = 64, alignment = 8 { }; +define block IRQ_STACK with size = 64, alignment = 8 { }; +define block FIQ_STACK with size = 64, alignment = 8 { }; +define block UND_STACK with size = 64, alignment = 8 { }; +define block ABT_STACK with size = 64, alignment = 8 { }; +define block HEAP with size = 0M, alignment = 8 { }; +"P2": place in [from 0x20f2'0000 to 0x20fe'ffff] { + rw, block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; +initialize by copy { rw }; + + Section Kind Address Size Object + ------- ---- ------- ---- ------ +"A0": 0x40 + .intvec ro code 0x20f0'0000 0x40 Boot.o [1] + - 0x20f0'0040 0x40 + +"P1": 0x10336 + .text ro code 0x20f0'0080 0x310c hcd.o [1] + .text ro code 0x20f0'318c 0xb0 list.o [1] + .text ro code 0x20f0'323c 0x210 core.o [1] + .text ro code 0x20f0'344c 0x1a8 I32DivMod.o [3] + .text ro code 0x20f0'35f4 0x384 hcd_queue.o [1] + .text ro code 0x20f0'3978 0xe4 timer.o [1] + .text ro code 0x20f0'3a5c 0x74 ABImemset.o [3] + .text ro code 0x20f0'3ad0 0x40 ABImemset48.o [3] + .text ro code 0x20f0'3b10 0x48 usb_os_adapter.o [1] + .text ro code 0x20f0'3b58 0xf6c uart.o [1] + .text ro code 0x20f0'4ac4 0x187c usb.o [1] + .text ro code 0x20f0'6340 0x14d4 hcd_intr.o [1] + .text ro code 0x20f0'7814 0xd4 ABImemcpy.o [3] + .text ro code 0x20f0'78e8 0x4 IntDivZer.o [3] + .text ro code 0x20f0'78ec 0x2cc heap_4.o [1] + .text ro code 0x20f0'7bb8 0x1c sysctl.o [1] + .text ro code 0x20f0'7bd4 0x70 sysinfo.o [1] + .text ro code 0x20f0'7c44 0xe8 aic.o [1] + .text ro code 0x20f0'7d2c 0x1e4 update.o [1] + .text ro code 0x20f0'7f10 0x1734 SpiBooter.o [1] + .text ro code 0x20f0'9644 0xcc crc32.o [1] + .text ro code 0x20f0'9710 0xca4 ark_dwc2.o [1] + .text ro code 0x20f0'a3b4 0x8 os_adapt.o [1] + .text ro code 0x20f0'a3bc 0xf34 usb_massstorage.o [1] + .CP15_clean_dcache_for_dma + ro code 0x20f0'b2f0 0x34 cp15_asm_iar.o [1] + .text ro code 0x20f0'b324 0x76c lcd.o [1] + .text ro code 0x20f0'ba90 0x114 gpio.o [1] + .text ro code 0x20f0'bba4 0x1b4 wdt.o [1] + .text ro code 0x20f0'bd58 0x164 platform.o [1] + .text ro code 0x20f0'bebc 0x8c pinctrl.o [1] + .text ro code 0x20f0'bf48 0x2b4 core_intr.o [1] + .text ro code 0x20f0'c1fc 0x4e0 params.o [1] + .text ro code 0x20f0'c6dc 0x1074 sdmmc.o [1] + .text ro code 0x20f0'd750 0x20 I64Shl.o [3] + .text ro code 0x20f0'd770 0x70c Entry.o [1] + .text ro code 0x20f0'de7c 0x8 ABImemclr4.o [3] + .text ro code 0x20f0'de84 0xe08 ff.o [1] + .text ro code 0x20f0'ec8c 0x20 strcat.o [2] + .text ro code 0x20f0'ecac 0x104 mmu.o [1] + .text ro code 0x20f0'edb0 0xa4 diskio.o [1] + .text ro code 0x20f0'ee54 0x84 memcmp.o [3] + .CP15_WriteTTB ro code 0x20f0'eed8 0x10 cp15_asm_iar.o [1] + .CP15_WriteDomainAccessControl + ro code 0x20f0'eee8 0x10 cp15_asm_iar.o [1] + .text ro code 0x20f0'eef8 0x104 cp15.o [1] + .CP15_ReadControl ro code 0x20f0'effc 0xc cp15_asm_iar.o [1] + .CP15_WriteControl ro code 0x20f0'f008 0x10 cp15_asm_iar.o [1] + .rodata const 0x20f0'f018 0x4d0 SpiBooter.o [1] + .rodata const 0x20f0'f4e8 0x2b0 Entry.o [1] + .text ro code 0x20f0'f798 0x1c4 Boot.o [1] + .rodata const 0x20f0'f95c 0x194 uart.o [1] + .text ro code 0x20f0'faf0 0x98 exception.o [1] + .text ro code 0x20f0'fb88 0x7a lz77_init_single.o [3] + .text ro code 0x20f0'fc02 0x3a zero_init3.o [3] + .rodata const 0x20f0'fc3c 0x74 ark_dwc2.o [1] + .rodata const 0x20f0'fcb0 0x74 sdmmc.o [1] + .rodata const 0x20f0'fd24 0x50 usb.o [1] + .text ro code 0x20f0'fd74 0x30 cmain.o [3] + .text ro code 0x20f0'fda4 0x4 low_level_init.o [2] + .text ro code 0x20f0'fda8 0x30 data_init.o [3] + Veneer ro code 0x20f0'fdd8 0x8 - Linker created - + .text ro code 0x20f0'fde0 0x4 exit.o [2] + .text ro code 0x20f0'fde4 0x14 exit.o [4] + .text ro code 0x20f0'fdf8 0x10 cexit.o [3] + .rodata const 0x20f0'fe08 0x28 hcd.o [1] + .rodata const 0x20f0'fe30 0x28 hcd_intr.o [1] + .iar.init_table const 0x20f0'fe58 0x20 - Linker created - + .rodata const 0x20f0'fe78 0x20 usb_massstorage.o [1] + .rodata const 0x20f0'fe98 0x8 ff.o [1] + .text ro code 0x20f0'fea0 0x4 xreturnswi.o [4] + .rodata const 0x20f0'fea4 0x0 zero_init3.o [3] + .rodata const 0x20f0'fea4 0x0 lz77_init_single.o [3] + Initializer bytes const 0x20f0'fea4 0x512 + - 0x20f1'03b6 0x10336 + +"P2", part 1 of 3: 0x904 + P2-1 0x20f2'0000 0x904 + .data inited 0x20f2'0000 0x58 sdmmc.o [1] + .data inited 0x20f2'0058 0x54 ark_dwc2.o [1] + .data inited 0x20f2'00ac 0x38 hcd.o [1] + .data inited 0x20f2'00e4 0x4c8 pinctrl.o [1] + .data inited 0x20f2'05ac 0x28 uart.o [1] + .data inited 0x20f2'05d4 0x31c update.o [1] + .data inited 0x20f2'08f0 0x8 update.o [1] + .data inited 0x20f2'08f8 0xc wdt.o [1] + - 0x20f2'0904 0x904 + +"P2", part 2 of 3: 0x3a988 + .bss zero 0x20f2'0910 0x14000 uart.o [1] + .bss zero 0x20f3'4910 0x13c00 usb.o [1] + .bss zero 0x20f4'8510 0x10004 SpiBooter.o [1] + .bss zero 0x20f5'8514 0x10d4 ark_dwc2.o [1] + .bss zero 0x20f5'95f0 0x900 uart.o [1] + .bss zero 0x20f5'9ef0 0x565 usb.o [1] + .bss zero 0x20f5'a458 0x554 usb_massstorage.o [1] + .bss zero 0x20f5'a9ac 0x404 crc32.o [1] + .bss zero 0x20f5'adb0 0x224 ff.o [1] + .bss zero 0x20f5'afd4 0x100 aic.o [1] + .bss zero 0x20f5'b0d4 0x100 SpiBooter.o [1] + .bss zero 0x20f5'b1d4 0x58 sysinfo.o [1] + .bss zero 0x20f5'b22c 0x20 heap_4.o [1] + .bss zero 0x20f5'b24c 0x20 uart.o [1] + .bss zero 0x20f5'b26c 0xc ff.o [1] + .bss zero 0x20f5'b278 0x8 timer.o [1] + .bss zero 0x20f5'b280 0x4 Entry.o [1] + .bss zero 0x20f5'b284 0x4 lcd.o [1] + .bss zero 0x20f5'b288 0x4 SpiBooter.o [1] + - 0x20f5'b28c 0x3a988 + +"P2", part 3 of 3: 0x85eb4 + .noinit uninit 0x20f5'b28c 0x80000 heap_4.o [1] + .noinit uninit 0x20fd'c000 0x4000 mmu.o [1] + CSTACK 0x20fe'0000 0x1000 + CSTACK uninit 0x20fe'0000 0x1000 + SVC_STACK 0x20fe'1000 0x40 + SVC_STACK uninit 0x20fe'1000 0x40 + IRQ_STACK 0x20fe'1040 0x40 + IRQ_STACK uninit 0x20fe'1040 0x40 + FIQ_STACK 0x20fe'1080 0x40 + FIQ_STACK uninit 0x20fe'1080 0x40 + UND_STACK 0x20fe'10c0 0x40 + UND_STACK uninit 0x20fe'10c0 0x40 + ABT_STACK 0x20fe'1100 0x40 + ABT_STACK uninit 0x20fe'1100 0x40 + - 0x20fe'1140 0x85eb4 + +Unused ranges: + + From To Size + ---- -- ---- + 0x20f1'03b6 0x20f1'ffff 0xfc4a + 0x20fe'1140 0x20fe'ffff 0xeec0 + + +******************************************************************************* +*** INIT TABLE +*** + + Address Size + ------- ---- +Zero (__iar_zero_init3) + 1 destination range, total size 0x3a97c: + 0x20f2'0910 0x3a97c + +Copy/lz77 (__iar_lz77_init_single3) + 1 source range, total size 0x512 (56% of destination): + 0x20f0'fea4 0x512 + 1 destination range, total size 0x904: + 0x20f2'0000 0x904 + + + +******************************************************************************* +*** MODULE SUMMARY +*** + + Module ro code ro data rw data + ------ ------- ------- ------- +command line/config: + --------------------------------------------- + Total: + +G:\mengxun\MAX_CARLINK_A270S\A58-STEPLDR\Debug\Obj: [1] + Boot.o 516 + Entry.o 1 804 688 4 + SpiBooter.o 5 940 1 232 65 800 + aic.o 232 256 + ark_dwc2.o 3 236 163 4 392 + core.o 528 + core_intr.o 692 + cp15.o 260 + cp15_asm_iar.o 112 + crc32.o 204 1 028 + diskio.o 164 + exception.o 152 + ff.o 3 592 8 560 + gpio.o 276 + hcd.o 12 556 72 56 + hcd_intr.o 5 332 40 + hcd_queue.o 900 + heap_4.o 716 524 320 + lcd.o 1 900 4 + list.o 176 + mmu.o 260 16 384 + os_adapt.o 8 + params.o 1 248 + pinctrl.o 140 688 1 224 + platform.o 356 + sdmmc.o 4 212 165 88 + sysctl.o 28 + sysinfo.o 112 88 + timer.o 228 8 + uart.o 3 948 427 84 296 + update.o 484 452 804 + usb.o 6 268 80 82 277 + usb_massstorage.o 3 892 32 1 364 + usb_os_adapter.o 72 + wdt.o 436 7 12 + --------------------------------------------- + Total: 60 980 4 054 782 965 + +dl7Sx_tln.a: [2] + exit.o 4 + low_level_init.o 4 + strcat.o 32 + --------------------------------------------- + Total: 40 + +rt7Sx_tl.a: [3] + ABImemclr4.o 8 + ABImemcpy.o 212 + ABImemset.o 116 + ABImemset48.o 64 + I32DivMod.o 424 + I64Shl.o 32 + IntDivZer.o 4 + cexit.o 16 + cmain.o 48 + data_init.o 48 + lz77_init_single.o 122 + memcmp.o 132 + zero_init3.o 58 + --------------------------------------------- + Total: 1 284 + +sh7Sxs_l.a: [4] + exit.o 20 + xreturnswi.o 4 + --------------------------------------------- + Total: 24 + + Gaps 3 467 + Linker created 8 32 4 416 +------------------------------------------------- + Grand Total: 62 336 4 086 790 848 + + +******************************************************************************* +*** ENTRY LIST +*** + +Entry Address Size Type Object +----- ------- ---- ---- ------ +.iar.init_table$$Base 0x20f0'fe58 -- Gb - Linker created - +.iar.init_table$$Limit 0x20f0'fe78 -- Gb - Linker created - +?main 0x20f0'fd74 Code Gb cmain.o [3] +ABT_STACK$$Base 0x20fe'1100 -- Gb - Linker created - +ABT_STACK$$Limit 0x20fe'1140 -- Gb - Linker created - +AIC_EnableIT 0x20f0'7c94 0x20 Code Gb aic.o [1] +AIC_Initialize 0x20f0'7c44 0x50 Code Gb aic.o [1] +AIC_IrqHandler 0x20f0'7ce4 0x40 Code Gb aic.o [1] +CBWTag 0x20f5'a818 0x4 Data Lc usb_massstorage.o [1] +CP15_DisableDcache 0x20f0'efdc 0x20 Code Gb cp15.o [1] +CP15_DisableIcache 0x20f0'ef2c 0x20 Code Gb cp15.o [1] +CP15_DisableMMU 0x20f0'ef7c 0x20 Code Gb cp15.o [1] +CP15_EnableDcache 0x20f0'efac 0x30 Code Gb cp15.o [1] +CP15_EnableIcache 0x20f0'ef0c 0x20 Code Gb cp15.o [1] +CP15_EnableMMU 0x20f0'ef5c 0x20 Code Gb cp15.o [1] +CP15_IsDcacheEnabled 0x20f0'ef9c 0x10 Code Gb cp15.o [1] +CP15_IsIcacheEnabled 0x20f0'eef8 0x14 Code Gb cp15.o [1] +CP15_IsMMUEnabled 0x20f0'ef4c 0x10 Code Gb cp15.o [1] +CP15_ReadControl 0x20f0'effc Code Gb cp15_asm_iar.o [1] +CP15_WriteControl 0x20f0'f008 Code Gb cp15_asm_iar.o [1] +CP15_WriteDomainAccessControl + 0x20f0'eee8 Code Gb cp15_asm_iar.o [1] +CP15_WriteTTB 0x20f0'eed8 Code Gb cp15_asm_iar.o [1] +CP15_clean_dcache_for_dma + 0x20f0'b2f0 Code Gb cp15_asm_iar.o [1] +CSTACK$$Base 0x20fe'0000 -- Gb - Linker created - +CSTACK$$Limit 0x20fe'1000 -- Gb - Linker created - +Capacity 0x20f2'0046 0x1 Data Lc sdmmc.o [1] +CardType 0x20f2'0044 0x1 Data Lc sdmmc.o [1] +FIQ_STACK$$Base 0x20fe'1080 -- Gb - Linker created - +FIQ_STACK$$Limit 0x20fe'10c0 -- Gb - Linker created - +FatFs 0x20f5'b270 0x8 Data Lc ff.o [1] +FlashBurn 0x20f0'9368 0x4 Code Gb SpiBooter.o [1] +GPIO_MODREG 0x20f0'baf0 0x10 Code Lc gpio.o [1] +GPIO_OFFSET 0x20f0'baa8 0x48 Code Lc gpio.o [1] +GPIO_WDATAREG 0x20f0'bb00 0x4 Code Lc gpio.o [1] +GetSysInfo 0x20f0'7bd4 0x8 Code Gb sysinfo.o [1] +HexToChar 0x20f0'3bbc 0x28 Code Lc uart.o [1] +INIT_LIST_HEAD 0x20f0'9734 0x4 Code Lc ark_dwc2.o [1] +INIT_LIST_HEAD 0x20f0'00d4 0x4 Code Lc hcd.o [1] +INIT_LIST_HEAD 0x20f0'3618 0x4 Code Lc hcd_queue.o [1] +INIT_LIST_ITEM 0x20f0'9738 0x4 Code Lc ark_dwc2.o [1] +INIT_LIST_ITEM 0x20f0'00d8 0x4 Code Lc hcd.o [1] +INIT_LIST_ITEM 0x20f0'361c 0x4 Code Lc hcd_queue.o [1] +INIT_LIST_ITEM 0x20f0'4ad4 0x4 Code Lc usb.o [1] +IRQ_STACK$$Base 0x20fe'1040 -- Gb - Linker created - +IRQ_STACK$$Limit 0x20fe'1080 -- Gb - Linker created - +InitSDMMCCard 0x20f0'd5bc 0x4c Code Gb sdmmc.o [1] +InitUart 0x20f0'3b58 0x64 Code Gb uart.o [1] +IntToStr 0x20f0'3c3c 0x30 Code Gb uart.o [1] +IsCardExist 0x20f0'd608 0x24 Code Gb sdmmc.o [1] +MMC_disk_initialize 0x20f0'd684 0x74 Code Gb sdmmc.o [1] +MMC_disk_read 0x20f0'd6f8 0x10 Code Gb sdmmc.o [1] +MMU_Init 0x20f0'ed54 0x4c Code Gb mmu.o [1] +MMU_Initialize 0x20f0'ecac 0xa8 Code Gb mmu.o [1] +PrintVariableValueHex 0x20f0'3cc0 0x34 Code Gb uart.o [1] +ReadSysInfo 0x20f0'7c08 0x8 Code Gb sysinfo.o [1] +Region$$Table$$Base 0x20f0'fe58 -- Gb - Linker created - +Region$$Table$$Limit 0x20f0'fe78 -- Gb - Linker created - +SDHC_Controls 0x20f2'001c 0x4 Data Lc sdmmc.o [1] +SD_Identify 0x20f0'd5a8 0x4 Code Lc sdmmc.o [1] +SD_Init 0x20f0'd5ac 0x4 Code Gb sdmmc.o [1] +SD_ReadSector 0x20f0'd5b0 0xc Code Gb sdmmc.o [1] +SVC_STACK$$Base 0x20fe'1000 -- Gb - Linker created - +SVC_STACK$$Limit 0x20fe'1040 -- Gb - Linker created - +SaveSysInfo 0x20f0'7c10 0x30 Code Gb sysinfo.o [1] +SendUartString 0x20f0'3c6c 0x54 Code Gb uart.o [1] +SetCSGpioEnable 0x20f0'7f10 0x1c Code Lc SpiBooter.o [1] +SetDefaultSysInfo 0x20f0'7bdc 0x2c Code Gb sysinfo.o [1] +SetSpiDataMode 0x20f0'7f2c 0x3c Code Lc SpiBooter.o [1] +ShortToStr 0x20f0'3be4 0x58 Code Lc uart.o [1] +Spec 0x20f2'0045 0x1 Data Lc sdmmc.o [1] +SpiDisable4ByteMode 0x20f0'817c 0x44 Code Lc SpiBooter.o [1] +SpiEmptyRxFIFO 0x20f0'7f80 0x1c Code Lc SpiBooter.o [1] +SpiEnable4ByteMode 0x20f0'81c0 0x44 Code Lc SpiBooter.o [1] +SpiEraseBlock 0x20f0'8e78 0x94 Code Lc SpiBooter.o [1] +SpiEraseSector 0x20f0'8de0 0x94 Code Lc SpiBooter.o [1] +SpiGetUpfileOffset 0x20f0'9468 0x150 Code Gb SpiBooter.o [1] +SpiInit 0x20f0'86b4 0x1cc Code Gb SpiBooter.o [1] +SpiLoadImage 0x20f0'8c34 0x150 Code Lc SpiBooter.o [1] +SpiNorBurn 0x20f0'90b8 0x2b0 Code Gb SpiBooter.o [1] +SpiNorBurnPage 0x20f0'901c 0x98 Code Gb SpiBooter.o [1] +SpiReadJedecId 0x20f0'85a4 0x98 Code Lc SpiBooter.o [1] +SpiReadPage 0x20f0'8204 0x190 Code Lc SpiBooter.o [1] +SpiReadPageQuadMode 0x20f0'83dc 0xfc Code Lc SpiBooter.o [1] +SpiReadSta 0x20f0'80d0 0x68 Code Lc SpiBooter.o [1] +SpiReadSta2 0x20f0'7fe0 0x78 Code Lc SpiBooter.o [1] +SpiReadSta3 0x20f0'8058 0x78 Code Lc SpiBooter.o [1] +SpiReadSysInfo 0x20f0'936c 0xcc Code Gb SpiBooter.o [1] +SpiSelectPad 0x20f0'84d8 0x30 Code Gb SpiBooter.o [1] +SpiSetFrameFormatMode 0x20f0'8394 0x48 Code Lc SpiBooter.o [1] +SpiWaitIdle 0x20f0'7f68 0x18 Code Lc SpiBooter.o [1] +SpiWriteEnable 0x20f0'8d88 0x50 Code Lc SpiBooter.o [1] +SpiWritePage 0x20f0'8f10 0xf0 Code Lc SpiBooter.o [1] +SpiWriteSta 0x20f0'8138 0x44 Code Lc SpiBooter.o [1] +SpiWriteSta2 0x20f0'7f9c 0x44 Code Lc SpiBooter.o [1] +SpiWriteSysInfo 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zjxi>X5)+ZuWwU0tzMFj_y$FsKhZ3!?XpOXvn{}df>+BQV4=2gNbR;#VDPv=*a%xOh z@i^^;itlNkL_fk4FVs3&{88&<@l5TL#YeSI!e3BYZ`D4{`>j@Ku~O25KWrTA%Q}1q z)ZnITJX@m#T=)kbtD_0D0WeOllPJ~^b`ptZV*C)^-bABSHrBs&D8wWs=k00YT{|d* zr&5bIXlFx+K;{U5nj(CnmE> zaWrcZPtNI_jBIibE@vQ(P>b$1+L%ltZ_NV0GiMq=9iffggQIHQZO*@T-S`L(IPl?V zl-x#c!WA3)3inL-(m!A#VjDROr;HN4f(IHF@C8E)RGWAS4|2j2rq*!sC9d>jhvJ@_ zerf6pN5nSvCeA!n=Tbbt;8OPx+ zrMr#NLigp4Qo`Q~#i(uUxtx_HKINz!^~E$ivZMDnhEvho#C5sD;Tca7&gNl-aT|$c z)~1Vr4{NE0;xOkR-K$Jq(w(N63cd)jY?$6=Jf#O%(*cbp*$h4~abP4w(c~~)BxmvR z!-6Tjja;aU+`x}|DwX=P)StH>cLCf4tI=8dSs%OUV~>Aq`^QfE_#2heI%4L~@KMLj89suhlaBUUPj%uU&363ZPW_1XLix+~Y4#EI(ZM5F&OBoJ@Zb@HN4NuwIK??SO`sT0rg1{VNl^ + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifdef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + /* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil. Backward + * compatibility is maintained if only one or the other is defined, but + * there is a conflict if both are defined. */ + #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined. INCLUDE_vTaskDelayUntil is no longer required and should be removed + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + /* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then + * the project's FreeRTOSConfig.h probably pre-dates the introduction of + * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever + * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility. + */ + #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #define INCLUDE_xTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 1 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. + * The CBMC proofs need a way to track assumptions and assertions. + * A configPRECONDITION statement should express an implicit invariant or + * assumption made. A configASSERT statement should express an invariant that must + * hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT( X ) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + +/* Used to perform any necessary initialisation - for example, open a file + * into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + +/* Use to close a trace, for example close a file into which trace has been + * written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + +/* Called after a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + +/* Called before stepping the tick count after waking from tickless idle + * sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + +/* Called before a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + +/* Called when a task attempts to take a mutex that is already held by a + * lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + * that holds the mutex. uxInheritedPriority is the priority the mutex holder + * will inherit (the priority of the task that is attempting to obtain the + * muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + +/* Called when a task releases a mutex, the holding of which had resulted in + * the task inheriting the priority of a higher priority task. + * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + * mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + +/* Task is about to block because it cannot write to a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the write was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SET_SEND + #define traceQUEUE_SET_SEND traceQUEUE_SEND +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#endif + +#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 + #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 1 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + +/* Defaults to uint16_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + +/* Defaults to size_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if lengths will always be less than the number of bytes + * in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + #if ( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if ( portTICK_TYPE_IS_ATOMIC == 0 ) + +/* Either variables of tick type cannot be read atomically, or + * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + * the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + +/* The tick type can be read atomically, so critical sections used when the + * tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to + * V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + +/* configPRINTF() was not defined, so define it away to nothing. To use + * configPRINTF() then define it as follows (where MyPrintFunction() is + * provided by the application writer): + * + * void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + * + * Then call like a standard printf() function, but placing brackets around + * all parameters so they are passed as a single parameter. For example: + * configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + +/* Backward compatibility within the scheduler code only - these definitions + * are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + +/* For libraries that break the list data hiding, and access list structure + * members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if ( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even + * if floating point hardware is otherwise supported by the FreeRTOS port in use. + * This constant is not supported by all FreeRTOS ports that include floating + * point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. + * This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on + * the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE \ + ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 4 ]; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void * pvDummy3; + StaticMiniListItem_t xDummy4; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void * pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void * pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void * pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void * pxDummy14; + #endif + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void * pvDummy1[ 3 ]; + + union + { + void * pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void * pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void * pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void * pvDummy5; + TaskFunction_t pvDummy6; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; +} StaticTimer_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the stream buffer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a stream buffer then the size of the stream buffer object needs to be + * know. The StaticStreamBuffer_t structure below is provided for this purpose. + * Its size and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* INC_FREERTOS_H */ diff --git a/A58-STEPLDR/FreeRTOS/Source/include/FreeRTOSConfig.h b/A58-STEPLDR/FreeRTOS/Source/include/FreeRTOSConfig.h new file mode 100644 index 00000000..45faf0c2 --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/include/FreeRTOSConfig.h @@ -0,0 +1,156 @@ +/* + * FreeRTOS V202104.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#define configCPU_CLOCK_HZ /* Not used in this port as the value comes from the Atmel libraries. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configUSE_PREEMPTION 0 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configMAX_PRIORITIES ( 32 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 512 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 512 * 1024) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 0 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_RECURSIVE_MUTEXES 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 0 +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 3 /* FreeRTOS+FAT requires 2 pointers if a CWD is supported. */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 16 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitsFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Cortex-A specific setting: FPU has 32 (rather than 16) d registers. See: +http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */ +#define configFPU_D32 0 + +/* Cortex-A specific setting: The address of the register within the interrupt +controller from which the address of the current interrupt's handling function +can be obtained. See: +http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */ +/* #define configINTERRUPT_VECTOR_ADDRESS 0xFC06E010UL */ + +/* Cortex-A specific setting: The address of End of Interrupt register within +the interrupt controller. See: +http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */ +/* #define configEOI_ADDRESS 0xFC06E038UL */ + +/* Cortex-A specific setting: configCLEAR_TICK_INTERRUPT() is a macro that is +called by the RTOS kernel's tick handler to clear the source of the tick +interrupt. See: +http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */ +/* Clear timer0 interrupt. */ +#define configCLEAR_TICK_INTERRUPT() + +/* Prevent C code being included in assembly files when the IAR compiler is +used. */ +#ifndef __IASMARM__ + + /* The interrupt nesting test creates a 20KHz timer. For convenience the + 20KHz timer is also used to generate the run time stats time base, removing + the need to use a separate timer for that purpose. The 20KHz timer + increments ulHighFrequencyTimerCounts, which is used as the time base. + Therefore the following macro is not implemented. */ + #define configGENERATE_RUN_TIME_STATS 0 + + /* The size of the global output buffer that is available for use when there + are multiple command interpreters running at once (for example, one on a UART + and one on TCP/IP). This is done to prevent an output buffer being defined by + each implementation - which would waste RAM. In this case, there is only one + command interpreter running. */ + #define configCOMMAND_INT_MAX_OUTPUT_SIZE 3000 + + /* Normal assert() semantics without relying on the provision of an assert.h + header file. */ + #define configASSERT( x ) if( ( x ) == 0 ) while(1); + + + + /****** Hardware specific settings. *******************************************/ + + /* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. FreeRTOS_Tick_Handler() must + * be installed as the peripheral's interrupt handler. + */ + void vConfigureTickInterrupt( void ); + #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() + +#endif /* __IASMARM__ */ + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/A58-STEPLDR/FreeRTOS/Source/include/list.h b/A58-STEPLDR/FreeRTOS/Source/include/list.h new file mode 100644 index 00000000..8323ab16 --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/include/list.h @@ -0,0 +1,413 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Macros that can be used to place known values within the list structures, + * then check that the known values do not get corrupted during the execution of + * the application. These may catch the list data structures being overwritten in + * memory. They will not catch data errors caused by incorrect configuration or + * use of FreeRTOS.*/ +#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */ + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + +/* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + +/* Define macros that will assert if one of the structure members does not + * contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ + { \ + List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ + } + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ifndef LIST_H */ diff --git a/A58-STEPLDR/FreeRTOS/Source/include/mpu_wrappers.h b/A58-STEPLDR/FreeRTOS/Source/include/mpu_wrappers.h new file mode 100644 index 00000000..5d9f2d17 --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/include/mpu_wrappers.h @@ -0,0 +1,185 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MPU_WRAPPERS_H +#define MPU_WRAPPERS_H + +/* This file redefines API functions to be called through a wrapper macro, but + * only for ports that are using the MPU. */ +#ifdef portUSING_MPU_WRAPPERS + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is + * included from queue.c or task.c to prevent it from having an effect within + * those files. */ + #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* + * Map standard (non MPU) API functions to equivalents that start + * "MPU_". This will cause the application code to call the MPU_ + * version, which wraps the non-MPU version with privilege promoting + * then demoting code, so the kernel code always runs will full + * privileges. + */ + +/* Map standard tasks.h API functions to the MPU equivalents. */ + #define xTaskCreate MPU_xTaskCreate + #define xTaskCreateStatic MPU_xTaskCreateStatic + #define vTaskDelete MPU_vTaskDelete + #define vTaskDelay MPU_vTaskDelay + #define xTaskDelayUntil MPU_xTaskDelayUntil + #define xTaskAbortDelay MPU_xTaskAbortDelay + #define uxTaskPriorityGet MPU_uxTaskPriorityGet + #define eTaskGetState MPU_eTaskGetState + #define vTaskGetInfo MPU_vTaskGetInfo + #define vTaskPrioritySet MPU_vTaskPrioritySet + #define vTaskSuspend MPU_vTaskSuspend + #define vTaskResume MPU_vTaskResume + #define vTaskSuspendAll MPU_vTaskSuspendAll + #define xTaskResumeAll MPU_xTaskResumeAll + #define xTaskGetTickCount MPU_xTaskGetTickCount + #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks + #define pcTaskGetName MPU_pcTaskGetName + #define xTaskGetHandle MPU_xTaskGetHandle + #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 + #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag + #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag + #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer + #define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer + #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook + #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle + #define uxTaskGetSystemState MPU_uxTaskGetSystemState + #define vTaskList MPU_vTaskList + #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter + #define xTaskGenericNotify MPU_xTaskGenericNotify + #define xTaskGenericNotifyWait MPU_xTaskGenericNotifyWait + #define ulTaskGenericNotifyTake MPU_ulTaskGenericNotifyTake + #define xTaskGenericNotifyStateClear MPU_xTaskGenericNotifyStateClear + #define ulTaskGenericNotifyValueClear MPU_ulTaskGenericNotifyValueClear + #define xTaskCatchUpTicks MPU_xTaskCatchUpTicks + + #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle + #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState + #define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut + #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState + +/* Map standard queue.h API functions to the MPU equivalents. */ + #define xQueueGenericSend MPU_xQueueGenericSend + #define xQueueReceive MPU_xQueueReceive + #define xQueuePeek MPU_xQueuePeek + #define xQueueSemaphoreTake MPU_xQueueSemaphoreTake + #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting + #define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable + #define vQueueDelete MPU_vQueueDelete + #define xQueueCreateMutex MPU_xQueueCreateMutex + #define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic + #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore + #define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic + #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder + #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive + #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive + #define xQueueGenericCreate MPU_xQueueGenericCreate + #define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic + #define xQueueCreateSet MPU_xQueueCreateSet + #define xQueueAddToSet MPU_xQueueAddToSet + #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet + #define xQueueSelectFromSet MPU_xQueueSelectFromSet + #define xQueueGenericReset MPU_xQueueGenericReset + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + #define vQueueAddToRegistry MPU_vQueueAddToRegistry + #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue + #define pcQueueGetName MPU_pcQueueGetName + #endif + +/* Map standard timer.h API functions to the MPU equivalents. */ + #define xTimerCreate MPU_xTimerCreate + #define xTimerCreateStatic MPU_xTimerCreateStatic + #define pvTimerGetTimerID MPU_pvTimerGetTimerID + #define vTimerSetTimerID MPU_vTimerSetTimerID + #define xTimerIsTimerActive MPU_xTimerIsTimerActive + #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle + #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall + #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode + #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode + #define xTimerGetPeriod MPU_xTimerGetPeriod + #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime + #define xTimerGenericCommand MPU_xTimerGenericCommand + +/* Map standard event_group.h API functions to the MPU equivalents. */ + #define xEventGroupCreate MPU_xEventGroupCreate + #define xEventGroupCreateStatic MPU_xEventGroupCreateStatic + #define xEventGroupWaitBits MPU_xEventGroupWaitBits + #define xEventGroupClearBits MPU_xEventGroupClearBits + #define xEventGroupSetBits MPU_xEventGroupSetBits + #define xEventGroupSync MPU_xEventGroupSync + #define vEventGroupDelete MPU_vEventGroupDelete + +/* Map standard message/stream_buffer.h API functions to the MPU + * equivalents. */ + #define xStreamBufferSend MPU_xStreamBufferSend + #define xStreamBufferReceive MPU_xStreamBufferReceive + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes + #define vStreamBufferDelete MPU_vStreamBufferDelete + #define xStreamBufferIsFull MPU_xStreamBufferIsFull + #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty + #define xStreamBufferReset MPU_xStreamBufferReset + #define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable + #define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable + #define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel + #define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate + #define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic + + +/* Remove the privileged function macro, but keep the PRIVILEGED_DATA + * macro so applications can place data in privileged access sections + * (useful when using statically allocated objects). */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL + + #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +/* Ensure API functions go in the privileged execution section. */ + #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) ) + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) ) + + #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +#else /* portUSING_MPU_WRAPPERS */ + + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL + #define portUSING_MPU_WRAPPERS 0 + +#endif /* portUSING_MPU_WRAPPERS */ + + +#endif /* MPU_WRAPPERS_H */ diff --git a/A58-STEPLDR/FreeRTOS/Source/include/portable.h b/A58-STEPLDR/FreeRTOS/Source/include/portable.h new file mode 100644 index 00000000..729cafaf --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/include/portable.h @@ -0,0 +1,222 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Portable layer API. Each function must be defined for each port. +*----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. + * Purely for reasons of backward compatibility the old method is still valid, but + * to make it clear that new projects should not use it, support for the port + * specific constants has been moved into the deprecated_definitions.h header + * file. */ +//#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h + * did not result in a portmacro.h header file being included - and it should be + * included here. In this case the path to the correct portmacro.h header file + * must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 64 + #define portBYTE_ALIGNMENT_MASK ( 0x003f ) +#endif + +#if portBYTE_ALIGNMENT == 32 + #define portBYTE_ALIGNMENT_MASK ( 0x001f ) +#endif + +#if portBYTE_ALIGNMENT == 16 + #define portBYTE_ALIGNMENT_MASK ( 0x000f ) +#endif + +#if portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) +#endif + +#if portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#endif + +#ifndef portBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "mpu_wrappers.h" + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif +#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #endif +#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + +/* Used by heap_5.c to define the start address and size of each memory region + * that together comprise the total FreeRTOS heap space. */ +typedef struct HeapRegion +{ + uint8_t * pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t * pxHeapStats ); + +/* + * Map to the memory management routines required for the port. + */ +void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void * pv ) PRIVILEGED_FUNCTION; +size_t xPortGetMemSize( void * pv ) PRIVILEGED_FUNCTION; +void * pvPortRealloc( void * pv, size_t xSize ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTABLE_H */ diff --git a/A58-STEPLDR/FreeRTOS/Source/include/projdefs.h b/A58-STEPLDR/FreeRTOS/Source/include/projdefs.h new file mode 100644 index 00000000..5a24244b --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/include/projdefs.h @@ -0,0 +1,120 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* + * Defines the prototype to which task functions must conform. Defined in this + * file to ensure the type is known before portable.h is included. + */ +typedef void (* TaskFunction_t)( void * ); + +/* Converts a time in milliseconds to a time in ticks. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdMS_TO_TICKS + #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) ) +#endif + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) +#define errQUEUE_EMPTY ( ( BaseType_t ) 0 ) +#define errQUEUE_FULL ( ( BaseType_t ) 0 ) + +/* FreeRTOS error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +/* Macros used for basic data corruption checks. */ +#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES + #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0 +#endif + +#if ( configUSE_16_BIT_TICKS == 1 ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a +#else + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL +#endif + +/* The following errno values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_ERRNO_NONE 0 /* No errors */ +#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */ +#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */ +#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */ +#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */ +#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */ +#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */ +#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */ +#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */ +#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */ +#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */ +#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */ +#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */ +#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */ +#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */ +#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */ +#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */ +#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */ +#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */ +#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */ +#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */ +#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */ +#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */ +#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */ +#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */ +#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */ +#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */ +#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */ +#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */ +#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */ +#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */ +#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */ +#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */ +#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */ +#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */ +#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */ +#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */ +#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */ +#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */ + +/* The following endian values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_LITTLE_ENDIAN 0 +#define pdFREERTOS_BIG_ENDIAN 1 + +/* Re-defining endian values for generic naming. */ +#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN +#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN + + +#endif /* PROJDEFS_H */ diff --git a/A58-STEPLDR/FreeRTOS/Source/list.c b/A58-STEPLDR/FreeRTOS/Source/list.c new file mode 100644 index 00000000..b5fa9c42 --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/list.c @@ -0,0 +1,198 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include +#include "FreeRTOS.h" +#include "list.h" + +/*----------------------------------------------------------- +* PUBLIC LIST API documented in list.h +*----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + /* The list structure contains a list item which is used to mark the + * end of the list. To initialise the list the list end is inserted + * as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + /* The list end value is the highest possible value in the list to + * ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + * when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + + /* Write known values into the list if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + + /* Write known values into the list item if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * const pxIndex = pxList->pxIndex; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + * makes the new list item the last item to be removed by a call to + * listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + pxIndex->pxPrevious = pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * pxIterator; + const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert the new list item into the list, sorted in xItemValue order. + * + * If the list already contains a list item with the same item value then the + * new list item should be placed after it. This ensures that TCBs which are + * stored in ready lists (all of which have the same xItemValue value) get a + * share of the CPU. However, if the xItemValue is the same as the back marker + * the iteration loop below will not end. Therefore the value is checked + * first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + pxIterator = pxList->xListEnd.pxPrevious; + } + else + { + /* *** NOTE *********************************************************** + * If you find your application is crashing here then likely causes are + * listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for + * more tips, and ensure configASSERT() is defined! + * https://www.FreeRTOS.org/a00110.html#configASSERT + * + * 1) Stack overflow - + * see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * 2) Incorrect interrupt priority assignment, especially on Cortex-M + * parts where numerically high priority values denote low actual + * interrupt priorities, which can seem counter intuitive. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition + * of configMAX_SYSCALL_INTERRUPT_PRIORITY on + * https://www.FreeRTOS.org/a00110.html + * 3) Calling an API function from within a critical section or when + * the scheduler is suspended, or calling an API function that does + * not end in "FromISR" from an interrupt. + * 4) Using a queue or semaphore before it has been initialised or + * before the scheduler has been started (are interrupts firing + * before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + { + /* There is nothing to do here, just iterating to the wanted + * insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + * item later. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ +/* The list item knows which list it is in. Obtain the list from the list + * item. */ + List_t * const pxList = pxItemToRemove->pxContainer; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + ( pxList->uxNumberOfItems )--; + + return pxList->uxNumberOfItems; +} +/*-----------------------------------------------------------*/ diff --git a/A58-STEPLDR/FreeRTOS/Source/portable/MemMang/heap_4.c b/A58-STEPLDR/FreeRTOS/Source/portable/MemMang/heap_4.c new file mode 100644 index 00000000..0958e073 --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/portable/MemMang/heap_4.c @@ -0,0 +1,545 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that combines + * (coalescences) adjacent memory blocks as they are freed, and in so doing + * limits memory fragmentation. + * + * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include +#include "FreeRTOS.h" + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + PRIVILEGED_DATA __no_init static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION; + +/* + * Called automatically to setup the required heap structures the first time + * pvPortMalloc() is called. + */ +static void prvHeapInit( void ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart, * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0; + +/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize + * member of an BlockLink_t structure is set then the block belongs to the + * application. When the bit is free the block is still part of the free heap + * space. */ +PRIVILEGED_DATA static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + //vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is + * set. The top bit of the block size member of the BlockLink_t structure + * is used to determine who owns the block - the application or the + * kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( ( xWantedSize > 0 ) && + ( ( xWantedSize + xHeapStructSize ) > xWantedSize ) ) /* Overflow check */ + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. Check for overflow. */ + if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) + > xWantedSize ) + { + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + //( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( unsigned int size ); + vApplicationMallocFailedHook(xWantedSize); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + //vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + //( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMemSize( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + return (pxLink->xBlockSize & ~xBlockAllocatedBit) - xHeapStructSize; + } + + return 0; +} +/*-----------------------------------------------------------*/ + +void * pvPortRealloc( void * pv, size_t xSize ) +{ + void * new_p = NULL; + uint32_t new_size; + uint32_t old_size = xPortGetMemSize(pv); + + new_size = xSize + (portBYTE_ALIGNMENT - (xSize & portBYTE_ALIGNMENT_MASK)); + if(old_size == new_size) return pv; /*Also avoid reallocating the same memory*/ + + new_p = pvPortMalloc(xSize); + if(new_p == NULL) { + return NULL; + } + + if(pv != NULL) { + /*Copy the old data to the new. Use the smaller size*/ + if(old_size != 0 && xSize != 0) { + int i; + uint8_t *psrc = pv; + uint8_t *pdst = new_p; + + for (i = 0; i < configMIN(xSize, old_size); i++) + pdst[i] = psrc[i]; + } + vPortFree(pv); + } + + return new_p; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */ + + //vTaskSuspendAll(); + { + pxBlock = xStart.pxNextFreeBlock; + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + do + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = pxBlock->pxNextFreeBlock; + } while( pxBlock != pxEnd ); + } + } + //( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + //taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + //taskEXIT_CRITICAL(); +} diff --git a/A58-STEPLDR/FreeRTOS/Source/portable/portASM.h b/A58-STEPLDR/FreeRTOS/Source/portable/portASM.h new file mode 100644 index 00000000..3f7d5848 --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/portable/portASM.h @@ -0,0 +1,113 @@ +;/* +; * FreeRTOS Kernel V10.4.3 +; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; * 1 tab == 4 spaces! +; */ + + EXTERN vTaskSwitchContext + EXTERN ulCriticalNesting + EXTERN pxCurrentTCB + EXTERN ulPortTaskHasFPUContext + EXTERN ulAsmAPIPriorityMask + +portSAVE_CONTEXT macro + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif ; configFPU_D32 + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + endm + +; /**********************************************************************/ + +portRESTORE_CONTEXT macro + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif ; configFPU_D32 + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. CPSR has the interrupt + ; enable bit set appropriately for the task about to execute. + RFEIA sp! + + endm + + + + + diff --git a/A58-STEPLDR/FreeRTOS/Source/portable/portmacro.h b/A58-STEPLDR/FreeRTOS/Source/portable/portmacro.h new file mode 100644 index 00000000..014d65d1 --- /dev/null +++ b/A58-STEPLDR/FreeRTOS/Source/portable/portmacro.h @@ -0,0 +1,166 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* IAR includes. */ +#ifdef __ICCARM__ + + #include + + #ifdef __cplusplus + extern "C" { + #endif + + /*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + /* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + + /*-----------------------------------------------------------*/ + + /* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #ifdef VG_DRIVER + #define portBYTE_ALIGNMENT 64 + #else + #define portBYTE_ALIGNMENT 32 + #endif + + /*-----------------------------------------------------------*/ + + /* Task utilities. */ + + /* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired )\ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm volatile ( "SWI 0" ); __ISB() + + + /*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */ + #define portENABLE_INTERRUPTS() __enable_irq() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */ + #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_interrupt_state(x) + + /*-----------------------------------------------------------*/ + + /* Task function macros as described on the FreeRTOS.org WEB site. These are + not required for this port but included in case common demo code that uses these + macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + /* Prototype of the FreeRTOS tick handler. This must be installed as the + handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + + /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + + /* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #define portNOP() __asm volatile( "NOP" ) + + + #ifdef __cplusplus + } /* extern C */ + #endif + + /* Suppress warnings that are generated by the IAR tools, but cannot be + fixed in the source code because to do so would cause other compilers to + generate warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + +#endif /* __ICCARM__ */ + +#endif /* PORTMACRO_H */ + diff --git a/A58-STEPLDR/Src/Boot.s b/A58-STEPLDR/Src/Boot.s new file mode 100644 index 00000000..e0d72439 --- /dev/null +++ b/A58-STEPLDR/Src/Boot.s @@ -0,0 +1,269 @@ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#define __ASSEMBLY__ + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +#define IRAM_BASE 0x300000 +#define SYS_CPU_CTL 0xe4900208 +#define AIC 0xFFFFF000 +#define AIC_IVR 0x10 +#define AIC_EOICR 0x38 + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + +/* + Exception vectors + */ +// SECTION .vectors:CODE:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + PUBLIC __vector + PUBLIC __iar_program_start + + ARM ; Always ARM mode after reset + +__vector: + ldr pc, Reset + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + IMPORT undef_handler + IMPORT swi_handler + IMPORT prefetch_handler + IMPORT data_abort_handler + IMPORT AIC_IrqHandler + IMPORT fiq_handler + +Reset: dc32 __iar_program_start +Undefined_Addr: dc32 undef_handler ;Undefined_Handler +SWI_Addr: dc32 swi_handler ;SWI_Handler +Prefetch_Addr: dc32 prefetch_handler ;ExceptionPAB +Abort_Addr: dc32 data_abort_handler ;ExceptionDAB +Reserved_Addr: dc32 0 ;ExceptionREV +IRQ_Addr: dc32 irqHandler +FIQ_Addr: dc32 fiq_handler + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + +CP_DIS_MASK DEFINE 0xFFFFEFFA + + SECTION .text:CODE:NOROOT(2) + EXTERN ?main + REQUIRE __vector + +__iar_program_start: + b reset_handler +// DCD 0x424b5241 +// DCD 0 +// DCD 0 + +reset_handler: +;================================================================== +; Reset registers +;================================================================== + MOV r2, #0 + MOV r3, #0 + MOV r4, #0 + MOV r5, #0 + MOV r6, #0 + MOV r7, #0 + MOV r8, #0 + MOV r9, #0 + MOV r10, #0 + MOV r11, #0 + MOV r12, #0 + +;================================================================== +; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +; This does not need to be done from a cold reset +;================================================================== + MRC p15, 0, r0, c1, c0, 0 ; Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + ;ORR r0, r0, #(0x1 << 12) ; Set I bit 12 to enable I Cache + BIC r0, r0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 ; Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 ; Write value back to CP15 System Control register + +;================================================================== +; Cache Invalidation code for Cortex-A7 +; NOTE: Neither Caches, nor MMU, nor BTB need post-reset invalidation on Cortex-A7, +; but forcing a cache invalidation, makes the code more portable to other CPUs (e.g. Cortex-A9) +;================================================================== + ; Invalidate L1 Instruction Cache + MRC p15, 1, r0, c0, c0, 1 ; Read Cache Level ID Register (CLIDR) + TST r0, #0x3 ; Harvard Cache? + MOV r0, #0 ; SBZ + MCRNE p15, 0, r0, c7, c5, 0 ; ICIALLU - Invalidate instruction cache and flush branch target cache + + ; Invalidate Data/Unified Caches + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ Finished ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +Loop1 ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT Skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +Loop2 MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +Loop3 ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 ; Invalidate by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE Loop3 + SUBS r7, r7, #1 ; Decrement the Set number + BGE Loop2 +Skip ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT Loop1 + +Finished + +;================================================================== +; Invalidate TLB +;================================================================== + MOV r0, #0 + MCR p15, 0, r0, c8, c7, 0 + +;================================================================== +; Branch Prediction Enable +;================================================================== + ;MOV r1, #0 + ;MRC p15, 0, r1, c1, c0, 0 /* Read Control Register configuration data */ + ;ORR r1, r1, #(0x1 << 11) /* Global BP Enable bit */ + ;MCR p15, 0, r1, c1, c0, 0 /* Write Control Register configuration data */ + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. + mrs r0,cpsr ; Original PSR value + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#SVC_MODE ; Set Supervisor mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#ABT_MODE ; Set Abort mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#UND_MODE ; Set Undefined mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(UND_STACK) ; End of UND_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#FIQ_MODE ; Set FIR mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#IRQ_MODE ; Set IRQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + bic r0,r0,#MODE_MSK ; Clear the mode bits + orr r0,r0,#SYS_MODE ; Set System mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(CSTACK) ; End of CSTACK + + /* Branch to main() */ + LDR r0, =?main + BLX r0 + + /* Loop indefinitely when program is finished */ +loop4: + B loop4 + + +/* + Handles incoming interrupt requests by branching to the corresponding + handler, as defined in the AIC. Supports interrupt nesting. + */ + +irqHandler: + NOP + NOP + ;/* IRQ entry {{{ */ /* save r0 in r13_IRQ */ + SUB lr,lr,#4 /* put return address in r0_SYS */ + STMFD sp!,{lr} /* save r1 in r14_IRQ (lr) */ + MRS lr,spsr /* put the SPSR in r1_SYS */ + STMFD sp!,{r0,lr} + ldr r0, = AIC_IrqHandler + ; ldr r0, [r0]; + MSR cpsr_c,#(ARM_MODE_SYS | I_BIT) /* SYSTEM, no IRQ, but FIQ enabled! */ /* save SPSR and PC on SYS stack */ + // mcr p15, 0, r0, c7, c10, 5 + STMFD sp!, {r1-r3, r4, r12, lr} /* save all other regs on SYS stack */ + AND r1, sp, #4 + SUB sp, sp, r1 + STMFD sp!, {r1, lr} + BLX r0 + LDMIA sp!, {r1, lr} + ADD sp, sp, r1 + LDMIA sp!, {r1-r3, r4, r12, lr} + MSR CPSR_c, #ARM_MODE_IRQ | I_BIT + LDMIA sp!, {r0, lr} + MSR SPSR_cxsf, lr + LDMIA sp!, {pc}^ + + + END + \ No newline at end of file diff --git a/A58-STEPLDR/Src/CommonDef.inc b/A58-STEPLDR/Src/CommonDef.inc new file mode 100644 index 00000000..a8daaedf --- /dev/null +++ b/A58-STEPLDR/Src/CommonDef.inc @@ -0,0 +1,58 @@ +;Pre-defined run mode constants +USERMODE EQU 0x10 +FIQMODE EQU 0x11 +IRQMODE EQU 0x12 +SVCMODE EQU 0x13 +ABORTMODE EQU 0x17 +UNDEFMODE EQU 0x1b +MODEMASK EQU 0x1f +NOINT EQU 0xc0 + + +;Stacks defination for each run mode +_STACK_BASEADDRESS EQU 0xC0008000 + +UserStackLen EQU 0x10 +SVCStackLen EQU 0x2000 +UndefStackLen EQU 0x10 +AbortStackLen EQU 0x10 +IRQStackLen EQU 0x400 +FIQStackLen EQU 0x10 + +UserStackStart EQU (_STACK_BASEADDRESS) +UndefStackStart EQU (UserStackStart - UserStackLen) +AbortStackStart EQU (UndefStackStart - UndefStackLen) +IRQStackStart EQU (AbortStackStart - AbortStackLen) +FIQStackStart EQU (IRQStackStart - IRQStackLen) +SVCStackStart EQU (FIQStackStart - FIQStackLen) + + +VICL_BASE EQU 0xE0C00000 +VICH_BASE EQU 0xE0B00000 +ENABLE_REG_OFFSET EQU 0x10 +CLR_REG_OFFSET EQU 0x14 +ADDRESS_REG_OFFSET EQU 0xF00 +VICL_RAW_STATUS EQU 0xE0C00008 ;Interrupt raw status low 32 vector +VICH_RAW_STATUS EQU 0xE0B00008 ;Interrupt raw status high 32 vector +VICL_SEL_REG EQU 0xE0C0000C ;Interrupt select reg for low 32 vector +VICH_SEL_REG EQU 0xE0B0000C ;Interrupt select reg for high 32 vector +VICL_ENABLE EQU 0xE0C00010 ;Interrupt Enable control low 32 vector +VICH_ENABLE EQU 0xE0B00010 ;Interrupt Enable control high 32 vector +VICL_CLR EQU 0xE0C00014 ;Interrupt clear control low 32 vector +VICH_CLR EQU 0xE0B00014 ;Interrupt clear control high 32 vector +VICL_ADDR_BASE EQU 0xE0C00100 +VICH_ADDR_BASE EQU 0xE0B00100 +VICL_PROORITY_BASE EQU 0xE0C00200 +VICH_PROORITY_BASE EQU 0xE0B00200 + +;ENABLE_VE EQU 0x01000000 +VICL_ADDRESS EQU 0xE0C00F00 +VICH_ADDRESS EQU 0xE0B00F00 + + +WDT_CTL EQU 0xE4B00000 + +ITCM0_BaseAddress EQU 0xA0000000 ;ITCM0 base : 0xA0000000, Size : 8KB, +ITCM1_BaseAddress EQU 0xA0002000 ;ITCM1 base : 0xA0002000, Size : 8KB, +DTCM0_BaseAddress EQU 0xA0004000 ;DTCM0 base : 0xA0004000, Size : 8KB, +DTCM1_BaseAddress EQU 0xA0006000 ;DTCM1 base : 0xA0006000, Size : 8KB, diff --git a/A58-STEPLDR/Src/Entry.c b/A58-STEPLDR/Src/Entry.c new file mode 100644 index 00000000..2ff265f5 --- /dev/null +++ b/A58-STEPLDR/Src/Entry.c @@ -0,0 +1,393 @@ +/* +********************************************************************** +Copyright (c)2021 Arkmicro Technologies Inc. All Rights Reserved +Filename: Entry.c +Version : 1.00 +Date : 2021.08.20 +Author : Sim +*********************************************************************** +*/ +#include "typedef.h" +#include "amt630h.h" +#include "uart.h" +#include "timer.h" +#include "aic.h" +#include "mmu.h" +#include "lcd.h" +#include "spi.h" +#include "sysinfo.h" +#include "sysctl.h" +#include "board.h" +#include "fs/ff.h" +#include "fs/diskio.h" +#include "crc32.h" +#include "sdmmc.h" + +#include + +extern void bootFromSPI(void); +extern void updateFromSD(int chipid); +extern void updateFromUSB(void); +int wdt_init(void); +void wdt_stop(void); +void wdt_start(void); + +static SysInfo *pSysInfo = NULL; + +void UpdateFromMedia(int drv) +{ + FRESULT fret; + FIL fp = {0}; + UINT32 size; + unsigned int checksum, calc_checksum; + int timeout = 0; + int update_ok = 0; + SysInfo *sysinfo = GetSysInfo(); +#if DEVICE_TYPE_SELECT == EMMC_FLASH + char launchemmcfile[32]; +#endif + char loaderfile[32]; + char stepldrfile[32]; + char appfile[32]; + FILINFO fileinfo = {0}; + int leftsize; + + if (drv == SDMMC) { + strcpy(loaderfile, LOADER_FILE_NAME); + strcpy(stepldrfile, STEPLDR_FILE_NAME); + strcpy(appfile, APP_FILE_NAME); + } else if (drv == USB) { +#if DEVICE_TYPE_SELECT == EMMC_FLASH + strcpy(launchemmcfile, "1:/"); + strcat(launchemmcfile, LAUNCHEMMC_FILE_NAME); +#endif + strcpy(loaderfile, "1:/"); + strcat(loaderfile, LOADER_FILE_NAME); + strcpy(stepldrfile, "1:/"); + strcat(stepldrfile, STEPLDR_FILE_NAME); + strcpy(appfile, "1:/"); + strcat(appfile, APP_FILE_NAME); + } else { + SendUartString("Unknown disk drv\r\n"); + return; + } + + fret = f_mount(drv, &g_fs); + if(fret == FR_OK) + SendUartString("Mount file ok\r\n"); + else + { + SendUartString("Mount file fail\r\n"); + return; + } + +#if DEVICE_TYPE_SELECT == EMMC_FLASH + SendUartString("burn emmc launcher start... \r\n"); +readlaunchemmc: + fret = f_open(&fp, launchemmcfile, FA_OPEN_EXISTING | FA_READ); + if(fret != FR_OK) { + SendUartString("Open file fail, don't update.\r\n"); + } else { + fret = f_read(&fp, (void *)IMAGE_ENTRY, LOADER_MAX_SIZE, &size); + f_close(&fp); + if(fret != FR_OK) { + if (timeout++ < 3) { + SendUartString("Read file fail, read again.\r\n"); + goto readlaunchemmc; + } + } else { + checksum = *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET); + *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET) = 0; + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, size, 0xffffffff); + *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET) = checksum; + if (calc_checksum != checksum) { + if (timeout++ < 3) { + SendUartString("read step emmc checksum fail, read again.\n"); + goto readlaunchemmc; + } + else { + SendUartString("read step emmc fail, don't update.\n"); + } + } else { + if (FlashBurn((void*)IMAGE_ENTRY, LOADER_OFFSET, size, 0)) { + SendUartString("burn step emmc fail.\n"); + goto end; + } + } + } + } + SendUartString("burn emmc launcher end. \r\n"); +#endif + + SendUartString("burn loader start... \r\n"); +readloader: + fret = f_open(&fp, loaderfile, FA_OPEN_EXISTING | FA_READ); + if(fret != FR_OK) { + SendUartString("Open file fail, don't update.\r\n"); + } else { + fret = f_read(&fp, (void *)IMAGE_ENTRY, LOADER_MAX_SIZE, &size); + f_close(&fp); + if(fret != FR_OK) { + if (timeout++ < 3) { + SendUartString("Read file fail, read again.\r\n"); + goto readloader; + } + } else { + checksum = *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET); + *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET) = 0; + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, size, 0xffffffff); + *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET) = checksum; + if (calc_checksum != checksum) { + if (timeout++ < 3) { + SendUartString("read loader checksum fail, read again.\n"); + goto readloader; + } + else { + SendUartString("read loader fail, don't update.\n"); + } + } else { +#if DEVICE_TYPE_SELECT != EMMC_FLASH + if (FlashBurn((void*)IMAGE_ENTRY, LOADER_OFFSET, size, 0)) { + SendUartString("burn loader fail.\n"); + goto end; + } +#else + if (sysinfo->loader_offset == LOADER_OFFSET) + sysinfo->loader_offset = LOADERB_OFFSET; + else + sysinfo->loader_offset = LOADER_OFFSET; + sysinfo->loader_size = size; + if (EmmcBurn((void*)IMAGE_ENTRY, sysinfo->loader_offset, size, 0)) { + SendUartString("burn emmc loader fail.\n"); + goto end; + } + +#endif + } + } + } + SendUartString("burn loader end. \r\n"); + + timeout = 0; + SendUartString("burn stepldr start... \r\n"); +readstepldr: + fret = f_open(&fp, stepldrfile, FA_OPEN_EXISTING | FA_READ); + if(fret != FR_OK) { + SendUartString("Open file fail, don't update.\r\n"); + } else { + fret = f_read(&fp, (void *)IMAGE_ENTRY, STEPLDR_MAX_SIZE, &size); + f_close(&fp); + if(fret != FR_OK) { + if (timeout++ < 3) { + SendUartString("Read file fail, read again.\r\n"); + goto readstepldr; + } else { + SendUartString("read stepldr fail, don't update.\n"); + } + } else { + checksum = *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET); + *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET) = 0; + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, size, 0xffffffff); + *(unsigned int*)(IMAGE_ENTRY + APPLDR_CHECKSUM_OFFSET) = checksum; + if (calc_checksum != checksum) { + if (timeout++ < 3) { + SendUartString("read stepldr checksum fail, read again.\n"); + goto readstepldr; + } + else { + SendUartString("read stepldr fail, don't update.\n"); + } + } else { + if (sysinfo->stepldr_offset == STEPLDRA_OFFSET) + sysinfo->stepldr_offset = STEPLDRB_OFFSET; + else + sysinfo->stepldr_offset = STEPLDRA_OFFSET; + sysinfo->stepldr_size = size; +#if DEVICE_TYPE_SELECT != EMMC_FLASH + if (FlashBurn((void*)IMAGE_ENTRY, sysinfo->stepldr_offset, size, 0)) { + SendUartString("burn stepldr fail.\n"); + goto end; + } +#else + if (EmmcBurn((void*)IMAGE_ENTRY, sysinfo->stepldr_offset, size, 0)) { + SendUartString("burn emmc stepldr fail.\n"); + goto end; + } + +#endif + } + } + } + SendUartString("burn stepldr end. \r\n"); + + timeout = 0; + SendUartString("burn app start... \r\n"); + update_logo_init(); + SendUartString("A274.5 PWM2 .\r\n"); + gpio_direction_output(6,1); +readapp: + fret = f_stat(appfile, &fileinfo); + if (fret != FR_OK) { + SendUartString("Get file info fail, don't update.\r\n"); + goto end; + } + leftsize = fileinfo.fsize; +#if DEVICE_TYPE_SELECT == EMMC_FLASH + if (sysinfo->image_offset == IMAGE_OFFSET) + sysinfo->image_offset = IMAGEB_OFFSET; + else + sysinfo->image_offset = IMAGE_OFFSET; + if(leftsize) + { + unsigned int start = sysinfo->image_offset; + unsigned int blkcnt; + unsigned int blkstart; + if(start % 512) + blkstart = start / 512 + 1; + else + blkstart = start / 512; + + if(fileinfo.fsize % 512) + blkcnt = fileinfo.fsize / 512 + 1; + else + blkcnt = fileinfo.fsize / 512; + + mmc_berase(blkstart, blkcnt); + } +#endif + + fret = f_open(&fp, appfile, FA_OPEN_EXISTING | FA_READ); + if(fret != FR_OK) { + SendUartString("Open file fail, don't update.\r\n"); + } else { + UpFileHeader *header = (UpFileHeader *)IMAGE_ENTRY; +#if DEVICE_TYPE_SELECT != EMMC_FLASH + UINT32 woff = IMAGE_OFFSET; +#else + UINT32 woff = sysinfo->image_offset; +#endif + UINT32 app_size; + + while (leftsize > 0) { + fret = f_read(&fp, (void *)IMAGE_ENTRY, IMAGE_READ_SIZE, &size); + if(fret != FR_OK) { + SendUartString("Read file fail\r\n"); + if (timeout++ < 3) { + SendUartString("Read file fail, read again.\r\n"); + f_close(&fp); + goto readapp; + } else { + SendUartString("read update file fail, don't update.\n"); + } + } else { + if (leftsize == fileinfo.fsize) { + calc_checksum = 0xffffffff; + checksum = header->checksum; + header->checksum = 0; + app_size = header->files[0].size; + } + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, size, calc_checksum); + if (leftsize == fileinfo.fsize) + header->checksum = checksum; +#if DEVICE_TYPE_SELECT != EMMC_FLASH + if(FlashBurn((void*)IMAGE_ENTRY, woff, size, 0)) { + SendUartString("burn app fail.\n"); + f_close(&fp); + goto end; + } +#else + if (mmc_write((void*)IMAGE_ENTRY, woff, size, 0)) { + SendUartString("burn app fail.\n"); + f_close(&fp); + goto end; + } +#endif + update_progress_set(100 - leftsize * 100 / fileinfo.fsize); + } + woff += size; + leftsize -= size; + } + f_close(&fp); + update_progress_set(100); + if (calc_checksum != checksum) { + SendUartString("app checksum fail, update again.\n"); + } else { + sysinfo->app_checksum = header->checksum = checksum; + sysinfo->app_size = app_size; + update_ok = 1; + } + } + SendUartString("burn app end.\r\n"); + + if (update_ok) { + SendUartString("update ok, save sysinfo.\r\n"); + sysinfo->update_status = UPDATE_STATUS_END; + SaveSysInfo(sysinfo); + } +end: + SendUartString("Update is finished.\r\n"); +} + + + +void main(void) +{ + wdt_init(); + timer_init(); + AIC_Initialize(); + InitUart(115200); + SendUartString("ARK AMT630HV100 STEPLDR V 1.0\r\n"); +#ifdef MMU_ENABLE + MMU_Init(); +#endif + SendUartString("HS VS >> GPIO .\r\n"); + vSysctlConfigure(SYS_PAD_CTRL05, 20, 0x0f, 0x00); + gpio_direction_output(90,0); + gpio_direction_output(91,0); + + if(SpiInit()) { + SendUartString("SpiInit failed.\n"); + while(1); + } +#if DEVICE_TYPE_SELECT == EMMC_FLASH + Emmcinit(0); +#endif + + if (ReadSysInfo()) { + SendUartString("read sysinfo fail, use default.\r\n"); + SetDefaultSysInfo(); + } + + pSysInfo = GetSysInfo(); + //pSysInfo->update_status = UPDATE_STATUS_START; + //pSysInfo->update_media_type = UPDATE_MEDIA_USB; + if (pSysInfo->update_status == UPDATE_STATUS_START) { + lcd_init(); + wdt_stop(); + switch (pSysInfo->update_media_type) { + case UPDATE_MEDIA_SD: + updateFromSD(0); + break; +#ifdef USB_SUPPORT + case UPDATE_MEDIA_USB: + __enable_irq(); + extern int ark_usb_init(void); + if (!ark_usb_init()) + UpdateFromMedia(USB); + break; +#endif + case UPDATE_MEDIA_UART: + __enable_irq(); + updateFromUart(UART_MCU_PORT); + break; + } + wdt_start(); + } + + __disable_irq(); +#if DEVICE_TYPE_SELECT != EMMC_FLASH + bootFromSPI(); +#else + bootFromEmmc(0); +#endif +} diff --git a/A58-STEPLDR/Src/SpiBooter.c b/A58-STEPLDR/Src/SpiBooter.c new file mode 100644 index 00000000..d2bfa9c7 --- /dev/null +++ b/A58-STEPLDR/Src/SpiBooter.c @@ -0,0 +1,1160 @@ +#include +#include "typedef.h" +#include "amt630h.h" +#include "uart.h" +#include "timer.h" +#include "gpio.h" +#include "spi.h" +#include "cp15.h" +#include "sysinfo.h" +#include "crc32.h" +#include "update.h" +#include "board.h" +#include "os_adapt.h" + +#if DEVICE_TYPE_SELECT == SPI_NOR_FLASH || DEVICE_TYPE_SELECT == EMMC_FLASH +#define SPI_CS_GPIO 32 + +#define SPI_RXFIFO_FULL (1<<4) +#define SPI_RXFIFO_NOTEMPTY (1<<3) +#define SPI_TXFIFO_EMPTY (1<<2) +#define SPI_TXFIFO_NOTFULL (1<<1) +#define SPIFLASH_BUSY (1<<0) + +/* SFUD support manufacturer JEDEC ID */ +#define SFUD_MF_ID_CYPRESS 0x01 +#define SFUD_MF_ID_FUJITSU 0x04 +#define SFUD_MF_ID_EON 0x1C +#define SFUD_MF_ID_ATMEL 0x1F +#define SFUD_MF_ID_MICRON 0x20 +#define SFUD_MF_ID_AMIC 0x37 +#define SFUD_MF_ID_SANYO 0x62 +#define SFUD_MF_ID_INTEL 0x89 +#define SFUD_MF_ID_ESMT 0x8C +#define SFUD_MF_ID_FUDAN 0xA1 +#define SFUD_MF_ID_HYUNDAI 0xAD +#define SFUD_MF_ID_SST 0xBF +#define SFUD_MF_ID_MICRONIX 0xC2 +#define SFUD_MF_ID_GIGADEVICE 0xC8 +#define SFUD_MF_ID_ISSI 0xD5 +#define SFUD_MF_ID_WINBOND 0xEF + +int SpiNorBurn(void *buf, unsigned int offset, unsigned int size, int show_progress); +extern void wdt_cpu_reboot(void); +static void SpiWriteEnable(void); + +/* flash chip information */ +typedef struct { + char *name; /**< flash chip name */ + uint8_t mf_id; /**< manufacturer ID */ + uint8_t type_id; /**< memory type ID */ + uint8_t capacity_id; /**< capacity ID */ + uint32_t capacity; /**< flash capacity (bytes) */ +} flash_chip; + +static const flash_chip flash_chip_table[] = +{ + {"W25Q40BV", SFUD_MF_ID_WINBOND, 0x40, 0x13, 512L*1024L}, + {"W25Q16BV", SFUD_MF_ID_WINBOND, 0x40, 0x15, 2L*1024L*1024L}, + {"W25Q32BV", SFUD_MF_ID_WINBOND, 0x40, 0x16, 4L*1024L*1024L}, + {"W25Q64CV", SFUD_MF_ID_WINBOND, 0x40, 0x17, 8L*1024L*1024L}, + {"W25Q64DW", SFUD_MF_ID_WINBOND, 0x60, 0x17, 8L*1024L*1024L}, + {"W25Q128BV", SFUD_MF_ID_WINBOND, 0x40, 0x18, 16L*1024L*1024L}, + {"W25Q256FV", SFUD_MF_ID_WINBOND, 0x40, 0x19, 32L*1024L*1024L}, + {"W25H256JV", SFUD_MF_ID_WINBOND, 0x90, 0x19, 32L*1024L*1024L}, + {"W25Q512JVFM", SFUD_MF_ID_WINBOND, 0x70, 0x20, 64L*1024L*1024L}, + {"SST25VF080B", SFUD_MF_ID_SST, 0x25, 0x8E, 1L*1024L*1024L}, + {"SST25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2L*1024L*1024L}, + {"EN25Q32B", SFUD_MF_ID_EON, 0x30, 0x16, 4L*1024L*1024L}, + {"GD25Q64B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x17, 8L*1024L*1024L}, + {"GD25Q16B", SFUD_MF_ID_GIGADEVICE, 0x40, 0x15, 2L*1024L*1024L}, + {"GD25Q32C", SFUD_MF_ID_GIGADEVICE, 0x40, 0x16, 4L*1024L*1024L}, + {"S25FL216K", SFUD_MF_ID_CYPRESS, 0x40, 0x15, 2L*1024L*1024L}, + {"S25FL032P", SFUD_MF_ID_CYPRESS, 0x02, 0x15, 4L*1024L*1024L}, + {"A25L080", SFUD_MF_ID_AMIC, 0x30, 0x14, 1L*1024L*1024L}, + {"F25L004", SFUD_MF_ID_ESMT, 0x20, 0x13, 512L*1024L}, + {"PCT25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2L*1024L*1024L}, + {"IS25LP128F", SFUD_MF_ID_ISSI, 0x60, 0x18, 16L*1024L*1024L}, + {"MX25L6433F", SFUD_MF_ID_MICRONIX, 0x20, 0x17, 8L*1024L*1024L}, + {"MX25L12845G", SFUD_MF_ID_MICRONIX, 0x20, 0x18, 16L*1024L*1024L}, + {"MX25L25645G", SFUD_MF_ID_MICRONIX, 0x20, 0x19, 32L*1024L*1024L}, + {"W25Q512JVFM", SFUD_MF_ID_WINBOND, 0x70, 0x20, 64L*1024L*1024L}, + {"GD25B512ME", SFUD_MF_ID_GIGADEVICE, 0x47, 0x1A, 64L*1024L*1024L}, +}; + +static int addr_in_4_byte = 0; + +static void SetCSGpioEnable(int enable) +{ + gpio_direction_output(SPI_CS_GPIO, !enable); +} + +static void SetSpiDataMode(unsigned int bitMode) +{ + unsigned int val = 0; + + (void)val; + while((rSPI_SR & SPI_BUSY)); + rSPI_SSIENR = 0; + val = rSPI_CTLR0; + val &=~(0x1f<<16); + val |=((bitMode-1)<<16); + rSPI_CTLR0 = val; + rSPI_SSIENR = 1; +} + +static void SpiWaitIdle(void) +{ + while(rSPI_SR & SPIFLASH_BUSY); + udelay(2); +} + +static void SpiEmptyRxFIFO(void) +{ + INT32 data = 0; + + (void)data; + + while(rSPI_SR & SPI_RXFIFO_NOTEMPTY) + data = rSPI_DR; +} + +#ifdef SPI0_QSPI_MODE +static void SpiWriteSta2(uint8_t status) +{ + SpiWriteEnable(); + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_WRITE_STATUS2; + rSPI_DR = status; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static UINT8 SpiReadSta2(void) +{ + UINT8 status; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_READ_STATUS2; + rSPI_DR = 0; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + PrintVariableValueHex("status s2 :", status); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + return status; +} +#endif + +static UINT8 SpiReadSta3(void) +{ + UINT8 status; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_READ_STATUS3; + rSPI_DR = 0; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + PrintVariableValueHex("status s3 :", status); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + return status; +} + +static UINT8 SpiReadSta(void) +{ + UINT8 status; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_READ_STATUS; + rSPI_DR = 0; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + status = rSPI_DR; + //PrintVariableValueHex("status:", status); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + return status; +} +static void SpiWriteSta(uint8_t status) +{ + SpiWriteEnable(); + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_WRITE_STATUS; + rSPI_DR = status; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} +static void SpiDisable4ByteMode(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_DISABLE_4BYTE_MODE; + while(!(rSPI_SR & SPI_TXFIFO_EMPTY)); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiEnable4ByteMode(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_ENABLE_4BYTE_MODE; + while(!(rSPI_SR & SPI_TXFIFO_EMPTY)); + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiReadPage(UINT32 pagenum, UINT32 *buf) +{ + UINT32 addr; + UINT32 val = 0; + INT32 i, j; + UINT8 tmpaddr[4]; + UINT8 *data = (UINT8*)buf; + + (void)val; + + addr = pagenum*BYTESPERPAGE; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiEmptyRxFIFO(); + SetCSGpioEnable(1); + + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADDR_READ_DATA; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + for (i = 0; i < 5; i++) { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val = rSPI_DR; + } + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_READ_DATA; + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val = rSPI_DR; + } + + if (addr_in_4_byte) { + for (i = 0; i < 4; i++) { + for (j = 0; j < WORDSPERPAGE; j++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = 0; + } + for (j = 0; j < WORDSPERPAGE; j++) { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + *data++ = rSPI_DR; + } + } + } else { + for (i = 0; i < WORDSPERPAGE; i++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = 0; + } + for(i = 0; i < WORDSPERPAGE; i++) { + while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + *buf++ = rSPI_DR; + } + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + if (addr_in_4_byte) + SetSpiDataMode(32); +} + +#ifdef SPI0_QSPI_MODE +//********format********* +//00 – Standard SPI Format +// 01 – Dual SPI Format +// 10 – Quad SPI Format +// 11 – Reserved +//********tmod********** +//00 –- Transmit & Receive +//01 –- Transmit Only +//10 –- Receive Only +//11 –- EEPROM Read +static void SpiSetFrameFormatMode(unsigned char format, unsigned char tmod) +{ + unsigned int val = 0; + + while((rSPI_SR & SPI_BUSY)); + rSPI_SSIENR = 0; + val = rSPI_CTLR0; + val &= ~((0x3 << 21) | (0x3 << 8)); + val |= ((format << 21) | (tmod << 8)); + rSPI_CTLR0 = val; + rSPI_SSIENR = 1; +} + +static void SpiReadPageQuadMode(UINT32 pagenum, UINT32 *buf) +{ + UINT32 addr; + UINT32 val = 0; + INT32 i; + UINT8 tmpaddr[4]; + + (void)val; + + addr = pagenum*BYTESPERPAGE; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiEmptyRxFIFO(); + SetCSGpioEnable(1); + + SpiSetFrameFormatMode(2, 2); + rSPI_SSIENR = 0; + if (addr_in_4_byte) { + //set instruction 8bits,1byte mode; addr 32bit,4bytes mode; 6 dummy clocks + rSPI_SPI_CTRLR0 = (6 << 11) | (2 << 8) | (8 << 2) | 1; + rSPI_CTLR1 = WORDSPERPAGE - 1; + rSPI_SSIENR = 1; + + rSPI_DR = SPI_QUAD_IO_READ_DATA + 1; + rSPI_DR = (tmpaddr[0] << 24) | (tmpaddr[1] << 16) | (tmpaddr[2] << 8) | tmpaddr[3]; + } else { + //set instruction 8bits,1byte mode; addr 24bit,4bytes mode; 6 dummy clocks + rSPI_SPI_CTRLR0 = (6 << 11) | (2 << 8) | (6 << 2) | 1; + rSPI_CTLR1 = WORDSPERPAGE - 1; + rSPI_SSIENR = 1; + + rSPI_DR = SPI_QUAD_IO_READ_DATA; + rSPI_DR = (tmpaddr[0] << 16) | (tmpaddr[1] << 8) | (tmpaddr[2] << 0); + } + + for(i=0; i 0x1000000) { + addr_in_4_byte = 1; + SpiEnable4ByteMode(); + } + break; + } + } + + if (!addr_in_4_byte) + SpiDisable4ByteMode(); + +#ifdef SPI0_QSPI_MODE + if((iupgrade_appsize; //根据串口升级的协议获取 + new_appoffset = NEW_APPFOOSET; //升级的程序固定写在这个地址，预留3M + int uup_file_type = sysinfo->reserved[9]; + if(uup_file_type == UPFILE_TYPE_APP){ + imageoff = AMT630_BIN_OFFSET; //固定的 运行区固定地址 + }else if(uup_file_type == UPFILE_TYPE_ANIMATION){ + imageoff = BOOTANIM_BIN_OFFSET; //固定的 运行区固定地址 + }else if(uup_file_type == UPFILE_TYPE_RESOURCE){ + imageoff = ROM_BIN_OFFSET; + } + //imageoff = AMT630_BIN_OFFSET; //固定的 运行区固定地址 + + SendUartString("start copy flash ok.\n"); + + //SpiReadPage(NEW_APPFOOSET / BYTESPERPAGE, buf); + count_max = new_appsize/IMAGE_RW_SIZE; + PrintVariableValueHex("max i ", count_max); + for(i=0;ichecksum; + pheader->checksum = 0; + }else if (uup_file_type == UPFILE_TYPE_RESOURCE) {//资源文件 + RomHeader *pheader = (RomHeader *)uup_buf; + appchecksum = pheader->checksum; + pheader->checksum = 0; + } + // unsigned int *tmp = (unsigned int *)(uup_buf + NEW_APPLDR_CHECKSUM_OFFSET); + // appchecksum=*tmp; + // *tmp=0; + calchecksum = xcrc32(uup_buf, IMAGE_RW_SIZE, 0xffffffff); + PrintVariableValueHex("appchecksum ", appchecksum); + PrintVariableValueHex("calchecksum ", calchecksum); + } + else + { + calchecksum = xcrc32(uup_buf, IMAGE_RW_SIZE, calchecksum); + // PrintVariableValueHex("calchecksum", calchecksum); + } + } + if(new_appsize%IMAGE_RW_SIZE)//若最后一包数据不满0x10000 则存数据并且继续计算校验和 + { + // PrintVariableValueHex("update_progress_set ", 99); + update_progress_set(99); + uint32_t red_add,wri_add,size,count; + int k; + uup_buf_len = 0; + count = (new_appsize%IMAGE_RW_SIZE )/0x1000; + red_add = NEW_APPFOOSET+new_appsize- new_appsize%IMAGE_RW_SIZE; + wri_add = imageoff+new_appsize- new_appsize%IMAGE_RW_SIZE; + size = 0x1000; + // PrintVariableValueHex("max k ", count); + for(k=0;kupgrade_flag){//若最后一包数据不满0x1000 则存数据并且继续计算校验和 + uint32_t add,add_size; + add = sysinfo->upgrade_flag/256; + add_size = sysinfo->upgrade_flag%256; + uup_buf_len = 0; + for(j=0;jupgrade_flag, 0); + uup_buf_len = 0; + + calchecksum = xcrc32(uup_buf, sysinfo->upgrade_flag, calchecksum); + // PrintVariableValueHex("end calchecksum", calchecksum); + } + + } + // PrintVariableValueHex("update_progress_set ", 100); + update_progress_set(100); + // SendUartString("end flash copy.\n"); + + PrintVariableValueHex("calchecksum", calchecksum); + PrintVariableValueHex("appchecksum", appchecksum); + + // if(calchecksum==appchecksum) + // { + // SendUartString("crc32 OK\n"); + sysinfo = GetSysInfo(); + if (uup_file_type == UPFILE_TYPE_APP) //代码文件 + sysinfo->app_size = new_appsize; + sysinfo->image_offset=0x40000; + sysinfo->upgrade_flag = 0; + sysinfo->upgrade_appsize =0; + sysinfo->reserved[9] =0; + SaveSysInfo(sysinfo); + wdt_cpu_reboot(); + return 0; + + // } + // else + // { + // SendUartString("crc32 ERROR\n"); + // return -1; + // } + +} + + +static void SpiLoadImage(void (*readfunc)(UINT32, UINT32 *)) +{ + unsigned int i = 0; + UINT32 *buf = (UINT32*)IMAGE_ENTRY; + UpFileHeader *header; + UpFileInfo *appfile; + UINT32 nPageCount; + UINT32 nPageStart; + UINT32 appsize; + SysInfo *sysinfo = GetSysInfo(); + + PrintVariableValueHex("image_offset", sysinfo->image_offset); + readfunc(sysinfo->image_offset / BYTESPERPAGE, buf); + header = (UpFileHeader*)buf; + appfile = &header->files[0]; + if (appfile->offset & (BYTESPERPAGE - 1)) { + SendUartString("\nImage positon is not align to flash pagesize, can't load.\r\n"); + while(1); + } + + if (sysinfo->app_size) + appsize = sysinfo->app_size; + else + appsize = appfile->size; + PrintVariableValueHex("appsize", appsize); + nPageCount = (appsize + BYTESPERPAGE - 1) / BYTESPERPAGE; + nPageStart = (appfile->offset + sysinfo->image_offset) / BYTESPERPAGE; + for(i = nPageStart; i < nPageStart + nPageCount; i++) + { + readfunc(i, buf); + buf += BYTESPERPAGE/4; + } + + PrintVariableValueHex("upgrade_flag", sysinfo->upgrade_flag); + PrintVariableValueHex("upgrade_appsize", sysinfo->upgrade_appsize); + PrintVariableValueHex("checksum", sysinfo->checksum); + if(sysinfo->upgrade_flag !=0 && sysinfo->upgrade_appsize!=0 ){ + if(sysinfo->upgrade_flag == 0xffffffff && sysinfo->upgrade_appsize == 0xffffffff){ + SysInfo *sysinfo = GetSysInfo(); + sysinfo->upgrade_flag = 0; + sysinfo->upgrade_appsize =0; + SaveSysInfo(sysinfo); + }else{ + lcd_init(); + wdt_stop(); + SendUartString("update_logo_init... \r\n"); + update_logo_init(); + SendUartString("PWM2 .\r\n"); + gpio_direction_output(6,1); + flash_copy_demo(); + wdt_start(); + } + } + +#ifdef MMU_ENABLE + CP15_clean_dcache_for_dma(IMAGE_ENTRY, IMAGE_ENTRY + appsize); +#endif +} + +static void SpiWriteEnable(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_WRITE_ENABLE; + SpiWaitIdle(); + SetCSGpioEnable(0); + while((SpiReadSta() & SPI_BUSY)); + while(!(SpiReadSta() & SPIFLASH_WRITEENABLE)); + SetSpiDataMode(32); +} + +static void SpiEraseSector(UINT32 sectorNum) +{ + UINT32 addr; + UINT8 tmpaddr[4]; + + addr = BYTESPERSECTOR*sectorNum; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiWriteEnable(); + SetCSGpioEnable(1); + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADD_SECTOR_ERASE; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_SECTOR_ERASE; + } + SpiWaitIdle(); + SetCSGpioEnable(0); + while((SpiReadSta() & SPIFLASH_WRITEENABLE)); +} + +static void SpiEraseBlock(UINT32 blockNum) +{ + UINT32 addr; + UINT8 tmpaddr[4]; + + addr = BYTESPERBLOCK*blockNum; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiWriteEnable(); + SetCSGpioEnable(1); + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADD_BLOCK_ERASE; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_BLOCK_ERASE; + } + SpiWaitIdle(); + SetCSGpioEnable(0); + while((SpiReadSta() & SPIFLASH_WRITEENABLE)); +} + +static void SpiWritePage(UINT32 pagenum, UINT32 *buf) +{ + UINT32 addr; + UINT32 val = 0;; + INT32 i; + UINT8 tmpaddr[4]; + UINT8 *data = (UINT8*)buf; + + (void)val; + + addr = pagenum*BYTESPERPAGE; + tmpaddr[0] = addr; + tmpaddr[1] = addr>>8; + tmpaddr[2] = addr>>16; + tmpaddr[3] = addr>>24; + + SpiWriteEnable(); + SetCSGpioEnable(1); + if (addr_in_4_byte) { + SetSpiDataMode(8); + rSPI_DR = SPI_4BYTEADD_PAGE_PROGRAM; + rSPI_DR = tmpaddr[3]; + rSPI_DR = tmpaddr[2]; + rSPI_DR = tmpaddr[1]; + rSPI_DR = tmpaddr[0]; + } else { + rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_PAGE_PROGRAM; + } + + if (addr_in_4_byte) { + for (i = 0; i < BYTESPERPAGE; i++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = *data++; + } + } else { + for (i = 0; i < WORDSPERPAGE; i++) { + while(!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = *buf++; + } + } + SpiWaitIdle(); + SetCSGpioEnable(0); + while(SpiReadSta() & SPI_BUSY); +} + +void bootFromSPI(void) +{ + void (*funPtr)(void); + +#ifdef SPI0_QSPI_MODE + SpiLoadImage(SpiReadPageQuadMode); +#else + SpiLoadImage(SpiReadPage); +#endif + + funPtr = (void (*)(void))IMAGE_ENTRY; + funPtr(); +} + +static unsigned int pagecheck[WORDSPERPAGE]; +/* offset is at least align to SECOTR_SIZE */ +int SpiNorBurnPage(int pagenum, unsigned int *buf) +{ + int timeout = 3; + unsigned int *tmp = (unsigned int *)buf; + int i; + +retry: + SpiWritePage(pagenum, buf); + SpiReadPage(pagenum, pagecheck); + for (i = 0; i < WORDSPERPAGE; i++) { + if (tmp[i] != pagecheck[i]) { + if (timeout-- > 0) { + PrintVariableValueHex("write: ", tmp[i]); + PrintVariableValueHex("read: ", pagecheck[i]); + SendUartString("burn check data fail, retry...\r\n"); + goto retry; + } else { + SendUartString("burn error!\r\n"); + return -1; + } + } + } + + return 0; +} + +/* offset is at least align to SECOTR_SIZE */ +int SpiNorBurn(void *buf, unsigned int offset, unsigned int size, int show_progress) +{ + int i, j; + int secstart, secnum; + int blkstart, blknum; + int pagestart, pagenum, pageburned; + int remain = size; + unsigned int *pbuf = (unsigned int *)buf; + + pagestart = offset / BYTESPERPAGE; + pagenum = (size + BYTESPERPAGE - 1) / BYTESPERPAGE; + pageburned = 0; + + while (remain > 0) { + unsigned int tmp = offset & (BYTESPERBLOCK - 1); + if (tmp) { + tmp = (BYTESPERBLOCK - tmp) / BYTESPERSECTOR; + secnum = (remain + BYTESPERSECTOR - 1) / BYTESPERSECTOR; + secnum = min(tmp, secnum); + secstart = offset / BYTESPERSECTOR; + for (i = 0; i < secnum; i++) { + SpiEraseSector(secstart + i); + for (j = 0; j < PAGESPERSECTORS; j++) { + if (SpiNorBurnPage(pagestart + j, pbuf)) + return -1; + pbuf += WORDSPERPAGE; + pageburned++; + remain -= BYTESPERPAGE; + if (remain <= 0) goto finish; + if (show_progress) + update_progress_set(pageburned * 100 / pagenum); + } + pagestart += PAGESPERSECTORS; + } + offset += secnum * BYTESPERSECTOR; + } else { + blkstart = offset / BYTESPERBLOCK; + blknum = remain / BYTESPERBLOCK; + for (i = 0; i < blknum; i++) { + SpiEraseBlock(blkstart + i); + for (j = 0; j < PAGESPERSECTORS * SECTORSPERBLOCK; j++) { + if (SpiNorBurnPage(pagestart + j, pbuf)) + return -1; + pbuf += WORDSPERPAGE; + pageburned++; + remain -= BYTESPERPAGE; + if (remain <= 0) goto finish; + if (show_progress) + update_progress_set(pageburned * 100 / pagenum); + } + pagestart += PAGESPERSECTORS * SECTORSPERBLOCK; + } + offset += blknum * BYTESPERBLOCK; + if (remain > 0) { + secstart = offset / BYTESPERSECTOR; + secnum = (remain + BYTESPERSECTOR - 1) / BYTESPERSECTOR; + for (i = 0; i < secnum; i++) { + SpiEraseSector(secstart + i); + for (j = 0; j < PAGESPERSECTORS; j++) { + if (SpiNorBurnPage(pagestart + j, pbuf)) + return -1; + pbuf += WORDSPERPAGE; + pageburned++; + remain -= BYTESPERPAGE; + if (remain <= 0) goto finish; + if (show_progress) + update_progress_set(pageburned * 100 / pagenum); + } + pagestart += PAGESPERSECTORS; + } + offset += secnum * BYTESPERSECTOR; + } + } + } + +finish: + if (show_progress) + update_progress_set(100); + + return 0; +} + +int FlashBurn(void *buf, unsigned int offset, unsigned int size, int show_progress) +{ + return SpiNorBurn(buf, offset, size, show_progress); +} + +int SpiReadSysInfo(SysInfo *info) +{ + UINT32 *buf = (UINT32*)IMAGE_ENTRY; + int pagestart; + int pagenum; + UINT32 checksum; + UINT32 calc_checksum; + int i; + + pagestart = SYSINFOA_OFFSET / BYTESPERPAGE; + pagenum = (sizeof(SysInfo) + BYTESPERPAGE - 1) / BYTESPERPAGE; + for(i = pagestart; i < pagestart + pagenum; i++) + { + SpiReadPage(i, buf); + buf += BYTESPERPAGE/4; + } + + checksum = *(UINT32*)(IMAGE_ENTRY + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, (void*)IMAGE_ENTRY, sizeof(SysInfo)); + return 0; + } + + buf = (UINT32*)IMAGE_ENTRY; + pagestart = SYSINFOB_OFFSET / BYTESPERPAGE; + for(i = pagestart; i < pagestart + pagenum; i++) + { + SpiReadPage(i, buf); + buf += BYTESPERPAGE/4; + } + + checksum = *(UINT32*)(IMAGE_ENTRY + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, (void*)IMAGE_ENTRY, sizeof(SysInfo)); + return 0; + } + + return -1; +} + +void SpiWriteSysInfo(SysInfo *info) +{ + SpiNorBurn(info, SYSINFOB_OFFSET, sizeof(SysInfo), 0); + SpiNorBurn(info, SYSINFOA_OFFSET, sizeof(SysInfo), 0); +} + +unsigned int SpiGetUpfileOffset(int type) +{ + SysInfo *sysinfo = GetSysInfo(); + + if (type == UPFILE_TYPE_WHOLE) { + if (sysinfo->image_offset == IMAGE_OFFSET) + sysinfo->image_offset = IMAGEB_OFFSET; + else + sysinfo->image_offset = IMAGE_OFFSET; + return sysinfo->image_offset; + } else if (type == UPFILE_TYPE_FIRSTLDR) { + return LOADER_OFFSET; + } else if (type == UPFILE_TYPE_STEPLDR) { + if (sysinfo->stepldr_offset == STEPLDRA_OFFSET) + sysinfo->stepldr_offset = STEPLDRB_OFFSET; + else + sysinfo->stepldr_offset = STEPLDRA_OFFSET; + return sysinfo->stepldr_offset; + } else { + unsigned int buf[WORDSPERPAGE]; + UpFileHeader *header; + UpFileInfo *appfile; + unsigned int offset; + int i; + + SpiReadPage(sysinfo->image_offset / BYTESPERPAGE, buf); + header = (UpFileHeader*)buf; + if (header->magic != MKTAG('U', 'P', 'D', 'F')) { + SendUartString("old update file isn't found in flash, can't support module update.\n"); + return 0xffffffff; + } + for (i = 0; i < header->filenum; i++) { + appfile = &header->files[i]; + if ((appfile->magic == UPFILE_APP_MAGIC && type == UPFILE_TYPE_APP) || + (appfile->magic == MKTAG('R', 'O', 'M', 'A') && type == UPFILE_TYPE_RESOURCE) || + (appfile->magic == MKTAG('B', 'A', 'N', 'I') && type == UPFILE_TYPE_ANIMATION)) { + offset = appfile->offset; + if (offset & (BYTESPERSECTOR - 1)) { + SendUartString("offset isn't align to sector erase size, can't support module update.\n"); + return 0xffffffff; + } + return offset + sysinfo->image_offset; + } + } + } + + return 0xffffffff; +} +#endif diff --git a/A58-STEPLDR/Src/SpinandBooter.c b/A58-STEPLDR/Src/SpinandBooter.c new file mode 100644 index 00000000..0c4f2435 --- /dev/null +++ b/A58-STEPLDR/Src/SpinandBooter.c @@ -0,0 +1,1616 @@ +#include +#include +#include "typedef.h" +#include "amt630h.h" +#include "uart.h" +#include "timer.h" +#include "gpio.h" +#include "cp15.h" +#include "sysinfo.h" +#include "crc32.h" +#include "update.h" +#include "board.h" +#include "os_adapt.h" + +#if DEVICE_TYPE_SELECT == SPI_NAND_FLASH +/* SPI commands */ +#define SPI_RXFIFO_ENABLE (1<<8) +#define SPI_TRANS_COMPLETE (1<<7) +#define SPI_RXFIFO_OVER (1<<6) + +#define SPI_TXFIFO_FULL (1<<2) +#define SPI_TXFIFO_REQ (1<<1) + +#define SPI_RXFIFO_FULL (1<<4) +#define SPI_RXFIFO_NOTEMPTY (1<<3) +#define SPI_TXFIFO_EMPTY (1<<2) +#define SPI_TXFIFO_NOTFULL (1<<1) +#define SPI_BUSY (1<<0) + +#define SPI0_CS0_GPIO 32 +#define SPI0_IO0_GPIO 34 +#define SPI_CS_GPIO SPI0_CS0_GPIO + + +/* SPI NAND commands */ +#define SPI_NAND_WRITE_ENABLE 0x06 +#define SPI_NAND_WRITE_DISABLE 0x04 +#define SPI_NAND_GET_FEATURE 0x0f +#define SPI_NAND_SET_FEATURE 0x1f +#define SPI_NAND_PAGE_READ 0x13 +#define SPI_NAND_READ_CACHE 0x03 +#define SPI_NAND_FAST_READ_CACHE 0x0b +#define SPI_NAND_READ_CACHE_X2 0x3b +#define SPI_NAND_READ_CACHE_X4 0x6b +#define SPI_NAND_READ_CACHE_DUAL_IO 0xbb +#define SPI_NAND_READ_CACHE_QUAD_IO 0xeb +#define SPI_NAND_READ_ID 0x9f +#define SPI_NAND_PROGRAM_LOAD 0x02 +#define SPI_NAND_PROGRAM_LOAD4 0x32 +#define SPI_NAND_PROGRAM_EXEC 0x10 +#define SPI_NAND_PROGRAM_LOAD_RANDOM 0x84 +#define SPI_NAND_PROGRAM_LOAD_RANDOM4 0xc4 +#define SPI_NAND_BLOCK_ERASE 0xd8 +#define SPI_NAND_RESET 0xff + +/* Registers common to all devices */ +#define SPI_NAND_LOCK_REG 0xa0 +#define SPI_NAND_PROT_UNLOCK_ALL 0x0 + +#define SPI_NAND_FEATURE_REG 0xb0 +#define SPI_NAND_ECC_EN (1 << 4) +#define SPI_NAND_QUAD_EN (1 << 0) + +#define SPI_NAND_STATUS_REG 0xc0 +#define SPI_NAND_STATUS_REG_ECC_MASK 0x3 +#define SPI_NAND_STATUS_REG_ECC_SHIFT 4 +#define SPI_NAND_STATUS_REG_PROG_FAIL (1 << 3) +#define SPI_NAND_STATUS_REG_ERASE_FAIL (1 << 2) +#define SPI_NAND_STATUS_REG_WREN (1 << 1) +#define SPI_NAND_STATUS_REG_BUSY (1 << 0) + +#define SPI_NAND_ECC_UNCORR 0x2 + +/* */ +#define MAX_SNF_BUF_SIZE 32 +#define MAX_SPARE_SIZE 64 +#define MAX_PAGE_SIZE 2048 +#define MAX_BLK_SIZE 2048 + +#define SNF_MAX_BLOCK_COUNT 2048 +#define SNF_REPLACE_BLK_PERCENT 2 //default: 2% +#define SNF_BBT_BLK_COUNT 4 +#define SNF_BBT_HEADER_SIZE 32 +#define SNF_BBT_HEADER_MASK "SNF BAD BLOCK TABLE" //<32 bytes. + + +enum { + SNF_OK, + SNF_ERR, + SNF_TIMEOUT, + SNF_BAD_BLK, +}; + +enum { + SNF_BLK_BAD = 0, + SNF_BLK_USED, + SNF_BLK_GOOD = 0xFF +}; + +typedef struct _snf_blk_node { + u8 status; + u16 replace; //replace bad block. +} snf_blk_node; + +typedef struct _snf_bbt { + u8 header_mask[SNF_BBT_HEADER_SIZE]; + snf_blk_node node[SNF_MAX_BLOCK_COUNT]; + u32 bad_blocks; + u32 reserved[8]; + u32 bbt_crc; +} snf_bbt; + +typedef struct spi_nand_plane_select +{ + /* plane select is used for block select */ + u32 rpb; //read page(from nand array to cache) bit. + u32 rcb; //read cache(from page cache to app buffer) bit. + u32 plb; //program load(write data to cache) bit. + u32 peb; //program excute(flush cache to nand array) bit. +} snf_ps; + +typedef struct spi_nand_cfg_tag +{ + char Name[MAX_SNF_BUF_SIZE]; + u8 MID; + u8 DID0; + u8 DID1; + u8 BBMType; + u32 BytePerPage; + u32 PagePerBlk; + u32 TotalBlk; + u32 SprSize; + int PsArrayIndex; +} spi_nand_cfg; + +typedef struct _snf_chip_info +{ + u8 Name[MAX_SNF_BUF_SIZE]; + u8 MID; + u8 DID0; + u8 DID1; + u8 BBMType; + u32 BytePerPage; + u32 BytePerBlk; + u32 TotalBlk; + u32 SprSize; + u32 FtlSprSize; + u32 PsArrayIndex; + // + u32 AvailableBlks; + u32 Capacity; + u32 AvailableCapacity; + u32 PagePerBlk; + u32 BbtBlkOffset; + u32 ReplaceBlks; + snf_bbt bbt; + snf_ps *ps; +} snf_chip_info; + +static int SpiNandFindAReplaceBlock(snf_chip_info *chip, u32 *block); +static int SpiNandUpdateBbt(void); +static int SpiNandCheckReplaceBlockValid(u32 block); +int SpiNandBurn(void *buf, u32 offset, u32 size, int show_progress); + +/* PlaneSelect bit array */ +static snf_ps g_SnfPsArray[] = { + [0] = {6, 12, 12, 6}, /* DS35Q2GA */ +}; + +static spi_nand_cfg g_SnfChipCfgArray[] = +{ + // name, MID, DID0, DID1, BBM, BytePerPage, PagePerBlk, TotalBlkCnt, SpareSize PlaneSelect + { "DS35Q1GA", 0xE5, 0x71, 0x00, 2, 2048, 64, 1024, 64, -1/* not use */}, + { "DS35Q2GA", 0xE5, 0x72, 0x00, 2, 2048, 64, 2048, 64, 0}, + { "GD5F2GM7", 0xc8, 0x92, 0x00, 2, 2048, 64, 2048, 64, -1}, +}; + +static snf_chip_info g_snf = {0}; + + +static void delay(u32 time) +{ + volatile u32 count = time; + while (count--); +} + +static void SetCSGpioEnable(int enable) +{ + gpio_direction_output(SPI_CS_GPIO, !enable); +} + +static void SpiWaitIdle(void) +{ + while (rSPI_SR & SPI_BUSY); + udelay(1); +} + +#if 0 +static void SpiEmptyRxFIFO(void) +{ + int data = 0; + (void)data; + + while (rSPI_SR & SPI_RXFIFO_NOTEMPTY) + data = rSPI_DR; +} +#endif + +static void SetSpiDataMode(u32 bitMode) +{ + u32 val = 0; + SpiWaitIdle();; + rSPI_SSIENR = 0; + val = rSPI_CTLR0; + val &=~(0x1f<<16); + val |=((bitMode-1)<<16); + rSPI_CTLR0 = val; + rSPI_SSIENR = 1; +} + +static void SpiSelectPad(void) +{ + u32 val; + /* pad config */ + val = rSYS_PAD_CTRL02; + val &= ~0xfff; + val |= (0x1 << 10)|(0x1 << 8)|(0x1 << 6)|(0x1 << 4)| (0x1 << 2)/* | (1<<0)*/; + rSYS_PAD_CTRL02 = val; + + /* clock config */ + val = rSYS_SSP_CLK_CFG; + val |= (0x1<<31) | (0x1<<30); + rSYS_SSP_CLK_CFG = val; + + //cs inactive first + SetCSGpioEnable(0); +} + +static void SpiSoftReset(void) +{ + u32 val; + + val = rSYS_SOFT_RST; + val &= ~(0x1<<8); + rSYS_SOFT_RST = val; + udelay(10); + val |= (0x1<<8); + rSYS_SOFT_RST = val; +} + +static void SpiInitialize() +{ + SpiSelectPad(); + SpiSoftReset(); + rSPI_SSIENR = 0; + rSPI_CTLR0 = 0; + rSPI_CTLR0 |= (0<<21)|(0x1f<<16)|(0x0<<12)|(0x0<<8)|(0x0<<4); +// rSPI_CTLR1 = 63; + rSPI_BAUDR = 4;//2;//16;//2; + rSPI_SER = 1; + rSPI_IMR = 0; + rSPI_SSIENR = 1; + SetCSGpioEnable(0); +} + + +static void SpinandSoftreset(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_RESET; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiNandReadId(void) +{ + u8 val[4]; + int i; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_READ_ID; + rSPI_DR = 0; + rSPI_DR = 0; + rSPI_DR = 0; + + for (i=0; i<4; i++) + { + while (!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val[i] = rSPI_DR; + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + + printf("ManufacturerID:0x%x, DeviceID:0x%x.\n", val[2], val[3]); + g_snf.MID = val[2]; + g_snf.DID0 = val[3]; +} + +static void SpiNandWriteReg(u8 opcode, u8 val) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_SET_FEATURE; + rSPI_DR = opcode; + rSPI_DR = val; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static u8 SpiNandReadReg(u8 opcode) +{ + u8 val; + int i; + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_GET_FEATURE; + rSPI_DR = opcode; + rSPI_DR = 0; + + for (i = 0; i < 3; i++) + { + while (!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + val = rSPI_DR; + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + + return val; +} + +static void SpiNandWriteEnable(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_WRITE_ENABLE; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiNandWriteDisable(void) +{ + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_WRITE_DISABLE; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static int SpiNandWaitTillReady(void) +{ + int timeout = 100; + u8 status; + + while (timeout--) + { + status = SpiNandReadReg(SPI_NAND_STATUS_REG); + //printk("status=0x%x.\n", status); + if (!(status & SPI_NAND_STATUS_REG_BUSY)) + return status; + delay(1000); + } + + return -SNF_TIMEOUT; +} + +static int SpiNandEnableECC(void) +{ + u8 status; + + status = SpiNandReadReg(SPI_NAND_FEATURE_REG); + status |= SPI_NAND_ECC_EN; + SpiNandWriteReg(SPI_NAND_FEATURE_REG, status); + + return SNF_OK; +} + +#ifdef SPI0_QSPI_MODE +static int SpiNandEnableQuad(void) +{ + u8 status; + + status = SpiNandReadReg(SPI_NAND_FEATURE_REG); + status |= SPI_NAND_QUAD_EN; + SpiNandWriteReg(SPI_NAND_FEATURE_REG, status); + + return SNF_OK; +} +#else +static int SpiNandDisableQuad(void) +{ + u8 status; + + status = SpiNandReadReg(SPI_NAND_FEATURE_REG); + status &= ~SPI_NAND_QUAD_EN; + SpiNandWriteReg(SPI_NAND_FEATURE_REG, status); + + return SNF_OK; +} +#endif + +static void SpiNandLoadPage(u32 page) +{ + if (g_snf.ps) { + int block = page / g_snf.PagePerBlk; + if (block % 2) + page |= (1 << g_snf.ps->rpb); //set plane select bit. + } + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_PAGE_READ; + rSPI_DR = (page >> 16) & 0xFF; + rSPI_DR = (page >> 8) & 0xFF; + rSPI_DR = page & 0xFF; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +static void SpiNandStorePage(u32 page) +{ + if (g_snf.ps) { + int block = page / g_snf.PagePerBlk; + if (block % 2) + page |= (1 << g_snf.ps->peb); //set plane select bit. + } + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_PROGRAM_EXEC; + rSPI_DR = (page >> 16) & 0xFF; + rSPI_DR = (page >> 8) & 0xFF; + rSPI_DR = page & 0xFF; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); +} + +#ifdef SPI0_QSPI_MODE +//********format********* +//00 – Standard SPI Format +// 01 – Dual SPI Format +// 10 – Quad SPI Format +// 11 – Reserved +//********tmod********** +//00 –- Transmit & Receive +//01 –- Transmit Only +//10 –- Receive Only +//11 –- EEPROM Read +static void SpiSetFrameFormatMode(u8 format, u8 tmod) +{ + u32 val = 0; + + while ((rSPI_SR & SPI_BUSY)); + rSPI_SSIENR = 0; + val = rSPI_CTLR0; + val &= ~((0x3 << 21) | (0x3 << 8)); + val |= ((format << 21) | (tmod << 8)); + rSPI_CTLR0 = val; + rSPI_SSIENR = 1; +} +#endif + +/* + * func: + * read data from page cache. + * param: + * offset: start offset in page cache. + * len: the len of data. + * buf: write data. + */ +static int SpiNandReadCache(u32 page, u32 offset, int len, u8 *buf) +{ + int left_size = len; + int block = page / g_snf.PagePerBlk; + u32 addr; + int i; + +#ifdef SPI0_QSPI_MODE + //Quad mode. + if (len / 4){ + addr = (offset & 0xFFFF); //3dummy bits(0) + 1bit plane select+ 12bits address. + if (g_snf.ps) { + if (block % 2) + addr |= (1 << g_snf.ps->rcb); //set read cache plane select bit. + } + addr = (addr << 8) | 0x0; + addr = ((addr >> 16) & 0xff) | (((addr >> 8) & 0xff) << 8) | ((addr & 0xff) << 16); + + SpiSetFrameFormatMode(2, 2); + rSPI_SSIENR = 0; + rSPI_SPI_CTRLR0 = (0 << 11) | (2 << 8) | (6 << 2) | 0; + rSPI_CTLR1 = len/4 - 1; + rSPI_SSIENR = 1; + + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_READ_CACHE_X4; + rSPI_DR = addr; + + for (i = 0; i < len/4; i++) + { + while (!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + ((u32 *)buf)[i] = rSPI_DR; + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + rSPI_SSIENR = 0; + rSPI_SPI_CTRLR0 = 0; + rSPI_CTLR1 = 0; + rSPI_SSIENR = 1; + SpiSetFrameFormatMode(0, 0); + + left_size = len % 4; + offset += len - left_size; + buf += len - left_size; + } +#endif + + //Standerd mode. + if (left_size){ + addr = (offset & 0xFFFF); //3bits dummy(0) + 1bit plane select + 12bits address. + if (g_snf.ps) { + if (block % 2) + addr |= (1 << g_snf.ps->rcb); //set read cache plane select bit. + } + + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_READ_CACHE; + rSPI_DR = (addr >> 8) & 0xFF; + rSPI_DR = addr & 0xFF; + rSPI_DR = 0x0; //dummy byte. + + for (i = 0; i < 4; i++) + { + while (!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + *buf = rSPI_DR; //Drop this value. + } + + for (i = 0; i < left_size; i++) + { + rSPI_DR = 0; + while (!(rSPI_SR & SPI_RXFIFO_NOTEMPTY)); + *buf++ = rSPI_DR; + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + } + + return SNF_OK; +} + +/* + * func: + * read spare area of a page. + * param: + * page: page index(0~n). + * buf: read buffer. + */ +static int SpiNandReadPageSpare(u32 page, char *buf) +{ + int status; + int ecc_status; + int page_size = g_snf.BytePerPage; + int spare_size = g_snf.SprSize; + + SpiNandLoadPage(page); + status = SpiNandWaitTillReady(); + if (status < 0) + return status; + + ecc_status = (status >> SPI_NAND_STATUS_REG_ECC_SHIFT) & SPI_NAND_STATUS_REG_ECC_MASK; + if (ecc_status == SPI_NAND_ECC_UNCORR) + { + //printf("%s, Bit errors greater than ECC capability(4 bits) and can not be corrected.\n", __func__); + printf("###ERR: %s (blk:%d, page:%d) ECC error, status:0x%x.\n", __func__, page / g_snf.PagePerBlk, page % g_snf.PagePerBlk, status); + return -SNF_BAD_BLK; + } + return SpiNandReadCache(page, page_size, spare_size, (u8 *)buf); +} + +/* + * func: + * write data to page cache. + * param: + * offset: start offset in cache. + * len: the len of data. + * buf: write data. + */ +static int SpiNandStoreCache(u32 page, u32 offset, int len, u8 *buf) +{ + int block = page / g_snf.PagePerBlk; + u32 addr; + int i; + + addr = (offset & 0xFFFF); //3bits dummy + 1bit plane select + 12bits address. + if (g_snf.ps) { + if (block % 2) + addr |= (1 << g_snf.ps->plb); //set read cache plane select bit. + } + +#ifdef SPI0_QSPI_MODE + //Quad mode. + if (len % 4 == 0){ + addr = ((addr >> 8) & 0xff) | ((addr & 0xff) << 8); + SpiSetFrameFormatMode(2, 1); + rSPI_SSIENR = 0; + rSPI_SPI_CTRLR0 = (0 << 11) | (2 << 8) | (4 << 2) | 0; + rSPI_CTLR1 = len/4 - 1; + rSPI_SSIENR = 1; + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_PROGRAM_LOAD4; + rSPI_DR = addr & 0xFFFF; + + for (i = 0; i < len/4; i++) + { + while (!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = ((u32 *)buf)[i]; + } + + SpiWaitIdle(); + SetCSGpioEnable(0); + rSPI_SSIENR = 0; + rSPI_SPI_CTRLR0 = 0; + rSPI_CTLR1 = 0; + rSPI_SSIENR = 1; + SpiSetFrameFormatMode(0, 0); + return SNF_OK; + } +#endif + + //Standerd mode. + SetSpiDataMode(8); + SetCSGpioEnable(1); + rSPI_DR = SPI_NAND_PROGRAM_LOAD; + rSPI_DR = (addr >> 8) & 0xFF; + rSPI_DR = addr & 0xFF; + for (i = 0; i < len; i++) + { + while (!(rSPI_SR & SPI_TXFIFO_NOTFULL)); + rSPI_DR = buf[i]; + } + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + + return SNF_OK; +} + +/* + * func: + * erase one block. + * param: + * block: block index. + * replaced: if this block to be replaced by a good block from BBT when it is a bad block. + */ +static int SpiNandEraseBlock(int block) +{ + u32 page_offset; + int status; + int timeout = 0; + +retry: + SpiNandWriteEnable(); + SetSpiDataMode(8); + SetCSGpioEnable(1); + page_offset = block * g_snf.PagePerBlk; + rSPI_DR = SPI_NAND_BLOCK_ERASE; + rSPI_DR = (page_offset >> 16) & 0xff; + rSPI_DR = (page_offset >> 8) & 0xff; + rSPI_DR = page_offset & 0xff; + SpiWaitIdle(); + SetCSGpioEnable(0); + SetSpiDataMode(32); + + status = SpiNandWaitTillReady(); + if (status < 0) { + if (timeout++ < 3) + goto retry; + printf("%s block%d erase timeout.\n", __func__, block); + return status; + } + + if (status & SPI_NAND_STATUS_REG_ERASE_FAIL) { + /*find a new bad block. */ + printf("%s block: %d erase failed\n", __func__, block); + return -SNF_BAD_BLK; + } + + return SNF_OK; +} + +/* + * func: + * read a few bytes in one page. + * param: + * page: the page index in falsh(0 ~ n). + * offset: read offset form one page. + * data: read data. + * size: read data size. + */ +static int SpiNandReadBytesInPage(u32 page, u32 offset, u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + int status; + int ecc_status; + + SpiNandLoadPage(page); + status = SpiNandWaitTillReady(); + if (status < 0) { + printf("###ERR: %s timeout, block:%d page:%d.\n", __func__, page / chip->PagePerBlk, page % chip->PagePerBlk); + return status; + } + + ecc_status = (status >> SPI_NAND_STATUS_REG_ECC_SHIFT) & SPI_NAND_STATUS_REG_ECC_MASK; + if (ecc_status == SPI_NAND_ECC_UNCORR) //ECC error meains bad block. + { + printf("###ERR: %s, block:%d, page:%d ECC error, status:0x%x..\n", __func__, page / chip->PagePerBlk, page % chip->PagePerBlk, status); + return -SNF_ERR;//-SNF_BAD_BLK; + } + return SpiNandReadCache(page, offset, size, data); +} + +/* + * func: + * read a whole page. + * param: + * page: page index. + * data: read buffer. + */ +static int SpiNandreadOnePage(u32 page, u8 *data) +{ + return SpiNandReadBytesInPage(page, 0, data, g_snf.BytePerPage); +} + +/* + * func: + * write a few bytes in one page. + * param: + * page: the page index in falsh(0 ~ n). + * offset: write offset form one page. + * data: write data. + * size: write data size. + */ +static int SpiNandWriteBytesInPage(u32 page, u32 offset, u8 *data, u32 size) +{ + int timeout = 0; + int ret; + +retry: + SpiNandWriteEnable(); + SpiNandStoreCache(page, offset, size, data); + SpiNandStorePage(page); + ret = SpiNandWaitTillReady(); + if (ret < 0) { + if (timeout++ < 3) + goto retry; + } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) { + ret = -SNF_BAD_BLK; + } + + return ret; +} + +/* + * func: + * write a whole page. + * param: + * page: page index. + * data: write data. + */ +static int SpiNandWriteOnePage(u32 page, u8 *data) +{ + return SpiNandWriteBytesInPage(page, 0, data, g_snf.BytePerPage); +} + +static int SpiNandReadPhysicalBlock(u32 block , u32 offset_in_block, u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + u8 *pdata = data; + u32 currpage, BytePerPage; + u32 offset_in_page; + u32 read_size; + int remain = size; + int ret; + + BytePerPage = chip->BytePerPage; + currpage = block * chip->PagePerBlk + offset_in_block / BytePerPage; + offset_in_page = offset_in_block % BytePerPage; + + while (remain > 0) { + read_size = ((BytePerPage - offset_in_page) >= remain) ? remain : (BytePerPage - offset_in_page); + ret = SpiNandReadBytesInPage(currpage, offset_in_page, pdata, read_size); + if (ret != SNF_OK) { + printf("%s read page:%d (blk: %d) failed\n", __func__, currpage, block); + break; + } + + if (offset_in_page) + offset_in_page = 0; + + currpage++; + remain -= read_size; + pdata += read_size; + } + + return ret; +} + +static int SpiNandReadInBlock(u32 block , u32 offset_in_block, u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + u32 blk = block; + int ret; + + //bad block check and replace. + if (chip->bbt.node[block].status == SNF_BLK_BAD) { + blk = chip->bbt.node[block].replace; + ret = SpiNandCheckReplaceBlockValid(blk); + if ((ret == SNF_OK) && (chip->bbt.node[blk].status != SNF_BLK_BAD)) { + //find replace block. + if (chip->bbt.node[blk].status != SNF_BLK_USED) { + printf("%s block:%d, replace blk:%d\n", __func__, block, blk); + chip->bbt.node[blk].status = SNF_BLK_USED; + } + } else { + printf("###ERR: %s, blk:%d is bad block, it's replace block:%d is Invalid.\n", __func__, block, blk); + return -SNF_BAD_BLK; + } + } + + return SpiNandReadPhysicalBlock(blk, offset_in_block, data, size); +} + +static int SpiNandReadData(u32 addr, void *data, int size) +{ + snf_chip_info *chip = &g_snf; + u8 *pdata; + u32 read_size, bytePerBlk; + u32 currblk,offset_in_block; + int remain; + int ret = SNF_OK; + + pdata = (u8 *)data; + remain = size; + bytePerBlk = chip->BytePerBlk; + currblk = addr / bytePerBlk; + offset_in_block = addr % bytePerBlk; + + //area check valid. + if ((addr + size) > chip->AvailableCapacity) { + printf("###ERR:%s, burn out of boundry.\n", __func__); + return -SNF_ERR; + } + + while (remain > 0) { + //read block. + read_size = ((bytePerBlk - offset_in_block) >= remain) ? remain : (bytePerBlk - offset_in_block); + ret = SpiNandReadInBlock(currblk, offset_in_block, pdata, read_size); + if (ret != SNF_OK) { + printf("###ERR:%s, SpiNandReadInBlock(%d) failed.\n", __func__, currblk); + break; + } + + if (offset_in_block) + offset_in_block = 0; + + currblk++; + pdata += read_size; + remain -= read_size; + if (remain < 0) { + ret = -SNF_ERR; + printf("###ERR:%s, Invalid remain.\n", __func__); + break; + } + } + + return ret; +} + +/* + * func: + * burn one page data to spi flash. + * param: + * page: page index. + * buf: data buffer(at least PAGE_SIZE). + */ +static int SpiNandBurnPage(int page, u8 *buf) +{ + int ret; + + ret = SpiNandWriteOnePage(page, buf); + if (ret == SNF_OK) { + u32 *tmp = (u32 *)buf; + int wordPerPage = g_snf.BytePerPage / 4; + u32 pagecheck[MAX_PAGE_SIZE/4]; + int i; + + ret = SpiNandreadOnePage(page, (u8 *)pagecheck); + if (ret == SNF_OK) { + for (i = 0; i < wordPerPage; i++) { + if (tmp[i] != pagecheck[i]) { + printf("%s(%d) checksum error, write:0x%x, read:0x%x, pos:%d\n", __func__, page, tmp[i], pagecheck[i], i); + return -SNF_ERR; + } + } + } else { + return -SNF_ERR; //read page should not create a bad block. + } + } else { + return ret; + } + + return ret; +} + +/* + * func: + * write random bytes data to flash. + * param: + * addr: write start address(must align with page). + * data: write data. + * size： write data size(random bytes). + */ +static int SpiNandBurnBlock(u32 block, u32 offset_in_block, const u8 *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + u8 *buf = (u8 *)data; + u32 left_size = size; + u8 pageBuf[MAX_PAGE_SIZE]; + u32 byte_per_page; + u32 start_page; + u32 whole_page_num; + u32 result; + u32 i; + + byte_per_page = chip->BytePerPage; + start_page = block * chip->PagePerBlk + offset_in_block / byte_per_page; + + if (offset_in_block % byte_per_page) { + printf("###ERR:%s, offset is not align with page\n", __func__); + return -SNF_ERR; + } + + if (left_size > 0) { + whole_page_num = left_size / byte_per_page; + for (i=0; i 0) { + memset(pageBuf + left_size, 0xff, MAX_PAGE_SIZE - left_size); + memcpy(pageBuf, buf, left_size); + result = SpiNandBurnPage(start_page, pageBuf); + if (result != SNF_OK) { + printf("%s Burn the last page(%d) failed, result:%d.\n", __func__, start_page, result); + return result; + } + } + + return result; +} + +static int SpiNandEraseWriteInBlock(u32 block, u32 offset_in_block, void *data, u32 size) +{ + snf_chip_info *chip = &g_snf; + int ret; + u32 blk = block; + u32 bbtUpdate = 0; + + //bad block check and replace. + if (chip->bbt.node[block].status == SNF_BLK_BAD) { + blk = chip->bbt.node[block].replace; + ret = SpiNandCheckReplaceBlockValid(blk); + if ((ret == SNF_OK) && (chip->bbt.node[blk].status != SNF_BLK_BAD)) { + //find replace block. + if (chip->bbt.node[blk].status != SNF_BLK_USED) { + printf("%s block:%d, replace blk:%d\n", __func__, block, blk); + chip->bbt.node[blk].status = SNF_BLK_USED; + } + } else { +retry: + //find a new replace block. + ret = SpiNandFindAReplaceBlock(chip, &blk); + if (ret != SNF_OK) { + printf("%s SpiNandFindAReplaceBlock failed, no replace block.\n", __func__); + goto exit; + } + printf("%s block:%d, find a new replace blk:%d\n", __func__, block, blk); + chip->bbt.node[block].replace = blk; + bbtUpdate = 1; + } + } + + if (offset_in_block == 0) { + ret = SpiNandEraseBlock(blk);//phy block + if (ret != SNF_OK) { + printf("###ERR:%s, SpiNandEraseBlock(%d) failed, mask bad block and try to find a replace block.\n", __func__, blk); + chip->bbt.node[blk].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbtUpdate = 1; + goto retry; + } + } + + ret = SpiNandBurnBlock(blk, offset_in_block, data, size);//phy block + if (ret != SNF_OK) { + if ((ret == -SNF_BAD_BLK) && (offset_in_block == 0)) { + printf("###ERR:%s, SpiNandBurnBlock %d failed, try to find replace block\n", __func__, blk); + chip->bbt.node[blk].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbtUpdate = 1; + goto retry; + } else { + printf("###ERR:%s, SpiNandBurnBlock %d failed, exit\n", __func__, blk); + } + } + +exit: + if (bbtUpdate) + SpiNandUpdateBbt(); + + return ret; +} + +/* + * func: + * check if the replace block is valid. + * param: + * block: block index. + */ +static int SpiNandCheckReplaceBlockValid(u32 block) +{ + snf_chip_info *chip = &g_snf; + + if ((block >= chip->AvailableBlks) && (block < chip->BbtBlkOffset)) { + return SNF_OK; + } + + return -SNF_ERR; +} + +/* + * func: + * check if a block is a bad block. + * param: + * blknum: block index. + */ +static int SpiNandCheckPhysicalBadBlock(u32 blknum) +{ + int page = blknum * g_snf.PagePerBlk; + int bbm = g_snf.BBMType; + char spareBuf[MAX_SPARE_SIZE] = {0}; + int ret; + + ret = SpiNandReadPageSpare(page, spareBuf); + if (ret != SNF_OK) { + printf("%s, SpiNandReadPageSpare page0 failed, ret:%d.\n", __func__, ret); + goto exit; + } + + if (spareBuf[0] == 0xFF) { + if (bbm == 2) { + ret = SpiNandReadPageSpare(page+1, spareBuf); + if (ret != SNF_OK) { + printf("%s, SpiNandReadPageSpare page1 failed, ret:%d.\n", __func__, ret); + goto exit; + } + if (spareBuf[0] == 0xFF) { + //printf(" good block:%d.\n", blknum); + return SNF_OK; + } else { + printf("%s, bad block:%d.\n", __func__, blknum); + } + } + } + +exit: + printf("%s bad block:%d.\n", __func__, blknum); + + return -SNF_BAD_BLK; +} + +/* + * func: + * find a good block form backup area to replay bad block. + * param: + * block: + */ +static int SpiNandFindAReplaceBlock(snf_chip_info *chip, u32 *block) +{ + int i; + + u32 replace_blk_start = chip->AvailableBlks; + u32 replace_blk_stop = chip->AvailableBlks + chip->ReplaceBlks; + + for (i=replace_blk_stop-1; i>=replace_blk_start; i--) { + if (chip->bbt.node[i].status == SNF_BLK_GOOD) { + *block = i; + chip->bbt.node[i].status = SNF_BLK_USED; + return SNF_OK; + } + } + + printf("%s failed, there are no valid replacement blocks.\n", __func__); + + return -SNF_ERR; +} + +static int SpiNandWriteBbt(u8 *buf , u32 size) +{ + snf_chip_info *chip = &g_snf; + int curr_block; + int i, ret; + int bbt_bad_blocks = 0; + int write_block_num = 0; + + for(i=0; iBbtBlkOffset + i; + + if(write_block_num >= 2) { + break; + } + + if(chip->bbt.node[curr_block].status == SNF_BLK_BAD) { + bbt_bad_blocks++; + continue; + } + + ret = SpiNandEraseBlock(curr_block); + if (ret != SNF_OK) { + printf("%s erase block(%d) failed, ret=%d\n", __func__, curr_block, ret); + if (ret == -SNF_BAD_BLK) { + chip->bbt.node[curr_block].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbt_bad_blocks++; + continue; + } + break; + } + + ret = SpiNandBurnBlock(curr_block, 0, buf, size); + if (ret != SNF_OK) { + printf("%s write block(%d) failed ret=%d\n", __func__, curr_block, ret); + if (ret == -SNF_BAD_BLK) { + chip->bbt.node[curr_block].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + bbt_bad_blocks++; + continue; + } + break; + } + + write_block_num++; + } + + if (bbt_bad_blocks) { + printf("%s, bbt has %d bad blcoks.\n", __func__, bbt_bad_blocks); + } + + return ret; +} + +static int SpiNandReadBbt(u8* buf, u32 size) +{ + snf_chip_info *chip = &g_snf; + u32 crc_size; + u32 checksum; + int curr_block; + int ret, i; + + crc_size = size - SNF_BBT_HEADER_SIZE - sizeof(chip->bbt.bbt_crc); + + for(i=0; iBbtBlkOffset + i; + ret = SpiNandReadPhysicalBlock(curr_block, 0, buf, size); + if (ret != SNF_OK) { + printf("%s SpiNandReadPhysicalBlock block:%d failed\n", __func__, curr_block); + continue; + } + + if (memcmp(chip->bbt.header_mask, SNF_BBT_HEADER_MASK, sizeof(SNF_BBT_HEADER_MASK))) { + printf("%s Not fond BBT header(block: %d).\n", __func__, curr_block); + ret = -SNF_ERR; + continue; + } + + checksum = xcrc32(buf + SNF_BBT_HEADER_SIZE, crc_size, 0xFFFFFFFF); + + if (chip->bbt.bbt_crc != checksum) { + printf("%s BBT information is abnormal(block: %d).\n", __func__, curr_block); + ret = -SNF_ERR; + continue; + } + + break; + } + + return ret; +} + +/* + * func: + * update bad block table. + * param: + */ +static int SpiNandUpdateBbt(void) +{ + snf_chip_info *chip = &g_snf; + int ret = SNF_OK; + u32 bbt_size, crc_size; + u8 *pbuf; + +#if 0 + for (i=0; iTotalBlk; i++) { + if (chip->bbt.node[i].status == SNF_BLK_BAD) { + printf("%s bad block:%d, resplace block:%d.\n", __func__, i, chip->bbt.node[i].replace); + } + } +#endif + pbuf = (u8 *)&chip->bbt; + bbt_size = sizeof(snf_bbt); + crc_size = bbt_size - SNF_BBT_HEADER_SIZE - sizeof(chip->bbt.bbt_crc); + + chip->bbt.bbt_crc = xcrc32(pbuf + SNF_BBT_HEADER_SIZE, crc_size, 0xFFFFFFFF); + + ret = SpiNandWriteBbt(pbuf, bbt_size); + if (ret != SNF_OK) { + printf("%s write bbt failed, ret:%d.\n", __func__, ret); + } + + return ret; +} + +/* + * func: + * bad block table initialize. + * param: + */ + static int SpiNandBbtInit(void) +{ + snf_chip_info *chip = &g_snf; + int ret = 0; + u32 bbt_size; + u8 *pbuf; + int i; + + pbuf = (u8 *)&chip->bbt; + bbt_size = sizeof(snf_bbt); + + ret = SpiNandReadBbt(pbuf, bbt_size); + if (ret != SNF_OK) { + memset(&chip->bbt, 0, bbt_size); + printf("%s Create a new BBT.\n", __func__); + for (i=0; iTotalBlk; i++) { + ret = SpiNandCheckPhysicalBadBlock(i); + if (ret == SNF_OK) { + chip->bbt.node[i].status = SNF_BLK_GOOD; + } else { + chip->bbt.node[i].status = SNF_BLK_BAD; + chip->bbt.bad_blocks++; + } + chip->bbt.node[i].replace = 0; + } + + memcpy(chip->bbt.header_mask, SNF_BBT_HEADER_MASK, sizeof(SNF_BBT_HEADER_MASK)); + SpiNandUpdateBbt(); + ret = SNF_OK; + } + + return ret; +} + +static int SpiNandSetAttribute(snf_chip_info *chip) +{ + spi_nand_cfg *cfg = g_SnfChipCfgArray; + int fond = 0; + int i; + + if (!chip) { + printf("SpiNandSetAttribute: Invalid chip.\n"); + return -SNF_ERR; + } + + for (i=0; iMID == cfg[i].MID) && (chip->DID0 == cfg[i].DID0)) { + fond = 1; + break; + } + } + + if (fond) { + memcpy(chip->Name, cfg[i].Name, MAX_SNF_BUF_SIZE); + chip->BBMType = cfg[i].BBMType; + chip->BytePerPage = cfg[i].BytePerPage; + chip->PagePerBlk = cfg[i].PagePerBlk; + chip->BytePerBlk = chip->BytePerPage * chip->PagePerBlk; + chip->TotalBlk = cfg[i].TotalBlk; + chip->SprSize = cfg[i].SprSize; + chip->FtlSprSize = 24; + chip->Capacity = chip->BytePerBlk * chip->TotalBlk; + chip->ReplaceBlks = chip->TotalBlk * SNF_REPLACE_BLK_PERCENT / 100; + chip->AvailableBlks = chip->TotalBlk - chip->ReplaceBlks - SNF_BBT_BLK_COUNT; + chip->AvailableCapacity = chip->AvailableBlks * chip->BytePerBlk; + chip->BbtBlkOffset = chip->TotalBlk - SNF_BBT_BLK_COUNT; + if ((cfg[i].PsArrayIndex < 0) || (cfg[i].PsArrayIndex >= sizeof(g_SnfPsArray)/sizeof(g_SnfPsArray[0]))) { + chip->ps = NULL; + } else { + chip->ps = &g_SnfPsArray[cfg[i].PsArrayIndex]; + } + printf("[SNF]:%s, Capacity:%dMB , AvailableCapacity:%dMB.\n", + chip->Name, chip->Capacity/1024/1024, chip->AvailableCapacity/1024/1024); + } else { + printf("Not find spi nand flash.\n"); + return -SNF_ERR; + } + + if (chip->BytePerPage > MAX_PAGE_SIZE) { + printf("###ERR: %s: Invalid MAX_PAGE_SIZE:%d.\n", __func__, MAX_PAGE_SIZE); + return -SNF_ERR; + } + if (chip->SprSize > MAX_SPARE_SIZE) { + printf("###ERR: %s: Invalid MAX_SPARE_SIZE:%d.\n", __func__, MAX_SPARE_SIZE); + return -SNF_ERR; + } + if (chip->TotalBlk > MAX_BLK_SIZE) { + printf("###ERR: %s: Invalid MAX_BLK_SIZE:%d.\n", __func__, MAX_BLK_SIZE); + return -SNF_ERR; + } + + return SNF_OK; +} + +int SpiInit(void) +{ + snf_chip_info *chip = &g_snf; + int ret; + + memset(chip, 0, sizeof(snf_chip_info)); + + /* spi controler init */ + SpiInitialize(); + + /* spi nand init */ + SpinandSoftreset(); + SpiNandWaitTillReady(); + SpiNandReadId(); + ret = SpiNandSetAttribute(chip); + if (ret != SNF_OK) { + printf("Not find spi nand flash.\n"); + return ret; + } + + SpiNandWriteReg(SPI_NAND_LOCK_REG, SPI_NAND_PROT_UNLOCK_ALL); + SpiNandEnableECC(); + +#ifdef SPI0_QSPI_MODE + SpiNandEnableQuad(); +#else + SpiNandDisableQuad(); +#endif + SpiNandWriteEnable(); + + ret = SpiNandBbtInit(); + if (ret != SNF_OK) + printf("%s SpiNandBbtInit failed.\n", __func__); + + SpiNandWriteDisable(); + + return ret; +} + +static int SpiNandLoadImage(void) +{ + int ret; + u32 *buf = (u32*)IMAGE_ENTRY; + UpFileHeader *header; + UpFileInfo *appfile; + u32 appsize; + SysInfo *sysinfo = GetSysInfo(); + u32 bytePerPage = g_snf.BytePerPage; + u32 image_offset = sysinfo->image_offset; + + ret = SpiNandReadData(image_offset, buf, bytePerPage); + if (ret != SNF_OK) { + printf("%s Read Image file header failed.\n", __func__); + while (1); + } + + header = (UpFileHeader*)buf; + appfile = &header->files[0]; + if (appfile->offset & (bytePerPage - 1)) { + SendUartString("\nImage positon is not align to flash pagesize, can't load.\r\n"); + while (1); + } + + if (sysinfo->app_size) + appsize = sysinfo->app_size; + else + appsize = appfile->size; + + ret = SpiNandReadData(appfile->offset + image_offset, buf, appsize); + if (ret != SNF_OK) { + printf("%s Read app file failed.\n", __func__); + while (1); + } + +#ifdef MMU_ENABLE + CP15_clean_dcache_for_dma(IMAGE_ENTRY, IMAGE_ENTRY + appsize); +#endif + return SNF_OK; +} + +void bootFromSPI(void) +{ + void (*funPtr)(void); + + SpiNandLoadImage(); + + funPtr = (void (*)(void))IMAGE_ENTRY; + funPtr(); +} + +/* + * func: + * burn data to spi flash. + * param: + * buf: data buffer. + * offset: address offset(must align with PAGE_SIZE). + * size: data size; + * show_progress: if show update progress in lcd. + */ +static int SpiNandBurn(void *buf, u32 offset, u32 size, int show_progress) +{ + snf_chip_info *chip = &g_snf; + u32 currblk, burn_size; + u32 bytePerBlk; + u32 offset_in_block; + int remain; + int ret = SNF_OK; + u8 *pbuf; + + pbuf = (u8 *)buf; + remain = size; + bytePerBlk = chip->BytePerBlk; + currblk = offset / bytePerBlk; + offset_in_block = offset % bytePerBlk; + + //area check valid. + if ((offset + size) > chip->AvailableCapacity) { + printf("###ERR:%s, burn out of boundry.\n", __func__); + return -SNF_ERR; + } + + //offset check align + if (offset % chip->BytePerPage) { + printf("###ERR:%s, offset is not align with page\n", __func__); + return -SNF_ERR; + } + + while (remain > 0) { + //burn block. + burn_size = ((bytePerBlk - offset_in_block) >= remain) ? remain : (bytePerBlk - offset_in_block); + ret = SpiNandEraseWriteInBlock(currblk, offset_in_block, pbuf, burn_size); + if (ret != SNF_OK) { + printf("###ERR:%s, erase write block(%d) failed.\n", __func__, currblk); + break; + } + + if (offset_in_block) + offset_in_block = 0; + + currblk++; + pbuf += burn_size; + remain -= burn_size; + if (remain < 0) { + ret = -SNF_ERR; + printf("###ERR:%s, Invalid remain\n", __func__); + break; + } + + if (show_progress) + update_progress_set((size - remain) * 100 / size); + } + + if (show_progress) + update_progress_set(100); + + SpiNandWriteDisable(); + + return ret; +} + +int FlashBurn(void *buf, u32 offset, u32 size, int show_progress) +{ + return SpiNandBurn(buf, offset, size, show_progress); +} + +int SpiReadSysInfo(SysInfo *info) +{ + u32 *buf = (u32*)IMAGE_ENTRY; + u32 checksum; + u32 calc_checksum; + int ret; + + ret = SpiNandReadData(SYSINFOA_OFFSET, buf, sizeof(SysInfo)); + if (ret != SNF_OK) { + printf("###ERR:%s, SYSINFOA_OFFSET read failed, ret:%d.\n", __func__, ret); + } + + checksum = *(u32*)(IMAGE_ENTRY + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((u8*)IMAGE_ENTRY, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, (void*)IMAGE_ENTRY, sizeof(SysInfo)); + printf("%s, SYSINFOA_OFFSET.\n", __func__); + return 0; + } + + buf = (u32*)IMAGE_ENTRY; + + ret = SpiNandReadData(SYSINFOB_OFFSET, buf, sizeof(SysInfo)); + if (ret != SNF_OK) { + printf("###ERR:%s, SYSINFOB_OFFSET read failed, ret:%d.\n", __func__, ret); + } + + checksum = *(u32*)(IMAGE_ENTRY + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((u8*)IMAGE_ENTRY, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, (void*)IMAGE_ENTRY, sizeof(SysInfo)); + printf("%s, SYSINFOB_OFFSET.\n", __func__); + return 0; + } + + return -1; +} + + +void SpiWriteSysInfo(SysInfo *info) +{ + SpiNandBurn(info, SYSINFOB_OFFSET, sizeof(SysInfo), 0); + SpiNandBurn(info, SYSINFOA_OFFSET, sizeof(SysInfo), 0); +} + +u32 SpiGetUpfileOffset(int type) +{ + int bytePerPage = g_snf.BytePerPage; + int bytePerBlk = g_snf.BytePerBlk; + SysInfo *sysinfo = GetSysInfo(); + + if (type == UPFILE_TYPE_WHOLE) { + if (sysinfo->image_offset == IMAGE_OFFSET) + sysinfo->image_offset = IMAGEB_OFFSET; + else + sysinfo->image_offset = IMAGE_OFFSET; + return sysinfo->image_offset; + } else if (type == UPFILE_TYPE_FIRSTLDR) { + return LOADER_OFFSET; + } else if (type == UPFILE_TYPE_STEPLDR) { + if (sysinfo->stepldr_offset == STEPLDRA_OFFSET) + sysinfo->stepldr_offset = STEPLDRB_OFFSET; + else + sysinfo->stepldr_offset = STEPLDRA_OFFSET; + return sysinfo->stepldr_offset; + } else { + u32 buf[MAX_PAGE_SIZE/4]; + UpFileHeader *header; + UpFileInfo *appfile; + u32 offset; + int i; + + SpiNandReadData(sysinfo->image_offset, buf, bytePerPage); + header = (UpFileHeader*)buf; + if (header->magic != MKTAG('U', 'P', 'D', 'F')) { + SendUartString("old update file isn't found in flash, can't support module update.\n"); + return 0xffffffff; + } + for (i = 0; i < header->filenum; i++) { + appfile = &header->files[i]; + if ((appfile->magic == UPFILE_APP_MAGIC && type == UPFILE_TYPE_APP) || + (appfile->magic == MKTAG('R', 'O', 'M', 'A') && type == UPFILE_TYPE_RESOURCE) || + (appfile->magic == MKTAG('B', 'A', 'N', 'I') && type == UPFILE_TYPE_ANIMATION)) { + offset = appfile->offset; + if (offset & (bytePerBlk - 1)) { + SendUartString("offset isn't align to block erase size, can't support module update.\n"); + return 0xffffffff; + } + return offset + sysinfo->image_offset; + } + } + } + + return 0xffffffff; +} +#endif diff --git a/A58-STEPLDR/Src/aic.c b/A58-STEPLDR/Src/aic.c new file mode 100644 index 00000000..d367f324 --- /dev/null +++ b/A58-STEPLDR/Src/aic.c @@ -0,0 +1,103 @@ + /** + * \file + * + * Implementation of Ark Interrupt Controller (AIC) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "amt630h.h" +#include "aic.h" +#include "timer.h" + +#include +#include + +#define ICSET 0x00 +#define ICPEND 0x04 +#define ICMODE 0x08 +#define ICMASK 0x0C +#define ICLEVEL 0x10 +#define IRQISPR 0x3C +#define IRQISPC 0x40 +#define IVEC_ADDR 0x78 + +typedef struct { + ISRFunction_t handler; + void *handler_param; +}IrqDesc_t; +static IrqDesc_t irq_descs[MAX_IRQ_NUM]; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +void AIC_Initialize(void) +{ + memset(irq_descs, 0, sizeof(irq_descs)); + + writel(0x8, REGS_AIC_BASE + ICSET); + udelay(10); + writel(0x5, REGS_AIC_BASE + ICSET); + writel(0x0, REGS_AIC_BASE + ICMODE); + writel(0xffffffff, REGS_AIC_BASE + ICMASK); + writel(0xffffffff, REGS_AIC_BASE + ICLEVEL); + writel(0xffffffff, REGS_AIC_BASE + IRQISPC); +} + +/** + * \brief Enables interrupts coming from the given (unique) source (ID_xxx). + * + * \param source Interrupt source to enable. + */ +void AIC_EnableIT(uint32_t source) +{ + writel(readl(REGS_AIC_BASE + ICMASK) & ~(1 << source), REGS_AIC_BASE + ICMASK); +} + +/** + * \brief Disables interrupts coming from the given (unique) source (ID_xxx). + * + * \param source Interrupt source to disable. + */ +void AIC_DisableIT(uint32_t source) +{ + writel(readl(REGS_AIC_BASE + ICMASK) | (1 << source), REGS_AIC_BASE + ICMASK); +} + +int32_t request_irq(uint32_t irq_source, int32_t priority, ISRFunction_t func, void *param) +{ + if (irq_source > MAX_IRQ_NUM - 1) { + return -1; + } + + irq_descs[irq_source].handler = func; + irq_descs[irq_source].handler_param = param; + AIC_EnableIT(irq_source); + + return 0; +} + +int32_t free_irq(uint32_t irq_source) +{ + if (irq_source > MAX_IRQ_NUM - 1) { + return -1; + } + + irq_descs[irq_source].handler = NULL; + irq_descs[irq_source].handler_param = NULL; + AIC_DisableIT(irq_source); + + return 0; +} + + +void AIC_IrqHandler(void) +{ + int32_t source = readl(REGS_AIC_BASE + IVEC_ADDR) >> 2; + if (irq_descs[source].handler) + irq_descs[source].handler(irq_descs[source].handler_param); + writel(1 << source, REGS_AIC_BASE + IRQISPC); +} diff --git a/A58-STEPLDR/Src/aic.h b/A58-STEPLDR/Src/aic.h new file mode 100644 index 00000000..229fb634 --- /dev/null +++ b/A58-STEPLDR/Src/aic.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \section Purpose + * + * Methods and definitions for configuring interrupts. + * + * \section Usage + * -# Enable or disable interrupt generation of a particular source with + * IRQ_EnableIT and IRQ_DisableIT. + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef AIC_H +#define AIC_H + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + + #ifdef __cplusplus + extern "C" { +#endif + +typedef void (*ISRFunction_t)( void *param ); + +extern void AIC_Initialize(void); +extern void AIC_EnableIT( uint32_t source); +extern void AIC_DisableIT(uint32_t source); +extern int32_t request_irq(uint32_t irq_source, int32_t priority, ISRFunction_t func, void *param); +extern int32_t free_irq(uint32_t irq_source); +extern void AIC_IrqHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif //#ifndef AIC_H + diff --git a/A58-STEPLDR/Src/amt630h.h b/A58-STEPLDR/Src/amt630h.h new file mode 100644 index 00000000..067f8edc --- /dev/null +++ b/A58-STEPLDR/Src/amt630h.h @@ -0,0 +1,485 @@ +/*********************************************************************** +Copyright (c)2020 Arkmicro Technologies Inc. All Rights Reserved +Filename: amt630h.h +Version : 1.0 +Date : 2020.04.08 +Author : Sim. Huang +History : +************************************************************************/ + +#ifndef _AMT630H_H_ +#define _AMT630H_H_ + +#include +#include + //change the Assemble logic valuable VECTOR_ENABLE //in file Boot.s +#define CLK_24MHZ 24000000 + +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AMT630H */ +/* ************************************************************************** */ +/** \addtogroup AMT630H_base Peripheral Base Address Definitions */ +/*@{*/ + +#define REGS_SYSCTL_BASE (0x60000000U) +#define REGS_SPI0_BASE (0x60100000U) +#define REGS_SPI1_BASE (0x60200000U) +#define REGS_IIC0_BASE (0x60300000U) +#define REGS_IIC1_BASE (0x60400000U) +#define REGS_UART0_BASE (0x60500000U) +#define REGS_UART1_BASE (0x60600000U) +#define REGS_UART2_BASE (0x60700000U) +#define REGS_UART3_BASE (0x60800000U) +#define REGS_GPIO_BASE (0x60900000U) +#define REGS_TIMER_BASE (0x60a00000U) +#define REGS_PWM_BASE (0x60b00000U) +#define REGS_WDT_BASE (0x60c00000U) +#define REGS_I2S_BASE (0x60d00000U) +#define REGS_MIPI_BASE (0x60e00000U) +#define REGS_RTC_BASE (0x61000000U) +#define REGS_ADC_BASE (0x61100000U) +#define REGS_RCRT_BASE (0x61200000U) +#define REGS_AES_BASE (0x61300000U) +#define REGS_AIC_BASE (0x61400000U) +#define REGS_CAN0_BASE (0x61500000U) +#define REGS_CAN1_BASE (0x61600000U) + +#define REGS_DMAC_BASE (0x70100000U) +#define REGS_GPU_BASE (0x70200000U) +#define REGS_USB_BASE (0x70300000U) +#define REGS_SDMMC0_BASE (0X70400000U) +#define REGS_ITU_BASE (0X70600000U) +#define REGS_LCD_BASE (0X71000000U) +#define REGS_PXP_BASE (0X71100000U) +#define REGS_ROTATE_BASE (0X71207000U) +#define REGS_JPG_BASE (0X71208000U) +#define REGS_DDRC_BASE (0X71300000U) + +#define SYS_IO_DRIVER00 0xe0 +#define SYS_IO_DRIVER01 0xe4 +#define SYS_IO_DRIVER02 0xe8 +#define SYS_IO_DRIVER03 0xec +#define SYS_IO_DRIVER04 0xf0 +#define SYS_IO_DRIVER05 0xf4 +#define SYS_IO_DRIVER06 0xf8 +#define SYS_IO_DRIVER07 0xfc + +/* register base address */ + +#define SDHC0_BASE 0x70400000 +#define USB_BASE 0x70300000//0x700C0000 +#define SSI1_BASE 0x60200000//0x48002000 +#define SSI0_BASE 0x60100000 +#define GPIO_BASE 0x60900000//0x40409000 +#define SYS_BASE 0x60000000//0x40408000 +#define TIMER_BASE 0x60a00000//0x40405000 +#define WDT_BASE 0x60c00000//0x40404000 +#define RTC_BASE 0x61000000//0x40406000 +#define UART0_BASE 0x60500000//0x4040B000 + +//uart +#define UART_BASE UART0_BASE +#define rUART_DR *((volatile unsigned int *)(UART_BASE + 0x00)) +#define rUART_RSR *((volatile unsigned int *)(UART_BASE + 0x04)) +#define rUART_FR *((volatile unsigned int *)(UART_BASE + 0x18)) +#define rUART_ILPR *((volatile unsigned int *)(UART_BASE + 0x20)) +#define rUART_IBRD *((volatile unsigned int *)(UART_BASE + 0x24)) +#define rUART_FBRD *((volatile unsigned int *)(UART_BASE + 0x28)) +#define rUART_LCR_H *((volatile unsigned int *)(UART_BASE + 0x2C)) +#define rUART_CR *((volatile unsigned int *)(UART_BASE + 0x30)) +#define rUART_IFLS *((volatile unsigned int *)(UART_BASE + 0x34)) +#define rUART_IMSC *((volatile unsigned int *)(UART_BASE + 0x38)) +#define rUART_RIS *((volatile unsigned int *)(UART_BASE + 0x3C)) +#define rUART_MIS *((volatile unsigned int *)(UART_BASE + 0x40)) +#define rUART_ICR *((volatile unsigned int *)(UART_BASE + 0x44)) +#define rUART_DMACR *((volatile unsigned int *)(UART_BASE + 0x48)) + + +/*************************************************************** + AHB slave interface registers definition +****************************************************************/ +/* AHB system */ +#define rSYS_BOOT_SAMPLE *((volatile unsigned int *)(SYS_BASE+0x0)) +#define rSYS_BUS_CLK_SEL *((volatile unsigned int *)(SYS_BASE+0x40)) +#define rSYS_PLLRFCK_CTL *((volatile unsigned int *)(SYS_BASE+0x44)) +#define rSYS_SDMMC_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x48)) +#define rSYS_VOU_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x4c)) +#define rSYS_PER_CLK_EN *((volatile unsigned int *)(SYS_BASE+0x50)) +#define rSYS_LCD_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x54)) +#define rSYS_SD_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x58)) +#define rSYS_SOFT_RST *((volatile unsigned int *)(SYS_BASE+0x5c)) +#define rSYS_SOFT1_RST *((volatile unsigned int *)(SYS_BASE+0x60)) +#define rSYS_SSP_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x64)) +#define rSYS_TIMER_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x68)) +#define rSYS_I2S_NCO_CFG *((volatile unsigned int *)(SYS_BASE+0x6c)) + +#define rSYS_DDRCTL_CFG *((volatile unsigned int *)(SYS_BASE+0x70)) +#define rSYS_DDRCTL1_CFG *((volatile unsigned int *)(SYS_BASE+0x74)) +#define rSYS_PERCTL_CFG *((volatile unsigned int *)(SYS_BASE+0x78)) +#define rSYS_TIMER1_CLK_CFG *((volatile unsigned int *)(SYS_BASE+0x7c)) +#define rSYS_ANA_CFG *((volatile unsigned int *)(SYS_BASE+0x80)) +#define rSYS_ANA1_CFG *((volatile unsigned int *)(SYS_BASE+0x84)) +#define rSYS_CPUPLL_CFG *((volatile unsigned int *)(SYS_BASE+0x88)) +#define rSYS_SYSPLL_CFG *((volatile unsigned int *)(SYS_BASE+0x8c)) + +#define rSYS_ANA2_CFG *((volatile unsigned int *)(SYS_BASE+0x98)) +#define rSYS_ANA3_CFG *((volatile unsigned int *)(SYS_BASE+0x9c)) + + + +#define rSYS_PAD_CTRL00 *((volatile unsigned int *)(SYS_BASE+0x30*4)) +#define rSYS_PAD_CTRL01 *((volatile unsigned int *)(SYS_BASE+0x31*4)) +#define rSYS_PAD_CTRL02 *((volatile unsigned int *)(SYS_BASE+0x32*4)) +#define rSYS_PAD_CTRL03 *((volatile unsigned int *)(SYS_BASE+0x33*4)) +#define rSYS_PAD_CTRL04 *((volatile unsigned int *)(SYS_BASE+0x34*4)) +#define rSYS_PAD_CTRL05 *((volatile unsigned int *)(SYS_BASE+0xD4)) +#define rSYS_PAD_CTRL06 *((volatile unsigned int *)(SYS_BASE+0x36*4)) +#define rSYS_PAD_CTRL07 *((volatile unsigned int *)(SYS_BASE+0x37*4)) + +#define rSYS_IO_DRIVER00 *((volatile unsigned int *)(SYS_BASE+0x38*4)) +#define rSYS_IO_DRIVER01 *((volatile unsigned int *)(SYS_BASE+0x39*4)) +#define rSYS_IO_DRIVER02 *((volatile unsigned int *)(SYS_BASE+0x3A*4)) +#define rSYS_IO_DRIVER03 *((volatile unsigned int *)(SYS_BASE+0x3B*4)) +#define rSYS_IO_DRIVER04 *((volatile unsigned int *)(SYS_BASE+0x3C*4)) +#define rSYS_IO_DRIVER05 *((volatile unsigned int *)(SYS_BASE+0x3D*4)) +#define rSYS_IO_DRIVER06 *((volatile unsigned int *)(SYS_BASE+0x3E*4)) +#define rSYS_IO_DRIVER07 *((volatile unsigned int *)(SYS_BASE+0x3F*4)) + + +/* Timer */ +#define rTIMER0_LOAD_COUNT (*(volatile unsigned int *)(TIMER_BASE + 0x00)) +#define rTIMER0_CURRENT_VALUE (*(volatile unsigned int *)(TIMER_BASE + 0x04)) +#define rTIMER0_CONTROL (*(volatile unsigned int *)(TIMER_BASE + 0x08)) +#define rTIMER0_EOI (*(volatile unsigned int *)(TIMER_BASE + 0x0C)) +#define rTIMER0_INT_STATUS (*(volatile unsigned int *)(TIMER_BASE + 0x10)) + +/* WDT */ +#define rWDT_CR (*(volatile unsigned int *)(WDT_BASE + 0x00)) +#define rWDT_PSR (*(volatile unsigned int *)(WDT_BASE + 0x04)) +#define rWDT_LDR (*(volatile unsigned int *)(WDT_BASE + 0x08)) +#define rWDT_VLR (*(volatile unsigned int *)(WDT_BASE + 0x0C)) +#define rWDT_ISR (*(volatile unsigned int *)(WDT_BASE + 0x10)) +#define rWDT_RCR (*(volatile unsigned int *)(WDT_BASE + 0x14)) +#define rWDT_TMR (*(volatile unsigned int *)(WDT_BASE + 0x18)) +#define rWDT_TCR (*(volatile unsigned int *)(WDT_BASE + 0x1C)) + +/* RTC */ +#define rRTC_CTL (*(volatile unsigned int *)(RTC_BASE + 0x00)) /*control register*/ +#define rRTC_ANAWEN (*(volatile unsigned int *)(RTC_BASE + 0x04)) /*analog block write enable register*/ +#define rRTC_ANACTL (*(volatile unsigned int *)(RTC_BASE + 0x08)) /*analog block control register*/ +#define rRTC_IM (*(volatile unsigned int *)(RTC_BASE + 0x0C)) /*interrupt mode register*/ +#define rRTC_STA (*(volatile unsigned int *)(RTC_BASE + 0x10)) /*rtc status register*/ +#define rRTC_ALMDAT (*(volatile unsigned int *)(RTC_BASE + 0x14)) /*alarm data register*/ +#define rRTC_DONT (*(volatile unsigned int *)(RTC_BASE + 0x18)) /*delay on timer register*/ +#define rRTC_RAM (*(volatile unsigned int *)(RTC_BASE + 0x1C)) /*ram bit register*/ +#define rRTC_CNTL (*(volatile unsigned int *)(RTC_BASE + 0x20)) /*rtc counter register*/ +#define rRTC_CNTH (*(volatile unsigned int *)(RTC_BASE + 0x24)) /*rtc sec counter register*/ + +/* UART0 */ +#define rUART0_DR (*(volatile unsigned int *)(UART0_BASE + 0x00)) +#define rUART0_RSR (*(volatile unsigned int *)(UART0_BASE + 0x04)) +#define rUART0_FR (*(volatile unsigned int *)(UART0_BASE + 0x18)) +#define rUART0_ILPR (*(volatile unsigned int *)(UART0_BASE + 0x20)) +#define rUART0_IBRD (*(volatile unsigned int *)(UART0_BASE + 0x24)) +#define rUART0_FBRD (*(volatile unsigned int *)(UART0_BASE + 0x28)) +#define rUART0_LCR_H (*(volatile unsigned int *)(UART0_BASE + 0x2C)) +#define rUART0_CR (*(volatile unsigned int *)(UART0_BASE + 0x30)) +#define rUART0_IFLS (*(volatile unsigned int *)(UART0_BASE + 0x34)) +#define rUART0_IMSC (*(volatile unsigned int *)(UART0_BASE + 0x38)) +#define rUART0_RIS (*(volatile unsigned int *)(UART0_BASE + 0x3C)) +#define rUART0_MIS (*(volatile unsigned int *)(UART0_BASE + 0x40)) +#define rUART0_ICR (*(volatile unsigned int *)(UART0_BASE + 0x44)) +#define rUART0_DMACR (*(volatile unsigned int *)(UART0_BASE + 0x48)) + + +/* SSI */ +#define rSPI_CONTROLREG (*(volatile unsigned int *)(SSI1_BASE + 0x08)) +#define rSPI_CONFIGREG (*(volatile unsigned int *)(SSI1_BASE + 0x0C)) +#define rSPI_INTREG (*(volatile unsigned int *)(SSI1_BASE + 0x10)) +#define rSPI_DMAREG (*(volatile unsigned int *)(SSI1_BASE + 0x14)) +#define rSPI_STATUSREG (*(volatile unsigned int *)(SSI1_BASE + 0x18)) +#define rSPI_PERIODREG (*(volatile unsigned int *)(SSI1_BASE + 0x1C)) +#define rSPI_TESTREG (*(volatile unsigned int *)(SSI1_BASE + 0x20)) +#define rSPI_MSGREG (*(volatile unsigned int *)(SSI1_BASE + 0x40)) +#define rSPI_RXDATA (*(volatile unsigned int *)(SSI1_BASE + 0x50)) +#define rSPI_TXDATA (*(volatile unsigned int *)(SSI1_BASE + 0x460)) +#define rSPI_TXFIFO (SSI_BASE + 0x460) +#define rSPI_RXFIFO (SSI_BASE + 0x50) + +/* SSI0 */ +#define rSPI_CTLR0 (*(volatile unsigned int *)(SSI0_BASE + 0x00)) +#define rSPI_CTLR1 (*(volatile unsigned int *)(SSI0_BASE + 0x04)) +#define rSPI_SSIENR (*(volatile unsigned int *)(SSI0_BASE + 0x08)) +#define rSPI_MWCR (*(volatile unsigned int *)(SSI0_BASE + 0x0c)) +#define rSPI_SER (*(volatile unsigned int *)(SSI0_BASE + 0x10)) +#define rSPI_BAUDR (*(volatile unsigned int *)(SSI0_BASE + 0x14)) +#define rSPI_TXFTLR (*(volatile unsigned int *)(SSI0_BASE + 0x18)) +#define rSPI_RXFTLR (*(volatile unsigned int *)(SSI0_BASE + 0x1C)) +#define rSPI_TXFLR (*(volatile unsigned int *)(SSI0_BASE + 0x20)) +#define rSPI_RXFLR (*(volatile unsigned int *)(SSI0_BASE + 0x24)) +#define rSPI_SR (*(volatile unsigned int *)(SSI0_BASE + 0x28)) +#define rSPI_IMR (*(volatile unsigned int *)(SSI0_BASE + 0x2C)) +#define rSPI_ISR (*(volatile unsigned int *)(SSI0_BASE + 0x30)) +#define rSPI_RISR (*(volatile unsigned int *)(SSI0_BASE + 0x34)) +#define rSPI_TXOICR (*(volatile unsigned int *)(SSI0_BASE + 0x38)) +#define rSPI_RXOICR (*(volatile unsigned int *)(SSI0_BASE + 0x3C)) +#define rSPI_RXUICR (*(volatile unsigned int *)(SSI0_BASE + 0x40)) +#define rSPI_MSTICR (*(volatile unsigned int *)(SSI0_BASE + 0x44)) +#define rSPI_ICR (*(volatile unsigned int *)(SSI0_BASE + 0x48)) +#define rSPI_DMACR (*(volatile unsigned int *)(SSI0_BASE + 0x4C)) +#define rSPI_DMATDLR (*(volatile unsigned int *)(SSI0_BASE + 0x50)) +#define rSPI_DMARDLR (*(volatile unsigned int *)(SSI0_BASE + 0x54)) +#define rSPI_IDR (*(volatile unsigned int *)(SSI0_BASE + 0x58)) +#define rSPI_SSI_COMP_VERSION (*(volatile unsigned int *)(SSI0_BASE + 0x5C)) +#define rSPI_DR (*(volatile unsigned int *)(SSI0_BASE + 0x60)) +#define SPI_DR (SSI0_BASE + 0x60) + +#define rSPI_RX_SAMPLE_DLY (*(volatile unsigned int *)(SSI0_BASE + 0xf0)) +#define rSPI_SPI_CTRLR0 (*(volatile unsigned int *)(SSI0_BASE + 0xf4)) +//#define rSPI_RSVD_1 (*(volatile unsigned int *)(SSI0_BASE + 0xf8)) +//#define rSPI_RSVD_1 (*(volatile unsigned int *)(SSI0_BASE + 0xfC)) + + + +/* GPIO */ +#define rGPIO_PA_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x00)) +#define rGPIO_PA_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x04)) +#define rGPIO_PA_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x08)) +#define rGPIO_PA_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x0C)) +#define rGPIO_PA_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x10)) + +#define rGPIO_PB_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x20)) +#define rGPIO_PB_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x24)) +#define rGPIO_PB_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x28)) +#define rGPIO_PB_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x2C)) +#define rGPIO_PB_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x30)) + +#define rGPIO_PC_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x40)) +#define rGPIO_PC_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x44)) +#define rGPIO_PC_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x48)) +#define rGPIO_PC_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x4C)) +#define rGPIO_PC_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x50)) + +#define rGPIO_PD_MOD (*(volatile unsigned int *)(GPIO_BASE + 0x60)) +#define rGPIO_PD_RDATA (*(volatile unsigned int *)(GPIO_BASE + 0x64)) +#define rGPIO_PD_INTEN (*(volatile unsigned int *)(GPIO_BASE + 0x68)) +#define rGPIO_PD_LEVEL (*(volatile unsigned int *)(GPIO_BASE + 0x6C)) +#define rGPIO_PD_PEND (*(volatile unsigned int *)(GPIO_BASE + 0x70)) + + +//DDR Reg + + +#define DDR_BASE 0x71300000 + +#define MEM_STA_REG *(volatile unsigned int *)(DDR_BASE + 0x00) +#define MEM_CMD_REG *(volatile unsigned int *)(DDR_BASE + 0x04) +#define DIR_CMD_REG *(volatile unsigned int *)(DDR_BASE + 0x08) +#define MEM_CFG_REG *(volatile unsigned int *)(DDR_BASE + 0x0C) +#define REF_PRD_REG *(volatile unsigned int *)(DDR_BASE + 0x10) +#define TCAS_REG *(volatile unsigned int *)(DDR_BASE + 0x14) +#define TDQSS_REG *(volatile unsigned int *)(DDR_BASE + 0x18) +#define TMRD_REG *(volatile unsigned int *)(DDR_BASE + 0x1C) +#define TRAS_REG *(volatile unsigned int *)(DDR_BASE + 0x20) +#define TRC_REG *(volatile unsigned int *)(DDR_BASE + 0x24) +#define TRCD_REG *(volatile unsigned int *)(DDR_BASE + 0x28) +#define TRFC_REG *(volatile unsigned int *)(DDR_BASE + 0x2C) +#define TRP_REG *(volatile unsigned int *)(DDR_BASE + 0x30) +#define TRRD_REG *(volatile unsigned int *)(DDR_BASE + 0x34) +#define TWR_REG *(volatile unsigned int *)(DDR_BASE + 0x38) +#define TWTR_REG *(volatile unsigned int *)(DDR_BASE + 0x3C) +#define TXP_REG *(volatile unsigned int *)(DDR_BASE + 0x40) +#define TXSR_REG *(volatile unsigned int *)(DDR_BASE + 0x44) +#define TESR_REG *(volatile unsigned int *)(DDR_BASE + 0x48) +#define MEM_CFG2_REG *(volatile unsigned int *)(DDR_BASE + 0x4C) +#define CHIP_CFG_REG *(volatile unsigned int *)(DDR_BASE + 0x200) +#define FEA_CTL_REG *(volatile unsigned int *)(DDR_BASE + 0x30C) + +typedef enum IRQn +{ + LCD_IRQn = 0, /**< 0 AMT630H LCD Interrupt ID */ + JPG_IRQn = 1, /**< 1 AMT630H Jpeg Decoder Interrupt (JPG) */ + GPU_IRQn = 2, /**< 2 AMT630H GPU Interrupt (GPU) */ + USB_IRQn = 3, /**< 3 AMT630H USB Controller Interrupt (USB) */ + PXP_IRQn = 4, /**< 4 AMT630H PXP Interrupt (PXP) */ + DMA_IRQn = 5, /**< 5 AMT630H DMA Controller Interrupt (DMAC) */ + SDMMC0_IRQn = 6, /**< 6 AMT630H SDMMC 0 Controller Interrupt (SDMMC0) */ + SPI0_IRQn = 7, /**< 7 AMT630H SPI 0 Controller Interrupt (SPI0) */ + SPI1_IRQn = 8, /**< 8 AMT630H SPI 1 Controller Interrupt (SPI1) */ + I2C0_IRQn = 9, /**< 9 AMT630H I2C0 Controller Interrupt (I2C0) */ + I2C1_IRQn = 10, /**< 10 AMT630H I2C1 Controller Interrupt (I2C1) */ + UART0_IRQn = 11, /**< 11 AMT630H UART 0 Controller Interrupt (UART0) */ + UART1_IRQn = 12, /**< 12 AMT630H UART 1 Controller Interrupt (UART1) */ + UART2_IRQn = 13, /**< 13 AMT630H UART 2 Controller Interrupt (UART2) */ + UART3_IRQn = 14, /**< 14 AMT630H UART 3 Controller Interrupt (UART3) */ + GPIOA_IRQn = 15, /**< 15 AMT630H GPIO0~31 Controller Interrupt (GPIOA) */ + GPIOB_IRQn = 16, /**< 16 AMT630H GPIO32~63 Controller Interrupt (GPIOB) */ + GPIOC_IRQn = 17, /**< 17 AMT630H GPIO64~95 Controller Interrupt (GPIOC) */ + GPIOD_IRQn = 18, /**< 18 AMT630H GPIO96~127 Controller Interrupt (GPIOD) */ + TIMER0_IRQn = 19, /**< 19 AMT630H Timer 0 Interrupt (TIMER0) */ + TIMER1_IRQn = 20, /**< 20 AMT630H Timer 1 Interrupt (TIMER1) */ + TIMER2_IRQn = 21, /**< 21 AMT630H Timer 2 Interrupt (TIMER2) */ + TIMER3_IRQn = 22, /**< 22 AMT630H Timer 3 Interrupt (TIMER3) */ + ITU_IRQn = 23, /**< 23 AMT630H ITU Controller Interrupt (ITU) */ + WDT_IRQn = 24, /**< 24 AMT630H Watchdog timer Interrupt (WDT) */ + RTC_I2S_IRQn = 25, /**< 25 AMT630H I2S Interrupt (I2S) */ + RTC_ALM_IRQn = 26, /**< 26 AMT630H RTC Controller Alarm Interrupt (RTCA) */ + RTC_PRD_IRQn = 27, /**< 27 AMT630H RTC Controller Period Interrupt (RTCP) */ + ADC_IRQn = 28, /**< 28 AMT630H ADC controller Interrupt (ADC) */ + RCRT_IRQn = 29, /**< 29 */ + CAN0_IRQn = 30, /**< 30 AMT630H CAN0 Controller Interrupt (CAN0) */ + CAN1_IRQn = 31, /**< 31 AMT630H CAN1 Controller Interrupt (CAN1) */ + MAX_IRQ_NUM = 32 /**< Number of peripheral IDs */ +} IRQn_Type; + +#define MMU_ENABLE + +#define SPI_NOR_FLASH 0 +#define SPI_NAND_FLASH 1 +#define EMMC_FLASH 2 +#define DEVICE_TYPE_SELECT SPI_NOR_FLASH +#define OTA_UPDATE_SUPPORT + +#if DEVICE_TYPE_SELECT == SPI_NAND_FLASH +#define LOADER_OFFSET 0x0 +#define LOADER_MAX_SIZE 0x4000 + +#define STEPLDRA_OFFSET 0x20000 +#define STEPLDRB_OFFSET 0x40000 +#define STEPLDR_MAX_SIZE 0x14000 + +#define SYSINFOA_OFFSET 0x60000 +#define SYSINFOB_OFFSET 0x80000 +#define SYSINFO_MAX_SIZE 0x1000 + +#define IMAGE_OFFSET 0xa0000 +#ifdef OTA_UPDATE_SUPPORT +#define IMAGEB_OFFSET 0xc00000 +#else +#define IMAGEB_OFFSET IMAGE_OFFSET +#endif +#define IMAGE_READ_SIZE 0x20000 + +#define LOADER_FILE_NAME "spildr.bin" +#define STEPLDR_FILE_NAME "stepldr.bin" +#define APP_FILE_NAME "update.bin" + +#elif DEVICE_TYPE_SELECT == SPI_NOR_FLASH +#define LOADER_OFFSET 0x0 +#define LOADER_MAX_SIZE 0x4000 + +#define STEPLDRA_OFFSET 0x4000 +#define STEPLDRB_OFFSET 0x20000 +#define STEPLDR_MAX_SIZE 0x14000 + +#define SYSINFOA_OFFSET 0x3c000 +#define SYSINFOB_OFFSET 0x3e000 +#define SYSINFO_MAX_SIZE 0x1000 + +#define IMAGE_OFFSET 0x40000 +#define IMAGE_MAX_SIZE 0xb00000 +#ifdef OTA_UPDATE_SUPPORT +#define IMAGEB_OFFSET 0xc00000 +#else +#define IMAGEB_OFFSET IMAGE_OFFSET +#endif +#define IMAGE_READ_SIZE 0x10000 + +#define OTA_OFFSET 0x1800000 + +#define LOADER_FILE_NAME "spildr.bin" +#define STEPLDR_FILE_NAME "stepldr.bin" +#define APP_FILE_NAME "update.bin" + +#elif DEVICE_TYPE_SELECT == EMMC_FLASH +/********************************************************************************************** +emmc������� +(0-------0x200000-------0x400000------0x500000---0xA00000-----0x40000000-----0x80000000-----end +|------------|--------------|--------------|---------|-------------|----------- --|-----------| +| | | | | | | | +| EMMCLDR | stepldr | SYSINFO | log | app1 | app2 | ota | +|____________|______________|______________|_________|_____________|______________|___________| + +**********************************************************************************************/ +#define LOADER_OFFSET 0x0 +#define LOADERB_OFFSET 0x100000 +#define LOADER_MAX_SIZE 0x4000 + +#define STEPLDRA_OFFSET 0x200000 +#define STEPLDRB_OFFSET 0x300000 +#define STEPLDR_MAX_SIZE 0x14000 + +#define SYSINFOA_OFFSET 0x400000 +#define SYSINFOB_OFFSET 0x500000 +#define SYSINFO_MAX_SIZE 0x1000 + +#define IMAGE_OFFSET 0xa00000 +#define IMAGEB_OFFSET 0x40000000 +#define IMAGE_MAX_SIZE 0xf00000 +#define IMAGE_READ_SIZE 0x80000 + +#define OTA_OFFSET 0x80000000 + +#define LOADER_FILE_NAME "emmcldr.bin" +#define LAUNCHEMMC_FILE_NAME "lnchemmc.bin" +#define STEPLDR_FILE_NAME "stepldr.bin" +#define APP_FILE_NAME "update.bin" + +#endif + +#define IMAGE_ENTRY 0x20000000 + +typedef struct { + unsigned int magic; + unsigned int offset; + unsigned int size; +} UpFileInfo; + +typedef struct { + unsigned int magic; + unsigned int filenum; + unsigned int size; + unsigned int checksum; + unsigned int reserved1; + unsigned int reserved2; + UpFileInfo files[]; +} UpFileHeader; + +#define ENOENT 2 /* No such file or directory */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define ENOMEM 12 /* Out of memory */ +#define ENODEV 19 /* No such device */ +#define EINVAL 22 /* Invalid argument */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define EPROTO 71 /* Protocol error */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ + +#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +//typedef unsigned long uintptr_t; + +#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) +#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) +#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ + char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ + + (align - 1)]; \ + \ + type *name = (type *)ALIGN((uintptr_t)__##name, align) +#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) +#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) +#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ + ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +#define reg32_read(addr) *((volatile uint32_t *)(addr)) +#define reg32_write(addr,val) *((volatile uint32_t *)(addr)) = (val) +#define readl(a) reg32_read(a) +#define writel(v, a) reg32_write(a, v) + +#endif // _AMT630H_H_ diff --git a/A58-STEPLDR/Src/board.h b/A58-STEPLDR/Src/board.h new file mode 100644 index 00000000..3b8e6b21 --- /dev/null +++ b/A58-STEPLDR/Src/board.h @@ -0,0 +1,164 @@ +#ifndef _BOARD_H +#define _BOARD_H + +/********** display configuration **********/ +#define LCD_INTERFACE_TTL 0 +#define LCD_INTERFACE_LVDS 1 +#define LCD_INTERFACE_CPU 2 +#define LCD_INTERFACE_MIPI 3 + +#define LCD_WIRING_MODE_RGB 0 +#define LCD_WIRING_MODE_RBG 1 +#define LCD_WIRING_MODE_GRB 2 +#define LCD_WIRING_MODE_GBR 3 +#define LCD_WIRING_MODE_BRG 4 +#define LCD_WIRING_MODE_BGR 5 + +#define LCD_WIRING_BIT_ORDER_MSB 0 +#define LCD_WIRING_BIT_ORDER_LSB 1 + +#define LVDS_PANEL_FORMAT_TI 0 +#define LVDS_PANEL_FORMAT_NS 1 + +#define LVDS_PANEL_DATA_8BIT 0 +#define LVDS_PANEL_DATA_6BIT 1 + +#define CPU_PANEL_18BIT_MODE 0 +#define CPU_PANEL_16BIT_MODE 1 +#define CPU_PANEL_9BIT_MODE 2 +#define CPU_PANEL_8BIT_MODE 3 + + +#define LCD_ROTATE_ANGLE_0 0 +#define LCD_ROTATE_ANGLE_90 1 +#define LCD_ROTATE_ANGLE_180 2 +#define LCD_ROTATE_ANGLE_270 3 + + +#ifdef DOUBLE_POINTER_HALO +#define LCD_WIDTH 1280 +#define LCD_HEIGHT 480 +#define LCD_BPP 16 +#define LCD_INTERFACE_TYPE LCD_INTERFACE_LVDS +#else +#define LCD_WIDTH 800 +#define LCD_HEIGHT 480 +#define LCD_BPP 32 +#define LCD_INTERFACE_TYPE LCD_INTERFACE_TTL +#endif + +#define LCD_H_FLIP 0//水平镜像 +#define LCD_V_FLIP 0//垂直镜像 +#define LCD_ROTATE_ANGLE LCD_ROTATE_ANGLE_0 + + +#if LCD_INTERFACE_TYPE == LCD_INTERFACE_TTL +#define LCD_WIRING_MODE LCD_WIRING_MODE_RGB +#define LCD_WIRING_BIT_ORDER LCD_WIRING_BIT_ORDER_LSB +#elif LCD_INTERFACE_TYPE == LCD_INTERFACE_LVDS +#define LCD_WIRING_MODE LCD_WIRING_MODE_BGR +#define LCD_WIRING_BIT_ORDER LCD_WIRING_BIT_ORDER_MSB +#define LVDS_SCREEN_RST_GPIO 74 +#define LVDS_PANEL_FORMAT LVDS_PANEL_FORMAT_TI +#define LVDS_PANEL_DATA LVDS_PANEL_DATA_8BIT +#elif LCD_INTERFACE_TYPE == LCD_INTERFACE_CPU +#define CPU_PANEL_DATA CPU_PANEL_8BIT_MODE +#elif LCD_INTERFACE_TYPE == LCD_INTERFACE_MIPI +#define LCD_WIRING_MODE LCD_WIRING_MODE_RGB +#define LCD_WIRING_BIT_ORDER LCD_WIRING_BIT_ORDER_MSB +#endif + +#define FB_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BPP / 8) + +#define VIDEO_DISPLAY_WIDTH LCD_WIDTH +#define VIDEO_DISPLAY_HEIGHT LCD_HEIGHT +#define VIDEO_DISPLAY_BUF_NUM 2 + +#if (LCD_WIDTH == 1024 && LCD_HEIGHT == 600) +#define LCD_TIMING_VBP 1 +#define LCD_TIMING_VFP 1 +#define LCD_TIMING_VSW 30 +#define LCD_TIMING_HBP 100 +#define LCD_TIMING_HFP 100 +#define LCD_TIMING_HSW 370 +#define LCD_CLK_FREQ 50000000 +#elif (LCD_WIDTH == 800 && LCD_HEIGHT == 480) +#define LCD_TIMING_VBP 1 +#define LCD_TIMING_VFP 1 +#define LCD_TIMING_VSW 30 +#define LCD_TIMING_HBP 50 +#define LCD_TIMING_HFP 50 +#define LCD_TIMING_HSW 180 +#define LCD_CLK_FREQ 35000000 +#elif (LCD_WIDTH == 480 && LCD_HEIGHT == 800) +#define LCD_TIMING_VBP 1 +#define LCD_TIMING_VFP 1 +#define LCD_TIMING_VSW 30 +#define LCD_TIMING_HBP 50 +#define LCD_TIMING_HFP 50 +#define LCD_TIMING_HSW 180 +#define LCD_CLK_FREQ 35000000 +#elif (LCD_WIDTH == 1280 && LCD_HEIGHT == 720) +#define LCD_TIMING_VBP 5 +#define LCD_TIMING_VFP 65 +#define LCD_TIMING_VSW 2 +#define LCD_TIMING_HBP 16 +#define LCD_TIMING_HFP 42 +#define LCD_TIMING_HSW 2 +#define LCD_CLK_FREQ 60000000 +#elif (LCD_WIDTH == 1280 && LCD_HEIGHT == 480) +#define LCD_TIMING_VBP 5 +#define LCD_TIMING_VFP 8 +#define LCD_TIMING_VSW 3 +#define LCD_TIMING_HBP 16 +#define LCD_TIMING_HFP 26 +#define LCD_TIMING_HSW 12 +#define LCD_CLK_FREQ 40000000 +#elif (LCD_WIDTH == 480 && LCD_HEIGHT == 1280) +#define LCD_TIMING_VBP 6// 14 +#define LCD_TIMING_VFP 6// 16 +#define LCD_TIMING_VSW 16// 2 +#define LCD_TIMING_HBP 16 +#define LCD_TIMING_HFP 36 +#define LCD_TIMING_HSW 26 +#define LCD_CLK_FREQ 50000000 +#elif (LCD_WIDTH == 480 && LCD_HEIGHT == 960) +#define LCD_TIMING_VBP 20 +#define LCD_TIMING_VFP 20 +#define LCD_TIMING_VSW 10 +#define LCD_TIMING_HBP 30 +#define LCD_TIMING_HFP 40 +#define LCD_TIMING_HSW 10 +#define LCD_CLK_FREQ 33330000 +#else +#error "no lcd timing configuraion." +#endif +/*******************************************/ + +/*********** uart configuration ************/ +#define UART_MCU_PORT 3 +/*******************************************/ + +/************ usb configuration ************/ +#define USB_SUPPORT +#define CONFIG_USB_DWC2_HOST 1 +#define CONFIG_USB_NEW_DWC2_HOST 1 +/*******************************************/ + +/************ spi configuration ************/ +#define SPI0_QSPI_MODE +/*******************************************/ + +/************ i2c configuration ************/ +//#define I2C_SUPPORT + +#ifdef I2C_SUPPORT +#define ANALOG_I2C_SUPPORT //Analog i2c support +#ifdef ANALOG_I2C_SUPPORT +#define I2C_GPIO0_SDA_PIN 49//51 +#define I2C_GPIO0_SCL_PIN 48//50 +#endif +#endif +/*******************************************/ + +#endif diff --git a/A58-STEPLDR/Src/cp15.c b/A58-STEPLDR/Src/cp15.c new file mode 100644 index 00000000..ca9cfc87 --- /dev/null +++ b/A58-STEPLDR/Src/cp15.c @@ -0,0 +1,365 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Reg Reads Writes +//---------------------------------------------------------------------------- +// 0 ID code Unpredictable +// 0 cache type Unpredictable +// 0 TCM status Unpredictable +// 1 Control Control +// 2 Translation table base Translation table base +// 3 Domain access control Domain access control +// 4 (Reserved) +// 5 Data fault status Data fault status +// 5 Instruction fault status Instruction fault status +// 6 Fault address Fault address +// 7 cache operations cache operations +// 8 Unpredictable TLB operations +// 9 cache lockdown cache lockdown +// 9 TCM region TCM region +// 10 TLB lockdown TLB lockdown +// 11 (Reserved) +// 12 (Reserved) +// 13 FCSE PID FCSE PID +// 13 Context ID Context ID +// 14 (Reserved) +// 15 Test configuration Test configuration +//----------------------------------------------------------------------------- + + +/** \page cp15_f CP15 Functions. + * + * \section CP15 function Usage + * + * Methods to manage the Coprocessor 15. Coprocessor 15, or System Control + * Coprocessor CP15, is used to configure and control all the items in the + * list below: + *
        + *
      • ARM core + *
      • caches (Icache, Dcache and write buffer) + *
      • TCM + *
      • MMU + *
      • Other system options + *
      + * \section Usage + * + * -# Enable or disable D cache with Enable_D_cache and Disable_D_cache + * -# Enable or disable I cache with Enable_I_cache and Disable_I_cache + * + * Related files:\n + * \ref cp15.h\n + * \ref cp15.c.\n + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "cp15.h" +#include "uart.h" + +#if defined(__ICCARM__) + #include +#endif +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Check Instruction cache + * \return 0 if I_cache disable, 1 if I_cache enable + */ +unsigned int CP15_IsIcacheEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & (1 << CP15_I_BIT)) != 0); +} + + +/** + * \brief Enable Instruction cache + */ +void CP15_EnableIcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is disabled + if ((control & (1 << CP15_I_BIT)) == 0) { + + control |= (1 << CP15_I_BIT); + CP15_WriteControl(control); + //SendUartString("I cache enabled.\n\r"); + } + else { + + //SendUartString("I cache is already enabled.\n\r"); + } +} + + +/** + * \brief Disable Instruction cache + */ +void CP15_DisableIcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is enabled + if ((control & (1 << CP15_I_BIT)) != 0) { + + control &= ~(1ul << CP15_I_BIT); + CP15_WriteControl(control); + //SendUartString("I cache disabled.\n\r"); + } + else { + + //SendUartString("I cache is already disabled.\n\r"); + } +} + +/** + * \brief Check MMU + * \return 0 if MMU disable, 1 if MMU enable + */ +unsigned int CP15_IsMMUEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & (1 << CP15_M_BIT)) != 0); +} + + +/** + * \brief Enable MMU + */ +void CP15_EnableMMU(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if MMU is disabled + if ((control & (1 << CP15_M_BIT)) == 0) { + + control |= (1 << CP15_M_BIT); + CP15_WriteControl(control); + //SendUartString("MMU enabled.\n\r"); + } + else { + + //SendUartString("MMU is already enabled.\n\r"); + } +} + + +/** + * \brief Disable MMU + */ +void CP15_DisableMMU(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if MMU is enabled + if ((control & (1 << CP15_M_BIT)) != 0) { + + control &= ~(1ul << CP15_M_BIT); + control &= ~(1ul << CP15_C_BIT); + CP15_WriteControl(control); + //SendUartString("MMU disabled.\n\r"); + } + else { + + //SendUartString("MMU is already disabled.\n\r"); + } +} + + +/** + * \brief Check D_cache + * \return 0 if D_cache disable, 1 if D_cache enable (with MMU of course) + */ +unsigned int CP15_IsDcacheEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0); +} + +/** + * \brief Enable Data cache + */ +void CP15_EnableDcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + if( !CP15_IsMMUEnabled() ) { + //SendUartString("Do nothing: MMU not enabled\r\n"); + } + else { + // Check if cache is disabled + if ((control & (1 << CP15_C_BIT)) == 0) { + + control |= (1 << CP15_C_BIT); + CP15_WriteControl(control); + //SendUartString("D cache enabled.\r\n"); + } + else { + + //SendUartString("D cache is already enabled.\r\n"); + } + } +} + +/** + * \brief Disable Data cache + */ +void CP15_DisableDcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is enabled + if ((control & (1 << CP15_C_BIT)) != 0) { + + control &= ~(1ul << CP15_C_BIT); + CP15_WriteControl(control); + //SendUartString("D cache disabled.\n\r"); + } + else { + + //SendUartString("D cache is already disabled.\n\r"); + } +} + +/** + * \brief Invalidate TLB + */ +void CP15_InvalidateTLB(void) +{ + asm("MCR p15, 0, %0, c8, c3, 0" : : "r"(1)); + asm("DSB"); +} + + +/** + * \brief Clean Data cache + */ +void CP15_CacheClean(uint8_t CacheType) +{ + //assert(!CacheType); + CP15_SelectDCache(); + + CP15_CleanDCacheBySetWay(); + asm("DSB"); + +} + +/** + * \brief Invalidate D/Icache + */ +void CP15_CacheInvalidate(uint8_t CacheType) +{ + if(CacheType) + { + CP15_SelectICache(); + CP15_InvalidateIcacheInnerSharable(); + asm("DSB"); + asm("ISB"); + } + else + { + CP15_SelectDCache(); + CP15_InvalidateDcacheBySetWay(); + asm("DSB"); + asm("ISB"); + } + + +} + +/** + * \brief Flush(Clean and invalidate) Data cache + */ +void CP15_CacheFlush(uint8_t CacheType) +{ + //assert(!CacheType); + + CP15_SelectDCache(); + CP15_CleanInvalidateDCacheBySetWay(); + + asm("DSB"); + +} + +/** + * \brief Invalidate Data cache by address + */ +void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add) +{ + + CP15_SelectDCache(); + CP15_InvalidateDcacheByMva(S_Add, E_Add); +} + +/** + * \brief Clean Data cache by address + */ +void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add) +{ + + CP15_SelectDCache(); + CP15_CleanDCacheByMva(S_Add, E_Add); +} + +/** + * \brief Flush Data cache by address + */ + +void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add) +{ + + CP15_SelectDCache(); + CP15_CleanInvalidateDcacheByMva(S_Add, E_Add); +} diff --git a/A58-STEPLDR/Src/cp15.h b/A58-STEPLDR/Src/cp15.h new file mode 100644 index 00000000..3141ad6f --- /dev/null +++ b/A58-STEPLDR/Src/cp15.h @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _CP15_H +#define _CP15_H + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define CP15_L4_BIT 15 // Determines if the T bit is set when load instructions + // change the PC: + // 0 = loads to PC set the T bit + // 1 = loads to PC do not set T bit + +#define CP15_RR_BIT 14 // RR bit Replacement strategy for Icache and Dcache: + // 0 = Random replacement + // 1 = Round-robin replacement. + +#define CP15_V_BIT 13 // V bit Location of exception vectors: + // 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C + // 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C + +#define CP15_I_BIT 12 // I bit Icache enable/disable: + // 0 = Icache disabled + // 1 = Icache enabled + +#define CP15_R_BIT 9 // R bit ROM protection + +#define CP15_S_BIT 8 // S bit System protection + +#define CP15_B_BIT 7 // B bit Endianness: + // 0 = Little-endian operation + // 1 = Big-endian operation. + +#define CP15_C_BIT 2 // C bit Dcache enable/disable: + // 0 = cache disabled + // 1 = cache enabled + +#define CP15_A_BIT 1 // A bit Alignment fault enable/disable: + // 0 = Data address alignment fault checking disabled + // 1 = Data address alignment fault checking enabled + +#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled. + // 0 = disabled + // 1 = enabled + +/** No access Any access generates a domain fault. */ +#define CP15_DOMAIN_NO_ACCESS 0x00 +/** Client Accesses are checked against the access permission bits in the section or page descriptor. */ +#define CP15_DOMAIN_CLIENT_ACCESS 0x01 +/** Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated. */ +#define CP15_DOMAIN_MANAGER_ACCESS 0x03 + + +#define CP15_ICache 1 +#define CP15_DCache 0 + +#define CP15_PMCNTENSET_ENABLE 31 +#define CP15_PMCR_DIVIDER 3 +#define CP15_PMCR_RESET 2 +#define CP15_PMCR_ENABLE 0 + + +/*------------------------------------------------------------------------------ */ +/* Exported functions */ +/*------------------------------------------------------------------------------ */ +extern unsigned int CP15_ReadID(void); +extern unsigned int CP15_ReadControl(void); +extern void CP15_ExclusiveCache(void); +extern void CP15_NonExclusiveCache(void); +extern void CP15_ISB(void); +extern void CP15_DSB(void); +extern void CP15_DMB(void); +extern void CP15_SelectDCache(void); +extern void CP15_SelectICache(void); +extern void CP15_WriteControl(unsigned int value); +extern void CP15_WriteTTB(unsigned int value); +extern void CP15_WriteDomainAccessControl(unsigned int value); + +extern void CP15_InvalidateIcacheInnerSharable(void); +extern void CP15_InvalidateBTBinnerSharable(void); +extern void CP15_InvalidateIcache(void); +extern void CP15_InvalidateIcacheByMva(void); +extern void CP15_InvalidateBTB(void); +extern void CP15_InvalidateBTBbyMva(uint32_t VA_Addr); + +extern void CP15_InvalidateDcacheBySetWay(void); +extern void CP15_CleanDCacheBySetWay(void); +extern void CP15_CleanInvalidateDCacheBySetWay(void); + +extern void CP15_InvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr ); +extern void CP15_CleanDCacheByMva(uint32_t startAddr, uint32_t endAddr ); +extern void CP15_CleanInvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr ); + +extern void CP15_CleanDCacheUMva(void); +extern void CP15_InvalidateTranslationTable(void); + +extern void CP15_coherent_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_invalidate_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_clean_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_flush_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_flush_kern_dcache_for_dma (uint32_t startAddr, uint32_t size ); + + + +/*------------------------------------------------------------------------------ */ +/* Exported functions from CP15.c */ +/*------------------------------------------------------------------------------ */ + +/** MMU (Status/Enable/Disable) */ +extern unsigned int CP15_IsMMUEnabled(void); +extern void CP15_EnableMMU(void); +extern void CP15_DisableMMU(void); + +/** I cache (Status/Enable/Disable) */ +extern unsigned int CP15_IsIcacheEnabled(void); +extern void CP15_EnableIcache(void); +extern void CP15_DisableIcache(void); + +/** D cache (Status/Enable/Disable) */ +extern unsigned int CP15_IsDcacheEnabled(void); +extern void CP15_EnableDcache(void); +extern void CP15_DisableDcache(void); + + +extern void CP15_InvalidateTLB(void); + + +extern void CP15_CacheClean(uint8_t CacheType); +extern void CP15_CacheInvalidate(uint8_t CacheType); +extern void CP15_CacheFlush(uint8_t CacheType); +extern void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add); +extern void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add); +extern void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add); + +#endif // #ifndef _CP15_H + diff --git a/A58-STEPLDR/Src/cp15_asm_iar.s b/A58-STEPLDR/Src/cp15_asm_iar.s new file mode 100644 index 00000000..efcafc33 --- /dev/null +++ b/A58-STEPLDR/Src/cp15_asm_iar.s @@ -0,0 +1,728 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA, + * OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + + +/** + * \addtogroup cp15_cache Cache Operations + * + * \section Usage + * + * They are performed as MCR instructions and only operate on a level 1 cache associated with + * ATM v7 processor. + * The supported operations are: + *
        + *
      • Any of these operations can be applied to + * -# any data cache + * -# any unified cache. + *
      • Invalidate by MVA + * Performs an invalidate of a data or unified cache line based on the address it contains. + *
      • Invalidate by set/way + * Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
      • Clean by MVA + * Performs a clean of a data or unified cache line based on the address it contains. + *
      • Clean by set/way + * Performs a clean of a data or unified cache line based on its location in the cache hierarchy. + *
      • Clean and Invalidate by MVA + * Performs a clean and invalidate of a data or unified cache line based on the address it contains. + *
      • Clean and Invalidate by set/way + * Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
      + * + * Related files:\n + * \ref cp15.h\n + * \ref cp15_arm_iar.s \n + */ + + + MODULE ?cp15 + + //// Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(2) + SECTION CSTACK:DATA:NOROOT(3) + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#define __ASSEMBLY__ + + +/*---------------------------------------------------------------------------- + * Functions to access CP15 coprocessor register + *----------------------------------------------------------------------------*/ + PUBLIC CP15_ReadID + PUBLIC CP15_ExclusiveCache + PUBLIC CP15_NonExclusiveCache + PUBLIC CP15_ISB + PUBLIC CP15_DSB + PUBLIC CP15_DMB + PUBLIC CP15_SelectICache + PUBLIC CP15_SelectDCache + PUBLIC CP15_ReadControl + PUBLIC CP15_WriteControl + PUBLIC CP15_WriteDomainAccessControl + PUBLIC CP15_WriteTTB + PUBLIC CP15_InvalidateIcacheInnerSharable + PUBLIC CP15_InvalidateBTBinnerSharable + PUBLIC CP15_InvalidateIcache + PUBLIC CP15_InvalidateIcacheByMva + PUBLIC CP15_InvalidateBTB + PUBLIC CP15_InvalidateBTBbyMva + + PUBLIC CP15_InvalidateDcacheBySetWay + PUBLIC CP15_CleanDCacheBySetWay + PUBLIC CP15_CleanInvalidateDCacheBySetWay + + PUBLIC CP15_InvalidateDcacheByMva + PUBLIC CP15_CleanDCacheByMva + PUBLIC CP15_CleanDCacheUMva + PUBLIC CP15_CleanInvalidateDcacheByMva + PUBLIC CP15_InvalidateTranslationTable + + PUBLIC CP15_coherent_dcache_for_dma + PUBLIC CP15_invalidate_dcache_for_dma + PUBLIC CP15_clean_dcache_for_dma + PUBLIC CP15_flush_dcache_for_dma + PUBLIC CP15_flush_kern_dcache_for_dma + +/** + * \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers. + * Reading from this register returns the device ID, the cache type, or the TCM status + * depending on the value of Opcode_2 used. + */ + SECTION .CP15_ReadID:DATA:NOROOT(2) + PUBLIC CP15_ReadID +CP15_ReadID: + mov r0, #0 + mrc p15, 0, r0, c0, c0, 0 + bx lr + + +/** + * \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_ISB:DATA:NOROOT(2) + PUBLIC CP15_ISB +CP15_ISB: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 4 + nop + bx lr + +/** + * \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_DSB:DATA:NOROOT(2) + PUBLIC CP15_DSB +CP15_DSB: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + nop + bx lr + +/** + * \brief Register c7 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_DMB:DATA:NOROOT(2) + PUBLIC CP15_DMB +CP15_DMB: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 5 + nop + bx lr + +/** + * \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_ExclusiveCache:DATA:NOROOT(2) + PUBLIC CP15_ExclusiveCache +CP15_ExclusiveCache: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR + orr r0, r0, #0x00000080 + mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR + nop + bx lr + + +/** + * \brief Register c1 accesses the ACTLR Register, to indicate cpu that L2 is in exclusive mode + */ + SECTION .CP15_NonExclusiveCache:DATA:NOROOT(2) + PUBLIC CP15_NonExclusiveCache +CP15_NonExclusiveCache: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR + bic r0, r0, #0x00000080 + mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR + nop + bx lr + +/** + * \brief Register c1 accesses the CSSELR Register, to select ICache + */ + SECTION .CP15_SelectICache:DATA:NOROOT(2) + PUBLIC CP15_SelectICache +CP15_SelectICache: + mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR + orr r0, r0, #0x1 ; Change 0th bit to ICache + mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR + nop + bx lr + +/** + * \brief Register c1 accesses the CSSELR Register, to select DCache + */ + SECTION .CP15_SelectDCache:DATA:NOROOT(2) + PUBLIC CP15_SelectDCache +CP15_SelectDCache: + mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR + and r0, r0, #0xFFFFFFFE ; Change 0th bit to ICache + mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR + nop + bx lr + + + +/** + * \brief Register c1 is the Control Register for the ARM926EJ-S processor. + * This register specifies the configuration used to enable and disable the + * caches and MMU. It is recommended that you access this register using a + * read-modify-write sequence + */ + SECTION .CP15_ReadControl:CODE:NOROOT(2) + PUBLIC CP15_ReadControl +CP15_ReadControl: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 0 + bx lr + + SECTION .CP15_WriteControl:CODE:NOROOT(2) + PUBLIC CP15_WriteControl +CP15_WriteControl: + mcr p15, 0, r0, c1, c0, 0 + dsb + isb + bx lr + + SECTION .CP15_WriteDomainAccessControl:CODE:NOROOT(2) + PUBLIC CP15_WriteDomainAccessControl +CP15_WriteDomainAccessControl: + mcr p15, 0, r0, c3, c0, 0 + dsb + isb + bx lr + +/** + * \brief ARMv7A architecture supports two translation tables + * Configure translation table base (TTB) control register cp15,c2 + * to a value of all zeros, indicates we are using TTB register 0. + * write the address of our page table base to TTB register 0. + */ + SECTION .CP15_WriteTTB:CODE:NOROOT(2) + PUBLIC CP15_WriteTTB +CP15_WriteTTB: + mcr p15, 0, r0, c2, c0, 0 + dsb + isb + bx lr + +/** + * \brief Invalidate I cache predictor array inner Sharable + */ + SECTION .CP15_InvalidateIcacheInnerSharable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcacheInnerSharable +CP15_InvalidateIcacheInnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 0 + bx lr + +/** + * \brief Invalidate entire branch predictor array inner Sharable + */ + SECTION .CP15_InvalidateBTBinnerSharable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateBTBinnerSharable +CP15_InvalidateBTBinnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 + bx lr + +/** + * \brief Invalidate all instruction caches to PoU, also flushes branch target cache + */ + SECTION .CP15_InvalidateIcache:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcache +CP15_InvalidateIcache: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + isb + bx lr + +/** + * \brief Invalidate instruction caches by VA to PoU + */ + SECTION .CP15_InvalidateIcacheByMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcacheByMva +CP15_InvalidateIcacheByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 1 + bx lr + +/** + * \brief Invalidate entire branch predictor array + */ + SECTION .CP15_InvalidateBTB:CODE:NOROOT(2) + PUBLIC CP15_InvalidateBTB +CP15_InvalidateBTB: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 + dsb + isb + bx lr + +/** + * \brief Invalidate branch predictor array entry by MVA + */ + SECTION .CP15_InvalidateBTBbyMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateBTBbyMva +CP15_InvalidateBTBbyMva: + mcr p15, 0, r0, c7, c5, 7 + bx lr + +/*********************************************************** +* +* ===Data Cache related maintenance functions=== +* +**************************************************************/ + + +// ===Data Cache maintenance by SetWay === + +/** + * \brief Invalidate entire data cache by set/way + */ + SECTION .CP15_InvalidateDcacheBySetWay:CODE:NOROOT(2) + PUBLIC CP15_InvalidateDcacheBySetWay +CP15_InvalidateDcacheBySetWay: + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ inv_finish ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +inv_cache_level_loop + ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT inv_skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +inv_set_loop + MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +inv_way_loop + ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 ; Invalidate by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE inv_way_loop + SUBS r7, r7, #1 ; Decrement the Set number + BGE inv_set_loop +inv_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT inv_cache_level_loop +inv_finish + NOP + BX lr + +/** + * \brief Clean entire data cache by set/way + */ + SECTION .CP15_CleanDCacheBySetWay:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheBySetWay +CP15_CleanDCacheBySetWay: + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ clean_finish ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +clean_cache_level_loop + ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT clean_skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_set_loop + MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +clean_way_loop + ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c10, 2 ; Clean by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE clean_way_loop + SUBS r7, r7, #1 ; Decrement the Set number + BGE clean_set_loop +clean_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_cache_level_loop +clean_finish + NOP + BX lr + +/** + * \brief Clean and Invalidate entire data cache by set/way + */ + SECTION .CP15_CleanInvalidateDCacheBySetWay:CODE:NOROOT(2) + PUBLIC CP15_CleanInvalidateDCacheBySetWay +CP15_CleanInvalidateDCacheBySetWay: + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x07000000 ; Extract coherency level + MOV r3, r3, LSR #23 ; Total cache levels << 1 + BEQ clinv_finish ; If 0, no need to clean + + MOV r10, #0 ; R10 holds current cache level << 1 +clinv_cache_level_loop + ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position + MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 ; Isolate those lower 3 bits + CMP r1, #2 + BLT clean_skip ; No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register + AND r2, r1, #7 ; Extract the line length field + ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clinv_set_loop + MOV r9, r4 ; R9 working copy of the max way size (right aligned) + +clinv_way_loop + ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; Factor in the Set number + MCR p15, 0, r11, c7, c14, 2 ; Clean and Invalidate by Set/Way + SUBS r9, r9, #1 ; Decrement the Way number + BGE clean_way_loop + SUBS r7, r7, #1 ; Decrement the Set number + BGE clean_set_loop +clinv_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_cache_level_loop +clinv_finish + NOP + BX lr + + + +// ===Data Cache maintenance by VA === + + +/** + * \brief Invalidate data cache by VA to Poc + */ + SECTION .CP15_InvalidateDcacheByMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateDcacheByMva +CP15_InvalidateDcacheByMva: + mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes + mov r3, r0 +inv_loop + mcr p15, 0, r0, c7, c6, 1 + add r3, r3, r2 + cmp r3, r1 + bls inv_loop + bx lr + + +/** + * \brief Clean data cache by MVA + */ + SECTION .CP15_CleanDCacheByMva:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheByMva +CP15_CleanDCacheByMva: + mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes + mov r3, r0 +clean_loop + mcr p15, 0, r0, c7, c10, 1 + add r3, r3, r2 + cmp r3, r1 + bls clean_loop + bx lr + +/** + * \brief Clean unified cache by MVA + */ + SECTION .CP15_CleanDCacheUMva:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheUMva +CP15_CleanDCacheUMva: + mov r0, #0 + mcr p15, 0, r0, c7, c11, 1 + bx lr + +/** + * \brief Clean and invalidate data cache by VA to PoC + */ + SECTION .CP15_CleanInvalidateDcacheByMva:CODE:NOROOT(2) + PUBLIC CP15_CleanInvalidateDcacheByMva +CP15_CleanInvalidateDcacheByMva: + mov r2, #0x20 ;Eight words per line, Cortex-A5 L1 Line Size 32 Bytes + mov r3, r0 +clinv_loop + mcr p15, 0, r0, c7, c14, 1 + add r3, r3, r2 + cmp r3, r1 + bls clinv_loop + bx lr + + +/** + * \brief Invalidate translation table + */ + SECTION .CP15_InvalidateTranslationTable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateTranslationTable +CP15_InvalidateTranslationTable: + mov r0, #0 + mcr p15, 0, r0, c8, c3, 0 + dsb + isb + mcr p15, 0, r0, c8, c7, 0 + dsb + isb + bx lr + +/** + * \brief flush translation table + */ + SECTION .CP15_FlushTranslationTable:CODE:NOROOT(2) + PUBLIC CP15_FlushTranslationTable +CP15_FlushTranslationTable: + mov r0, #0 + mcr p15, 0, r0, c8, c3, 0 + dsb + isb + bx lr + + +/** + * \brief Ensure that the I and D caches are coherent within specified + * region. This is typically used when code has been written to + * a memory region, and will be executed. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_coherent_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_coherent_dcache_for_dma +CP15_coherent_dcache_for_dma: +// dcache_line_size r2, r3 + + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r12, r0, r3 +loop1: + mcr p15, 0, r12, c7, c11, 1 // clean D line to the point of unification + add r12, r12, r2 + cmp r12, r1 + blo loop1 + dsb + +// .macro icache_line_size, reg, tmp + mrc p15, 0, r3, c0, c0, 1 // read ctr + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r12, r0, r3 +loop2: + mcr p15, 0, r12, c7, c5, 1 // invalidate I line + add r12, r12, r2 + cmp r12, r1 + blo loop2 + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 //invalidate BTB Inner Shareable + mcr p15, 0, r0, c7, c5, 6 // invalidate BTB + dsb + isb + bx lr + + +/** + * \brief Invalidate the data cache within the specified region; we will + * be performing a DMA operation in this region and we want to + * purge old data in the cache. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_invalidate_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_invalidate_dcache_for_dma +CP15_invalidate_dcache_for_dma: + +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + tst r0, r3 + bic r0, r0, r3 + + mcrne p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line + + tst r1, r3 + bic r1, r1, r3 + mcrne p15, 0, r1, c7, c14, 1 // clean & invalidate D / U line +loop3: + mcr p15, 0, r0, c7, c6, 1 // invalidate D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop3 + dsb + bx lr + + +/** + * \brief Clean the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_clean_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_clean_dcache_for_dma +CP15_clean_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r0, r0, r3 +loop4: + mcr p15, 0, r0, c7, c10, 1 // clean D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop4 + dsb + bx lr + + +/** + * \brief Flush the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_flush_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_flush_dcache_for_dma +CP15_flush_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + sub r3, r2, #1 + bic r0, r0, r3 +loop5: + mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop5 + dsb + bx lr + + +/** + * \brief CP15_flush_kern_dcache_for_dma + * Ensure that the data held in the page kaddr is written back to the page in question. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_flush_kern_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_flush_kern_dcache_for_dma +CP15_flush_kern_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 + + mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D line / unified line + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb + bx lr + END + diff --git a/A58-STEPLDR/Src/crc32.c b/A58-STEPLDR/Src/crc32.c new file mode 100644 index 00000000..74e68f3d --- /dev/null +++ b/A58-STEPLDR/Src/crc32.c @@ -0,0 +1,51 @@ +#include +#include + +#define CRC32_POLY 0x04C11DB7L + +unsigned int get_sum_poly(unsigned char top_byte) +{ + /// sum all the polys at various offsets + unsigned int sum_poly = top_byte << 24; + int i; + + for (i = 0; i < 8; ++i) { + /// check the top bit + if( ( sum_poly >> 31 ) != 0 ) + /// TODO : understand why '<<' first + sum_poly = ( sum_poly << 1 ) ^ CRC32_POLY; + else + sum_poly <<= 1; + } + + return sum_poly; +} + +void create_table(unsigned int *table) +{ + for( int i = 0; i < 256; ++ i ) + { + table[i] = get_sum_poly( (unsigned char) i ); + } +} + +static const unsigned int *crc32_table = NULL; + +unsigned int +xcrc32(const unsigned char *buf, int len, unsigned int init) +{ + unsigned int crc = init; + static unsigned int table[256]; + + if (!crc32_table) { + create_table(table); + crc32_table = &table[0]; + } + + while (len--) + { + crc = (crc << 8) ^ crc32_table[((crc >> 24) ^ *buf) & 255]; + buf++; + } + return crc; +} diff --git a/A58-STEPLDR/Src/crc32.h b/A58-STEPLDR/Src/crc32.h new file mode 100644 index 00000000..2312956a --- /dev/null +++ b/A58-STEPLDR/Src/crc32.h @@ -0,0 +1,7 @@ +#ifndef _CRC32_H +#define _CRC32_H + +unsigned int +xcrc32(const unsigned char *buf, int len, unsigned int init); + +#endif \ No newline at end of file diff --git a/A58-STEPLDR/Src/exception.c b/A58-STEPLDR/Src/exception.c new file mode 100644 index 00000000..b6293bb6 --- /dev/null +++ b/A58-STEPLDR/Src/exception.c @@ -0,0 +1,38 @@ +#include "uart.h" + +void undef_handler() +{ + SendUartString("\r\nUndef EXC"); + while(1); +} + +void prefetch_handler() +{ + SendUartString("\r\nPrefetch EXC"); + while(1); +} + +void data_abort_handler() +{ + SendUartString("\r\nData abort EXC"); + while(1); +} + +void irq_handler() +{ + SendUartString("\r\nIRQ EXC"); + while(1); +} + +void fiq_handler() +{ + SendUartString("\r\nFIQ EXC"); + while(1); +} + +void swi_handler() +{ + SendUartString("\r\nSWI EXC"); + while(1); +} + diff --git a/A58-STEPLDR/Src/fs/diskio.c b/A58-STEPLDR/Src/fs/diskio.c new file mode 100644 index 00000000..2b5ed3eb --- /dev/null +++ b/A58-STEPLDR/Src/fs/diskio.c @@ -0,0 +1,238 @@ +/*-----------------------------------------------------------------------*/ +/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */ +/*-----------------------------------------------------------------------*/ +/* This is a stub disk I/O module that acts as front end of the existing */ +/* disk I/O modules and attach it to FatFs module with common interface. */ +/*-----------------------------------------------------------------------*/ + +#include "diskio.h" + +//#include + +//#include "sdfmd.h" +//#include +//#include + +//extern DWORD SDInitialize(void); +//extern DWORD WriteSector(PBYTE pData, DWORD dwStartSector, DWORD dwNumber); +//extern DWORD ReadSector(PBYTE pData, DWORD dwStartSector, DWORD dwNumber); +//extern void Delay(UINT32 count); + +/*-----------------------------------------------------------------------*/ +/* Correspondence between physical drive number and physical drive. */ +/* Note that Tiny-FatFs supports only single drive and always */ +/* accesses drive number 0. */ + +/*-----------------------------------------------------------------------*/ +/* Inidialize a Drive */ +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + DSTATUS stat; + int result; + + switch (drv) { + /*case ATA : + result = ATA_disk_initialize(); + // translate the reslut code here + + return stat;*/ + + case SDMMC : + result = MMC_disk_initialize(); + // translate the reslut code here + if(result < 0) + stat = STA_NOINIT; + else + stat = 0; + return stat; + + case USB : + result = USB_disk_initialize(); + // translate the reslut code here + if(result < 0) + stat = STA_NOINIT; + else + stat = 0; + + return stat; + + } + return STA_NOINIT; + +} + + + +/*-----------------------------------------------------------------------*/ +/* Return Disk Status */ + +DSTATUS disk_status ( + BYTE drv /* Physical drive nmuber (0..) */ +) +{ + //drv = drv; + return 0; +#if 0 + + DSTATUS stat; + int result; + + + switch (drv) { + case ATA : + result = ATA_disk_status(); + // translate the reslut code here + + return stat; + + case SDMMC : + result = MMC_disk_status(); + // translate the reslut code here + + return stat; +#if 0 + case USB : + result = USB_disk_status(); + // translate the reslut code here + + return stat; +#endif + } + return STA_NOINIT; +#endif +} + + + +/*-----------------------------------------------------------------------*/ +/* Read Sector(s) */ + +DRESULT disk_read ( + BYTE drv, /* Physical drive nmuber (0..) */ + BYTE *buff, /* Data buffer to store read data */ + DWORD sector, /* Sector address (LBA) */ + BYTE count /* Number of sectors to read (1..255) */ +) +{ + DRESULT res; + int result; + + switch (drv) { + /*case ATA : + result = ATA_disk_read(buff, sector, count); + // translate the reslut code here + + return res;*/ + + case SDMMC : + result = MMC_disk_read(buff, sector, count); + // translate the reslut code here + if(result == 0) + res = RES_ERROR; + else + res = RES_OK; + return res; + + case USB : + result = USB_disk_read(buff, sector, count); + // translate the reslut code here + if(result == 0) + res = RES_ERROR; + else + res = RES_OK; + return res; + } + + return RES_PARERR; +} + + + +/*-----------------------------------------------------------------------*/ +/* Write Sector(s) */ + +#if _READONLY == 0 +DRESULT disk_write ( + BYTE drv, /* Physical drive nmuber (0..) */ + const BYTE *buff, /* Data to be written */ + DWORD sector, /* Sector address (LBA) */ + BYTE count /* Number of sectors to write (1..255) */ +) +{ + DRESULT res; + int result; + + switch (drv) { + case ATA : + result = ATA_disk_write(buff, sector, count); + // translate the reslut code here + + return res; + + case SDMMC : + result = MMC_disk_write(buff, sector, count); + // translate the reslut code here + + return res; +#if 0 + case USB : + result = USB_disk_write(buff, sector, count); + // translate the reslut code here + + return res; +#endif + } + return RES_PARERR; +} +#endif /* _READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous Functions */ + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0..) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + DRESULT res; + int result; + + switch (drv) { + /*case ATA : + // pre-process here + + result = ATA_disk_ioctl(ctrl, buff); + // post-process here + + return res;*/ + + case SDMMC : + // pre-process here + + result = MMC_disk_ioctl(ctrl, buff); + // post-process here + if(result < 0) + res = RES_PARERR; + else + res = RES_OK; + return res; + + case USB : + // pre-process here + + result = USB_disk_ioctl(ctrl, buff); + if(result < 0) + res = RES_PARERR; + else + res = RES_OK; + + return res; + } + return RES_PARERR; +} + diff --git a/A58-STEPLDR/Src/fs/diskio.h b/A58-STEPLDR/Src/fs/diskio.h new file mode 100644 index 00000000..3b839b4e --- /dev/null +++ b/A58-STEPLDR/Src/fs/diskio.h @@ -0,0 +1,86 @@ +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file R0.06 (C)ChaN, 2007 +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO +#define _DISKIO + +#define _READONLY 1 /* 1: Read-only mode */ +#define _USE_IOCTL 1 + +#include "integer.h" + + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + +DSTATUS disk_initialize (BYTE); +DSTATUS disk_status (BYTE); +DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); +#if _READONLY == 0 +DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); +#endif +DRESULT disk_ioctl (BYTE, BYTE, void*); +void disk_timerproc (void); + + + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl() */ + +/* Generic command */ +#define CTRL_SYNC 0 /* Mandatory for read/write configuration */ +#define GET_SECTOR_COUNT 1 /* Mandatory for only f_mkfs() */ +#define GET_SECTOR_SIZE 2 +#define GET_BLOCK_SIZE 3 /* Mandatory for only f_mkfs() */ +#define CTRL_POWER 4 +#define CTRL_LOCK 5 +#define CTRL_EJECT 6 +/* MMC/SDC command */ +#define MMC_GET_TYPE 10 +#define MMC_GET_CSD 11 +#define MMC_GET_CID 12 +#define MMC_GET_OCR 13 +#define MMC_GET_SDSTAT 14 +/* ATA/CF command */ +#define ATA_GET_REV 20 +#define ATA_GET_MODEL 21 +#define ATA_GET_SN 22 + +#define SDMMC 0 +#define USB 1 +#define ATA 2 + +int MMC_disk_initialize(void); + +int MMC_disk_read(void *buff, DWORD sector, BYTE count); + +int MMC_disk_ioctl(BYTE ctrl, void *buff); + +int USB_disk_initialize(void); + +int USB_disk_read(void *buff, DWORD sector, BYTE count); + +int USB_disk_ioctl(BYTE ctrl, void *buff); + +#endif diff --git a/A58-STEPLDR/Src/fs/ff.c b/A58-STEPLDR/Src/fs/ff.c new file mode 100644 index 00000000..fbe8008b --- /dev/null +++ b/A58-STEPLDR/Src/fs/ff.c @@ -0,0 +1,2057 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.06 (C)ChaN, 2008 +/-----------------------------------------------------------------------------/ +/ The FatFs module is an experimenal project to implement FAT file system to +/ cheap microcontrollers. This is a free software and is opened for education, +/ research and development under license policy of following trems. +/ +/ Copyright (C) 2008, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is no warranty. +/ * You can use, modify and/or redistribute it for personal, non-profit or +/ commercial use without restriction under your responsibility. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) patition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algolithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a plysical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close +/ without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same +/ or following cluster. +/---------------------------------------------------------------------------*/ + +#include +#include "ff.h" /* FatFs declarations */ +#include "diskio.h" /* Include file for user provided disk functions */ + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ +DWORD get_fattime(void) +{ + return 0x12345678; +} + +static +FATFS *FatFs[_DRIVES]; /* Pointer to the file system objects (logical drives) */ +static +WORD fsid; /* File system mount ID */ + +FATFS g_fs; + +/*-----------------------------------------------------------------------*/ +/* Change window offset */ +/*-----------------------------------------------------------------------*/ + +static +BOOL move_window ( /* TRUE: successful, FALSE: failed */ + FATFS *fs, /* File system object */ + DWORD sector /* Sector number to make apperance in the fs->win[] */ +) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + + wsect = fs->winsect; + if (wsect != sector) { /* Changed current window */ +#if !_FS_READONLY + BYTE n; + if (fs->winflag) { /* Write back dirty window if needed */ + if (disk_write(fs->drive, fs->win, wsect, 1) != RES_OK) + return FALSE; + fs->winflag = 0; + if (wsect < (fs->fatbase + fs->sects_fat)) { /* In FAT area */ + for (n = fs->n_fats; n >= 2; n--) { /* Refrect the change to FAT copy */ + wsect += fs->sects_fat; + disk_write(fs->drive, fs->win, wsect, 1); + } + } + } +#endif + if (sector) { + if (disk_read(fs->drive, fs->win, sector, 1) != RES_OK) + return FALSE; + fs->winsect = sector; + } + } + return TRUE; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Clean-up cached data */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +FRESULT sync ( /* FR_OK: successful, FR_RW_ERROR: failed */ + FATFS *fs /* File system object */ +) +{ + fs->winflag = 1; + if (!move_window(fs, 0)) return FR_RW_ERROR; +#if _USE_FSINFO + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { + fs->winsect = 0; + memset(fs->win, 0, 512); + ST_WORD(&fs->win[BS_55AA], 0xAA55); + ST_DWORD(&fs->win[FSI_LeadSig], 0x41615252); + ST_DWORD(&fs->win[FSI_StrucSig], 0x61417272); + ST_DWORD(&fs->win[FSI_Free_Count], fs->free_clust); + ST_DWORD(&fs->win[FSI_Nxt_Free], fs->last_clust); + disk_write(fs->drive, fs->win, fs->fsi_sector, 1); + fs->fsi_flag = 0; + } +#endif + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drive, CTRL_SYNC, NULL) != RES_OK) + return FR_RW_ERROR; + return FR_OK; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Get a cluster status */ +/*-----------------------------------------------------------------------*/ + +static +DWORD get_cluster ( /* 0,>=2: successful, 1: failed */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to get the link information */ +) +{ + WORD wc, bc; + DWORD fatsect; + + + if (clust >= 2 && clust < fs->max_clust) { /* Is it a valid cluster#? */ + fatsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = (WORD)clust * 3 / 2; + if (!move_window(fs, fatsect + (bc / SS(fs)))) break; + wc = fs->win[bc & (SS(fs) - 1)]; bc++; + if (!move_window(fs, fatsect + (bc / SS(fs)))) break; + wc |= (WORD)fs->win[bc & (SS(fs) - 1)] << 8; + return (clust & 1) ? (wc >> 4) : (wc & 0xFFF); + + case FS_FAT16 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 2)))) break; + return LD_WORD(&fs->win[((WORD)clust * 2) & (SS(fs) - 1)]); + + case FS_FAT32 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 4)))) break; + return LD_DWORD(&fs->win[((WORD)clust * 4) & (SS(fs) - 1)]) & 0x0FFFFFFF; + } + } + + return 1; /* Out of cluster range, or an error occured */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change a cluster status */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +BOOL put_cluster ( /* TRUE: successful, FALSE: failed */ + FATFS *fs, /* File system object */ + DWORD clust, /* Cluster# to change (must be 2 to fs->max_clust-1) */ + DWORD val /* New value to mark the cluster */ +) +{ + WORD bc; + BYTE *p; + DWORD fatsect; + + + fatsect = fs->fatbase; + switch (fs->fs_type) { + case FS_FAT12 : + bc = (WORD)clust * 3 / 2; + if (!move_window(fs, fatsect + (bc / SS(fs)))) return FALSE; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clust & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->winflag = 1; + if (!move_window(fs, fatsect + (bc / SS(fs)))) return FALSE; + p = &fs->win[bc & (SS(fs) - 1)]; + *p = (clust & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 2)))) return FALSE; + ST_WORD(&fs->win[((WORD)clust * 2) & (SS(fs) - 1)], (WORD)val); + break; + + case FS_FAT32 : + if (!move_window(fs, fatsect + (clust / (SS(fs) / 4)))) return FALSE; + ST_DWORD(&fs->win[((WORD)clust * 4) & (SS(fs) - 1)], val); + break; + + default : + return FALSE; + } + fs->winflag = 1; + return TRUE; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +BOOL remove_chain ( /* TRUE: successful, FALSE: failed */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to remove chain from */ +) +{ + DWORD nxt; + + + while (clust >= 2 && clust < fs->max_clust) { + nxt = get_cluster(fs, clust); + if (nxt == 1) return FALSE; + if (!put_cluster(fs, clust, 0)) return FALSE; + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust++; +#if _USE_FSINFO + fs->fsi_flag = 1; +#endif + } + clust = nxt; + } + return TRUE; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Stretch or create a cluster chain */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +DWORD create_chain ( /* 0: No free cluster, 1: Error, >=2: New cluster number */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to stretch, 0 means create new */ +) +{ + DWORD cstat, ncl, scl, mcl = fs->max_clust; + + + if (clust == 0) { /* Create new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (scl == 0 || scl >= mcl) scl = 1; + } + else { /* Stretch existing chain */ + cstat = get_cluster(fs, clust); /* Check the cluster status */ + if (cstat < 2) return 1; /* It is an invalid cluster */ + if (cstat < mcl) return cstat; /* It is already followed by next cluster */ + scl = clust; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= mcl) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free custer */ + } + cstat = get_cluster(fs, ncl); /* Get the cluster status */ + if (cstat == 0) break; /* Found a free cluster */ + if (cstat == 1) return 1; /* Any error occured */ + if (ncl == scl) return 0; /* No free custer */ + } + + if (!put_cluster(fs, ncl, 0x0FFFFFFF)) return 1; /* Mark the new cluster "in use" */ + if (clust != 0 && !put_cluster(fs, clust, ncl)) return 1; /* Link it to previous one if needed */ + + fs->last_clust = ncl; /* Update fsinfo */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; +#if _USE_FSINFO + fs->fsi_flag = 1; +#endif + } + + return ncl; /* Return new cluster number */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + +static +DWORD clust2sect ( /* !=0: sector number, 0: failed - invalid cluster# */ + FATFS *fs, /* File system object */ + DWORD clust /* Cluster# to be converted */ +) +{ + clust -= 2; + if (clust >= (fs->max_clust - 2)) return 0; /* Invalid cluster# */ + return clust * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Move directory pointer to next */ +/*-----------------------------------------------------------------------*/ + +static +BOOL next_dir_entry ( /* TRUE: successful, FALSE: could not move next */ + DIR *dj /* Pointer to directory object */ +) +{ + DWORD clust; + WORD idx; + + + idx = dj->index + 1; + if ((idx & ((SS(dj->fs) - 1) / 32)) == 0) { /* Table sector changed? */ + dj->sect++; /* Next sector */ + if (dj->clust == 0) { /* In static table */ + if (idx >= dj->fs->n_rootdir) return FALSE; /* Reached to end of table */ + } else { /* In dynamic table */ + if (((idx / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ + clust = get_cluster(dj->fs, dj->clust); /* Get next cluster */ + if (clust < 2 || clust >= dj->fs->max_clust) /* Reached to end of table */ + return FALSE; + dj->clust = clust; /* Initialize for new cluster */ + dj->sect = clust2sect(dj->fs, clust); + } + } + } + dj->index = idx; /* Lower several bits of dj->index indicates offset in dj->sect */ + return TRUE; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file status from directory entry */ +/*-----------------------------------------------------------------------*/ + +#if _FS_MINIMIZE <= 1 +static +void get_fileinfo ( /* No return code */ + FILINFO *finfo, /* Ptr to store the file information */ + const BYTE *dir /* Ptr to the directory entry */ +) +{ + BYTE n, c, a; + char *p; + + + p = &finfo->fname[0]; + a = _USE_NTFLAG ? dir[DIR_NTres] : 0; /* NT flag */ + for (n = 0; n < 8; n++) { /* Convert file name (body) */ + c = dir[n]; + if (c == ' ') break; + if (c == 0x05) c = 0xE5; + if (a & 0x08 && c >= 'A' && c <= 'Z') c += 0x20; + *p++ = c; + } + if (dir[8] != ' ') { /* Convert file name (extension) */ + *p++ = '.'; + for (n = 8; n < 11; n++) { + c = dir[n]; + if (c == ' ') break; + if (a & 0x10 && c >= 'A' && c <= 'Z') c += 0x20; + *p++ = c; + } + } + *p = '\0'; + + finfo->fattrib = dir[DIR_Attr]; /* Attribute */ + finfo->fsize = LD_DWORD(&dir[DIR_FileSize]); /* Size */ + finfo->fdate = LD_WORD(&dir[DIR_WrtDate]); /* Date */ + finfo->ftime = LD_WORD(&dir[DIR_WrtTime]); /* Time */ +} +#endif /* _FS_MINIMIZE <= 1 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a paragraph and create the name in format of directory entry */ +/*-----------------------------------------------------------------------*/ + +static +char make_dirfile ( /* 1: error - detected an invalid format, '\0'or'/': next character */ + const char **path, /* Pointer to the file path pointer */ + char *dirname /* Pointer to directory name buffer {Name(8), Ext(3), NT flag(1)} */ +) +{ + BYTE n, t, c, a, b; + + + memset(dirname, ' ', 8+3); /* Fill buffer with spaces */ + a = 0; b = 0x18; /* NT flag */ + n = 0; t = 8; + for (;;) { + c = *(*path)++; + if (c == '\0' || c == '/') { /* Reached to end of str or directory separator */ + if (n == 0) break; + dirname[11] = _USE_NTFLAG ? (a & b) : 0; + return c; + } + if (c <= ' ' || c == 0x7F) break; /* Reject invisible chars */ + if (c == '.') { + if (!(a & 1) && n >= 1 && n <= 8) { /* Enter extension part */ + n = 8; t = 11; continue; + } + break; + } + if (_USE_SJIS && + ((c >= 0x81 && c <= 0x9F) || /* Accept S-JIS code */ + (c >= 0xE0 && c <= 0xFC))) { + if (n == 0 && c == 0xE5) /* Change heading \xE5 to \x05 */ + c = 0x05; + a ^= 0x01; goto md_l2; + } + if (c == '"') break; /* Reject " */ + if (c <= ')') goto md_l1; /* Accept ! # $ % & ' ( ) */ + if (c <= ',') break; /* Reject * + , */ + if (c <= '9') goto md_l1; /* Accept - 0-9 */ + if (c <= '?') break; /* Reject : ; < = > ? */ + if (!(a & 1)) { /* These checks are not applied to S-JIS 2nd byte */ + if (c == '|') break; /* Reject | */ + if (c >= '[' && c <= ']') break;/* Reject [ \ ] */ + if (_USE_NTFLAG && c >= 'A' && c <= 'Z') + (t == 8) ? (b &= 0xF7) : (b &= 0xEF); + if (c >= 'a' && c <= 'z') { /* Convert to upper case */ + c -= 0x20; + if (_USE_NTFLAG) (t == 8) ? (a |= 0x08) : (a |= 0x10); + } + } + md_l1: + a &= 0xFE; + md_l2: + if (n >= t) break; + dirname[n++] = c; + } + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Trace a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT trace_path ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Pointer to directory object to return last directory */ + char *fn, /* Pointer to last segment name to return {file(8),ext(3),attr(1)} */ + const char *path, /* Full-path string to trace a file or directory */ + BYTE **dir /* Pointer to pointer to found entry to retutn */ +) +{ + DWORD clust; + char ds; + BYTE *dptr = NULL; + FATFS *fs = dj->fs; + + + /* Initialize directory object */ + clust = fs->dirbase; + if (fs->fs_type == FS_FAT32) { + dj->clust = dj->sclust = clust; + dj->sect = clust2sect(fs, clust); + } else { + dj->clust = dj->sclust = 0; + dj->sect = clust; + } + dj->index = 0; + + if (*path == '\0') { /* Null path means the root directory */ + *dir = NULL; return FR_OK; + } + + for (;;) { + ds = make_dirfile(&path, fn); /* Get a paragraph into fn[] */ + if (ds == 1) return FR_INVALID_NAME; + for (;;) { + if (!move_window(fs, dj->sect)) return FR_RW_ERROR; + dptr = &fs->win[(dj->index & ((SS(fs) - 1) / 32)) * 32]; /* Pointer to the directory entry */ + if (dptr[DIR_Name] == 0) /* Has it reached to end of dir? */ + return !ds ? FR_NO_FILE : FR_NO_PATH; + if (dptr[DIR_Name] != 0xE5 /* Matched? */ + && !(dptr[DIR_Attr] & AM_VOL) + && !memcmp(&dptr[DIR_Name], fn, 8+3) ) break; + if (!next_dir_entry(dj)) /* Next directory pointer */ + return !ds ? FR_NO_FILE : FR_NO_PATH; + } + if (!ds) { *dir = dptr; return FR_OK; } /* Matched with end of path */ + if (!(dptr[DIR_Attr] & AM_DIR)) return FR_NO_PATH; /* Cannot trace because it is a file */ + clust = ((DWORD)LD_WORD(&dptr[DIR_FstClusHI]) << 16) | LD_WORD(&dptr[DIR_FstClusLO]); /* Get cluster# of the directory */ + dj->clust = dj->sclust = clust; /* Restart scanning at the new directory */ + dj->sect = clust2sect(fs, clust); + dj->index = 2; + } +} + + + + +/*-----------------------------------------------------------------------*/ +/* Reserve a directory entry */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +FRESULT reserve_direntry ( /* FR_OK: successful, FR_DENIED: no free entry, FR_RW_ERROR: a disk error occured */ + DIR *dj, /* Target directory to create new entry */ + BYTE **dir /* Pointer to pointer to created entry to retutn */ +) +{ + DWORD clust, sector; + BYTE c, n, *dptr; + FATFS *fs = dj->fs; + + + /* Re-initialize directory object */ + clust = dj->sclust; + if (clust != 0) { /* Dyanmic directory table */ + dj->clust = clust; + dj->sect = clust2sect(fs, clust); + } else { /* Static directory table */ + dj->sect = fs->dirbase; + } + dj->index = 0; + + do { + if (!move_window(fs, dj->sect)) return FR_RW_ERROR; + dptr = &fs->win[(dj->index & ((SS(dj->fs) - 1) / 32)) * 32]; /* Pointer to the directory entry */ + c = dptr[DIR_Name]; + if (c == 0 || c == 0xE5) { /* Found an empty entry */ + *dir = dptr; return FR_OK; + } + } while (next_dir_entry(dj)); /* Next directory pointer */ + /* Reached to end of the directory table */ + + /* Abort when it is a static table or could not stretch dynamic table */ + if (clust == 0 || !(clust = create_chain(fs, dj->clust))) return FR_DENIED; + if (clust == 1 || !move_window(fs, 0)) return FR_RW_ERROR; + + /* Cleanup the expanded table */ + fs->winsect = sector = clust2sect(fs, clust); + memset(fs->win, 0, SS(fs)); + for (n = fs->csize; n; n--) { + if (disk_write(fs->drive, fs->win, sector, 1) != RES_OK) + return FR_RW_ERROR; + sector++; + } + fs->winflag = 1; + *dir = fs->win; + + return FR_OK; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Load boot record and check if it is an FAT boot record */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record or error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + if (disk_read(fs->drive, fs->win, sect, 1) != RES_OK) /* Load boot record */ + return 2; + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if (!memcmp(&fs->win[BS_FilSysType], "FAT", 3)) /* Check FAT signature */ + return 0; + if (!memcmp(&fs->win[BS_FilSysType32], "FAT32", 5) && !(fs->win[BPB_ExtFlags] & 0x80)) + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Make sure that the file system is valid */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT auto_mount ( /* FR_OK(0): successful, !=0: any error occured */ + const char **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ +) +{ + BYTE drv, fmt, *tbl; + DSTATUS stat; + DWORD bootsect, fatsize, totalsect, maxclust; + const char *p = *path; + FATFS *fs; + + + /* Get drive number from the path name */ + while (*p == ' ') p++; /* Strip leading spaces */ + drv = p[0] - '0'; /* Is there a drive number? */ + if (drv <= 9 && p[1] == ':') + p += 2; /* Found a drive number, get and strip it */ + else + drv = 0; /* No drive number is given, use drive number 0 as default */ + if (*p == '/') p++; /* Strip heading slash */ + *path = p; /* Return pointer to the path name */ + + /* Check if the drive number is valid or not */ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; /* Is the drive number valid? */ + *rfs = fs = FatFs[drv]; /* Returen pointer to the corresponding file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object registered? */ + + if (fs->fs_type) { /* If the logical drive has been mounted */ + stat = disk_status(fs->drive); + if (!(stat & STA_NOINIT)) { /* and physical drive is kept initialized (has not been changed), */ +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + return FR_OK; /* The file system object is valid */ + } + } + + /* The logical drive must be re-mounted. Following code attempts to mount the logical drive */ + + memset(fs, 0, sizeof(FATFS)); /* Clean-up the file system object */ + fs->drive = LD2PD(drv); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drive); /* Initialize low level disk I/O layer */ + if (stat & STA_NOINIT) /* Check if the drive is ready */ + return FR_NOT_READY; +#if S_MAX_SIZ > 512 /* Get disk sector size if needed */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > S_MAX_SIZ) + return FR_NO_FILESYSTEM; +#endif +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + /* Search FAT partition on the drive */ + fmt = check_fs(fs, bootsect = 0); /* Check sector 0 as an SFD format */ +#if 0 + if (fmt == 1) { /* Not an FAT boot record, it may be patitioned */ + /* Check a partition listed in top of the partition table */ + tbl = &fs->win[MBR_Table + LD2PT(drv) * 16]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bootsect); /* Check the partition */ + } + } +#else +// if (fmt == 1) + { + int i; + /* Check a first fat partition listed in partition table */ + for(i = 0; i < 4; i++) { + tbl = &fs->win[MBR_Table + i * 16]; /* Partition table */ + if (tbl[4] == 0x01 || tbl[4] == 0x04 || tbl[4] == 0x06 || tbl[4] == 0x0B || + tbl[4] == 0x0C || tbl[4] == 0x0E) { /* Is the FAT partition? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bootsect); /* Check the partition */ + break; + } + } + } +#endif + if (fmt || LD_WORD(&fs->win[BPB_BytsPerSec]) != SS(fs)) /* No valid FAT patition is found */ + return FR_NO_FILESYSTEM; + + /* Initialize the file system object */ + fatsize = LD_WORD(&fs->win[BPB_FATSz16]); /* Number of sectors per FAT */ + if (!fatsize) fatsize = LD_DWORD(&fs->win[BPB_FATSz32]); + fs->sects_fat = fatsize; + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + fatsize *= fs->n_fats; /* (Number of sectors in FAT area) */ + fs->fatbase = bootsect + LD_WORD(&fs->win[BPB_RsvdSecCnt]); /* FAT start sector (lba) */ + fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + fs->n_rootdir = LD_WORD(&fs->win[BPB_RootEntCnt]); /* Nmuber of root directory entries */ + totalsect = LD_WORD(&fs->win[BPB_TotSec16]); /* Number of sectors on the file system */ + if (!totalsect) totalsect = LD_DWORD(&fs->win[BPB_TotSec32]); + fs->max_clust = maxclust = (totalsect /* max_clust = Last cluster# + 1 */ + - LD_WORD(&fs->win[BPB_RsvdSecCnt]) - fatsize - fs->n_rootdir / (SS(fs)/32) + ) / fs->csize + 2; + + fmt = FS_FAT12; /* Determine the FAT sub type */ + if (maxclust >= 0xFF7) fmt = FS_FAT16; + if (maxclust >= 0xFFF7) fmt = FS_FAT32; + + if (fmt == FS_FAT32) + fs->dirbase = LD_DWORD(&fs->win[BPB_RootClus]); /* Root directory start cluster */ + else + fs->dirbase = fs->fatbase + fatsize; /* Root directory start sector (lba) */ + fs->database = fs->fatbase + fatsize + fs->n_rootdir / (SS(fs)/32); /* Data start sector (lba) */ + +#if !_FS_READONLY + /* Initialize allocation information */ + fs->free_clust = 0xFFFFFFFF; +#if _USE_FSINFO + /* Get fsinfo if needed */ + if (fmt == FS_FAT32) { + fs->fsi_sector = bootsect + LD_WORD(&fs->win[BPB_FSInfo]); + if (disk_read(fs->drive, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(&fs->win[BS_55AA]) == 0xAA55 && + LD_DWORD(&fs->win[FSI_LeadSig]) == 0x41615252 && + LD_DWORD(&fs->win[FSI_StrucSig]) == 0x61417272) { + fs->last_clust = LD_DWORD(&fs->win[FSI_Nxt_Free]); + fs->free_clust = LD_DWORD(&fs->win[FSI_Free_Count]); + } + } +#endif +#endif + + fs->fs_type = fmt; /* FAT syb-type */ + fs->id = ++fsid; /* File system mount ID */ + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/dir object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + const FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ +) +{ + if (!fs || !fs->fs_type || fs->id != id) + return FR_INVALID_OBJECT; + if (disk_status(fs->drive) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Locical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + BYTE drv, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ +) +{ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + + if (FatFs[drv]) FatFs[drv]->fs_type = 0; /* Clear old object */ + + FatFs[drv] = fs; /* Register and clear new object */ + if (fs) fs->fs_type = 0; + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL *fp, /* Pointer to the blank file object */ + const char *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + fp->fs = NULL; /* Clear file object */ +#if !_FS_READONLY + mode &= (FA_READ|FA_WRITE|FA_CREATE_ALWAYS|FA_OPEN_ALWAYS|FA_CREATE_NEW); + res = auto_mount(&path, &dj.fs, (BYTE)(mode & (FA_WRITE|FA_CREATE_ALWAYS|FA_OPEN_ALWAYS|FA_CREATE_NEW))); +#else + mode &= FA_READ; + res = auto_mount(&path, &dj.fs, 0); +#endif + if (res != FR_OK) return res; + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + +#if !_FS_READONLY + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS|FA_OPEN_ALWAYS|FA_CREATE_NEW)) { + DWORD ps, rs; + if (res != FR_OK) { /* No file, create new */ + if (res != FR_NO_FILE) return res; + res = reserve_direntry(&dj, &dir); + if (res != FR_OK) return res; + memset(dir, 0, 32); /* Initialize the new entry with open name */ + memcpy(&dir[DIR_Name], fn, 8+3); + dir[DIR_NTres] = fn[11]; + mode |= FA_CREATE_ALWAYS; + } + else { /* Any object is already existing */ + if (mode & FA_CREATE_NEW) /* Cannot create new */ + return FR_EXIST; + if (!dir || (dir[DIR_Attr] & (AM_RDO|AM_DIR))) /* Cannot overwrite it (R/O or DIR) */ + return FR_DENIED; + if (mode & FA_CREATE_ALWAYS) { /* Resize it to zero if needed */ + rs = ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); /* Get start cluster */ + ST_WORD(&dir[DIR_FstClusHI], 0); /* cluster = 0 */ + ST_WORD(&dir[DIR_FstClusLO], 0); + ST_DWORD(&dir[DIR_FileSize], 0); /* size = 0 */ + dj.fs->winflag = 1; + ps = dj.fs->winsect; /* Remove the cluster chain */ + if (!remove_chain(dj.fs, rs) || !move_window(dj.fs, ps)) + return FR_RW_ERROR; + dj.fs->last_clust = rs - 1; /* Reuse the cluster hole */ + } + } + if (mode & FA_CREATE_ALWAYS) { + dir[DIR_Attr] = 0; /* Reset attribute */ + ps = get_fattime(); + ST_DWORD(&dir[DIR_CrtTime], ps); /* Created time */ + dj.fs->winflag = 1; + mode |= FA__WRITTEN; /* Set file changed flag */ + } + } + /* Open an existing file */ + else { +#endif /* !_FS_READONLY */ + if (res != FR_OK) return res; /* Trace failed */ + if (!dir || (dir[DIR_Attr] & AM_DIR)) /* It is a directory */ + return FR_NO_FILE; +#if !_FS_READONLY + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + return FR_DENIED; + } + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dir; +#endif + fp->flag = mode; /* File access mode */ + fp->org_clust = /* File start cluster */ + ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); + fp->fsize = LD_DWORD(&dir[DIR_FileSize]); /* File size */ + fp->fptr = 0; fp->csect = 255; /* File pointer */ + fp->curr_sect = 0; + fp->fs = dj.fs; fp->id = dj.fs->id; /* Owner file system object of the file */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL *fp, /* Pointer to the file object */ + void *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clust, sect, remain; + UINT rcnt, cc; + BYTE *rbuff = buff; + + + *br = 0; + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; /* Check error flag */ + if (!(fp->flag & FA_READ)) return FR_DENIED; /* Check access mode */ + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data transferred */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + clust = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_cluster(fp->fs, fp->curr_clust); + if (clust < 2 || clust >= fp->fs->max_clust) goto fr_error; + fp->curr_clust = clust; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust) + fp->csect; /* Get current sector */ + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_read(fp->fs->drive, rbuff, sect, (BYTE)cc) != RES_OK) + goto fr_error; + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } + if (sect != fp->curr_sect) { /* Is window offset changed? */ +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write back file I/O buffer if needed */ + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + goto fr_error; + fp->flag &= (BYTE)~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drive, fp->buffer, sect, 1) != RES_OK) /* Fill file I/O buffer with file data */ + goto fr_error; + fp->curr_sect = sect; + } + fp->csect++; /* Next sector address in the cluster */ + } + rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector from file I/O buffer */ + if (rcnt > btr) rcnt = btr; + memcpy(rbuff, &fp->buffer[fp->fptr % SS(fp->fs)], rcnt); + } + + return FR_OK; + +fr_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL *fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clust, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + + + *bw = 0; + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; /* Check error flag */ + if (!(fp->flag & FA_WRITE)) return FR_DENIED; /* Check access mode */ + if (fp->fsize + btw < fp->fsize) return FR_OK; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data transferred */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (fp->csect >= fp->fs->csize) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clust = fp->org_clust; /* Follow from the origin */ + if (clust == 0) /* When there is no cluster chain, */ + fp->org_clust = clust = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ + clust = create_chain(fp->fs, fp->curr_clust); /* Trace or streach cluster chain */ + } + if (clust == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clust == 1 || clust >= fp->fs->max_clust) goto fw_error; + fp->curr_clust = clust; /* Update current cluster */ + fp->csect = 0; /* Reset sector address in the cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust) + fp->csect; /* Get current sector */ + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (fp->csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - fp->csect; + if (disk_write(fp->fs->drive, wbuff, sect, (BYTE)cc) != RES_OK) + goto fw_error; + fp->csect += (BYTE)cc; /* Next sector address in the cluster */ + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } + if (sect != fp->curr_sect) { /* Is window offset changed? */ + if (fp->flag & FA__DIRTY) { /* Write back file I/O buffer if needed */ + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + goto fw_error; + fp->flag &= (BYTE)~FA__DIRTY; + } + if (fp->fptr < fp->fsize && /* Fill file I/O buffer with file data */ + disk_read(fp->fs->drive, fp->buffer, sect, 1) != RES_OK) + goto fw_error; + fp->curr_sect = sect; + } + fp->csect++; /* Next sector address in the cluster */ + } + wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; + memcpy(&fp->buffer[fp->fptr % SS(fp->fs)], wbuff, wcnt); + fp->flag |= FA__DIRTY; + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file changed flag */ + return FR_OK; + +fw_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the file object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ + /* Write back data buffer if needed */ + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + return FR_RW_ERROR; + fp->flag &= (BYTE)~FA__DIRTY; + } + /* Update the directory entry */ + if (!move_window(fp->fs, fp->dir_sect)) + return FR_RW_ERROR; + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(&dir[DIR_FileSize], fp->fsize); /* Update file size */ + ST_WORD(&dir[DIR_FstClusLO], fp->org_clust); /* Update start cluster */ + ST_WORD(&dir[DIR_FstClusHI], fp->org_clust >> 16); + tim = get_fattime(); /* Updated time */ + ST_DWORD(&dir[DIR_WrtTime], tim); + fp->flag &= (BYTE)~FA__WRITTEN; + res = sync(fp->fs); + } + } + return res; +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + + +#if !_FS_READONLY + res = f_sync(fp); +#else + res = validate(fp->fs, fp->id); +#endif + if (res == FR_OK) fp->fs = NULL; + return res; +} + + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL *fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + DWORD clust, csize, nsect, ifptr; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = 0; fp->csect = 255; + nsect = 0; + if (ofs > 0) { + csize = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / csize >= (ifptr - 1) / csize) {/* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(csize - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clust = fp->curr_clust; + } else { /* When seek to back cluster, */ + clust = fp->org_clust; /* start from the first cluster */ +#if !_FS_READONLY + if (clust == 0) { /* If no cluster chain, create a new chain */ + clust = create_chain(fp->fs, 0); + if (clust == 1) goto fk_error; + fp->org_clust = clust; + } +#endif + fp->curr_clust = clust; + } + if (clust != 0) { + while (ofs > csize) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clust = create_chain(fp->fs, clust); /* Force streached if in write mode */ + if (clust == 0) { /* When disk gets full, clip file size */ + ofs = csize; break; + } + } else +#endif + clust = get_cluster(fp->fs, clust); /* Follow cluster chain if not in write mode */ + if (clust < 2 || clust >= fp->fs->max_clust) goto fk_error; + fp->curr_clust = clust; + fp->fptr += csize; + ofs -= csize; + } + fp->fptr += ofs; + fp->csect = (BYTE)(ofs / SS(fp->fs)); /* Sector offset in the cluster */ + if (ofs & (SS(fp->fs) - 1)) { + nsect = clust2sect(fp->fs, clust) + fp->csect; /* Current sector */ + fp->csect++; + } + } + } + if (nsect && nsect != fp->curr_sect) { +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty buffer if needed */ + if (disk_write(fp->fs->drive, fp->buffer, fp->curr_sect, 1) != RES_OK) + goto fk_error; + fp->flag &= (BYTE)~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drive, fp->buffer, nsect, 1) != RES_OK) + goto fk_error; + fp->curr_sect = nsect; + } + +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set changed flag if the file was extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + + return FR_OK; + +fk_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a directroy object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR *dj, /* Pointer to directory object to create */ + const char *path /* Pointer to the directory path */ +) +{ + FRESULT res; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj->fs, 0); + if (res == FR_OK) { + res = trace_path(dj, fn, path, &dir); /* Trace the directory path */ + if (res == FR_OK) { /* Trace completed */ + if (dir) { /* It is not the root dir */ + if (dir[DIR_Attr] & AM_DIR) { /* The entry is a directory */ + dj->clust = ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); + dj->sect = clust2sect(dj->fs, dj->clust); + dj->index = 2; + } else { /* The entry is not a directory */ + res = FR_NO_FILE; + } + } + dj->id = dj->fs->id; + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entry in Sequense */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR *dj, /* Pointer to the directory object */ + FILINFO *finfo /* Pointer to file information to return */ +) +{ + BYTE *dir, c, res; + + + res = validate(dj->fs, dj->id); /* Check validity of the object */ + if (res != FR_OK) return (FRESULT)res; + + finfo->fname[0] = 0; + while (dj->sect) { + if (!move_window(dj->fs, dj->sect)) + return FR_RW_ERROR; + dir = &dj->fs->win[(dj->index & ((SS(dj->fs) - 1) >> 5)) * 32]; /* pointer to the directory entry */ + c = dir[DIR_Name]; + if (c == 0) break; /* Has it reached to end of dir? */ + if (c != 0xE5 && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ + get_fileinfo(finfo, dir); + if (!next_dir_entry(dj)) dj->sect = 0; /* Next entry */ + if (finfo->fname[0]) break; /* Found valid entry */ + } + + return FR_OK; +} + + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const char *path, /* Pointer to the file path */ + FILINFO *finfo /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 0); + if (res == FR_OK) { + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) { /* Trace completed */ + if (dir) /* Found an object */ + get_fileinfo(finfo, dir); + else /* It is root dir */ + res = FR_INVALID_NAME; + } + } + + return res; +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) return res; + if (fp->flag & FA__ERROR) return FR_RW_ERROR; /* Check error flag */ + if (!(fp->flag & FA_WRITE)) return FR_DENIED; /* Check access mode */ + + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + if (!remove_chain(fp->fs, fp->org_clust)) goto ft_error; + fp->org_clust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_cluster(fp->fs, fp->curr_clust); + if (ncl < 2) goto ft_error; + if (ncl < fp->fs->max_clust) { + if (!put_cluster(fp->fs, fp->curr_clust, 0x0FFFFFFF)) goto ft_error; + if (!remove_chain(fp->fs, ncl)) goto ft_error; + } + } + } + + return FR_OK; + +ft_error: /* Abort this file due to an unrecoverable error */ + fp->flag |= FA__ERROR; + return FR_RW_ERROR; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const char *drv, /* Pointer to the logical drive number (root dir) */ + DWORD *nclust, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ +) +{ + FRESULT res; + DWORD n, clust, sect; + BYTE fat, f, *p; + + + /* Get drive number */ + res = auto_mount(&drv, fatfs, 0); + if (res != FR_OK) return res; + + /* If number of free cluster is valid, return it without cluster scan. */ + if ((*fatfs)->free_clust <= (*fatfs)->max_clust - 2) { + *nclust = (*fatfs)->free_clust; + return FR_OK; + } + + /* Get number of free clusters */ + fat = (*fatfs)->fs_type; + n = 0; + if (fat == FS_FAT12) { + clust = 2; + do { + if ((WORD)get_cluster(*fatfs, clust) == 0) n++; + } while (++clust < (*fatfs)->max_clust); + } else { + clust = (*fatfs)->max_clust; + sect = (*fatfs)->fatbase; + f = 0; p = 0; + do { + if (!f) { + if (!move_window(*fatfs, sect++)) return FR_RW_ERROR; + p = (*fatfs)->win; + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; f += 1; + } else { + if (LD_DWORD(p) == 0) n++; + p += 4; f += 2; + } + } while (--clust); + } + (*fatfs)->free_clust = n; +#if _USE_FSINFO + if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; +#endif + + *nclust = n; + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const char *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, *sdir; + DWORD dclust, dsect; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 1); + if (res != FR_OK) return res; + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res != FR_OK) return res; /* Trace failed */ + if (!dir) return FR_INVALID_NAME; /* It is the root directory */ + if (dir[DIR_Attr] & AM_RDO) return FR_DENIED; /* It is a R/O object */ + dsect = dj.fs->winsect; + dclust = ((DWORD)LD_WORD(&dir[DIR_FstClusHI]) << 16) | LD_WORD(&dir[DIR_FstClusLO]); + + if (dir[DIR_Attr] & AM_DIR) { /* It is a sub-directory */ + dj.clust = dclust; /* Check if the sub-dir is empty or not */ + dj.sect = clust2sect(dj.fs, dclust); + dj.index = 2; + do { + if (!move_window(dj.fs, dj.sect)) return FR_RW_ERROR; + sdir = &dj.fs->win[(dj.index & ((SS(dj.fs) - 1) >> 5)) * 32]; + if (sdir[DIR_Name] == 0) break; + if (sdir[DIR_Name] != 0xE5 && !(sdir[DIR_Attr] & AM_VOL)) + return FR_DENIED; /* The directory is not empty */ + } while (next_dir_entry(&dj)); + } + + if (!move_window(dj.fs, dsect)) return FR_RW_ERROR; /* Mark the directory entry 'deleted' */ + dir[DIR_Name] = 0xE5; + dj.fs->winflag = 1; + if (!remove_chain(dj.fs, dclust)) return FR_RW_ERROR; /* Remove the cluster chain */ + + return sync(dj.fs); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const char *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, *fw, n; + char fn[8+3+1]; + DWORD sect, dsect, dclust, pclust, tim; + + + res = auto_mount(&path, &dj.fs, 1); + if (res != FR_OK) return res; + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) return FR_EXIST; /* Any file or directory is already existing */ + if (res != FR_NO_FILE) return res; + + res = reserve_direntry(&dj, &dir); /* Reserve a directory entry */ + if (res != FR_OK) return res; + sect = dj.fs->winsect; + dclust = create_chain(dj.fs, 0); /* Allocate a cluster for new directory table */ + if (dclust == 1) return FR_RW_ERROR; + dsect = clust2sect(dj.fs, dclust); + if (!dsect) return FR_DENIED; + if (!move_window(dj.fs, dsect)) return FR_RW_ERROR; + + fw = dj.fs->win; + memset(fw, 0, SS(dj.fs)); /* Clear the new directory table */ + for (n = 1; n < dj.fs->csize; n++) { + if (disk_write(dj.fs->drive, fw, ++dsect, 1) != RES_OK) + return FR_RW_ERROR; + } + memset(&fw[DIR_Name], ' ', 8+3); /* Create "." entry */ + fw[DIR_Name] = '.'; + fw[DIR_Attr] = AM_DIR; + tim = get_fattime(); + ST_DWORD(&fw[DIR_WrtTime], tim); + memcpy(&fw[32], &fw[0], 32); fw[33] = '.'; /* Create ".." entry */ + ST_WORD(&fw[ DIR_FstClusLO], dclust); + ST_WORD(&fw[ DIR_FstClusHI], dclust >> 16); + pclust = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pclust == dj.fs->dirbase) pclust = 0; + ST_WORD(&fw[32+DIR_FstClusLO], pclust); + ST_WORD(&fw[32+DIR_FstClusHI], pclust >> 16); + dj.fs->winflag = 1; + + if (!move_window(dj.fs, sect)) return FR_RW_ERROR; + memset(&dir[0], 0, 32); /* Initialize the new entry */ + memcpy(&dir[DIR_Name], fn, 8+3); /* Name */ + dir[DIR_NTres] = fn[11]; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(&dir[DIR_WrtTime], tim); /* Crated time */ + ST_WORD(&dir[DIR_FstClusLO], dclust); /* Table start cluster */ + ST_WORD(&dir[DIR_FstClusHI], dclust >> 16); + + return sync(dj.fs); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change File Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const char *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 1); + if (res == FR_OK) { + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) { /* Trace completed */ + if (!dir) { + res = FR_INVALID_NAME; /* Root directory */ + } else { + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + res = sync(dj.fs); + } + } + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const char *path, /* Pointer to the file/directory name */ + const FILINFO *finfo /* Pointer to the timestamp to be set */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + char fn[8+3+1]; + + + res = auto_mount(&path, &dj.fs, 1); + if (res == FR_OK) { + res = trace_path(&dj, fn, path, &dir); /* Trace the file path */ + if (res == FR_OK) { /* Trace completed */ + if (!dir) { + res = FR_INVALID_NAME; /* Root directory */ + } else { + ST_WORD(&dir[DIR_WrtTime], finfo->ftime); + ST_WORD(&dir[DIR_WrtDate], finfo->fdate); + res = sync(dj.fs); + } + } + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const char *path_old, /* Pointer to the old name */ + const char *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR dj; + DWORD sect_old; + BYTE *dir_old, *dir_new, direntry[32-11]; + char fn[8+3+1]; + + + res = auto_mount(&path_old, &dj.fs, 1); + if (res != FR_OK) return res; + + res = trace_path(&dj, fn, path_old, &dir_old); /* Check old object */ + if (res != FR_OK) return res; /* The old object is not found */ + if (!dir_old) return FR_NO_FILE; + sect_old = dj.fs->winsect; /* Save the object information */ + memcpy(direntry, &dir_old[DIR_Attr], 32-11); + + res = trace_path(&dj, fn, path_new, &dir_new); /* Check new object */ + if (res == FR_OK) return FR_EXIST; /* The new object name is already existing */ + if (res != FR_NO_FILE) return res; /* Is there no old name? */ + res = reserve_direntry(&dj, &dir_new); /* Reserve a directory entry */ + if (res != FR_OK) return res; + + memcpy(&dir_new[DIR_Attr], direntry, 32-11); /* Create new entry */ + memcpy(&dir_new[DIR_Name], fn, 8+3); + dir_new[DIR_NTres] = fn[11]; + dj.fs->winflag = 1; + + if (!move_window(dj.fs, sect_old)) return FR_RW_ERROR; /* Delete old entry */ + dir_old[DIR_Name] = 0xE5; + + return sync(dj.fs); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Multiple of 32 and <= 2048 */ +#define N_FATS 1 /* 1 or 2 */ +#define MAX_SECTOR 64000000UL /* Maximum partition size */ +#define MIN_SECTOR 2000UL /* Minimum partition size */ + + + +FRESULT f_mkfs ( + BYTE drv, /* Logical drive number */ + BYTE partition, /* Partitioning rule 0:FDISK, 1:SFD */ + WORD allocsize /* Allocation unit size [bytes] */ +) +{ + BYTE fmt, m, *tbl; + DWORD b_part, b_fat, b_dir, b_data; /* Area offset (LBA) */ + DWORD n_part, n_rsv, n_fat, n_dir; /* Area size */ + DWORD n_clust, n; + FATFS *fs; + DSTATUS stat; + + + /* Check validity of the parameters */ + if (drv >= _DRIVES) return FR_INVALID_DRIVE; + if (partition >= 2) return FR_MKFS_ABORTED; + for (n = 512; n <= 32768U && n != allocsize; n <<= 1); + if (n != allocsize) return FR_MKFS_ABORTED; + + /* Check mounted drive and clear work area */ + fs = FatFs[drv]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + drv = LD2PD(drv); + + /* Get disk statics */ + stat = disk_initialize(drv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_part) != RES_OK || n_part < MIN_SECTOR) + return FR_MKFS_ABORTED; + if (n_part > MAX_SECTOR) n_part = MAX_SECTOR; + b_part = (!partition) ? 63 : 0; /* Boot sector */ + n_part -= b_part; +#if S_MAX_SIZ > 512 /* Check disk sector size */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK + || SS(fs) > S_MAX_SIZ + || SS(fs) > allocsize) + return FR_MKFS_ABORTED; +#endif + allocsize /= SS(fs); /* Number of sectors per cluster */ + + /* Pre-compute number of clusters and FAT type */ + n_clust = n_part / allocsize; + fmt = FS_FAT12; + if (n_clust >= 0xFF5) fmt = FS_FAT16; + if (n_clust >= 0xFFF5) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + switch (fmt) { + case FS_FAT12: + n_fat = ((n_clust * 3 + 1) / 2 + 3 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + case FS_FAT16: + n_fat = ((n_clust * 2) + 4 + SS(fs) - 1) / SS(fs); + n_rsv = 1 + partition; + n_dir = N_ROOTDIR * 32 / SS(fs); + break; + default: + n_fat = ((n_clust * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 33 - partition; + n_dir = 0; + } + b_fat = b_part + n_rsv; /* FATs start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory start sector */ + b_data = b_dir + n_dir; /* Data start sector */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK) return FR_MKFS_ABORTED; + n = (b_data + n - 1) & ~(n - 1); + n_fat += (n - b_data) / N_FATS; + /* b_dir and b_data are no longer used below */ + + /* Determine number of cluster and final check of validity of the FAT type */ + n_clust = (n_part - n_rsv - n_fat * N_FATS - n_dir) / allocsize; + if ( (fmt == FS_FAT16 && n_clust < 0xFF5) + || (fmt == FS_FAT32 && n_clust < 0xFFF5)) + return FR_MKFS_ABORTED; + + /* Create partition table if needed */ + if (!partition) { + DWORD n_disk = b_part + n_part; + + tbl = &fs->win[MBR_Table]; + ST_DWORD(&tbl[0], 0x00010180); /* Partition start in CHS */ + if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */ + n_disk = n_disk / 63 / 255; + tbl[7] = (BYTE)n_disk; + tbl[6] = (BYTE)((n_disk >> 2) | 63); + } else { + ST_WORD(&tbl[6], 0xFFFF); + } + tbl[5] = 254; + if (fmt != FS_FAT32) /* System ID */ + tbl[4] = (n_part < 0x10000) ? 0x04 : 0x06; + else + tbl[4] = 0x0c; + ST_DWORD(&tbl[8], 63); /* Partition start in LBA */ + ST_DWORD(&tbl[12], n_part); /* Partition size in LBA */ + ST_WORD(&tbl[64], 0xAA55); /* Signature */ + if (disk_write(drv, fs->win, 0, 1) != RES_OK) + return FR_RW_ERROR; + } + + /* Create boot record */ + tbl = fs->win; /* Clear buffer */ + memset(tbl, 0, SS(fs)); + ST_DWORD(&tbl[BS_jmpBoot], 0x90FEEB); /* Boot code (jmp $, nop) */ + ST_WORD(&tbl[BPB_BytsPerSec], SS(fs)); /* Sector size */ + tbl[BPB_SecPerClus] = (BYTE)allocsize; /* Sectors per cluster */ + ST_WORD(&tbl[BPB_RsvdSecCnt], n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + ST_WORD(&tbl[BPB_RootEntCnt], SS(fs) / 32 * n_dir); /* Number of rootdir entries */ + if (n_part < 0x10000) { /* Number of total sectors */ + ST_WORD(&tbl[BPB_TotSec16], n_part); + } else { + ST_DWORD(&tbl[BPB_TotSec32], n_part); + } + tbl[BPB_Media] = 0xF8; /* Media descripter */ + ST_WORD(&tbl[BPB_SecPerTrk], 63); /* Number of sectors per track */ + ST_WORD(&tbl[BPB_NumHeads], 255); /* Number of heads */ + ST_DWORD(&tbl[BPB_HiddSec], b_part); /* Hidden sectors */ + n = get_fattime(); /* Use current time as a VSN */ + if (fmt != FS_FAT32) { + ST_DWORD(&tbl[BS_VolID], n); /* Volume serial number */ + ST_WORD(&tbl[BPB_FATSz16], n_fat); /* Number of secters per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + memcpy(&tbl[BS_VolLab], "NO NAME FAT ", 19); /* Volume lavel, FAT signature */ + } else { + ST_DWORD(&tbl[BS_VolID32], n); /* Volume serial number */ + ST_DWORD(&tbl[BPB_FATSz32], n_fat); /* Number of secters per FAT */ + ST_DWORD(&tbl[BPB_RootClus], 2); /* Root directory cluster (2) */ + ST_WORD(&tbl[BPB_FSInfo], 1); /* FSInfo record (bs+1) */ + ST_WORD(&tbl[BPB_BkBootSec], 6); /* Backup boot record (bs+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + memcpy(&tbl[BS_VolLab32], "NO NAME FAT32 ", 19); /* Volume lavel, FAT signature */ + } + ST_WORD(&tbl[BS_55AA], 0xAA55); /* Signature */ + if (disk_write(drv, tbl, b_part+0, 1) != RES_OK) + return FR_RW_ERROR; + if (fmt == FS_FAT32) + disk_write(drv, tbl, b_part+6, 1); + + /* Initialize FAT area */ + for (m = 0; m < N_FATS; m++) { + memset(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + if (fmt != FS_FAT32) { + n = (fmt == FS_FAT12) ? 0x00FFFFF8 : 0xFFFFFFF8; + ST_DWORD(&tbl[0], n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + ST_DWORD(&tbl[0], 0xFFFFFFF8); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(&tbl[4], 0xFFFFFFFF); + ST_DWORD(&tbl[8], 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ + } + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_RW_ERROR; + memset(tbl, 0, SS(fs)); /* Following FAT entries are filled by zero */ + for (n = 1; n < n_fat; n++) { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_RW_ERROR; + } + } + + /* Initialize Root directory */ + m = (BYTE)((fmt == FS_FAT32) ? allocsize : n_dir); + do { + if (disk_write(drv, tbl, b_fat++, 1) != RES_OK) + return FR_RW_ERROR; + } while (--m); + + /* Create FSInfo record if needed */ + if (fmt == FS_FAT32) { + ST_WORD(&tbl[BS_55AA], 0xAA55); + ST_DWORD(&tbl[FSI_LeadSig], 0x41615252); + ST_DWORD(&tbl[FSI_StrucSig], 0x61417272); + ST_DWORD(&tbl[FSI_Free_Count], n_clust - 1); + ST_DWORD(&tbl[FSI_Nxt_Free], 0xFFFFFFFF); + disk_write(drv, tbl, b_part+1, 1); + disk_write(drv, tbl, b_part+7, 1); + } + + return (disk_ioctl(drv, CTRL_SYNC, NULL) == RES_OK) ? FR_OK : FR_RW_ERROR; +} + +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC >= 1 +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ +char* fgets ( + char* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer */ + FIL* fil /* Pointer to the file object */ +) +{ + int i = 0; + char *p = buff; + UINT rc; + + + while (i < len - 1) { /* Read bytes until buffer gets filled */ + f_read(fil, p, 1, &rc); + if (rc != 1) break; /* Break when no data to read */ +#if _USE_STRFUNC >= 2 + if (*p == '\r') continue; /* Strip '\r' */ +#endif + i++; + if (*p++ == '\n') break; /* Break when reached end of line */ + } + *p = 0; + return i ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ +int fputc ( + int chr, /* A character to be output */ + FIL* fil /* Ponter to the file object */ +) +{ + UINT bw; + char c; + + +#if _USE_STRFUNC >= 2 + if (chr == '\n') fputc ('\r', fil); /* LF -> CRLF conversion */ +#endif + if (!fil) { /* Special value may be used to switch the destination to any other device */ + /* put_console(chr); */ + return chr; + } + c = (char)chr; + f_write(fil, &c, 1, &bw); /* Write a byte to the file */ + return bw ? chr : EOF; /* Return the resulut */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ +int fputs ( + const char* str, /* Pointer to the string to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + int n; + + + for (n = 0; *str; str++, n++) { + if (fputc(*str, fil) == EOF) return EOF; + } + return n; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ +int fprintf ( + FIL* fil, /* Pointer to the file object */ + const char* str, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + UCHAR c, f, r; + ULONG val; + char s[16]; + int i, w, res, cc; + + + va_start(arp, str); + + for (cc = res = 0; cc != EOF; res += cc) { + c = *str++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape cahracter */ + cc = fputc(c, fil); + if (cc != EOF) cc = 1; + continue; + } + w = f = 0; + c = *str++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *str++; + } + while (c >= '0' && c <= '9') { /* Precision */ + w = w * 10 + (c - '0'); + c = *str++; + } + if (c == 'l') { /* Prefix: Size is long int */ + f |= 2; c = *str++; + } + if (c == 's') { /* Type is string */ + cc = fputs(va_arg(arp, char*), fil); + continue; + } + if (c == 'c') { /* Type is character */ + cc = fputc(va_arg(arp, char), fil); + if (cc != EOF) cc = 1; + continue; + } + r = 0; + if (c == 'd') r = 10; /* Type is signed decimal */ + if (c == 'u') r = 10; /* Type is unsigned decimal */ + if (c == 'X') r = 16; /* Type is unsigned hexdecimal */ + if (r == 0) break; /* Unknown type */ + if (f & 2) { /* Get the value */ + val = (ULONG)va_arg(arp, long); + } else { + val = (c == 'd') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int); + } + /* Put numeral string */ + if (c == 'd') { + if (val >= 0x80000000) { + val = 0 - val; + f |= 4; + } + } + i = sizeof(s) - 1; s[i] = 0; + do { + c = (UCHAR)(val % r + '0'); + if (c > '9') c += 7; + s[--i] = c; + val /= r; + } while (i && val); + if (i && (f & 4)) s[--i] = '-'; + w = sizeof(s) - 1 - w; + while (i && i > w) s[--i] = (f & 1) ? '0' : ' '; + cc = fputs(&s[i], fil); + } + + va_end(arp); + return (cc == EOF) ? cc : res; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC >= 1*/ diff --git a/A58-STEPLDR/Src/fs/ff.h b/A58-STEPLDR/Src/fs/ff.h new file mode 100644 index 00000000..15053b22 --- /dev/null +++ b/A58-STEPLDR/Src/fs/ff.h @@ -0,0 +1,343 @@ +/*--------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.06 (C)ChaN, 2008 +/---------------------------------------------------------------------------/ +/ FatFs module is an experimenal project to implement FAT file system to +/ cheap microcontrollers. This is a free software and is opened for education, +/ research and development under license policy of following trems. +/ +/ Copyright (C) 2008, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is no warranty. +/ * You can use, modify and/or redistribute it for personal, non-profit or +/ commercial use without any restriction under your responsibility. +/ * Redistributions of source code must retain the above copyright notice. +/ +/---------------------------------------------------------------------------*/ + +#ifndef _FATFS +#define _FATFS + +#define _MCU_ENDIAN 2 +/* The _MCU_ENDIAN defines which access method is used to the FAT structure. +/ 1: Enable word access. +/ 2: Disable word access and use byte-by-byte access instead. +/ When the architectural byte order of the MCU is big-endian and/or address +/ miss-aligned access results incorrect behavior, the _MCU_ENDIAN must be set to 2. +/ If it is not the case, it can also be set to 1 for good code efficiency. */ + +#define _FS_READONLY 1 +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + +#define _FS_MINIMIZE 0 +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename are removed. +/ 2: f_opendir and f_readdir are removed in addition to level 1. +/ 3: f_lseek is removed in addition to level 2. */ + +#define _USE_STRFUNC 0 +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + +#define _USE_MKFS 0 +/* When _USE_MKFS is set to 1 and _FS_READONLY is set to 0, f_mkfs function is +/ enabled. */ + +#define _DRIVES 2 +/* Number of logical drives to be used. This affects the size of internal table. */ + +#define _MULTI_PARTITION 0 +/* When _MULTI_PARTITION is set to 0, each logical drive is bound to same +/ physical drive number and can mount only 1st primaly partition. When it is +/ set to 1, each logical drive can mount a partition listed in Drives[]. */ + +#define _USE_FSINFO 1 +/* To enable FSInfo support on FAT32 volume, set _USE_FSINFO to 1. */ + +#define _USE_SJIS 0 +/* When _USE_SJIS is set to 1, Shift-JIS code transparency is enabled, otherwise +/ only US-ASCII(7bit) code can be accepted as file/directory name. */ + +#define _USE_NTFLAG 1 +/* When _USE_NTFLAG is set to 1, upper/lower case of the file name is preserved. +/ Note that the files are always accessed in case insensitive. */ + + +#include "integer.h" + + + +/* Definitions corresponds to multiple sector size (not tested) */ +#define S_MAX_SIZ 512U /* Do not change */ +#if S_MAX_SIZ > 512U +#define SS(fs) ((fs)->s_size) +#else +#define SS(fs) 512U +#endif + + +/* File system object structure */ +typedef struct _FATFS { + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries */ + DWORD winsect; /* Current sector appearing in the win[] */ + DWORD sects_fat; /* Sectors per fat */ + DWORD max_clust; /* Maximum cluster# + 1 */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (cluster# for FAT32) */ + DWORD database; /* Data start sector */ +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ +#if _USE_FSINFO + DWORD fsi_sector; /* fsinfo sector */ + BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + BYTE pad2; +#endif +#else + BYTE pad3; + BYTE pad2; +#endif + BYTE fs_type; /* FAT sub type */ + BYTE csize; /* Number of sectors per cluster */ +#if S_MAX_SIZ > 512U + WORD s_size; /* Sector size */ +#endif + BYTE n_fats; /* Number of FAT copies */ + BYTE drive; /* Physical drive number */ + BYTE winflag; /* win[] dirty flag (1:must be written back) */ + BYTE pad1; + BYTE win[S_MAX_SIZ]; /* Disk access window for Directory/FAT */ +} FATFS; + + +/* Directory object structure */ +typedef struct _DIR { + WORD id; /* Owner file system mount ID */ + WORD index; /* Current index */ + FATFS* fs; /* Pointer to the owner file system object */ + DWORD sclust; /* Start cluster */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ +} DIR; + + +/* File object structure */ +typedef struct _FIL { + WORD id; /* Owner file system mount ID */ + BYTE flag; /* File status flags */ + BYTE csect; /* Sector address in the cluster */ + FATFS* fs; /* Pointer to the owner file system object */ + DWORD fptr; /* File R/W pointer */ + DWORD fsize; /* File size */ + DWORD org_clust; /* File start cluster */ + DWORD curr_clust; /* Current cluster */ + DWORD curr_sect; /* Current sector */ +#if _FS_READONLY == 0 + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Ponter to the directory entry in the window */ +#endif + BYTE buffer[S_MAX_SIZ]; /* File R/W buffer */ +} FIL; + + +/* File status structure */ +typedef struct _FILINFO { + DWORD fsize; /* Size */ + WORD fdate; /* Date */ + WORD ftime; /* Time */ + BYTE fattrib; /* Attribute */ + char fname[8+1+3+1]; /* Name (8.3 format) */ +} FILINFO; + + + +/* Definitions corresponds to multi partition */ + +#if _MULTI_PARTITION != 0 /* Multiple partition cfg */ + +typedef struct _PARTITION { + BYTE pd; /* Physical drive # (0-255) */ + BYTE pt; /* Partition # (0-3) */ +} PARTITION; +extern +const PARTITION Drives[]; /* Logical drive# to physical location conversion table */ +#define LD2PD(drv) (Drives[drv].pd) /* Get physical drive# */ +#define LD2PT(drv) (Drives[drv].pt) /* Get partition# */ + +#else /* Single partition cfg */ + +#define LD2PD(drv) (drv) /* Physical drive# is equal to logical drive# */ +#define LD2PT(drv) 0 /* Always mounts the 1st partition */ + +#endif + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* 0 */ + FR_NOT_READY, /* 1 */ + FR_NO_FILE, /* 2 */ + FR_NO_PATH, /* 3 */ + FR_INVALID_NAME, /* 4 */ + FR_INVALID_DRIVE, /* 5 */ + FR_DENIED, /* 6 */ + FR_EXIST, /* 7 */ + FR_RW_ERROR, /* 8 */ + FR_WRITE_PROTECTED, /* 9 */ + FR_NOT_ENABLED, /* 10 */ + FR_NO_FILESYSTEM, /* 11 */ + FR_INVALID_OBJECT, /* 12 */ + FR_MKFS_ABORTED /* 13 */ +} FRESULT; + + + +/*-----------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ +FRESULT f_open (FIL*, const char*, BYTE); /* Open or create a file */ +FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */ +FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */ +FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ +FRESULT f_close (FIL*); /* Close an open file object */ +FRESULT f_opendir (DIR*, const char*); /* Open an existing directory */ +FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ +FRESULT f_stat (const char*, FILINFO*); /* Get file status */ +FRESULT f_getfree (const char*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ +FRESULT f_truncate (FIL*); /* Truncate file */ +FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ +FRESULT f_unlink (const char*); /* Delete an existing file or directory */ +FRESULT f_mkdir (const char*); /* Create a new directory */ +FRESULT f_chmod (const char*, BYTE, BYTE); /* Change file/dir attriburte */ +FRESULT f_utime (const char*, const FILINFO*); /* Change file/dir timestamp */ +FRESULT f_rename (const char*, const char*); /* Rename/Move a file or directory */ +FRESULT f_mkfs (BYTE, BYTE, WORD); /* Create a file system on the drive */ +#if _USE_STRFUNC +#define feof(fp) ((fp)->fptr == (fp)->fsize) +#define EOF -1 +int fputc (int, FIL*); /* Put a character to the file */ +int fputs (const char*, FIL*); /* Put a string to the file */ +int fprintf (FIL*, const char*, ...); /* Put a formatted string to the file */ +char* fgets (char*, int, FIL*); /* Get a string from the file */ +#endif + +/* User defined function to give a current time to fatfs module */ + +DWORD get_fattime (void); /* 31-25: Year(0-127 org.1980), 24-21: Month(1-12), 20-16: Day(1-31) */ + /* 15-11: Hour(0-23), 10-5: Minute(0-59), 4-0: Second(0-29 *2) */ + + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 +#if _FS_READONLY == 0 +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif +#define FA__ERROR 0x80 + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ + + + +/* Offset of FAT structure members */ + +#define BS_jmpBoot 0 +#define BS_OEMName 3 +#define BPB_BytsPerSec 11 +#define BPB_SecPerClus 13 +#define BPB_RsvdSecCnt 14 +#define BPB_NumFATs 16 +#define BPB_RootEntCnt 17 +#define BPB_TotSec16 19 +#define BPB_Media 21 +#define BPB_FATSz16 22 +#define BPB_SecPerTrk 24 +#define BPB_NumHeads 26 +#define BPB_HiddSec 28 +#define BPB_TotSec32 32 +#define BS_55AA 510 + +#define BS_DrvNum 36 +#define BS_BootSig 38 +#define BS_VolID 39 +#define BS_VolLab 43 +#define BS_FilSysType 54 + +#define BPB_FATSz32 36 +#define BPB_ExtFlags 40 +#define BPB_FSVer 42 +#define BPB_RootClus 44 +#define BPB_FSInfo 48 +#define BPB_BkBootSec 50 +#define BS_DrvNum32 64 +#define BS_BootSig32 66 +#define BS_VolID32 67 +#define BS_VolLab32 71 +#define BS_FilSysType32 82 + +#define FSI_LeadSig 0 +#define FSI_StrucSig 484 +#define FSI_Free_Count 488 +#define FSI_Nxt_Free 492 + +#define MBR_Table 446 + +#define DIR_Name 0 +#define DIR_Attr 11 +#define DIR_NTres 12 +#define DIR_CrtTime 14 +#define DIR_CrtDate 16 +#define DIR_FstClusHI 20 +#define DIR_WrtTime 22 +#define DIR_WrtDate 24 +#define DIR_FstClusLO 26 +#define DIR_FileSize 28 + + + +/* Multi-byte word access macros */ + +#if _MCU_ENDIAN==1 /* Use word access */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#elif _MCU_ENDIAN==2 /* Use byte-by-byte access */ +#define LD_WORD(ptr) (WORD)(((WORD)*(volatile BYTE*)((ptr)+1)<<8)|(WORD)*(volatile BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*(volatile BYTE*)((ptr)+3)<<24)|((DWORD)*(volatile BYTE*)((ptr)+2)<<16)|((WORD)*(volatile BYTE*)((ptr)+1)<<8)|*(volatile BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(volatile BYTE*)(ptr)=(BYTE)(val); *(volatile BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(volatile BYTE*)(ptr)=(BYTE)(val); *(volatile BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(volatile BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(volatile BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24) +#else +#error Do not forget to set _MCU_ENDIAN properly! +#endif + +extern FATFS g_fs; + +#endif /* _FATFS */ diff --git a/A58-STEPLDR/Src/fs/integer.h b/A58-STEPLDR/Src/fs/integer.h new file mode 100644 index 00000000..66285de1 --- /dev/null +++ b/A58-STEPLDR/Src/fs/integer.h @@ -0,0 +1,33 @@ +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _INTEGER + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef signed char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +/* Boolean type */ +#undef FALSE +#undef TRUE + +typedef enum { FALSE = 0, TRUE } BOOL; + +#define _INTEGER +#endif diff --git a/A58-STEPLDR/Src/fs/sd_if.h b/A58-STEPLDR/Src/fs/sd_if.h new file mode 100644 index 00000000..e2abd88b --- /dev/null +++ b/A58-STEPLDR/Src/fs/sd_if.h @@ -0,0 +1,10 @@ +#ifndef SD_IF_H__ +#define SD_IF_H__ + +int MMC_disk_initialize(); + +int MMC_disk_read(void *buff, DWORD sector, BYTE count); + +int MMC_disk_ioctl(BYTE ctrl, void *buff); + +#endif diff --git a/A58-STEPLDR/Src/gpio.c b/A58-STEPLDR/Src/gpio.c new file mode 100644 index 00000000..69a45e8e --- /dev/null +++ b/A58-STEPLDR/Src/gpio.c @@ -0,0 +1,96 @@ +#include "amt630h.h" +#include "pinctrl.h" + +#define GPIO_SWPORTA_DR 0x00 +#define GPIO_SWPORTA_DDR 0x04 +#define GPIO_SWPORTA_CTL 0x08 +#define GPIO_SWPORTA_INTEN 0x30 +#define GPIO_SWPORTA_INTMASK 0x34 +#define GPIO_SWPORTA_INTTYPE_LEVEL 0x38 +#define GPIO_SWPORTA_INT_POLARITY 0x3c +#define GPIO_SWPORTA_INTSTATUS 0x40 +#define GPIO_SWPORTA_RAW_INTSTATUS 0x44 +#define GPIO_SWPORTA_DEBOUNCE 0x48 +#define GPIO_SWPORTA_EOI 0x4c +#define GPIO_SWPORTA_EXT_PORTA 0x50 +#define GPIO_SWPORTA_EXT_PORTB 0x54 +#define GPIO_SWPORTA_EXT_PORTC 0x58 +#define GPIO_SWPORTA_EXT_PORTD 0x5c +#define GPIO_SWPORTA_LS_SYNC 0x60 +#define GPIO_SWPORTA_ID_CODE 0x64 +#define GPIO_SWPORTA_INT_BOTHEDGE 0x68 +#define GPIO_SWPORTA_VER_ID_CODE 0x6C +#define GPIO_SWPORTA_CONFIG_REG2 0x70 +#define GPIO_SWPORTA_CONFIG_REG1 0x74 + +#define GPIO_NUM 128 + +static uint32_t gpio_get_regbase(int gpio) +{ + int gpiox = (gpio >> 5) & 0x3; + + return REGS_GPIO_BASE + 0x80 * gpiox; +} + +static int GPIO_OFFSET(unsigned gpio) +{ + if (gpio == 96) + return 2; + else if (gpio == 97) + return 0; + else if (gpio == 98) + return 3; + else if (gpio == 99) + return 1; + else + return gpio & 0x1F; +} + +static void *GPIO_MODREG(unsigned gpio) +{ + return (void*)(gpio_get_regbase(gpio) + GPIO_SWPORTA_DDR); +} + +static void *GPIO_WDATAREG(unsigned gpio) +{ + return (void*)(gpio_get_regbase(gpio) + GPIO_SWPORTA_DR); +} + +static void *GPIO_RDATAREG(unsigned gpio) +{ + return (void*)(gpio_get_regbase(gpio) + GPIO_SWPORTA_EXT_PORTA); +} + +void gpio_request(unsigned gpio) +{ + pinctrl_gpio_request(gpio); +} + +void gpio_direction_output(unsigned gpio, int value) +{ + gpio_request(gpio); + writel(readl(GPIO_MODREG(gpio)) | (1 << GPIO_OFFSET(gpio)), GPIO_MODREG(gpio)); + if (value) + writel(readl(GPIO_WDATAREG(gpio)) | (1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); + else + writel(readl(GPIO_WDATAREG(gpio)) & ~(1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); +} + +void gpio_direction_input(unsigned gpio) +{ + gpio_request(gpio); + writel(readl(GPIO_MODREG(gpio)) & ~(1 << GPIO_OFFSET(gpio)), GPIO_MODREG(gpio)); +} + +void gpio_set_value(unsigned gpio, int value) +{ + if (value) + writel(readl(GPIO_WDATAREG(gpio)) | (1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); + else + writel(readl(GPIO_WDATAREG(gpio)) & ~(1 << GPIO_OFFSET(gpio)), GPIO_WDATAREG(gpio)); +} + +int gpio_get_value(unsigned gpio) +{ + return !!(readl(GPIO_RDATAREG(gpio)) & (1 << GPIO_OFFSET(gpio))); +} diff --git a/A58-STEPLDR/Src/gpio.h b/A58-STEPLDR/Src/gpio.h new file mode 100644 index 00000000..6a9e2391 --- /dev/null +++ b/A58-STEPLDR/Src/gpio.h @@ -0,0 +1,23 @@ +#ifndef _GPIO_H +#define _GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +void gpio_request(unsigned gpio); + +void gpio_direction_output(unsigned gpio, int value); + +void gpio_direction_input(unsigned gpio); + +void gpio_set_value(unsigned gpio, int value); + +int gpio_get_value(unsigned gpio); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/A58-STEPLDR/Src/i2c-gpio.c b/A58-STEPLDR/Src/i2c-gpio.c new file mode 100644 index 00000000..07b235fc --- /dev/null +++ b/A58-STEPLDR/Src/i2c-gpio.c @@ -0,0 +1,650 @@ +#include +#include "cp15.h" +#include "board.h" +#include "amt630h.h" +#include "errno.h" +#include "timer.h" +#include "os_adapt.h" +#include "gpio.h" +#include "trace.h" +#include "i2c.h" +#include "i2c-gpio.h" + + +#ifdef ANALOG_I2C_SUPPORT + +struct i2c_gpio_private_data { + struct i2c_adapter adap; + struct i2c_algo_bit_data bit_data; + struct i2c_gpio_platform_data pdata; +}; + +/* Toggle SDA by changing the direction of the pin */ +static void i2c_gpio_setsda_dir(void *data, int state) +{ + struct i2c_gpio_platform_data *pdata = data; + + if (state) + gpio_direction_input(pdata->sda_pin); + else + gpio_direction_output(pdata->sda_pin, 0); +} + +/* + * Toggle SDA by changing the output value of the pin. This is only + * valid for pins configured as open drain (i.e. setting the value + * high effectively turns off the output driver.) + */ +static void i2c_gpio_setsda_val(void *data, int state) +{ + struct i2c_gpio_platform_data *pdata = data; + + gpio_direction_output(pdata->sda_pin, state); + + gpio_set_value(pdata->sda_pin, state); +} + +/* Toggle SCL by changing the direction of the pin. */ +static void i2c_gpio_setscl_dir(void *data, int state) +{ + struct i2c_gpio_platform_data *pdata = data; + + if (state) + gpio_direction_input(pdata->scl_pin); + else + gpio_direction_output(pdata->scl_pin, 0); +} + +/* + * Toggle SCL by changing the output value of the pin. This is used + * for pins that are configured as open drain and for output-only + * pins. The latter case will break the i2c protocol, but it will + * often work in practice. + */ +static void i2c_gpio_setscl_val(void *data, int state) +{ + struct i2c_gpio_platform_data *pdata = data; + + gpio_direction_output(pdata->scl_pin, state); + + gpio_set_value(pdata->scl_pin, state); +} + +static int i2c_gpio_getsda(void *data) +{ + struct i2c_gpio_platform_data *pdata = data; + + gpio_direction_input(pdata->sda_pin); + + return gpio_get_value(pdata->sda_pin); +} + +static int i2c_gpio_getscl(void *data) +{ + struct i2c_gpio_platform_data *pdata = data; + + gpio_direction_input(pdata->scl_pin); + + return gpio_get_value(pdata->scl_pin); +} + +/* --- setting states on the bus with the right timing: --------------- */ + +#define setsda(adap, val) adap->setsda(adap->data, val) +#define setscl(adap, val) adap->setscl(adap->data, val) +#define getsda(adap) adap->getsda(adap->data) +#define getscl(adap) adap->getscl(adap->data) + +static __INLINE void sdalo(struct i2c_algo_bit_data *adap) +{ + setsda(adap, 0); + udelay((adap->udelay + 1) / 2); +} + +static __INLINE void sdahi(struct i2c_algo_bit_data *adap) +{ + setsda(adap, 1); + udelay((adap->udelay + 1) / 2); +} + +static __INLINE void scllo(struct i2c_algo_bit_data *adap) +{ + setscl(adap, 0); + udelay(adap->udelay / 2); +} + +/* + * Raise scl line, and do checking for delays. This is necessary for slower + * devices. + */ +static int sclhi(struct i2c_algo_bit_data *adap) +{ + unsigned long start = 0; + + setscl(adap, 1); + + /* Not all adapters have scl sense line... */ + if (!adap->getscl) + goto done; +#if 0 + start = xTaskGetTickCount(); + while (!getscl(adap)) { + /* This hw knows how to read the clock line, so we wait + * until it actually gets high. This is safer as some + * chips may hold it low ("clock stretching") while they + * are processing data internally. + */ + if (xTaskGetTickCount() > start + adap->timeout) { + /* Test one last time, as we may have been preempted + * between last check and timeout test. + */ + if (getscl(adap)) + break; + return -ETIMEDOUT; + } + taskYIELD(); + } +#else + while (!getscl(adap)) { + udelay(1); + if (++start > adap->timeout) { + /* Test one last time, as we may have been preempted + * between last check and timeout test. + */ + if (getscl(adap)) + break; + return -ETIMEDOUT; + } + } +#endif +done: + udelay(adap->udelay); + return 0; +} + + +/* --- other auxiliary functions -------------------------------------- */ +static void i2c_start(struct i2c_algo_bit_data *adap) +{ + /* assert: scl, sda are high */ + setsda(adap, 0); + udelay(adap->udelay); + scllo(adap); +} + +static void i2c_repstart(struct i2c_algo_bit_data *adap) +{ + /* assert: scl is low */ + sdahi(adap); + sclhi(adap); + setsda(adap, 0); + udelay(adap->udelay); + scllo(adap); +} + + +static void i2c_stop(struct i2c_algo_bit_data *adap) +{ + /* assert: scl is low */ + sdalo(adap); + sclhi(adap); + setsda(adap, 1); + udelay(adap->udelay); +} + + + +/* send a byte without start cond., look for arbitration, + check ackn. from slave */ +/* returns: + * 1 if the device acknowledged + * 0 if the device did not ack + * -ETIMEDOUT if an error occurred (while raising the scl line) + */ +static int i2c_outb(struct i2c_adapter *i2c_adap, unsigned char c) +{ + int i; + int sb; + int ack; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + /* assert: scl is low */ + for (i = 7; i >= 0; i--) { + sb = (c >> i) & 1; + setsda(adap, sb); + udelay((adap->udelay + 1) / 2); + if (sclhi(adap) < 0) { /* timed out */ + TRACE_DEBUG("i2c_outb: 0x%02x, timeout at bit #%d\n", (int)c, i); + return -ETIMEDOUT; + } + /* FIXME do arbitration here: + * if (sb && !getsda(adap)) -> ouch! Get out of here. + * + * Report a unique code, so higher level code can retry + * the whole (combined) message and *NOT* issue STOP. + */ + scllo(adap); + } + sdahi(adap); //--- + //sdalo(adap); //+++ + if (sclhi(adap) < 0) { /* timeout */ + TRACE_DEBUG("i2c_outb: 0x%02x, timeout at ack\n", (int)c); + return -ETIMEDOUT; + } + + /* read ack: SDA should be pulled down by slave, or it may + * NAK (usually to report problems with the data we wrote). + */ + ack = !getsda(adap); /* ack: sda is pulled low -> success */ + TRACE_DEBUG("i2c_outb: 0x%02x %s\n", (int)c, ack ? "A" : "NA"); + + scllo(adap); + //sdalo(adap); //+++ + + return ack; + /* assert: scl is low (sda undef) */ +} + + +static int i2c_inb(struct i2c_adapter *i2c_adap) +{ + /* read byte via i2c port, without start/stop sequence */ + /* acknowledge is sent in i2c_read. */ + int i; + unsigned char indata = 0; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + /* assert: scl is low */ + sdahi(adap); //--- + for (i = 0; i < 8; i++) { + if (sclhi(adap) < 0) { /* timeout */ + TRACE_DEBUG("i2c_inb: timeout at bit #%d\n", 7 - i); + return -ETIMEDOUT; + } + indata *= 2; + if (getsda(adap)) + indata |= 0x01; + setscl(adap, 0); + udelay(i == 7 ? adap->udelay / 2 : adap->udelay); + } + /* assert: scl is low */ + return indata; +} + +/* try_address tries to contact a chip for a number of + * times before it gives up. + * return values: + * 1 chip answered + * 0 chip did not answer + * -x transmission error + */ +static int try_address(struct i2c_adapter *i2c_adap, + unsigned char addr, int retries) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + int i, ret = 0; + + for (i = 0; i <= retries; i++) { + ret = i2c_outb(i2c_adap, addr); + if (ret == 1 || i == retries) + break; + TRACE_DEBUG("emitting stop condition\n"); + i2c_stop(adap); + udelay(adap->udelay); +// taskYIELD(); + TRACE_DEBUG("emitting start condition\n"); + i2c_start(adap); + } + if (i && ret) + TRACE_DEBUG("Used %d tries to %s client at " + "0x%02x: %s\n", i + 1, + addr & 1 ? "read from" : "write to", addr >> 1, + ret == 1 ? "success" : "failed, timeout?"); + return ret; +} + +static int sendbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + const unsigned char *temp = msg->buf; + int count = msg->len; + unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; + int retval; + int wrcount = 0; + + while (count > 0) { + retval = i2c_outb(i2c_adap, *temp); + + /* OK/ACK; or ignored NAK */ + if ((retval > 0) || (nak_ok && (retval == 0))) { + count--; + temp++; + wrcount++; + + /* A slave NAKing the master means the slave didn't like + * something about the data it saw. For example, maybe + * the SMBus PEC was wrong. + */ + } else if (retval == 0) { + TRACE_ERROR("sendbytes: NAK bailout.\n"); + return -EIO; + + /* Timeout; or (someday) lost arbitration + * + * FIXME Lost ARB implies retrying the transaction from + * the first message, after the "winning" master issues + * its STOP. As a rule, upper layer code has no reason + * to know or care about this ... it is *NOT* an error. + */ + } else { + TRACE_ERROR("sendbytes: error %d\n", retval); + return retval; + } + } + return wrcount; +} + +static int acknak(struct i2c_adapter *i2c_adap, int is_ack) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + /* assert: sda is high */ + if (is_ack) /* send ack */ + setsda(adap, 0); + udelay((adap->udelay + 1) / 2); + if (sclhi(adap) < 0) { /* timeout */ + TRACE_ERROR("readbytes: ack/nak timeout\n"); + return -ETIMEDOUT; + } + scllo(adap); + return 0; +} + +static int readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + int inval; + int rdcount = 0; /* counts bytes read */ + unsigned char *temp = msg->buf; + int count = msg->len; + const unsigned flags = msg->flags; + + while (count > 0) { + inval = i2c_inb(i2c_adap); + if (inval >= 0) { + *temp = inval; + rdcount++; + } else { /* read timed out */ + break; + } + + temp++; + count--; + + /* Some SMBus transactions require that we receive the + transaction length as the first read byte. */ + if (rdcount == 1 && (flags & I2C_M_RECV_LEN)) { + if (inval <= 0 || inval > I2C_SMBUS_BLOCK_MAX) { + if (!(flags & I2C_M_NO_RD_ACK)) + acknak(i2c_adap, 0); + TRACE_ERROR("readbytes: invalid block length (%d)\n", inval); + return -EPROTO; + } + /* The original count value accounts for the extra + bytes, that is, either 1 for a regular transaction, + or 2 for a PEC transaction. */ + count += inval; + msg->len += inval; + } + + TRACE_DEBUG( "readbytes: 0x%02x %s\n", + inval, + (flags & I2C_M_NO_RD_ACK) + ? "(no ack/nak)" + : (count ? "A" : "NA")); + + if (!(flags & I2C_M_NO_RD_ACK)) { + inval = acknak(i2c_adap, count); + if (inval < 0) + return inval; + } + } + return rdcount; +} + +/* doAddress initiates the transfer by generating the start condition (in + * try_address) and transmits the address in the necessary format to handle + * reads, writes as well as 10bit-addresses. + * returns: + * 0 everything went okay, the chip ack'ed, or IGNORE_NAK flag was set + * -x an error occurred (like: -ENXIO if the device did not answer, or + * -ETIMEDOUT, for example if the lines are stuck...) + */ +static int bit_doAddress(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + unsigned short flags = msg->flags; + unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + unsigned char addr; + int ret, retries; + + retries = nak_ok ? 0 : i2c_adap->retries; + + if (flags & I2C_M_TEN) { + /* a ten bit address */ + addr = 0xf0 | ((msg->addr >> 7) & 0x06); + TRACE_DEBUG("addr0: %d\n", addr); + /* try extended address code...*/ + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) { + TRACE_ERROR("died at extended address code\n"); + return -ENXIO; + } + /* the remaining 8 bit address */ + ret = i2c_outb(i2c_adap, msg->addr & 0xff); + if ((ret != 1) && !nak_ok) { + /* the chip did not ack / xmission error occurred */ + TRACE_ERROR("died at 2nd address code\n"); + return -ENXIO; + } + if (flags & I2C_M_RD) { + TRACE_DEBUG("emitting repeated start condition\n"); + i2c_repstart(adap); + /* okay, now switch into reading mode */ + addr |= 0x01; + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) { + TRACE_ERROR("died at repeated address code\n"); + return -EIO; + } + } + } else { /* normal 7bit address */ + addr = msg->addr << 1; + if (flags & I2C_M_RD) + addr |= 1; + if (flags & I2C_M_REV_DIR_ADDR) + addr ^= 1; + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) + return -ENXIO; + } + + return 0; +} + +static int bit_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msgs[], int num) +{ + struct i2c_msg *pmsg; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + int i, ret; + unsigned short nak_ok; + + TRACE_DEBUG("emitting start condition\n"); + i2c_start(adap); + for (i = 0; i < num; i++) { + pmsg = &msgs[i]; + nak_ok = pmsg->flags & I2C_M_IGNORE_NAK; + if (!(pmsg->flags & I2C_M_NOSTART)) { + if (i) { + if (msgs[i - 1].flags & I2C_M_STOP) { + TRACE_DEBUG("emitting enforced stop/start condition\n"); + i2c_stop(adap); + i2c_start(adap); + } else { + TRACE_DEBUG("emitting repeated start condition\n"); + i2c_repstart(adap); + } + } + ret = bit_doAddress(i2c_adap, pmsg); + if ((ret != 0) && !nak_ok) { + TRACE_DEBUG("NAK from device addr 0x%02x msg #%d\n", msgs[i].addr, i); + goto bailout; + } + } + if (pmsg->flags & I2C_M_RD) { + /* read bytes into buffer*/ + ret = readbytes(i2c_adap, pmsg); + if (ret >= 1) + TRACE_DEBUG("read %d byte%s\n", ret, ret == 1 ? "" : "s"); + if (ret < pmsg->len) { + if (ret >= 0) + ret = -EIO; + goto bailout; + } + } else { + /* write bytes from buffer */ + ret = sendbytes(i2c_adap, pmsg); + if (ret >= 1) + TRACE_DEBUG("wrote %d byte%s\n", ret, ret == 1 ? "" : "s"); + if (ret < pmsg->len) { + if (ret >= 0) + ret = -EIO; + goto bailout; + } + } + } + ret = i; + +bailout: + TRACE_DEBUG("emitting stop condition\n"); + i2c_stop(adap); + + return ret; +} + +struct i2c_gpio_platform_data i2c_gpio[] = { + { + .devid = 0, + .sda_pin = I2C_GPIO0_SDA_PIN, + .scl_pin = I2C_GPIO0_SCL_PIN, + .udelay = 5, /* clk freq 500/udelay kHz */ + .timeout = configTICK_RATE_HZ / 10, /* 100ms */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 1, + } +}; + +const struct i2c_algorithm i2c_bit_algo = { + .master_xfer = bit_xfer, +}; + +int i2c_bit_add_bus(struct i2c_adapter *adap) +{ + int ret; + + /* register new adapter to i2c module... */ + adap->algo = &i2c_bit_algo; + adap->retries = 3; + + ret = i2c_add_adapter(adap); + if (ret < 0) + return ret; + + return 0; +} + +static int i2c_gpio_add_device(struct i2c_gpio_platform_data *pdevdata) +{ + struct i2c_gpio_private_data *priv; + struct i2c_gpio_platform_data *pdata; + struct i2c_algo_bit_data *bit_data; + struct i2c_adapter *adap; + int ret; + + priv = pvPortMalloc(sizeof(*priv)); + if (!priv) { + TRACE_ERROR("[%s] pvPortMalloc failed, devid:%d\n", __func__, pdevdata->devid); + return -ENOMEM; + } + memset(priv, 0, sizeof(*priv)); + + adap = &priv->adap; + bit_data = &priv->bit_data; + pdata = &priv->pdata; + + memcpy(pdata, pdevdata, sizeof(*pdata)); + gpio_request(pdata->sda_pin); + gpio_request(pdata->scl_pin); + + if (pdata->sda_is_open_drain) { + gpio_direction_output(pdata->sda_pin, 1); + bit_data->setsda = i2c_gpio_setsda_val; + } else { + gpio_direction_input(pdata->sda_pin); + bit_data->setsda = i2c_gpio_setsda_dir; + } + + if (pdata->scl_is_open_drain || pdata->scl_is_output_only) { + gpio_direction_output(pdata->scl_pin, 1); + bit_data->setscl = i2c_gpio_setscl_val; + } else { + gpio_direction_input(pdata->scl_pin); + bit_data->setscl = i2c_gpio_setscl_dir; + } + + if (!pdata->scl_is_output_only) + bit_data->getscl = i2c_gpio_getscl; + bit_data->getsda = i2c_gpio_getsda; + + if (pdata->udelay) + bit_data->udelay = pdata->udelay; + else if (pdata->scl_is_output_only) + bit_data->udelay = 50; /* 10 kHz */ + else + bit_data->udelay = 5; /* 100 kHz */ + + if (pdata->timeout) + bit_data->timeout = pdata->timeout; + else + bit_data->timeout = configTICK_RATE_HZ / 10; /* 100 ms */ + + bit_data->data = pdata; + + snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdata->devid); + + adap->algo_data = bit_data; + + ret = i2c_bit_add_bus(adap); + if (ret) { + TRACE_ERROR("[%s] i2c_bit_add_bus failed, devid:%d\n", __func__, pdata->devid); + return ret; + } + + TRACE_INFO("using pins %u (SDA) and %u (SCL%s)\n", + pdata->sda_pin, pdata->scl_pin, + pdata->scl_is_output_only + ? ", no clock stretching" : ""); + + return 0; +} + +void i2c_gpio_init(void) +{ + int i; + + for(i=0; i +#include "FreeRTOS.h" +#include "amt630h.h" +#include "board.h" +#include "timer.h" +#include "i2c.h" +#include "i2c-gpio.h" + + +#ifdef I2C_SUPPORT +#define MAX_I2C_DEVICE_NUM 4 + +static struct i2c_adapter *i2c_devs[MAX_I2C_DEVICE_NUM] = {NULL}; +static int i2c_devices_count = 0; + +int i2c_add_adapter(struct i2c_adapter *adap) +{ + if (i2c_devices_count >= MAX_I2C_DEVICE_NUM) + return -1; + + /* Set default timeout to 1 second if not already set */ + if (adap->timeout == 0) + adap->timeout = configTICK_RATE_HZ; + + i2c_devs[i2c_devices_count++] = adap; + + return 0; +} + +struct i2c_adapter *i2c_open(const char *i2cdev) +{ + struct i2c_adapter *adap; + int i; + + for (i = 0; i < i2c_devices_count; i++) { + adap = i2c_devs[i]; + if (!strcmp(adap->name, i2cdev)) { + adap->open_count++; + return adap; + } + } + + return NULL; +} + +int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + unsigned long orig_jiffies; + int ret, try; + + configASSERT(adap && msgs); + + /* Retry automatically on arbitration loss */ + orig_jiffies = get_timer(0); + for (ret = 0, try = 0; try <= adap->retries; try++) { + ret = adap->algo->master_xfer(adap, msgs, num); + if (ret != -EAGAIN) + break; + if (get_timer(orig_jiffies) > adap->timeout) + break; + } + + return ret; +} + +void i2c_init(void) +{ +#ifdef ANALOG_I2C_SUPPORT + i2c_gpio_init(); +#endif +} +#endif diff --git a/A58-STEPLDR/Src/i2c.h b/A58-STEPLDR/Src/i2c.h new file mode 100644 index 00000000..d07d9a66 --- /dev/null +++ b/A58-STEPLDR/Src/i2c.h @@ -0,0 +1,177 @@ +#ifndef _I2C_H +#define _I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +struct i2c_adapter; + +/** + * struct i2c_msg - an I2C transaction segment beginning with START + * @addr: Slave address, either seven or ten bits. When this is a ten + * bit address, I2C_M_TEN must be set in @flags and the adapter + * must support I2C_FUNC_10BIT_ADDR. + * @flags: I2C_M_RD is handled by all adapters. No other flags may be + * provided unless the adapter exported the relevant I2C_FUNC_* + * flags through i2c_check_functionality(). + * @len: Number of data bytes in @buf being read from or written to the + * I2C slave address. For read transactions where I2C_M_RECV_LEN + * is set, the caller guarantees that this buffer can hold up to + * 32 bytes in addition to the initial length byte sent by the + * slave (plus, if used, the SMBus PEC); and this value will be + * incremented by the number of block data bytes received. + * @buf: The buffer into which data is read, or from which it's written. + * + * An i2c_msg is the low level representation of one segment of an I2C + * transaction. It is visible to drivers in the @i2c_transfer() procedure, + * to userspace from i2c-dev, and to I2C adapter drivers through the + * @i2c_adapter.@master_xfer() method. + * + * Except when I2C "protocol mangling" is used, all I2C adapters implement + * the standard rules for I2C transactions. Each transaction begins with a + * START. That is followed by the slave address, and a bit encoding read + * versus write. Then follow all the data bytes, possibly including a byte + * with SMBus PEC. The transfer terminates with a NAK, or when all those + * bytes have been transferred and ACKed. If this is the last message in a + * group, it is followed by a STOP. Otherwise it is followed by the next + * @i2c_msg transaction segment, beginning with a (repeated) START. + * + * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then + * passing certain @flags may have changed those standard protocol behaviors. + * Those flags are only for use with broken/nonconforming slaves, and with + * adapters which are known to support the specific mangling options they + * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR). + */ +struct i2c_msg { + uint16_t addr; /* slave address */ + uint16_t flags; +#define I2C_M_RD 0x0001 /* read data, from slave to master */ + /* I2C_M_RD is guaranteed to be 0x0001! */ +#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */ +#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */ +#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_NOSTART */ +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + uint16_t len; /* msg length */ + uint8_t *buf; /* pointer to msg data */ +}; + +/* To determine what functionality is present */ + +#define I2C_FUNC_I2C 0x00000001 +#define I2C_FUNC_10BIT_ADDR 0x00000002 +#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_IGNORE_NAK etc. */ +#define I2C_FUNC_SMBUS_PEC 0x00000008 +#define I2C_FUNC_NOSTART 0x00000010 /* I2C_M_NOSTART */ +#define I2C_FUNC_SLAVE 0x00000020 +#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */ +#define I2C_FUNC_SMBUS_QUICK 0x00010000 +#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000 +#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000 +#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000 +#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000 +#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000 +#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000 +#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000 +#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000 +#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000 +#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */ +#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */ +#define I2C_FUNC_SMBUS_HOST_NOTIFY 0x10000000 + +#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \ + I2C_FUNC_SMBUS_WRITE_BYTE) +#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \ + I2C_FUNC_SMBUS_WRITE_BYTE_DATA) +#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \ + I2C_FUNC_SMBUS_WRITE_WORD_DATA) +#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \ + I2C_FUNC_SMBUS_WRITE_BLOCK_DATA) +#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \ + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK) + +#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \ + I2C_FUNC_SMBUS_BYTE | \ + I2C_FUNC_SMBUS_BYTE_DATA | \ + I2C_FUNC_SMBUS_WORD_DATA | \ + I2C_FUNC_SMBUS_PROC_CALL | \ + I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \ + I2C_FUNC_SMBUS_I2C_BLOCK | \ + I2C_FUNC_SMBUS_PEC) + +/* + * Data for SMBus Messages + */ +#define I2C_SMBUS_BLOCK_MAX 32 /* As specified in SMBus standard */ +union i2c_smbus_data { + uint8_t byte; + uint16_t word; + uint8_t block[I2C_SMBUS_BLOCK_MAX + 2]; /* block[0] is used for length */ + /* and one more for user-space compatibility */ +}; + +/* i2c_smbus_xfer read or write markers */ +#define I2C_SMBUS_READ 1 +#define I2C_SMBUS_WRITE 0 + +/* SMBus transaction types (size parameter in the above functions) + Note: these no longer correspond to the (arbitrary) PIIX4 internal codes! */ +#define I2C_SMBUS_QUICK 0 +#define I2C_SMBUS_BYTE 1 +#define I2C_SMBUS_BYTE_DATA 2 +#define I2C_SMBUS_WORD_DATA 3 +#define I2C_SMBUS_PROC_CALL 4 +#define I2C_SMBUS_BLOCK_DATA 5 +#define I2C_SMBUS_I2C_BLOCK_BROKEN 6 +#define I2C_SMBUS_BLOCK_PROC_CALL 7 /* SMBus 2.0 */ +#define I2C_SMBUS_I2C_BLOCK_DATA 8 + +/*flags for the client struct: */ +#define I2C_CLIENT_PEC 0x04 /* Use Packet Error Checking */ +#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */ + /* Must equal I2C_M_TEN below */ +#define I2C_CLIENT_SLAVE 0x20 /* we are the slave */ +#define I2C_CLIENT_HOST_NOTIFY 0x40 /* We want to use I2C host notify */ +#define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */ +#define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */ + /* Must match I2C_M_STOP|IGNORE_NAK */ + +struct i2c_algorithm { + /* master_xfer should return the number of messages successfully + processed, or a negative value on error */ + int (*master_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num); + int (*reg_slave)(struct i2c_adapter *adap); + int (*unreg_slave)(struct i2c_adapter *adap); +}; + +/* + * i2c_adapter is the structure used to identify a physical i2c bus along + * with the access algorithms necessary to access it. + */ +struct i2c_adapter { + const struct i2c_algorithm *algo; /* the algorithm to access the bus */ + void *algo_data; + void *dw_dev; + int retries; + int timeout; /* in jiffies */ + int open_count; + unsigned short flags; /* div., see below */ + unsigned short addr; /* chip address - NOTE: 7bit */ + char name[16]; +}; + +void i2c_init(void); +int i2c_add_adapter(struct i2c_adapter *adap); +struct i2c_adapter *i2c_open(const char *i2cdev); +void i2c_close(struct i2c_adapter *adap); +int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/A58-STEPLDR/Src/lcd.c b/A58-STEPLDR/Src/lcd.c new file mode 100644 index 00000000..a0c63465 --- /dev/null +++ b/A58-STEPLDR/Src/lcd.c @@ -0,0 +1,696 @@ +#include "amt630h.h" +#include "board.h" +#include "lcd.h" +#include "gpio.h" +#include "sysctl.h" +#include "timer.h" + +/* LCD timing */ +#define LCD_PARAM0 0x000 +#define LCD_PARAM1 0x004 +#define LCD_PARAM2 0x008 +#define LCD_PARAM3 0x00C +#define LCD_PARAM4 0x010 +#define LCD_PARAM5 0x014 +#define LCD_PARAM6 0x018 +#define LCD_PARAM7 0x01C +#define LCD_PARAM8 0x020 +#define LCD_PARAM9 0x024 +#define LCD_PARAM10 0x028 +#define LCD_PARAM11 0x02C +#define LCD_PARAM12 0x030 +#define LCD_PARAM13 0x034 +#define LCD_PARAM14 0x038 +#define LCD_PARAM15 0x03C +#define LCD_PARAM16 0x040 +#define LCD_PARAM17 0x044 +#define LCD_PARAM18 0x048 +#define LCD_PARAM19 0x04C +#define LCD_PARAM20 0x050 +#define LCD_PARAM21 0x054 +#define LCD_PARAM22 0x058 + +/* OSD */ +#define LCD_OSD0_PARAM0 0x05C +#define LCD_OSD0_PARAM1 0x060 +#define LCD_OSD0_PARAM2 0x064 +#define LCD_OSD0_PARAM3 0x068 +#define LCD_OSD0_PARAM4 0x06C +#define LCD_OSD0_PARAM5 0x070 +#define LCD_OSD1_PARAM0 0x074 +#define LCD_OSD1_PARAM1 0x078 +#define LCD_OSD1_PARAM2 0x07C +#define LCD_OSD1_PARAM3 0x080 +#define LCD_OSD1_PARAM4 0x084 +#define LCD_OSD1_PARAM5 0x088 +#define LCD_OSD01_PARAM 0x08C +#define LCD_OSD_COEF_SYNC 0x090 +#define LCD_OSD0_PARAM2_RD 0x280 +#define LCD_OSD0_PARAM3_RD 0x284 +#define LCD_OSD0_PARAM4_RD 0x288 +#define LCD_OSD1_PARAM2_RD 0x28C +#define LCD_OSD1_PARAM3_RD 0x290 +#define LCD_OSD1_PARAM4_RD 0x294 + +/* Dithering */ +#define LCD_DITHERING_CFG0 0x0BC +#define LCD_DITHERING_CFG1 0x0C0 +#define LCD_DITHERING_CFG2 0x0C4 +#define LCD_INTR_CLR 0x0C8 +#define LCD_STATUS_REG 0x0CC +#define LCD_R_BIT_ORDER 0x130 +#define LCD_G_BIT_ORDER 0x134 +#define LCD_B_BIT_ORDER 0x138 +#define LCD_GAMMA_REG 0x13c + +/* CPU screen & SRGB screen */ +#define LCD_SRGB_CFG 0x200 +#define LCD_CPU_SCR_SOFT_REG 0x0E0 +#define LCD_CPU_SCR_CTRL_REG 0x0E4 +#define LCD_ADR_CLR_DATA_REG0 0x0E8 +#define LCD_ADR_CLR_DATA_REG1 0x0EC +#define LCD_ADR_CLR_DATA_REG2 0x0F0 +#define LCD_ADR_CLR_DATA_REG3 0x0F4 +#define LCD_ADR_CLR_DATA_REG4 0x0F8 +#define LCD_ADR_CLR_DATA_REG5 0x0FC +#define LCD_ADR_CLR_DATA_REG6 0x100 +#define LCD_ADR_CLR_DATA_REG7 0x104 +#define LCD_ADR_CLR_DATA_REG8 0x108 +#define LCD_ADR_CLR_DATA_REG9 0x10C +#define LCD_ADR_CLR_DATA_REGA 0x110 +#define LCD_ADR_CLR_DATA_REGB 0x114 +#define LCD_ADR_CLR_DATA_REGC 0x118 +#define LCD_ADR_CLR_DATA_REGD 0x11C +#define LCD_ADR_CLR_DATA_REGE 0x120 +#define LCD_ADR_CLR_DATA_REGF 0x124 +#define LCD_CPU_SCREEN_STATUS 0x128 +#define LCD_OSD_CCM_REG0 0x208 +#define LCD_OSD_CCM_REG1 0x20C +#define LCD_OSD_CCM_REG2 0x210 +#define LCD_OSD_CCM_REG3 0x214 +#define LCD_OSD_CCM_REG4 0x218 +#define LCD_OSD_CCM_REG5 0x21C +#define LCD_CCM_EN_REG0 0x238 +#define LCD_CCM_EN_REG1 0x23C +#define LCD_CCM_EN_REG2 0x240 +#define LCD_CCM_EN_REG3 0x244 +#define LCD_CCM_EN_REG4 0x248 +#define LCD_CCM_EN_REG5 0x24C +#define LCD_CCM_EN_REG 0x250 +#define LCD_ITU_EAV_CODE_CFG 0x254 +#define LCD_ITU_SAV_CODE_CFG 0x258 +#define LCD_HLOCK_CFG_RG 0x25C + +static uint32_t fb_addr = 0; + +struct ark_lcd_timing +{ + uint32_t vs_start; + uint32_t hs_start; + uint32_t hd; //width + uint32_t vd; //height + uint32_t vbp; + uint32_t vfp; + uint32_t vsw; + uint32_t hbp; + uint32_t hfp; + uint32_t hsw; +}; + +static void ark_lcd_writel(uint32_t reg, uint32_t mask, uint8_t offset, uint32_t val) +{ + uint32_t tmp = readl(REGS_LCD_BASE+reg); + tmp &= (~(mask << offset)); + tmp |= (val << offset); + writel(tmp, REGS_LCD_BASE+reg); +} + +int ark_lcd_set_osd_sync(LCD_OSD_LAYER osd) +{ + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + if(osd == LCD_OSD0) + writel(readl(REGS_LCD_BASE+LCD_OSD_COEF_SYNC)|(1<<0), REGS_LCD_BASE+LCD_OSD_COEF_SYNC); + else if(osd == LCD_OSD1) + writel(readl(REGS_LCD_BASE+LCD_OSD_COEF_SYNC)|(1<<1), REGS_LCD_BASE+LCD_OSD_COEF_SYNC); + else if(osd == LCD_OSD_NUMS) + writel(readl(REGS_LCD_BASE+LCD_OSD_COEF_SYNC)|(3<<0), REGS_LCD_BASE+LCD_OSD_COEF_SYNC); + return 0; +} + +static int ark_lcd_set_osd_stride(LCD_OSD_LAYER osd, uint32_t width) +{ + uint32_t reg = LCD_OSD0_PARAM5 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + if(width > 0xFFF) { + return -1; + } + ark_lcd_writel(reg, 0xFFF, 0, width); + + return 0; +} + +int ark_lcd_get_osd_size(LCD_OSD_LAYER osd, uint32_t *width, uint32_t *height) +{ + uint32_t reg = LCD_OSD0_PARAM0 + osd*0x18; + uint32_t val; + + if(osd>= LCD_OSD_NUMS) { + return -1; + } + val = readl(REGS_LCD_BASE+reg); + *width = (val >> 6) & 0xFFF; + *height = (val >> 18) & 0xFFF; + + return 0; +} + + +int ark_lcd_set_osd_size(LCD_OSD_LAYER osd, uint32_t width, uint32_t height) +{ + uint32_t reg = LCD_OSD0_PARAM0 + osd*0x18; + + if(osd>= LCD_OSD_NUMS) { + return -1; + } + width &= 0xFFF; + height &= 0xFFF; + ark_lcd_writel(reg, 0xFFFFFF, 6, (height<<12)|width); + ark_lcd_set_osd_stride(osd, width); + + return 0; +} + +int ark_lcd_set_osd_format(LCD_OSD_LAYER osd, LCD_OSD_FORMAT format) +{ + uint32_t reg = LCD_OSD0_PARAM0 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + if(format >= LCD_OSD_FORAMT_NUMS) { + return -1; + } + ark_lcd_writel(reg, 0x7, 3, format); + + return 0; +} + +int ark_lcd_osd_enable(LCD_OSD_LAYER osd, uint8_t enable) +{ + uint32_t reg = LCD_OSD0_PARAM0 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + ark_lcd_writel(reg, 0x1, 1, (enable?1:0)); + + return 0; +} + +int ark_lcd_osd_coeff_enable(LCD_OSD_LAYER osd, uint8_t enable) +{ + uint32_t reg = LCD_OSD0_PARAM0 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + ark_lcd_writel(reg, 0x1, 0, (enable?1:0)); + + return 0; +} + +int ark_lcd_osd_set_coeff(LCD_OSD_LAYER osd, uint32_t value) +{ + uint32_t reg = LCD_OSD0_PARAM1 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + ark_lcd_writel(reg, 0xFF, 24, value); + + return 0; +} + +int ark_lcd_set_osd_possition(LCD_OSD_LAYER osd, uint32_t h, uint32_t v) +{ + uint32_t reg = LCD_OSD0_PARAM1 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + if((v > 0xFFF) || (h > 0xFFF)) { + return -1; + } + ark_lcd_writel(reg, 0xFFFFFF, 0, ((v<<12)|h)); + + return 0; +} + +int ark_lcd_get_osd_yaddr(LCD_OSD_LAYER osd, uint32_t *yaddr) +{ + uint32_t reg = LCD_OSD0_PARAM2 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + *yaddr = readl(REGS_LCD_BASE+reg); + + return 0; +} + +int ark_lcd_set_osd_yaddr(LCD_OSD_LAYER osd, uint32_t yaddr) +{ + uint32_t reg = LCD_OSD0_PARAM2 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + writel(yaddr, REGS_LCD_BASE+reg); + + return 0; +} + +int ark_lcd_set_osd_uaddr(LCD_OSD_LAYER osd, uint32_t uaddr) +{ + uint32_t reg = LCD_OSD0_PARAM3 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + writel(uaddr, REGS_LCD_BASE+reg); + + return 0; +} + +int ark_lcd_set_osd_vaddr(LCD_OSD_LAYER osd, uint32_t vaddr) +{ + uint32_t reg = LCD_OSD0_PARAM4 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + writel(vaddr, REGS_LCD_BASE+reg); + + return 0; +} + +int ark_lcd_set_osd_mult_coef(LCD_OSD_LAYER osd, uint32_t value) +{ + uint32_t reg = LCD_OSD0_PARAM5 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + if(value > 0x7F) { + return -1; + } + ark_lcd_writel(reg, 0x7F, 24, value); + + return 0; +} + +int ark_lcd_set_osd_h_offset(LCD_OSD_LAYER osd, uint32_t offset) +{ + uint32_t reg = LCD_OSD0_PARAM5 + osd*0x18; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + if(offset > 0xFFF) { + return -1; + } + ark_lcd_writel(reg, 0xFFF, 12, offset); + + return 0; +} + +int ark_lcd_set_osd_yuv420_mode(LCD_OSD_LAYER osd, LCD_OSD_YUV420_MODE mode) +{ + uint32_t reg = LCD_OSD01_PARAM; + + if(osd >= LCD_OSD_NUMS) { + return -1; + } + + if(mode > LCD_OSD_Y_UV420) { + return -1; + } + + if (osd == LCD_OSD0) + ark_lcd_writel(reg, 0x1, 12, mode); + else + ark_lcd_writel(reg, 0x1, 14, mode); + + return 0; +} + + +int ark_lcd_enable(uint8_t enable) +{ + ark_lcd_writel(LCD_PARAM0, 0x01, 0, (enable?1:0)); + + return 0; +} + +static int ark_lcd_timing_init(struct ark_lcd_timing *timing) +{ + uint32_t VS_START, HS_START, HD, VD; + uint32_t VBP, VFP, VSW, TV; + uint32_t HBP, HFP, HSW, TH; + uint32_t lcd_param0, lcd_param1, lcd_param2, lcd_param3 ; + uint32_t lcd_param4, lcd_param5, lcd_param6, lcd_param7 ; + uint32_t lcd_param8, lcd_param9, lcd_param10, lcd_param11 ; + uint32_t lcd_param12, lcd_param13, lcd_param14, lcd_param15 ; + uint32_t lcd_param16, lcd_param17; + uint8_t stop_lcd = 0 ; + + VS_START = timing->vs_start; + HS_START = timing->hs_start; + HD = timing->hd; + VD = timing->vd; + VBP = timing->vbp; + VFP = timing->vfp; + VSW = timing->vsw; + TV =(VS_START+VSW+VBP+VD+VFP); + HBP = timing->hbp; + HFP = timing->hfp; + HSW = timing->hsw; + TH = (HS_START+HSW+HBP+HD+HFP); +#define lcd_enable 0 // 1 +#define screen_width HD +#define rgb_pad_mode LCD_WIRING_MODE +#define direct_enable 0 +#define mem_lcd_enable 0 +#define range_coeff_y 0 +#define range_coeff_uv 0 +#define lcd_done_intr_enable 1 +#define dac_for_video 0 +#define dac_for_cvbs 0 + +#define lcd_interlace_flag 0 +#define screen_type 1 //pRGB_i 0 pRGB_p 1 sRGB_p 2 ITU656 3 +#define VSW1_enable 0 +#define LcdVComp 0 +#define itu_pal_ntsc 0 +#define hsync_ivs 1 +#define vsync_ivs 1 +#define lcd_ac_ivs 0 +#define test_on_flag 0 + +#define back_color (0x00<<16)|(0x00<<8)|(0x00) +#define DEN_h_rise (HFP+HSW+HBP) +#define DEN_h_fall (HFP+HSW+HBP+HD)//(20+800*1) +#define DEN0_v_rise (VFP+VSW+VBP) +#define DEN0_v_fall (VFP+VSW+VBP+VD) +#define DEN1_v_rise (VFP+VSW+VBP) +#define DEN1_v_fall (VFP+VSW+VBP+VD) + +// ֡Ƶ = LCDʱ/(CPL * LPS) +// ÿʱڸ +#define CPL (TH) // clock cycles per line max 4096 ; from register timing2 16 +#define LPS (TV) // Lines per screen value ; from register timing1 0 + +#define HSW_rise (HFP) +#define HSW_fall (HFP+HSW) + +#define VSW0_v_rise (VFP) // Vertical sync width value ; from register timing1 10 +#define VSW0_v_fall (VFP+VSW) // Vertical sync width value ; from register timing1 10 + +#define VSW0_h_rise (HFP) +#define VSW0_h_fall (HFP+HSW) + +#define VSW1_v_rise (VFP) // Vertical sync width value ; from register timing1 10 +#define VSW1_v_fall (VFP+VSW) // Vertical sync width value ; from register timing1 10 + +#define VSW1_h_rise (HFP) +#define VSW1_h_fall (HFP+HSW) + + writel(0, REGS_LCD_BASE+LCD_PARAM0); + lcd_param0 = + lcd_enable | + (screen_width<<1) | + (rgb_pad_mode<<13) | + (direct_enable<<16) | + (mem_lcd_enable<<17)| + (range_coeff_y<<18) | + (range_coeff_uv<<22)| + (lcd_done_intr_enable<<26)| + (dac_for_video<<27) | + (dac_for_cvbs<<28) | + (1<<30) | + (stop_lcd<<31); + + lcd_param1 = + (lcd_interlace_flag<<0) | + (screen_type<<1) | + (VSW1_enable<<13) | + (LcdVComp<<14) | + (itu_pal_ntsc<<15) | + (hsync_ivs<<17) | + (vsync_ivs<<18) | + (lcd_ac_ivs<<19) | + (1<<21) | + (1<<23) | + (test_on_flag<<31); + + lcd_param2 = + (back_color<<0) | + (1<<24) | + (1<<25); + + lcd_param3 = + (DEN_h_rise<<0) | + (DEN_h_fall<<12) ; + + lcd_param4 = + (DEN0_v_rise<<0) | + (DEN0_v_fall<<12) ; + + lcd_param5 = + (DEN1_v_rise<<0) | + (DEN1_v_fall<<12 ) ; + + lcd_param6 = + (CPL<<0) | // clock cycles per line max 4096 ; from register timing2 16 + (LPS<<12) ; // Lines per screen value ; from register timing1 0 + + lcd_param7 = + (HSW_rise<<0)| + (HSW_fall<<12) ; + + lcd_param8 = + (VSW0_v_rise<<0)| // Vertical sync width value ; from register timing1 10 + (VSW0_v_fall<<12) ; // Vertical sync width value ; from register timing1 10 + + lcd_param9 = + (VSW0_h_rise <<0 )| + (VSW0_h_fall <<12 ) ; + + lcd_param10 = + (VSW1_v_rise<<0)| + (VSW1_v_fall<<12) ; + + lcd_param11 = + (VSW1_h_rise<<0)| + (VSW1_h_fall<<12) ; + + lcd_param12 = 66 | (129<<9) | (25<<18); + lcd_param13 = 38 | (74<<9) | (112<<18); + lcd_param14 = 112 | (94<<9) | (18<<18); + + lcd_param15 = 256 | (0<<9) | (351<<18); + lcd_param16 = 256 | (86<<9) | (179<<18); + lcd_param17 = 256 | (443<<10) | (0<<19); + + writel(lcd_param1, REGS_LCD_BASE+LCD_PARAM1); + writel(lcd_param2, REGS_LCD_BASE+LCD_PARAM2); + writel(lcd_param3, REGS_LCD_BASE+LCD_PARAM3); + writel(lcd_param4, REGS_LCD_BASE+LCD_PARAM4); + writel(lcd_param5, REGS_LCD_BASE+LCD_PARAM5); + writel(lcd_param6, REGS_LCD_BASE+LCD_PARAM6); + writel(lcd_param7, REGS_LCD_BASE+LCD_PARAM7); + writel(lcd_param8, REGS_LCD_BASE+LCD_PARAM8); + writel(lcd_param9, REGS_LCD_BASE+LCD_PARAM9); + writel(lcd_param10, REGS_LCD_BASE+LCD_PARAM10); + writel(lcd_param11, REGS_LCD_BASE+LCD_PARAM11); + writel(lcd_param12, REGS_LCD_BASE+LCD_PARAM12); + writel(lcd_param13, REGS_LCD_BASE+LCD_PARAM13); + writel(lcd_param14, REGS_LCD_BASE+LCD_PARAM14); + writel(lcd_param15, REGS_LCD_BASE+LCD_PARAM15); + writel(lcd_param16, REGS_LCD_BASE+LCD_PARAM16); + writel(lcd_param17, REGS_LCD_BASE+LCD_PARAM17); + writel(lcd_param0, REGS_LCD_BASE+LCD_PARAM0); + +#if LCD_WIRING_BIT_ORDER == LCD_WIRING_BIT_ORDER_LSB + writel((0<<21|1<<18|2<<15|3<<12|4<<9|5<<6|6<<3|7<<0), REGS_LCD_BASE+LCD_R_BIT_ORDER); + writel((0<<21|1<<18|2<<15|3<<12|4<<9|5<<6|6<<3|7<<0), REGS_LCD_BASE+LCD_G_BIT_ORDER); + writel((0<<21|1<<18|2<<15|3<<12|4<<9|5<<6|6<<3|7<<0), REGS_LCD_BASE+LCD_B_BIT_ORDER); +#elif LCD_WIRING_BIT_ORDER == LCD_WIRING_BIT_ORDER_MSB + writel((7<<21|6<<18|5<<15|4<<12|3<<9|2<<6|1<<3|0<<0), REGS_LCD_BASE+LCD_R_BIT_ORDER); + writel((7<<21|6<<18|5<<15|4<<12|3<<9|2<<6|1<<3|0<<0), REGS_LCD_BASE+LCD_G_BIT_ORDER); + writel((7<<21|6<<18|5<<15|4<<12|3<<9|2<<6|1<<3|0<<0), REGS_LCD_BASE+LCD_B_BIT_ORDER); +#endif + + return 0; +} + +static int ark_lcd_hw_init() +{ + uint32_t HD, VD; + + HD = LCD_WIDTH; + VD = LCD_HEIGHT; + +#if LCD_H_FLIP + uint8_t osd_0_hflip = 1; + uint8_t osd_1_hflip = 1; + uint8_t osd_0_uvfirst = 1; +#else + uint8_t osd_0_hflip = 0; + uint8_t osd_1_hflip = 0; + uint8_t osd_0_uvfirst = 0; +#endif +#if LCD_V_FLIP + uint8_t osd_0_vflip = 1; + uint8_t osd_1_vflip = 1; +#else + uint8_t osd_0_vflip = 0; + uint8_t osd_1_vflip = 0; +#endif + uint8_t osd_0_yuv420mode = 1; + //uint8_t osd_0_yuv422mode = 0; + uint32_t osd_01_param = + //osd_0_yuv422mode<<20| + osd_0_hflip<<16| + osd_0_vflip<<17| + osd_1_hflip<<18| + osd_1_vflip<<19| + osd_0_yuv420mode<<12| + osd_0_uvfirst<<13; + writel(osd_01_param, REGS_LCD_BASE+LCD_OSD01_PARAM); + //osd0 init + ark_lcd_set_osd_size(LCD_OSD0, HD, VD); + ark_lcd_set_osd_format(LCD_OSD0, LCD_OSD_FORAMT_YUV420); + ark_lcd_set_osd_possition(LCD_OSD0, 0, 0); + ark_lcd_set_osd_yaddr(LCD_OSD0, fb_addr); + ark_lcd_set_osd_uaddr(LCD_OSD0, fb_addr + HD * VD); + ark_lcd_set_osd_vaddr(LCD_OSD0, fb_addr + HD * VD); + ark_lcd_set_osd_h_offset(LCD_OSD0, 0); + ark_lcd_set_osd_mult_coef(LCD_OSD0, 64); + ark_lcd_osd_enable(LCD_OSD0, 0); + ark_lcd_set_osd_sync(LCD_OSD0); + + //osd1 init + ark_lcd_set_osd_size(LCD_OSD1, HD, VD); +#if LCD_BPP == 32 + ark_lcd_set_osd_format(LCD_OSD1, LCD_OSD_FORAMT_ARGB888); + ark_lcd_osd_coeff_enable(LCD_OSD1, 0); +#elif LCD_BPP == 16 + ark_lcd_set_osd_format(LCD_OSD1, LCD_OSD_FORAMT_RGB565); + ark_lcd_osd_coeff_enable(LCD_OSD1, 1); + ark_lcd_osd_set_coeff(LCD_OSD1, 255); +#endif + ark_lcd_set_osd_possition(LCD_OSD1, 0, 0); + ark_lcd_set_osd_h_offset(LCD_OSD1, 0); + ark_lcd_set_osd_mult_coef(LCD_OSD1, 64); + ark_lcd_set_osd_yaddr(LCD_OSD1, fb_addr); + ark_lcd_osd_enable(LCD_OSD1, 0); + ark_lcd_set_osd_sync(LCD_OSD1); + + ark_lcd_enable(1); + + return 0; +} + +#define LCD_SRC_FREQ 396000000//498000000 +static int ark_lcd_clk_init(uint32_t freq) +{ + int div; + + if (freq > 16000000) { + vSysctlConfigure(SYS_VOU_CLK_CFG, 0, 3, 0); + div = DIV_ROUND_UP(LCD_SRC_FREQ, freq); + } else if (freq >= 14000000) { //14-16MH配置为16MHZ + vSysctlConfigure(SYS_VOU_CLK_CFG, 0, 3, 0); + div = DIV_ROUND_UP(LCD_SRC_FREQ, 16000000); + } else { + vSysctlConfigure(SYS_VOU_CLK_CFG, 0, 3, 2); + div = DIV_ROUND_UP(24000000, freq); + } + + vSysctlConfigure(SYS_VOU_CLK_CFG, 3, 0x1f, div - 1); + + return 0; +} + + +#if LCD_INTERFACE_TYPE == LCD_INTERFACE_LVDS +static void lvds_screen_reset(void) +{ + gpio_direction_output(LVDS_SCREEN_RST_GPIO, 0); + udelay(100); + gpio_direction_output(LVDS_SCREEN_RST_GPIO, 1); + mdelay(20); +} +#endif + +int lcd_init(void) +{ + struct ark_lcd_timing timing; + int ret = 0; + + /* lcd pad select */ +#if LCD_INTERFACE_TYPE == LCD_INTERFACE_TTL + vSysctlConfigure(SYS_PAD_CTRL04, 0, 0xffffffff, 0x55555555); + vSysctlConfigure(SYS_PAD_CTRL05, 0, 0xffffff, 0x555555); +#elif LCD_INTERFACE_TYPE == LCD_INTERFACE_LVDS + vSysctlConfigure(SYS_PAD_CTRL04, 0, 0xfffff, 0xaaaaa); +#endif + +#if LCD_INTERFACE_TYPE == LCD_INTERFACE_MIPI + mipi_init(); +#endif + + /* lcd timing init */ + timing.vs_start = 0; + timing.hs_start = 0; + timing.hd = LCD_WIDTH; + timing.vd = LCD_HEIGHT; + timing.vbp = LCD_TIMING_VBP; + timing.vfp = LCD_TIMING_VFP; + timing.vsw = LCD_TIMING_VSW; + timing.hbp = LCD_TIMING_HBP; + timing.hfp = LCD_TIMING_HFP; + timing.hsw = LCD_TIMING_HSW; + ark_lcd_clk_init(LCD_CLK_FREQ); + ark_lcd_timing_init(&timing); + ark_lcd_hw_init(); + +#if LCD_INTERFACE_TYPE == LCD_INTERFACE_LVDS + mdelay(2); + uint32_t lvds_cfg = 0xe0ec; +#if LVDS_PANEL_FORMAT == LVDS_PANEL_FORMAT_TI + lvds_cfg |= (1 << 16); +#endif +#if LVDS_PANEL_DATA == LVDS_PANEL_DATA_8BIT + lvds_cfg &= ~(1 << 15); + lvds_cfg |= (1 << 4) | 1; +#endif + writel(lvds_cfg, REGS_SYSCTL_BASE + SYS_ANA3_CFG); + lvds_screen_reset(); +#endif + + return ret; +} diff --git a/A58-STEPLDR/Src/lcd.h b/A58-STEPLDR/Src/lcd.h new file mode 100644 index 00000000..1cf2fad2 --- /dev/null +++ b/A58-STEPLDR/Src/lcd.h @@ -0,0 +1,65 @@ +/* + * ark_lcd.h + * + */ + +#ifndef _LCD_H +#define _LCD_H + +typedef enum { + LCD_OSD0 = 0, + LCD_OSD1, + LCD_OSD_NUMS, +}LCD_OSD_LAYER; + +typedef enum { + LCD_OSD_FORAMT_YUV420 = 0, + LCD_OSD_FORAMT_ARGB888, + LCD_OSD_FORAMT_RGB565, + LCD_OSD_FORAMT_RGB454, + LCD_OSD_FORAMT_NUMS, +}LCD_OSD_FORMAT; + +typedef enum { + LCD_OSD_Y_U_V420 = 0, + LCD_OSD_Y_UV420, +}LCD_OSD_YUV420_MODE; + +#define LCD_UI_LAYER LCD_OSD1 + + +/* osd layer set func */ +/************************************************************/ +int ark_lcd_set_osd_size(LCD_OSD_LAYER osd, uint32_t width, uint32_t height); +int ark_lcd_set_osd_format(LCD_OSD_LAYER osd, LCD_OSD_FORMAT format); +int ark_lcd_set_osd_yaddr(LCD_OSD_LAYER osd, uint32_t yaddr); +int ark_lcd_set_osd_uaddr(LCD_OSD_LAYER osd, uint32_t yaddr); +int ark_lcd_set_osd_vaddr(LCD_OSD_LAYER osd, uint32_t yaddr); +int ark_lcd_osd_enable(LCD_OSD_LAYER osd, uint8_t enable); + +/* Interface with default argument value, may be you need them. If you not sure, ingore them */ +int ark_lcd_set_osd_possition(LCD_OSD_LAYER osd, uint32_t h, uint32_t v); +int ark_lcd_set_osd_h_offset(LCD_OSD_LAYER osd, uint32_t offset); +int ark_lcd_osd_coeff_enable(LCD_OSD_LAYER osd, uint8_t enable); +int ark_lcd_osd_set_coeff(LCD_OSD_LAYER osd, uint32_t value); +int ark_lcd_set_osd_mult_coef(LCD_OSD_LAYER osd, uint32_t value); +int ark_lcd_set_osd_yuv420_mode(LCD_OSD_LAYER osd, LCD_OSD_YUV420_MODE mode); + +/* after calling the osd layer set func, you should call */ +/* this function to flush the parameters for atom option */ +int ark_lcd_set_osd_sync(LCD_OSD_LAYER osd); + +/************************************************************/ + +int ark_lcd_get_osd_size(LCD_OSD_LAYER osd, uint32_t *width, uint32_t *height); +int ark_lcd_get_osd_format(LCD_OSD_LAYER osd, LCD_OSD_FORMAT *format); +int ark_lcd_get_osd_yaddr(LCD_OSD_LAYER osd, uint32_t *yaddr); +uint32_t ark_lcd_get_virt_addr(void); + +int ark_lcd_enable(uint8_t enable); +int ark_lcd_wait_for_vsync(void); + +int lcd_init(void); +void lcd_uninit(void); + +#endif diff --git a/A58-STEPLDR/Src/mipi.c b/A58-STEPLDR/Src/mipi.c new file mode 100644 index 00000000..afe5f72e --- /dev/null +++ b/A58-STEPLDR/Src/mipi.c @@ -0,0 +1,346 @@ +#include "amt630h.h" +#include "board.h" +#include "sysctl.h" +#include "timer.h" +#include "uart.h" + +#if LCD_INTERFACE_TYPE == LCD_INTERFACE_MIPI +/* Global macro defination */ +#define MIPI_WTIRE_DATA 0x70 +#define MIPI_WTIRE_COMMAND 0x6c + +#define ARK_MIPI_WRITEL(reg, val) writel(val, REGS_MIPI_BASE + reg); udelay(200) +#define ARK_MIPI_READL(reg) readl(REGS_MIPI_BASE + reg) + +/* Mipi panel parameters */ +#define LPDT_LPK 0x39 //1cmd + >=2data +#define LPDT_SPK 0x15 //1cmd + 1data. +#define NORM_LPK 0x05 //1cmd + +#define MIPI_WIDTH LCD_WIDTH +#define MIPI_HEIGHT LCD_HEIGHT +#define MIPI_VBP LCD_TIMING_VBP +#define MIPI_VFP LCD_TIMING_VFP +#define MIPI_VSW LCD_TIMING_VSW +#define MIPI_HBP LCD_TIMING_HBP +#define MIPI_HFP LCD_TIMING_HFP +#define MIPI_HSW LCD_TIMING_HSW +#define MIPI_SPEED 460000000 + +#define MIPI_LANE 4 //1-4LANE +#define DISPLAY_MODE 0 //0: nornal mode; 1: test colour bar mode. +#define MIPI_NP_POLARITY_INVERSE 0 //0: clk and data NP polarity normal; 1:clk and data NP polarity inverse. +//#define MIPI_RESET_GPIO 73 +/* End of mipi panel parameters */ + +#define MIPI_SEND_DATA(arg...) do { \ + uint8_t buf[] = {arg}; \ + mipi_write_data(buf, sizeof(buf)); \ + mdelay(2); \ + } while (0) + +static void mipi_set_speed(uint32_t speed) +{ + speed = speed / 1000000; + + if ((speed >= 200) && (speed <= 219)) + { + ARK_MIPI_WRITEL(0xb8, 0x06); + } + else if((speed >= 220) && (speed <= 239)) + { + ARK_MIPI_WRITEL(0xb8, 0x26); + } + else if((speed >= 240) && (speed <= 249)) + { + ARK_MIPI_WRITEL(0xb8, 0x46); + } + else if((speed >= 250) && (speed <= 269)) + { + ARK_MIPI_WRITEL(0xb8, 0x08); + } + else if((speed >= 270) && (speed <= 299)) + { + ARK_MIPI_WRITEL(0xb8, 0x28); + } + else if((speed >= 300) && (speed <= 329)) + { + ARK_MIPI_WRITEL(0xb8, 0x0a); + } + else if((speed >= 330) && (speed <= 359)) + { + ARK_MIPI_WRITEL(0xb8, 0x2a); + } + else if((speed >= 260) && (speed <= 399)) + { + ARK_MIPI_WRITEL(0xb8, 0x4a); + } + else if((speed >= 400) && (speed <= 449)) + { + ARK_MIPI_WRITEL(0xb8, 0x0c); + } + else if((speed >= 450) && (speed <= 499)) + { + ARK_MIPI_WRITEL(0xb8, 0x2c); + } + else if((speed >= 500) && (speed <= 549)) + { + ARK_MIPI_WRITEL(0xb8, 0x0e); + } + else if((speed >= 550) && (speed <= 599)) + { + ARK_MIPI_WRITEL(0xb8, 0x2e); + } + else if((speed >= 600) && (speed <= 649)) + { + ARK_MIPI_WRITEL(0xb8, 0x10); + } + else if((speed >= 650) && (speed <= 699)) + { + ARK_MIPI_WRITEL(0xb8, 0x30); + } + else if((speed >= 700) && (speed <= 749)) + { + ARK_MIPI_WRITEL(0xb8, 0x12); + } + else if((speed >= 750) && (speed <= 799)) + { + ARK_MIPI_WRITEL(0xb8, 0x32); + } + else if((speed >= 800) && (speed <= 849)) + { + ARK_MIPI_WRITEL(0xb8, 0x52); + } + else if((speed >= 850) && (speed <= 899)) + { + ARK_MIPI_WRITEL(0xb8, 0x72); + } + else if((speed >= 900) && (speed <= 949)) + { + ARK_MIPI_WRITEL(0xb8, 0x14); + } + else if((speed >= 950) && (speed <= 1000)) + { + ARK_MIPI_WRITEL(0xb8, 0x34); + } + else + { + ARK_MIPI_WRITEL(0xb8, 0x2c); + } +} + +static int mipi_write_data(const uint8_t *buffer, int length) +{ + uint32_t value = 0; + int mult = length / 4; + int left = length % 4; + int i = 0; + + if (!buffer || (length <= 0)) + { + if (!buffer) + SendUartString("mipi_write_data buffer NULL\n"); + if (length <= 0) + SendUartString("mipi_write_data data length invalid\n"); + return -1; + } + + if (length == 1) //only 1cmd. + { + ARK_MIPI_WRITEL(MIPI_WTIRE_COMMAND, (buffer[0]<<8) | NORM_LPK); + } + else if (length == 2) //1cmd + 1data. + { + ARK_MIPI_WRITEL(MIPI_WTIRE_DATA, (buffer[1]<<8)|buffer[0]); + ARK_MIPI_WRITEL(MIPI_WTIRE_COMMAND, (length<<8) | LPDT_SPK); + } + else //1cmd + >=2data. + { + for (i=0; i YES + ( 0 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* SRAM address (after remap) 0x0030_0000 */ + pTB[0x003] = (0x003 << 20)| // Physical Address + // ( 1 << 12)| // TEX[0] + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => YES + ( 0 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* DDRAM address (after remap) 0x2000_0000 */ + for(addr = 0x200; addr < 0x240; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 1 << 18)| // 16MB Supersection + ( 3 << 10)| // Access in supervisor mode (AP) + ( 1 << 12)| // TEX[0] + ( 0 << 5)| // Domain 0x0, Supersection only support domain 0 + ( 0 << 4)| // (XN) + ( 1 << 3)| // C bit : cachable => YES + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* DDRAM non-cache address (after remap) 0x3000_0000 */ + for(addr = 0x300; addr < 0x340; addr++) + pTB[addr] = ((addr - 0x100) << 20)| // Physical Address + ( 1 << 18)| // 16MB Supersection + ( 3 << 10)| // Access in supervisor mode (AP) + ( 1 << 12)| // TEX[0] + ( 0 << 5)| // Domain 0x0, Supersection only support domain 0 + ( 0 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => YES + ( 0 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + // periph address 0x60000000 ~ 0x80000000 + for(addr = 0x600; addr < 0x800; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + CP15_WriteTTB((unsigned int)pTB); + /* Program the domain access register */ + CP15_WriteDomainAccessControl(0xC0000003); // only domain 0 & 15: access are not checked +} + +void MMU_Init(void) +{ + if(CP15_IsIcacheEnabled()) + CP15_DisableIcache(); + if(CP15_IsDcacheEnabled()) + CP15_DisableDcache(); + + if(CP15_IsMMUEnabled()) + CP15_DisableMMU(); + + MMU_Initialize((unsigned int*)_MMUTT_STARTADDRESS); + + CP15_EnableMMU(); + CP15_EnableIcache(); + CP15_EnableDcache(); +} diff --git a/A58-STEPLDR/Src/mmu.h b/A58-STEPLDR/Src/mmu.h new file mode 100644 index 00000000..230c45ba --- /dev/null +++ b/A58-STEPLDR/Src/mmu.h @@ -0,0 +1,21 @@ +#ifndef _MMU_ +#define _MMU_ +#include "cp15.h" +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void MMU_Init(void); +extern void dma_flush_range(unsigned int ulStart, unsigned int ulEnd); +extern void dma_inv_range (unsigned int ulStart, unsigned int ulEnd); +extern void dma_clean_range(unsigned int ulStart, unsigned int ulEnd); +extern unsigned int vaddr_to_page_addr (unsigned int addr); +extern unsigned int page_addr_to_vaddr (unsigned int addr); + + + +#endif /* #ifndef _MMU_ */ + diff --git a/A58-STEPLDR/Src/os_adapt.c b/A58-STEPLDR/Src/os_adapt.c new file mode 100644 index 00000000..e1bc8f0b --- /dev/null +++ b/A58-STEPLDR/Src/os_adapt.c @@ -0,0 +1,11 @@ +#include "os_adapt.h" + +void *malloc(size_t size) +{ + return pvPortMalloc(size); +} + +void free(void *ptr) +{ + vPortFree(ptr); +} diff --git a/A58-STEPLDR/Src/os_adapt.h b/A58-STEPLDR/Src/os_adapt.h new file mode 100644 index 00000000..65c13457 --- /dev/null +++ b/A58-STEPLDR/Src/os_adapt.h @@ -0,0 +1,378 @@ +#ifndef _OS_ADAPT_H +#define _OS_ADAPT_H + +#include +#include "FreeRTOS.h" +#include "list.h" +#include "typedef.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define __INLINE inline + +#define PAGE_SIZE 4096 +#define ARCH_DMA_MINALIGN 32 + +#define USEC_PER_MSEC 1000 +#define MSEC_PER_SEC 1000 + +#define BUG() PrintVariableValueHex("bug on", __LINE__); +#define BUG_ON(condition) if (condition) BUG() +#define WARN_ON(condition) if (condition) BUG() + +#define barrier() +#define wmb() +#define EXPORT_SYMBOL(x) + +#define dev_dbg(dev, ...) TRACE_DEBUG(__VA_ARGS__) +#define dev_vdbg dev_dbg +#define dev_info(dev, ...) TRACE_INFO(__VA_ARGS__) +#define dev_warn(dev, ...) TRACE_WARNING(__VA_ARGS__) +#define dev_err(dev, ...) TRACE_ERROR(__VA_ARGS__) + +#define __iomem volatile + +#define unlikely(x) (x) +#define likely(x) (x) + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) +#define DIV_ROUND_UP_ULL(ll, d) (((unsigned long long)(ll) + (d) - 1) / (d)) + + +#define BITS_PER_BYTE 8 +#define BITS_PER_LONG 32 + +#define BIT(nr) (1UL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) + +#define min(x,y) ((x)<(y)?(x):(y)) + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. */ +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define VOID void +#define BOOL int +#define TRUE 1 +#define FALSE 0 + +#define FAR +#define NEAR + +typedef unsigned long long u64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; +//typedef s32 ssize_t; +typedef u32 __le32; +typedef UINT32 AARCHPTR; +typedef u32 dma_addr_t; +typedef u32 phys_addr_t; +typedef phys_addr_t resource_size_t; +typedef unsigned gfp_t; + +#define le16_to_cpu(x) (x) +#define le32_to_cpu(x) (x) +#define cpu_to_le32(x) (x) + +#define ___constant_swab32(x) ((u32)( \ + (((u32)(x) & (u32)0x000000ffUL) << 24) | \ + (((u32)(x) & (u32)0x0000ff00UL) << 8) | \ + (((u32)(x) & (u32)0x00ff0000UL) >> 8) | \ + (((u32)(x) & (u32)0xff000000UL) >> 24))) + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + + +#define DECLARE_BITMAP(name,bits) \ + unsigned long name[BITS_TO_LONGS(bits)] + +typedef struct { + int counter; +} atomic_t; + +typedef struct refcount_struct { + atomic_t refs; +} refcount_t; + +#define REFCOUNT_INIT(n) { .refs = ATOMIC_INIT(n), } + +struct kref { + refcount_t refcount; +}; + +#define KREF_INIT(n) { .refcount = REFCOUNT_INIT(n), } + +#define small_const_nbits(nbits) \ + (nbits && (nbits) <= BITS_PER_LONG) + + +#define reg8_read(addr) *((volatile uint8_t *)(addr)) +#define reg16_read(addr) *((volatile uint16_t *)(addr)) +#define reg32_read(addr) *((volatile uint32_t *)(addr)) + +#define reg8_write(addr,val) *((volatile uint8_t *)(addr)) = (val) +#define reg16_write(addr,val) *((volatile uint16_t *)(addr)) = (val) +#define reg32_write(addr,val) *((volatile uint32_t *)(addr)) = (val) + +#define mem8_read(addr) *((volatile uint8_t *)(addr)) +#define mem16_read(addr) *((volatile uint16_t *)(addr)) +#define mem32_read(addr) *((volatile uint32_t *)(addr)) + +#define mem8_write(addr,val) *((volatile uint8_t *)(addr)) = (val) +#define mem16_write(addr,val) *((volatile uint16_t *)(addr)) = (val) +#define mem32_write(addr,val) *((volatile uint32_t *)(addr)) = (val) + +#define readb(a) reg8_read(a) +#define readw(a) reg16_read(a) +#define readl(a) reg32_read(a) + +#define writeb(v, a) reg8_write(a, v) +#define writew(v, a) reg16_write(a, v) +#define writel(v, a) reg32_write(a, v) + +static __INLINE void memset_s(void *dest, size_t destMax, int c, size_t count) +{ + memset(dest, c, destMax); +} + +static __INLINE void bitmap_zero(unsigned long *dst, unsigned int nbits) +{ + if (small_const_nbits(nbits)) + *dst = 0UL; + else { + unsigned int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); + memset(dst, 0, len); + } +} + +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ +static __INLINE int fls(u32 x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + +/* + * __fls() returns the bit position of the last bit set, where the + * LSB is 0 and MSB is 31. Zero input is undefined. + */ +static __INLINE unsigned long __fls(unsigned long x) +{ + return fls(x) - 1; +} + +/* + * ffs() returns zero if the input was zero, otherwise returns the bit + * position of the first set bit, where the LSB is 1 and MSB is 32. + */ +static __INLINE int ffs(int x) +{ + return fls(x & -x); +} + + +/* + * __ffs() returns the bit position of the first bit set, where the + * LSB is 0 and MSB is 31. Zero input is undefined. + */ +static __INLINE unsigned long __ffs(unsigned long x) +{ + return ffs(x) - 1; +} + + +#define MAX_ERRNO 4095 +#define IS_ERR_VALUE(x) (x) >= (unsigned long)-MAX_ERRNO + +static __INLINE void *ERR_PTR(long error) +{ + return (void *) error; +} + +static __INLINE long PTR_ERR(const void *ptr) +{ + return (long) ptr; +} + +static __INLINE long IS_ERR(const void *ptr) +{ + return IS_ERR_VALUE((unsigned long)ptr); +} + +static __INLINE int IS_ERR_OR_NULL(const void *ptr) +{ + return !ptr || IS_ERR_VALUE((unsigned long)ptr); +} + +static __INLINE void set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static __INLINE void clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static __INLINE int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It may be reordered on other architectures than x86. + * It also implies a memory barrier. + */ +static __INLINE int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + + old = *p; + *p = old | mask; + + return (old & mask) != 0; +} + +static __INLINE int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + + old = *p; + *p = old & ~mask; + + return (old & mask) != 0; +} + + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static __INLINE void list_splice_init(List_t *list, List_t *head) +{ + ListItem_t *pxIndex = head->pxIndex; + ListItem_t *first = list->pxIndex->pxNext; + ListItem_t *last = list->pxIndex->pxPrevious; + + if (!listLIST_IS_EMPTY(list)) { + first->pxPrevious = pxIndex->pxPrevious; + last->pxNext = pxIndex; + pxIndex->pxPrevious->pxNext = first; + pxIndex->pxPrevious = last; + head->uxNumberOfItems += list->uxNumberOfItems; + vListInitialise(list); + } +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static __INLINE void list_move(ListItem_t *item, List_t *list, ListItem_t *pos) +{ + void *pvOwner = item->pvOwner; + + uxListRemove(item); + item->pvOwner = pvOwner; + item->pxNext = pos->pxNext; + item->pxNext->pxPrevious = item; + item->pxPrevious = pos; + pos->pxNext = item; + + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + item->pxContainer = list; + + list->uxNumberOfItems++; + +} + +#define list_for_each_entry(pxListItem, pvOwner, list) \ + for (pxListItem = listGET_HEAD_ENTRY(list), \ + pvOwner = listGET_LIST_ITEM_OWNER(pxListItem); \ + pxListItem != listGET_END_MARKER(list); \ + pxListItem = listGET_NEXT(pxListItem), \ + pvOwner = listGET_LIST_ITEM_OWNER(pxListItem)) + +#define list_entry(pxListItem) listGET_LIST_ITEM_OWNER(pxListItem) + +#define list_first_entry(pxList) listGET_LIST_ITEM_OWNER(listGET_HEAD_ENTRY(pxList)) + + +#define SG_MITER_ATOMIC (1 << 0) /* use kmap_atomic */ +#define SG_MITER_TO_SG (1 << 1) /* flush back to phys on unmap */ +#define SG_MITER_FROM_SG (1 << 2) /* nop */ + +void *malloc(size_t size); +extern void free(void *ptr); + +struct device { + const char *init_name; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/A58-STEPLDR/Src/pinctrl.c b/A58-STEPLDR/Src/pinctrl.c new file mode 100644 index 00000000..dcf21c82 --- /dev/null +++ b/A58-STEPLDR/Src/pinctrl.c @@ -0,0 +1,147 @@ +#include "amt630h.h" +#include "pinctrl.h" +#include "sysctl.h" + +#define PINCTL_REG_BASE REGS_SYSCTL_BASE + +/* typedef struct { + +} xPinFunction_t; */ + +typedef struct { + int reg; + int offset; + int mask; +} xPinmap_t; + +static xPinmap_t amt630h_pin_map[] = { + {0xc0, 0, 0x3}, + {0xc0, 2, 0x3}, + {0xc0, 4, 0x3}, + {0xc0, 6, 0x3}, + {0xc0, 8, 0x3}, + {0xc0, 10, 0x3}, + {0xc0, 12, 0x3}, + {0xc0, 14, 0x3}, + {0xc0, 16, 0x3}, + {0xc0, 18, 0x3}, + {0xc0, 20, 0x3}, + {0xc0, 22, 0x3}, + {0xc0, 24, 0x3}, + {0xc0, 26, 0x3}, + {0xc0, 28, 0x3}, + {0xc0, 30, 0x3}, + {0xc4, 0, 0x3}, + {0xc4, 2, 0x3}, + {0xc4, 4, 0x3}, + {0xc4, 6, 0x3}, + {0xc4, 8, 0x3}, + {0xc4, 10, 0x3}, + {0xc4, 12, 0x3}, + {0xc4, 14, 0x3}, + {0xc4, 16, 0x3}, + {0xc4, 18, 0x3}, + {0xc4, 20, 0x3}, + {0xc4, 22, 0x3}, + {0xc4, 24, 0x3}, + {0xc4, 26, 0x3}, + {0xc4, 28, 0x3}, + {0xc4, 30, 0x3}, + {0xc8, 0, 0x3}, + {0xc8, 2, 0x3}, + {0xc8, 4, 0x3}, + {0xc8, 6, 0x3}, + {0xc8, 8, 0x3}, + {0xc8, 10, 0x3}, + {0xc8, 12, 0x3}, + {0xc8, 14, 0x3}, + {0xc8, 16, 0x3}, + {0xc8, 18, 0x3}, + {0xc8, 20, 0x3}, + {0xc8, 22, 0x3}, + {0xc8, 24, 0x3}, + {0xc8, 26, 0x3}, + {0xc8, 28, 0x3}, + {0xc8, 30, 0x3}, + {0xcc, 0, 0x3}, + {0xcc, 2, 0x3}, + {0xcc, 4, 0x3}, + {0xcc, 6, 0x3}, + {0xcc, 8, 0x3}, + {0xcc, 10, 0x3}, + {0xcc, 12, 0x3}, + {0xcc, 14, 0x3}, + {0xcc, 16, 0x3}, + {0xcc, 18, 0x3}, + {0xcc, 20, 0x3}, + {0xcc, 22, 0x3}, + {0xcc, 24, 0x3}, + {0xcc, 26, 0x3}, + {0xcc, 28, 0x3}, + {0xcc, 30, 0x3}, + {0xd0, 0, 0x3}, + {0xd0, 2, 0x3}, + {0xd0, 4, 0x3}, + {0xd0, 6, 0x3}, + {0xd0, 8, 0x3}, + {0xd0, 10, 0x3}, + {0xd0, 12, 0x3}, + {0xd0, 14, 0x3}, + {0xd0, 16, 0x3}, + {0xd0, 18, 0x3}, + {0xd0, 20, 0x3}, + {0xd0, 22, 0x3}, + {0xd0, 24, 0x3}, + {0xd0, 26, 0x3}, + {0xd0, 28, 0x3}, + {0xd0, 30, 0x3}, + {0xd4, 0, 0x3}, + {0xd4, 2, 0x3}, + {0xd4, 4, 0x3}, + {0xd4, 6, 0x3}, + {0xd4, 8, 0x3}, + {0xd4, 10, 0x3}, + {0xd4, 12, 0x3}, + {0xd4, 14, 0x3}, + {0xd4, 16, 0x3}, + {0xd4, 18, 0x3}, + {0xd4, 20, 0x3}, + {0xd4, 22, 0x3}, + {0xd4, 24, 0x3}, + {0xd4, 26, 0x3}, + {0xd4, 28, 0x3}, + {0xd4, 30, 0x3}, + {0xd8, 4, 0x3}, + {0xd8, 0, 0x3}, + {0xd8, 6, 0x3}, + {0xd8, 2, 0x3}, + {0xd8, 8, 0x3}, + {0xd8, 10, 0x3}, + /* pad not mux with gpio */ + +}; + +static void pinctrl_set_pin(int npin, int val, int drive) +{ + xPinmap_t *pctrl; + uint32_t reg; + + pctrl = &amt630h_pin_map[npin]; + + reg = readl(PINCTL_REG_BASE + pctrl->reg); + reg &= ~(pctrl->mask << pctrl->offset); + reg |= val << pctrl->offset; + writel(reg, PINCTL_REG_BASE + pctrl->reg); + + if (drive != PAD_DRIVE_DEFAULT) { + uint32_t drv_reg = SYS_IO_DRIVER00 + npin / 16 * 4; + uint32_t offset = (npin % 16) * 2; + uint32_t drv_val = drive - 1; + vSysctlConfigure(drv_reg, offset, 3, drv_val); + } +} + +void pinctrl_gpio_request(int gpio) +{ + pinctrl_set_pin(gpio, 0, PAD_DRIVE_DEFAULT); +} diff --git a/A58-STEPLDR/Src/pinctrl.h b/A58-STEPLDR/Src/pinctrl.h new file mode 100644 index 00000000..69de8e80 --- /dev/null +++ b/A58-STEPLDR/Src/pinctrl.h @@ -0,0 +1,65 @@ +#ifndef _PINCTRL_H +#define _PINCTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PGRP_I2C0, + PGRP_I2C1, + PGRP_LCD_TTL_CH0, + PGRP_LCD_TTL_CH1, + PGRP_LCD_LVDS, + PGRP_LCD_SRGB, + PGRP_LCD_ITU601, + PGRP_UART0, + PGRP_UART1, + PGRP_UART2, + PGRP_UART3, + PGRP_SPI0, + PGRP_SPI1, + PGRP_PWM0, + PGRP_PWM1, + PGRP_PWM2, + PGRP_PWM3, + PGRP_PWM0_IN, + PGRP_PWM1_IN, + PGRP_PWM2_IN, + PGRP_PWM3_IN, + PGRP_SDMMC0, + PGRP_ITU_CH0, + PGRP_ITU_CH0_INV, + PGRP_ITU_CH1, + PGRP_ITU_CH1_INV, + PGRP_CAN0_CH0, + PGRP_CAN0_CH1, + PGRP_CAN0_CH2, + PGRP_CAN1_CH0, + PGRP_CAN1_CH1, + PGRP_CAN1_CH2, + PGRP_I2S0_PLAY, + PGRP_I2S0_RECORD, + PGRP_I2S1_PLAY, + PGRP_I2S1_RECORD, + PGRP_RCRT, +}ePingroupID; + +typedef enum { + PAD_DRIVE_DEFAULT, + PAD_DRIVE_2MA, + PAD_DRIVE_4MA, + PAD_DRIVE_8MA, + PAD_DRIVE_12MA, +}ePadDrive; + +void vPinctrlSetup(void); +void pinctrl_gpio_request(int gpio); +void pinctrl_set_group(int groupid); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/A58-STEPLDR/Src/pxp.c b/A58-STEPLDR/Src/pxp.c new file mode 100644 index 00000000..6066d659 --- /dev/null +++ b/A58-STEPLDR/Src/pxp.c @@ -0,0 +1,207 @@ +#include "FreeRTOS.h" +#include "board.h" +#include "amt630h.h" +#include "pxp.h" +#include "timer.h" +#include "aic.h" +#include "uart.h" + +#define PXP_CTRL 0x000 +#define PXP_CTRL_SET 0x004 +#define PXP_CTRL_CLR 0x008 +#define PXP_CTRL_TOG 0x00C +#define PXP_STAT 0x010 +#define PXP_STAT_SET 0x014 +#define PXP_STAT_CLR 0x018 +#define PXP_STAT_TOG 0x01c +#define PXP_OUTBUF 0x020 +#define PXP_OUTBUF2 0x030 +#define PXP_OUTSIZE 0x040 +#define PXP_S0BUF 0x050 +#define PXP_S0UBUF 0x060 +#define PXP_S0VBUF 0x070 +#define PXP_S0PARAM 0x080 +#define PXP_S0BACKGROUND 0x090 +#define PXP_S0CLIP 0x0A0 +#define PXP_S0SCALE 0x0B0 +#define PXP_S0OFFSET 0x0C0 +#define PXP_CSCCOEFF0 0x0D0 +#define PXP_CSCCOEFF1 0x0E0 +#define PXP_CSCCOEFF2 0x0F0 +#define PXP_NEXT 0x100 +#define PXP_PAGETABLE 0x170 +#define PXP_S0CKEYL 0x180 +#define PXP_S0CKEYH 0x190 +#define PXP_OLCKEYL 0x1A0 +#define PXP_OLCKEYH 0x1B0 +#define PXP_OL0BUF 0x200 +#define PXP_OL0SIZE 0x210 +#define PXP_OL0PARAM 0x220 +#define PXP_OL1BUF 0x240 +#define PXP_OL1SIZE 0x250 +#define PXP_OL1PARAM 0x260 +#define PXP_OL2BUF 0x280 +#define PXP_OL2SIZE 0x290 +#define PXP_OL2PARAM 0x2A0 +#define PXP_OL3BUF 0x2C0 +#define PXP_OL3SIZE 0x2D0 +#define PXP_OL3PARAM 0x2E0 +#define PXP_OL4BUF 0x300 +#define PXP_OL4SIZE 0x310 +#define PXP_OL4PARAM 0x320 +#define PXP_OL5BUF 0x340 +#define PXP_OL5SIZE 0x350 +#define PXP_OL5PARAM 0x360 +#define PXP_OL6BUF 0x380 +#define PXP_OL6SIZE 0x390 +#define PXP_OL6PARAM 0x3A0 +#define PXP_OL7BUF 0x3C0 +#define PXP_OL7SIZE 0x3D0 +#define PXP_OL7PARAM 0x3E0 +// offss for "NEXT" pointers +#define PXP_NEXTCTRL 0x000 +#define PXP_NEXTRGBBUF 0x004 +#define PXP_NEXTRGBBUF2 0x008 +#define PXP_NEXTRGBSIZE 0x00C +#define PXP_NEXTS0BUF 0x010 +#define PXP_NEXTS0UBUF 0x014 +#define PXP_NEXTS0VBUF 0x018 +#define PXP_NEXTS0PARAM 0x01C +#define PXP_NEXTS0BACKGROUND 0x020 +#define PXP_NEXTS0CLIP 0x024 +#define PXP_NEXTS0SCALE 0x028 +#define PXP_NEXTS0OFFSET 0x02C +#define PXP_NEXTS0CKEYL 0x030 +#define PXP_NEXTS0CKEYH 0x034 +#define PXP_NEXTOLCKEYL 0x038 +#define PXP_NEXTOLCKEYH 0x03C +#define PXP_NEXTOL0BUF 0x040 +#define PXP_NEXTOL0SIZE 0x044 +#define PXP_NEXTOL0PARAM 0x048 +#define PXP_NEXTOL1BUF 0x050 +#define PXP_NEXTOL1SIZE 0x054 +#define PXP_NEXTOL1PARAM 0x058 +#define PXP_NEXTOL2BUF 0x060 +#define PXP_NEXTOL2SIZE 0x064 +#define PXP_NEXTOL2PARAM 0x068 +#define PXP_NEXTOL3BUF 0x070 +#define PXP_NEXTOL3SIZE 0x074 +#define PXP_NEXTOL3PARAM 0x078 +#define PXP_NEXTOL4BUF 0x080 +#define PXP_NEXTOL4SIZE 0x084 +#define PXP_NEXTOL4PARAM 0x088 +#define PXP_NEXTOL5BUF 0x090 +#define PXP_NEXTOL5SIZE 0x094 +#define PXP_NEXTOL5PARAM 0x098 +#define PXP_NEXTOL6BUF 0x0A0 +#define PXP_NEXTOL6SIZE 0x0A4 +#define PXP_NEXTOL6PARAM 0x0A8 +#define PXP_NEXTOL7BUF 0x0B0 +#define PXP_NEXTOL7SIZE 0x0B4 +#define PXP_NEXTOL7PARAM 0x0B8 + +static uint32_t pxpbase = REGS_PXP_BASE; + +void waitforpxp_done(unsigned int count) +{ + uint32_t status = 0; + while(count--) + { + status = readl(pxpbase + PXP_STAT); +// printf("+++++++++++status 0x%x++++++++++++++\n",status); + if(status & 1) + break; + } + if(count == 0) + SendUartString("pxp timeout.\n"); +} + + +/* this function can not used in isr */ +int pxp_scaler_rotate(uint32_t s0buf, uint32_t s0ubuf, uint32_t s0vbuf, + int s0format, uint32_t s0width, uint32_t s0height, + uint32_t outbuf, uint32_t outbuf2, int outformat, + uint32_t outwidth, uint32_t outheight, int outangle) +{ + uint32_t ctrl; + int ret = 0; + + configASSERT(outangle >= PXP_ROTATE_0 && outangle <= PXP_ROTATE_270); + + if (outangle == PXP_ROTATE_90 || outangle == PXP_ROTATE_270) { + uint32_t tmp = outheight; + outheight = outwidth; + outwidth = tmp; + } + + writel(1UL << 31, pxpbase + PXP_CTRL); + udelay(10); + writel(0, pxpbase + PXP_CTRL); + + writel(outbuf, pxpbase + PXP_OUTBUF); + writel(outbuf2, pxpbase + PXP_OUTBUF2); + writel((0xffUL << 24) | (outwidth << 12) | outheight, pxpbase + PXP_OUTSIZE); + writel(s0buf, pxpbase + PXP_S0BUF); + writel(s0ubuf, pxpbase + PXP_S0UBUF); + writel(s0vbuf, pxpbase + PXP_S0VBUF); + writel((((s0width >> 3) & 0xff) << 8) | ((s0height >> 3) & 0xff), pxpbase + PXP_S0PARAM); + writel(0, pxpbase + PXP_S0BACKGROUND); + writel((((outwidth >> 3) & 0xff) << 8) | ((outheight >> 3) & 0xff), pxpbase + PXP_S0CLIP); + writel(((s0height * 0x1000 / (outheight + 2)) << 16) | (s0width * 0x1000 / (outwidth + 2)), + pxpbase + PXP_S0SCALE); + //YCbCr->RGB Coefficient Values bit31 ycbcr_mode + writel((1 << 31) | 0x1f0 | (0x180 << 9) | (0x12a << 18), pxpbase + PXP_CSCCOEFF0); + writel(0x204 | (0x198 <<16), pxpbase + PXP_CSCCOEFF1); + writel(0x79c | (0x730 <<16), pxpbase + PXP_CSCCOEFF2); + + ctrl = (1 << 19) | (1 << 18) | ((s0format & 0xf) << 12) | (outangle << 8) | +#ifdef PXP_OUTPUT_MIRROR + (1<< 10) | +#endif + ((outformat & 0xf) << 4) | 3; + + writel(ctrl, pxpbase + PXP_CTRL); + + waitforpxp_done(10000000); + + return ret; +} + +int pxp_rotate(uint32_t s0buf, uint32_t s0ubuf, uint32_t s0vbuf, + int s0format, uint32_t s0width, uint32_t s0height, + uint32_t outbuf, uint32_t outbuf2, int outformat, + int outangle) +{ + uint32_t ctrl; + int ret = 0; + + configASSERT(outangle >= PXP_ROTATE_0 && outangle <= PXP_ROTATE_270); + + writel(1UL << 31, pxpbase + PXP_CTRL); + udelay(10); + writel(0, pxpbase + PXP_CTRL); + + writel(outbuf, pxpbase + PXP_OUTBUF); + writel(outbuf2, pxpbase + PXP_OUTBUF2); + writel((0xffUL << 24) | (s0width << 12) | s0height, pxpbase + PXP_OUTSIZE); + writel(s0buf, pxpbase + PXP_S0BUF); + writel(s0ubuf, pxpbase + PXP_S0UBUF); + writel(s0vbuf, pxpbase + PXP_S0VBUF); + writel((((s0width >> 3) & 0xff) << 8) | ((s0height >> 3) & 0xff), pxpbase + PXP_S0PARAM); + writel(0, pxpbase + PXP_S0BACKGROUND); + //YCbCr->RGB Coefficient Values bit31 ycbcr_mode + writel((1 << 31) | 0x1f0 | (0x180 << 9) | (0x12a << 18), pxpbase + PXP_CSCCOEFF0); + writel(0x204 | (0x198 <<16), pxpbase + PXP_CSCCOEFF1); + writel(0x79c | (0x730 <<16), pxpbase + PXP_CSCCOEFF2); + + ctrl = ((s0format & 0xf) << 12) | (outangle << 8) | +#ifdef PXP_OUTPUT_MIRROR + (1<< 10) | +#endif + ((outformat & 0xf) << 4) | 3; + + writel(ctrl, pxpbase + PXP_CTRL); + + waitforpxp_done(10000); + return ret; +} diff --git a/A58-STEPLDR/Src/pxp.h b/A58-STEPLDR/Src/pxp.h new file mode 100644 index 00000000..f7f9182f --- /dev/null +++ b/A58-STEPLDR/Src/pxp.h @@ -0,0 +1,51 @@ +#ifndef _PXP_H +#define _PXP_H + +typedef enum { + PXP_SRC_FMT_RGB888 = 0x1, /* 32-bit pixels (unpacked 24-bit format) */ + PXP_SRC_FMT_RGB565 = 0x4, /* 16-bit pixels */ + PXP_SRC_FMT_RGB555 = 0x5, /* 16-bit pixels */ + PXP_SRC_FMT_YUV422 = 0x8, /* 16-bit pixels */ + PXP_SRC_FMT_YUV420 = 0x9, /* 16-bit pixels */ + PXP_SRC_FMT_UYVY1P422 = 0xa, /* 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ + PXP_SRC_FMT_VYUY1P422 = 0xb, /* 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ + PXP_SRC_FMT_YUV2P422 = 0xc, /* 16-bit pixels (2-plane UV interleaved bytes) */ + PXP_SRC_FMT_YUV2P420 = 0xd, /* 16-bit pixels */ + PXP_SRC_FMT_YVU2P422 = 0xe, /* 16-bit pixels (2-plane VU interleaved bytes) */ + PXP_SRC_FMT_YVU2P420 = 0xf, /* 16-bit pixels */ +} PXP_SRC_FMT; + +typedef enum { + PXP_OUT_FMT_ARGB8888 = 0x0, /* 32-bit pixels */ + PXP_OUT_FMT_RGB888 = 0x1, /* 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) */ + PXP_OUT_FMT_RGB888P = 0x2, /* 24-bit pixels (packed 24-bit format) */ + PXP_OUT_FMT_ARGB1555 = 0x3, /* 16-bit pixels */ + PXP_OUT_FMT_RGB565 = 0x4, /* 16-bit pixels */ + PXP_OUT_FMT_RGB555 = 0x5, /* 16-bit pixels */ + PXP_OUT_FMT_YUV444 = 0x7, /* 32-bit pixels (1-plane XYUV unpacked) */ + PXP_OUT_FMT_UYVY1P422 = 0xa, /* 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ + PXP_OUT_FMT_VYUY1P422 = 0xb, /* 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ + PXP_OUT_FMT_YUV2P422 = 0xc, /* 16-bit pixels (2-plane UV interleaved bytes) */ + PXP_OUT_FMT_YUV2P420 = 0xd, /* 16-bit pixels (2-plane VU) */ + PXP_OUT_FMT_YVU2P422 = 0xe, /* 16-bit pixels (2-plane VU interleaved bytes) */ + PXP_OUT_FMT_YVU2P420 = 0xf, /* 16-bit pixels (2-plane VU) */ +} PXP_OUT_FMT; + +/* clockwise rotate */ +typedef enum { + PXP_ROTATE_0 = 0, + PXP_ROTATE_90 = 1, + PXP_ROTATE_180 = 2, + PXP_ROTATE_270 = 3, +} PXP_ROTATE; + +int pxp_scaler_rotate(uint32_t s0buf, uint32_t s0ubuf, uint32_t s0vbuf, + int s0format, uint32_t s0width, uint32_t s0height, + uint32_t outbuf, uint32_t outbuf2, int outformat, + uint32_t outwidth, uint32_t outheight, int outangle); +int pxp_rotate(uint32_t s0buf, uint32_t s0ubuf, uint32_t s0vbuf, + int s0format, uint32_t s0width, uint32_t s0height, + uint32_t outbuf, uint32_t outbuf2, int outformat, + int outangle); + +#endif diff --git a/A58-STEPLDR/Src/sdmmc.c b/A58-STEPLDR/Src/sdmmc.c new file mode 100644 index 00000000..f271995a --- /dev/null +++ b/A58-STEPLDR/Src/sdmmc.c @@ -0,0 +1,1752 @@ +/* +********************************************************************** +Copyright (c)2007 Arkmicro Technologies Inc. All Rights Reserved +Filename: sdmmc.c +Version : 1.0 +Date : 2015.12.01 +Abstract: ark1680 soc sd driver +History : +*********************************************************************** +*/ +#include +#include "typedef.h" +#include "amt630h.h" +#include "sdmmc.h" +#include "uart.h" +#include "timer.h" +#include "fs/ff.h" +#include "fs/diskio.h" +#include "os_adapt.h" +#include "sysinfo.h" +#include "update.h" +#include "crc32.h" +#include "cp15.h" + +#define SDMMC_BUS_CLK 40000000//CLK_24MHZ + +#define INIT_CLOCK 400000 +#define SD_TRUE 1 +#define SD_FAULSE 0 +#define TIMEOUT_SD 10000 + + +#if SD_DEBUG +#define DEBUG_MSG(fmt, ...) printf(fmt, __VA_ARGS__) +#else +#define DEBUG_MSG(fmt, ...) +#endif + +static UINT32 lg_ulChip; +static UINT32 SDHC_Controls[1] = {SDHC0_BASE}; +static UINT32 mmc_voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; +#define READ_INT32(r) *((volatile UINT32 *)(r)) +#define WRITE_INT32(r,d) (*((volatile UINT32 *)(r)) = d) + +#define SDHC_REG_READ32(c,r)\ + (READ_INT32(SDHC_Controls[(c)] + (r))) +#define SDHC_REG_WRITE32(c,r,v)\ + (WRITE_INT32(SDHC_Controls[(c)] + (r),(v))) + +#define SDMMC_CTRL 0x00 +#define SDMMC_PWREN 0x04 +#define SDMMC_CLKDIV 0x08 +#define SDMMC_CLKSRC 0x0C +#define SDMMC_CLKENA 0x10 +#define SDMMC_TMOUT 0x14 +#define SDMMC_CTYPE 0x18 +#define SDMMC_BLKSIZ 0x1C +#define SDMMC_BYTCNT 0x20 +#define SDMMC_INTMASK 0x24 +#define SDMMC_CMDARG 0x28 +#define SDMMC_CMD 0x2C +#define SDMMC_RESP0 0x30 +#define SDMMC_RESP1 0x34 +#define SDMMC_RESP2 0x38 +#define SDMMC_RESP3 0x3C +#define SDMMC_MINTSTS 0x40 +#define SDMMC_RINTSTS 0x44 +#define SDMMC_STATUS 0x48 +#define SDMMC_FIFOTH 0x4C +#define SDMMC_CDETECT 0x50 +#define SDMMC_WRTPRT 0x54 +#define SDMMC_GPIO 0x58 +#define SDMMC_TCBCNT 0x5C +#define SDMMC_TBBCNT 0x60 +#define SDMMC_DEBNCE 0x64 +#define SDMMC_USRID 0x68 +#define SDMMC_VERID 0x6C +#define SDMMC_HCON 0x70 +#define SDMMC_UHS_REG 0x74 +#define SDMMC_BMOD 0x80 +#define SDMMC_PLDMND 0x84 +#define SDMMC_DBADDR 0x88 +#define SDMMC_IDSTS 0x8C +#define SDMMC_IDINTEN 0x90 +#define SDMMC_DATA 0x200 +#define SDMMC_FIFO (SDHC_Controls[lg_ulChip] + 0x200) + +/* Interrupt Mask register */ +#define SDMMC_INTMSK_ALL 0xffffffff +#define SDMMC_INTMSK_RE (1 << 1) +#define SDMMC_INTMSK_CDONE (1 << 2) +#define SDMMC_INTMSK_DTO (1 << 3) +#define SDMMC_INTMSK_TXDR (1 << 4) +#define SDMMC_INTMSK_RXDR (1 << 5) +#define SDMMC_INTMSK_DCRC (1 << 7) +#define SDMMC_INTMSK_RTO (1 << 8) +#define SDMMC_INTMSK_DRTO (1 << 9) +#define SDMMC_INTMSK_HTO (1 << 10) +#define SDMMC_INTMSK_FRUN (1 << 11) +#define SDMMC_INTMSK_HLE (1 << 12) +#define SDMMC_INTMSK_SBE (1 << 13) +#define SDMMC_INTMSK_ACD (1 << 14) +#define SDMMC_INTMSK_EBE (1 << 15) + +/* Raw interrupt Regsiter */ +#define SDMMC_DATA_ERR (SDMMC_INTMSK_EBE | SDMMC_INTMSK_SBE | SDMMC_INTMSK_HLE |\ + SDMMC_INTMSK_FRUN | SDMMC_INTMSK_EBE | SDMMC_INTMSK_DCRC) +#define SDMMC_DATA_TOUT (SDMMC_INTMSK_HTO | SDMMC_INTMSK_DRTO) + +/* CTRL register */ +#define SDMMC_CTRL_RESET (1 << 0) +#define SDMMC_CTRL_FIFO_RESET (1 << 1) +#define SDMMC_CTRL_DMA_RESET (1 << 2) +#define SDMMC_DMA_EN (1 << 5) +#define SDMMC_CTRL_SEND_AS_CCSD (1 << 10) +#define SDMMC_IDMAC_EN (1 << 25) +#define SDMMC_RESET_ALL (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |\ + SDMMC_CTRL_DMA_RESET) + +/* CMD register */ +#define SDMMC_CMD_RESP_EXP (1 << 6) +#define SDMMC_CMD_RESP_LENGTH (1 << 7) +#define SDMMC_CMD_CHECK_CRC (1 << 8) +#define SDMMC_CMD_DATA_EXP (1 << 9) +#define SDMMC_CMD_RW (1 << 10) +#define SDMMC_CMD_SEND_STOP (1 << 12) +#define SDMMC_CMD_ABORT_STOP (1 << 14) +#define SDMMC_CMD_PRV_DAT_WAIT (1 << 13) +#define SDMMC_CMD_UPD_CLK (1 << 21) +#define SDMMC_CMD_USE_HOLD_REG (1 << 29) +#define SDMMC_CMD_START (1UL << 31) + +/* CLKENA register */ +#define SDMMC_CLKEN_ENABLE (1 << 0) +#define SDMMC_CLKEN_LOW_PWR (1 << 16) + +/* Card-type registe */ +#define SDMMC_CTYPE_1BIT 0 +#define SDMMC_CTYPE_4BIT (1 << 0) +#define SDMMC_CTYPE_8BIT (1 << 16) + +/* Status Register */ +#define SDMMC_BUSY (1 << 9) +#define SDMMC_FIFO_MASK 0x1fff +#define SDMMC_FIFO_SHIFT 17 + +/* FIFOTH Register */ +#define MSIZE(x) ((x) << 28) +#define RX_WMARK(x) ((x) << 16) +#define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) + +#define fifo_tran_over() do{}while (!(SDHC_REG_READ32(lg_ulChip,SDMMC_STATUS) & 0x00000004)) +#define confi_fifo_full() do{}while (!(SDHC_REG_READ32(lg_ulChip,SDMMC_STATUS) & 0x00000008)) +//#define confi_fifo_unempty() do{}while ((rSTATUS & 0x00000004)) + +/* frequency bases */ +/* divided by 10 to be nice to platforms without floating point */ +static const int fbase[] = { + 10000, + 100000, + 1000000, + 10000000, +}; + +/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice + * to platforms without floating point. + */ +static const UINT8 multipliers[] = { + 0, /* reserved */ + 10, + 12, + 13, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 70, + 80, +}; + +//extern volatile FS_CARD SDCard; + +static UINT32 fifoth_val; +static UINT32 sd_ocr; +static UINT32 sd_cid[4]; +static UINT32 sd_csd[4]; +static UINT32 sd_rca; +static UINT32 read_bl_len; +static UINT32 write_bl_len; +static UINT32 erase_grp_size; +static UINT64 capacity_user; + +typedef enum {MMC, SD}CARDTYPE; +static CARDTYPE CardType = SD; // 1 sd card, 0 means MMC +static enum {Ver0, Ver1, Ver2} Spec = Ver1; +static enum {Standard, High} Capacity = Standard; +//static INT8 *sd_spec[3]={"1.0 & 1.01", "1.1", "2.0"}; +//static INT8 *mmc_spec[5]={"1.0-1.2", "1.4", "2.0-2.2","3.1-3.2-3.31","4.x"}; +//static UINT8 SD_SPEC; +//static UINT8 MMC_SPEC; + +static UINT32 g_MatchSdVcc = 1; + +#define SDMMC_SECTOR_SIZE 512 + +static void select_sd_pad(UINT32 ulChip) +{ + UINT32 val; + UINT32 regval; + val = rSYS_BOOT_SAMPLE; + val = (val>>2)&0x1; + + if(val == 1) + { /*sd0 128pin*/ + regval = rSYS_PAD_CTRL01; + regval &= ~((0x3<<12)|(0x3<<10)|(0x3<<8)|(0x3<<6)|(0x3<<4)|(0x3<<2)|(0x3<<0)); + regval |= ((0x1<<12)|(0x1<<10)|(0x1<<8)|(0x1<<6)|(0x1<<4)|(0x1<<2)|(0x1<<0)); + rSYS_PAD_CTRL01 = regval; + regval = rSYS_PAD_CTRL07; + regval &= ~((0x1<<26)|(0x1<<25)|(0x1<<24)|(0x1<<2)|(0x1<<1)|(0x1<<0)); + rSYS_PAD_CTRL07 = regval; + } + else + { + /*sd0 96pin*/ + regval = rSYS_PAD_CTRL01; + regval &= ~((0x3<<20)|(0x3<<18)|(0x3<<16)|(0x3<<14)); + regval |= ((0x3<<20)|(0x3<<18)|(0x3<<16)|(0x3<<14)); + rSYS_PAD_CTRL01 = regval; + + regval = rSYS_PAD_CTRL02; + regval &= ~((0x3<<28)|(0x3<<26)|(0x3<<24)); + regval |= ((0x2<<28)|(0x2<<26)|(0x2<<24)); + rSYS_PAD_CTRL02 = regval; + + regval = rSYS_PAD_CTRL07; + regval &= ~((0x1<<31)|(0x1<<26)|(0x1<<25)|(0x1<<24)); + regval |= (0x1<<31)|(0x1<<26)|(0x1<<25)|(0x1<<24); + rSYS_PAD_CTRL07 = regval; + + } +// rSYS_SDMMC_CLK_CFG |= (1<<6); +} + +static int sdmmc_wait_reset(UINT32 value) +{ + unsigned long timeout = 1000; + UINT32 ctrl; + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CTRL, value); + + while (timeout--) { + ctrl = SDHC_REG_READ32(lg_ulChip, SDMMC_CTRL); + if (!(ctrl & SDMMC_RESET_ALL)) + return -1; + } + return 0; +} + +static int sdmmc_data_transfer(struct mmc_data *data) +{ + int ret = 0; + UINT32 timeout = 240000; + UINT32 mask, size, i, len = 0; + UINT32 *buf = NULL; + ULONG start = get_timer(0); + UINT32 fifo_depth = (((fifoth_val & RX_WMARK_MASK) >> + RX_WMARK_SHIFT) + 1) * 2; + + size = data->blocksize * data->blocks / 4; + if (data->flags == MMC_DATA_READ) + buf = (unsigned int *)data->dest; + else + buf = (unsigned int *)data->src; + + for (;;) { + mask = SDHC_REG_READ32(lg_ulChip, SDMMC_RINTSTS); + /* Error during data transfer. */ + if (mask & (SDMMC_DATA_ERR | SDMMC_DATA_TOUT)) { + DEBUG_MSG("%s: DATA ERROR!\n", __func__); + ret = -1; + break; + } + + if (size) { + len = 0; + if (data->flags == MMC_DATA_READ && + (mask & SDMMC_INTMSK_RXDR)) { + while (size) { + len = SDHC_REG_READ32(lg_ulChip, SDMMC_STATUS); + len = (len >> SDMMC_FIFO_SHIFT) & + SDMMC_FIFO_MASK; + len = min(size, len); + for (i = 0; i < len; i++) + *buf++ = SDHC_REG_READ32(lg_ulChip, SDMMC_DATA); + size = size > len ? (size - len) : 0; + } + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, + SDMMC_INTMSK_RXDR); + } else if (data->flags == MMC_DATA_WRITE && + (mask & SDMMC_INTMSK_TXDR)) { + while (size) { + len = SDHC_REG_READ32(lg_ulChip, SDMMC_STATUS); + len = fifo_depth - ((len >> + SDMMC_FIFO_SHIFT) & + SDMMC_FIFO_MASK); + len = min(size, len); + for (i = 0; i < len; i++) + SDHC_REG_WRITE32(lg_ulChip, SDMMC_DATA, + *buf++); + size = size > len ? (size - len) : 0; + } + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, + SDMMC_INTMSK_TXDR); + } + } + + /* Data arrived correctly. */ + if (mask & SDMMC_INTMSK_DTO) { + ret = 0; + break; + } + + /* Check for timeout. */ + if (get_timer(start) > timeout) { + DEBUG_MSG("%s: Timeout waiting for data!\n", + __func__); + ret = -1; + break; + } + } + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, mask); + + return ret; +} + +static int sdmmc_set_transfer_mode(struct mmc_data *data) +{ + unsigned long mode; + + mode = SDMMC_CMD_DATA_EXP; + if (data->flags & MMC_DATA_WRITE) + mode |= SDMMC_CMD_RW; + + return mode; +} + +static int mmc_send_cmd(struct mmc_cmd *cmd, struct mmc_data *data) +{ + int ret = 0, flags = 0, i; + unsigned int timeout = 500; + UINT32 retry = 100000; + UINT32 mask; + ULONG start = get_timer(0); + + while (SDHC_REG_READ32(lg_ulChip, SDMMC_STATUS) & SDMMC_BUSY) { + if (get_timer(start) > timeout) { + DEBUG_MSG("%s: Timeout on data busy\n", __func__); + return SDMMC_RW_CMDTIMEROUT; + } + } + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, SDMMC_INTMSK_ALL); + + if (data) { + SDHC_REG_WRITE32(lg_ulChip, SDMMC_BLKSIZ, data->blocksize); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_BYTCNT, + data->blocksize * data->blocks); + sdmmc_wait_reset(SDMMC_CTRL_FIFO_RESET); + } + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMDARG, cmd->cmdarg); + + if (data) + flags = sdmmc_set_transfer_mode(data); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -1; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + flags |= SDMMC_CMD_ABORT_STOP; + else + flags |= SDMMC_CMD_PRV_DAT_WAIT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + flags |= SDMMC_CMD_RESP_EXP; + if (cmd->resp_type & MMC_RSP_136) + flags |= SDMMC_CMD_RESP_LENGTH; + } + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= SDMMC_CMD_CHECK_CRC; + + flags |= (cmd->cmdidx | SDMMC_CMD_START | SDMMC_CMD_USE_HOLD_REG); + + DEBUG_MSG("Sending CMD%d\n",cmd->cmdidx); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMD, flags); + + for (i = 0; i < retry; i++) { + mask = SDHC_REG_READ32(lg_ulChip, SDMMC_RINTSTS); + if (mask & SDMMC_INTMSK_CDONE) { + if (!data) + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, mask); + break; + } + } + + if (i == retry) { + DEBUG_MSG("%s: Timeout.\n", __func__); + return SDMMC_RW_CMDTIMEROUT; + } + + if (mask & SDMMC_INTMSK_RTO) { + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + DEBUG_MSG("%s: Response Timeout.\n", __func__); + return SDMMC_RW_CMDTIMEROUT; + } else if (mask & SDMMC_INTMSK_RE) { + DEBUG_MSG("%s: Response Error.\n", __func__); + return -1; + } + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP3); + cmd->response[1] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP2); + cmd->response[2] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP1); + cmd->response[3] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP0); + } else { + cmd->response[0] = SDHC_REG_READ32(lg_ulChip, SDMMC_RESP0); + } + } + + if (data) { + ret = sdmmc_data_transfer(data); + } + + udelay(100); + + return ret; +} + +/* static void GetCardInfo(INT32 *CID, CARDTYPE ct) +{ + UINT16 Year; + UINT8 Month; + UINT8 CardName[7]; + UINT8 RevisionN; + UINT8 RevisionM; + + if(ct== MMC) + { + Month = (UINT8)((CID[0]&0x0000f000)>>12); + Year = (unsigned long)((CID[0]&0x00000f00)>>8)+1997; + RevisionN = (UINT8)((CID[1]&0x00f00000)>>20); + RevisionM = (UINT8)((CID[1]&0x000f0000)>>16); + CardName[0] = (UINT8)(CID[3]&0x000000ff); + CardName[1] = (UINT8)((CID[2]&0xff000000)>>24); + CardName[2] = (UINT8)((CID[2]&0x00ff0000)>>16); + CardName[3] = (UINT8)((CID[2]&0x0000ff00)>>8); + CardName[4] = (UINT8)(CID[2]&0x000000ff); + CardName[5] = (UINT8)((CID[1]&0xff000000)>>24); + CardName[6] = '\0'; + DEBUG_MSG("Product Name : %s\n", CardName); + DEBUG_MSG("Product revision : %d.%d\n", RevisionN, RevisionM); + DEBUG_MSG("Manufacturing date %d-%d\n", Month, Year); + } + else + { + Month = (UINT8)((CID[0]&0x00000f00)>>8); + Year = (unsigned long)((CID[0]&0x000ff000)>>12)+2000; + RevisionN = (UINT8)((CID[1]&0xf0000000)>>28); + RevisionM = (UINT8)((CID[1]&0x0f00000)>>24); + CardName[0] = (UINT8)(CID[3]&0x000000ff); + CardName[1] = (UINT8)((CID[2]&0xff000000)>>24); + CardName[2] = (UINT8)((CID[2]&0x00ff0000)>>16); + CardName[3] = (UINT8)((CID[2]&0x0000ff00)>>8); + CardName[4] = (UINT8)(CID[2]&0x000000ff); + CardName[5] = '\0'; + DEBUG_MSG("Product Name : %s\n", CardName); + DEBUG_MSG("Product revision : %d.%d\n", RevisionN, RevisionM); + DEBUG_MSG("Manufacturing date %d-%d\n", Month, Year); + } +} */ + +/* static UINT8 GetSD_SPEC(UINT32 *scr) +{ + UINT8 ss; + ss=(UINT8)(scr[0]&0x0000000f); + + return ss; +} + +static UINT8 GetMMC_SPEC(void) +{ + UINT8 ss; + ss = (sd_csd[3]>>26)&0x0000000f; + + return ss; +} */ + +INT32 data_tran_over(void) +{ + INT32 count_sd = 0; + INT32 tt; + + do + { + count_sd++; + if(count_sd > TIMEOUT_SD) + return -1; + + //tt = rSDMMC_RINTSTS; //Command done + tt = SDHC_REG_READ32(lg_ulChip, SDMMC_RINTSTS); + }while (!(tt & 0x00000008)); + + if((tt&0xBFC2) != 0) + { + DEBUG_MSG("This rSDMMC_RINTSTS = 0x%x\n", tt); + + + //rSDMMC_RINTSTS = 0x0000ffff; + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, 0x0000ffff); + return -1; + } + //rSDMMC_RINTSTS = 0x0000ffff; + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, 0x0000ffff); + + return 0; // 0 means successful +} + +static INT32 mmc_go_idle(void) +{ + struct mmc_cmd cmd; + int err; + + udelay(1000); + + cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_NONE; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + udelay(2000); + + return 0; +} + +static int mmc_set_blocklen(int len) +{ + struct mmc_cmd cmd; + int err; + + cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = len; + + err = mmc_send_cmd(&cmd, NULL); + + return err; +} + + +static int sd_select_bus_width(int w) +{ + int err; + struct mmc_cmd cmd; + + if ((w != 4) && (w != 1)) + return -1; + + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = sd_rca << 16; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; + cmd.resp_type = MMC_RSP_R1; + if (w == 4) + cmd.cmdarg = 2; + else if (w == 1) + cmd.cmdarg = 0; + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + return 0; +} + +/* static UINT8 get_width(UINT32 *scr) +{ + if((scr[0]&0x00000f00) == 0x00000500) + return 4; + else + return 1; +} */ + +static int sdmmc_setup_bus(UINT32 freq) +{ + UINT32 div, status; + int timeout = 10000; + unsigned long sclk = SDMMC_BUS_CLK; + + div = sclk / freq; + if (sclk % freq && sclk > freq) + div += 1; + + div = (sclk != freq) ? DIV_ROUND_UP(div, 2) : 0; + +#if 0 + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); +#endif + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKENA, 0); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKSRC, 0); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKDIV, div); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMD, SDMMC_CMD_PRV_DAT_WAIT | + SDMMC_CMD_UPD_CLK | SDMMC_CMD_START); + + do { + status = SDHC_REG_READ32(lg_ulChip, SDMMC_CMD); + if (timeout-- < 0) { + DEBUG_MSG("%s: Timeout!\n", __func__); + return -1; + } + } while (status & SDMMC_CMD_START); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CLKENA, SDMMC_CLKEN_ENABLE | + SDMMC_CLKEN_LOW_PWR); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CMD, SDMMC_CMD_PRV_DAT_WAIT | + SDMMC_CMD_UPD_CLK | SDMMC_CMD_START); + + timeout = 10000; + do { + status = SDHC_REG_READ32(lg_ulChip, SDMMC_CMD); + if (timeout-- < 0) { + DEBUG_MSG("%s: Timeout!\n", __func__); + return -1; + } + } while (status & SDMMC_CMD_START); + + return 0; +} + +static int sdmmc_hw_init() +{ + UINT32 fifo_size; + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_PWREN, 1); + + if (!sdmmc_wait_reset(SDMMC_RESET_ALL)) { + DEBUG_MSG("%s[%d] Fail-reset!!\n", __func__, __LINE__); + return -1; + } + + /* Enumerate at 400KHz */ + sdmmc_setup_bus(INIT_CLOCK); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_RINTSTS, 0xFFFFFFFF); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_INTMASK, 0); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_TMOUT, 0xFFFFFFFF); + + SDHC_REG_WRITE32(lg_ulChip, SDMMC_IDINTEN, 0); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_BMOD, 1); + + fifo_size = SDHC_REG_READ32(lg_ulChip, SDMMC_FIFOTH); + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | + TX_WMARK(fifo_size / 2); + SDHC_REG_WRITE32(lg_ulChip, SDMMC_FIFOTH, fifoth_val); + + return 0; +} + +static int mmc_send_if_cond() +{ + struct mmc_cmd cmd; + int err; + + cmd.cmdidx = SD_CMD_SEND_IF_COND; + /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ + cmd.cmdarg = (1 << 8) | 0xaa; + cmd.resp_type = MMC_RSP_R7; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + if ((cmd.response[0] & 0xff) != 0xaa) + return -1; + else + Spec = Ver2; + + return 0; +} + +static int sd_send_op_cond() +{ + int timeout = 1000; + int err; + struct mmc_cmd cmd; + + while (1) { + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + + /* + * Most cards do not answer if some reserved bits + * in the ocr are set. However, Some controller + * can set bit 7 (reserved for low voltages), but + * how to manage low voltages SD card is not yet + * specified. + */ + cmd.cmdarg = mmc_voltages & 0xff8000; + + if (Spec == Ver2) + cmd.cmdarg |= OCR_HCS; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + if (cmd.response[0] & OCR_BUSY) + break; + + if (timeout-- <= 0) + return -1; + + udelay(1000); + } + + sd_ocr = cmd.response[0]; + if ((sd_ocr & OCR_HCS) == OCR_HCS) + Capacity = High; + sd_rca = 0; + + return 0; +} + +static int mmc_send_op_cond_iter(int use_arg) +{ + struct mmc_cmd cmd; + int err; + + cmd.cmdidx = MMC_CMD_SEND_OP_COND; + cmd.resp_type = MMC_RSP_R3; + cmd.cmdarg = 0; + if (use_arg) + cmd.cmdarg = OCR_HCS | + (mmc_voltages & + (sd_ocr & OCR_VOLTAGE_MASK)) | + (sd_ocr & OCR_ACCESS_MODE); + + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + sd_ocr = cmd.response[0]; + return 0; +} + +static int mmc_send_op_cond() +{ + int err, i; + + /* Some cards seem to need this */ + mmc_go_idle(); + + /* Asking to the card its capabilities */ + for (i = 0; i < 2; i++) { + err = mmc_send_op_cond_iter(i != 0); + if (err) + return err; + + /* exit if not busy (flag seems to be inverted) */ + if (sd_ocr & OCR_BUSY) + break; + } + + return 0; +} + +static int mmc_complete_op_cond() +{ + int timeout = 1000; + ULONG start; + int err; + + if (!(sd_ocr & OCR_BUSY)) { + /* Some cards seem to need this */ + mmc_go_idle(); + + start = get_timer(0); + while (1) { + err = mmc_send_op_cond_iter(1); + if (err) + return err; + if (sd_ocr & OCR_BUSY) + break; + if (get_timer(start) > timeout) + return -1; + udelay(100); + } + } + + if ((sd_ocr & OCR_HCS) == OCR_HCS); + Capacity = High; + sd_rca = 1; + + return 0; +} + +int mmc_send_status(int timeout) +{ + struct mmc_cmd cmd; + int err, retries = 5; + + cmd.cmdidx = MMC_CMD_SEND_STATUS; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = sd_rca << 16; + + while (1) { + err = mmc_send_cmd(&cmd, NULL); + if (!err) { + if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && + (cmd.response[0] & MMC_STATUS_CURR_STATE) != + MMC_STATE_PRG) + break; + + if (cmd.response[0] & MMC_STATUS_MASK) { + return -1; + } + } else if (--retries < 0) + return err; + + if (timeout-- <= 0) + break; + + udelay(1000); + } + + if (timeout <= 0) { + return -1; + } + + return 0; +} + +int mmc_switch(UINT8 set, UINT8 index, UINT8 value) +{ + struct mmc_cmd cmd; + int timeout = 1000; + int retries = 3; + int ret; + + cmd.cmdidx = MMC_CMD_SWITCH; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | + (index << 16) | + (value << 8); + + while (retries > 0) { + ret = mmc_send_cmd(&cmd, NULL); + + /* Waiting for the ready status */ + if (!ret) { + ret = mmc_send_status(timeout); + return ret; + } + + retries--; + } + + return ret; +} + +static int mmc_startup() +{ + int err; + UINT mult, freq; + UINT64 cmult, csize; + struct mmc_cmd cmd; + + /* Put the Card in Identify Mode */ + cmd.cmdidx = MMC_CMD_ALL_SEND_CID; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = 0; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + memcpy(sd_cid, cmd.response, 16); + + /* + * For MMC cards, set the Relative Address. + * For SD cards, get the Relatvie Address. + * This also puts the cards into Standby State + */ + cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; + cmd.cmdarg = sd_rca << 16; + cmd.resp_type = MMC_RSP_R6; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + if (CardType == SD) + sd_rca = (cmd.response[0] >> 16) & 0xffff; + + /* Get the Card-Specific Data */ + cmd.cmdidx = MMC_CMD_SEND_CSD; + cmd.resp_type = MMC_RSP_R2; + cmd.cmdarg = sd_rca << 16; + + err = mmc_send_cmd(&cmd, NULL); + + if (err) + return err; + + sd_csd[0] = cmd.response[0]; + sd_csd[1] = cmd.response[1]; + sd_csd[2] = cmd.response[2]; + sd_csd[3] = cmd.response[3]; + + /* divide frequency by 10, since the mults are 10x bigger */ + freq = fbase[(cmd.response[0] & 0x7)]; + mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; + read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); + + if (CardType == SD)//tf ka + write_bl_len = read_bl_len; + else//emmc + write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); + + if (Capacity == High) { + csize = (sd_csd[1] & 0x3f) << 16 + | (sd_csd[2] & 0xffff0000) >> 16; + cmult = 8; + } else { + csize = (sd_csd[1] & 0x3ff) << 2 + | (sd_csd[2] & 0xc0000000) >> 30; + cmult = (sd_csd[2] & 0x00038000) >> 15; + } + capacity_user = (csize + 1) << (cmult + 2); + capacity_user *= read_bl_len; + if (read_bl_len > MMC_MAX_BLOCK_LEN) + read_bl_len = MMC_MAX_BLOCK_LEN; + + if (write_bl_len > MMC_MAX_BLOCK_LEN) + write_bl_len = MMC_MAX_BLOCK_LEN; + + erase_grp_size = 0x400; + + /* Select the card, and put it into Transfer Mode */ + cmd.cmdidx = MMC_CMD_SELECT_CARD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = sd_rca << 16; + err = mmc_send_cmd(&cmd, NULL); + if (err) + return err; + + mmc_set_blocklen(read_bl_len); + sdmmc_setup_bus(freq * mult); + if (CardType == SD) + { + err = sd_select_bus_width(4); + SDHC_REG_WRITE32(0, SDMMC_CTYPE, 0x00000001); + } + else + { + err = mmc_switch(EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_4); + SDHC_REG_WRITE32(0, SDMMC_CTYPE, 0x00000001); + } + if (err) + return err; + + return 0; +} + +INT32 sd_mmc_card_identify(void) +{ + INT32 ret; + INT32 op_cond_pending = 0; + + CardType = SD; + Capacity = Standard; //need to re_initialize in case of MMC card + + sdmmc_hw_init(); + + // set the controller 1bit mode + SDHC_REG_WRITE32(lg_ulChip, SDMMC_CTYPE, 0x00000000); + + if (mmc_go_idle()) + return -1; + + /* Test for SD version 2 */ + mmc_send_if_cond(); + + if (g_MatchSdVcc) + ret = sd_send_op_cond(); + else + ret = SDMMC_RW_CMDTIMEROUT; + + if (ret == SDMMC_RW_CMDTIMEROUT) + { + /* If the command timed out, we check for an MMC card */ + ret = mmc_send_op_cond(); + if (ret) { + DEBUG_MSG("Card did not respond to voltage select!\n"); + return -1; + } + CardType = MMC; + op_cond_pending = 1; + } + + if (op_cond_pending) + mmc_complete_op_cond(); + + return 0; +} + +static int mmc_read_blocks(void *dst, ULONG start, ULONG blkcnt) +{ + struct mmc_cmd cmd; + struct mmc_data data; + + if (blkcnt > 1) + cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; + + if (Capacity == High) + cmd.cmdarg = start; + else + cmd.cmdarg = start * read_bl_len; + + cmd.resp_type = MMC_RSP_R1; + + data.dest = dst; + data.blocks = blkcnt; + data.blocksize = read_bl_len; + data.flags = MMC_DATA_READ; + + if (mmc_send_cmd(&cmd, &data)) + return 0; + + if (blkcnt > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + if (mmc_send_cmd(&cmd, NULL)) { + return 0; + } + } + + return blkcnt; +} + +static INT32 SD_Identify(UINT32 Unit) +{ + INT32 ret; + + ret = sd_mmc_card_identify(); + +// if(ret) +// DEBUG_MSG("SD_Identify fails\n"); + + return ret; +} + +INT32 SD_Init(UINT32 Unit) +{ + INT32 ret; + + ret = mmc_startup(); + + return ret; +} + +INT32 SD_ReadSector(UINT32 Unit,ULONG Sector,UINT8 *pBuffer, ULONG Count) +{ + INT32 ret; + + ret = mmc_read_blocks((UINT32 *)pBuffer, Sector, Count); + + return ret; +} + +INT32 InitSDMMCCard() +{ + INT32 result = -1; + + if (!SD_Identify(lg_ulChip)) + { + SendUartString("SDMMC card successfully\n"); + if (!SD_Init(lg_ulChip)) + { + result = 0; + } + } + else + { + SendUartString("SDMMC card identify failed\n"); + } + + return result; +} + +int IsCardExist(void) +{ + return !(SDHC_REG_READ32(lg_ulChip, SDMMC_CDETECT) & 0x1); +} + +#ifdef CHECK_FISRT_FILE +static BYTE *g_rBuffer = g_fs.win; + +static INT32 check_fatfs(UINT8 *buf) +{ + if (!memcmp(&buf[BS_FilSysType], "FAT", 3)) /* Check FAT signature */ + return 0; + if (!memcmp(&buf[BS_FilSysType32], "FAT32", 5) && !(buf[BPB_ExtFlags] & 0x80)) + return 0; + + return 1; +} + +static INT32 check_loaderfile(void) +{ + BYTE fmt, *tbl; + DWORD bootsect = 0, fatsize, fatbase, totalsect, csize, n_rootdir, maxclust, dirbase; + INT i; + + if (mmc_read_blocks((UINT32 *)g_rBuffer, 0, 1) != 1) + return 1; + + fmt = check_fatfs(g_rBuffer); +#if 0 + if (fmt == 1) { /* Not an FAT boot record, it may be patitioned */ + /* Check a partition listed in top of the partition table */ + tbl = &g_rBuffer[MBR_Table]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + if (mmc_read_blocks((UINT32 *)g_rBuffer, bootsect, 1) != 1) + return 1; + fmt = check_fatfs(g_rBuffer); /* Check the partition */ + } + } +#else + /* Check a first fat partition listed in partition table */ + for(i = 0; i < 4; i++) { + tbl = &g_rBuffer[MBR_Table + i * 16]; /* Partition table */ + if (tbl[4] == 0x01 || tbl[4] == 0x04 || tbl[4] == 0x06 || tbl[4] == 0x0B || + tbl[4] == 0x0C || tbl[4] == 0x0E) { /* Is the FAT partition? */ + bootsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + if (mmc_read_blocks((UINT32 *)g_rBuffer, bootsect, 1) != 1) + return 1; + fmt = check_fatfs(g_rBuffer); /* Check the partition */ + break; + } + } +#endif + if (fmt || LD_WORD(&g_rBuffer[BPB_BytsPerSec]) != 512) /* No valid FAT patition is found */ + { + SendUartString("Not found fatfs.\r\n"); + return 2; + } + + /* Initialize the file system object */ + fatsize = LD_WORD(&g_rBuffer[BPB_FATSz16]); /* Number of sectors per FAT */ + if (!fatsize) fatsize = LD_DWORD(&g_rBuffer[BPB_FATSz32]); + fatsize *= g_rBuffer[BPB_NumFATs]; /* (Number of sectors in FAT area) */ + fatbase = bootsect + LD_WORD(&g_rBuffer[BPB_RsvdSecCnt]); /* FAT start sector (lba) */ + csize = g_rBuffer[BPB_SecPerClus]; /* Number of sectors per cluster */ + n_rootdir = LD_WORD(&g_rBuffer[BPB_RootEntCnt]); /* Nmuber of root directory entries */ + totalsect = LD_WORD(&g_rBuffer[BPB_TotSec16]); /* Number of sectors on the file system */ + if (!totalsect) totalsect = LD_DWORD(&g_rBuffer[BPB_TotSec32]); + maxclust = (totalsect /* max_clust = Last cluster# + 1 */ + - LD_WORD(&g_rBuffer[BPB_RsvdSecCnt]) - fatsize - n_rootdir / (512/32) + ) / csize + 2; + + fmt = FS_FAT12; /* Determine the FAT sub type */ + if (maxclust >= 0xFF7) fmt = FS_FAT16; + if (maxclust >= 0xFFF7) fmt = FS_FAT32; + + dirbase = fatbase + fatsize; /* Root directory start sector (lba) */ + + if (fmt == FS_FAT32) + { + DWORD clust = LD_DWORD(&g_rBuffer[BPB_RootClus]); + if(clust <= maxclust) + dirbase += csize * (clust - 2); /* Root directory start cluster */ + } + + if (mmc_read_blocks((UINT32 *)g_rBuffer, dirbase, 1) != 1) + return 1; + + //оʱһļλڵڶĿ¼ + if (!memcmp(&g_rBuffer[0], "ARKSDLDRBIN", 11) || + !memcmp(&g_rBuffer[32], "ARKSDLDRBIN", 11) + ) + { + return 0; + } + //Win10¸ʽԶһSystem Volume InformationĿ¼ + else if (!memcmp(&g_rBuffer[64], "SYSTEM~1 ", 11)) + { + if (!memcmp(&g_rBuffer[96], "ARKSDLDRBIN", 11) || + !memcmp(&g_rBuffer[128], "ARKSDLDRBIN", 11)) + return 0; + } + //о + else if (!memcmp(&g_rBuffer[96], "SYSTEM~1 ", 11)) + { + if (!memcmp(&g_rBuffer[128], "ARKSDLDRBIN", 11) || + !memcmp(&g_rBuffer[160], "ARKSDLDRBIN", 11)) + return 0; + } + else + { + SendUartString("Not found ARKSDLDR.bin.\r\n"); + return 3; + } + + return -1; +} +#endif + +extern void UpdateFromMedia(int drv); +void updateFromSD(int chipid) +{ + lg_ulChip = chipid; + g_MatchSdVcc = 1; + select_sd_pad(lg_ulChip); + + if(!IsCardExist()) + { + SendUartString("Card is not in the slot.\r\n"); + return; + } + else + { + if(InitSDMMCCard()) + { + SendUartString("InitSDMMCCard fail.\r\n"); + return; + } + } + + UpdateFromMedia(SDMMC); +} + +// for fatfs's sd interface +static unsigned long sdmmc_disk_size; +#define SECOTR_SIZE 512 + +int MMC_disk_initialize() +{ + UINT64 secotrs; + + /* if(InitSDMMCCard() < 0) + { + SendUartString("disk mount fail!\r\n"); + return -1; + } + else + SendUartString("disk mount success!\r\n"); */ + + secotrs = capacity_user / SECOTR_SIZE; + if(secotrs == -1) return -1; + //֧4G + if(secotrs * SECOTR_SIZE > (unsigned int)-1 ) + secotrs = ((unsigned int)-1)/SECOTR_SIZE; + sdmmc_disk_size = secotrs * SECOTR_SIZE; + + return 0; +} + +int MMC_disk_read(void *buff, DWORD sector, BYTE count) +{ + return SD_ReadSector(0, sector, buff, count); +} + +int MMC_disk_ioctl(BYTE ctrl, void *buff) +{ + switch(ctrl) + { + case CTRL_SYNC: + break; + case GET_SECTOR_COUNT: + *(DWORD*)buff = sdmmc_disk_size / SECOTR_SIZE; + break; + case GET_BLOCK_SIZE: + *(DWORD*)buff = 1; + break; + default: + return -1; + } + return 0; +} +static ulong mmc_erase_t(ulong start, lbaint_t blkcnt) +{ + struct mmc_cmd cmd; + ulong end; + int err, start_cmd, end_cmd; + + if (Capacity == High) { + end = start + blkcnt - 1; + } else { + end = (start + blkcnt - 1) * write_bl_len; + start *= write_bl_len; + } + + if (0) { + start_cmd = SD_CMD_ERASE_WR_BLK_START; + end_cmd = SD_CMD_ERASE_WR_BLK_END; + } else { + start_cmd = MMC_CMD_ERASE_GROUP_START; + end_cmd = MMC_CMD_ERASE_GROUP_END; + } + + cmd.cmdidx = start_cmd; + cmd.cmdarg = start; + cmd.resp_type = MMC_RSP_R1; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = end_cmd; + cmd.cmdarg = end; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = MMC_CMD_ERASE; + cmd.cmdarg = MMC_ERASE_ARG; + cmd.resp_type = MMC_RSP_R1b; + + err = mmc_send_cmd(&cmd, NULL); + if (err) + goto err_out; + + return 0; + +err_out: + SendUartString("mmc erase failed\n"); + return err; +} + +ulong mmc_berase( lbaint_t start, lbaint_t blkcnt) +{ + int err = 0; + lbaint_t blk = 0, blk_r = 0; + int timeout = 1000; + + while (blk < blkcnt) { + if (0/*IS_SD(mmc) && mmc->ssr.au*/) { + ; + //blk_r = ((blkcnt - blk) > mmc->ssr.au) ? + // mmc->ssr.au : (blkcnt - blk); + } else { + blk_r = ((blkcnt - blk) > erase_grp_size) ? + erase_grp_size : (blkcnt - blk); + } + err = mmc_erase_t(start + blk, blk_r); + if (err) + break; + + blk += blk_r; + + /* Waiting for the ready status */ + if (mmc_send_status(timeout)) + return 0; + } + + return blk; +} + +static ulong mmc_write_blocks(lbaint_t start, + lbaint_t blkcnt, const void *src) +{ + struct mmc_cmd cmd; + struct mmc_data data; + int timeout = 1000; + +/* if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) { + printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", + start + blkcnt, mmc_get_blk_desc(mmc)->lba); + return 0; + }*/ + + if (blkcnt == 0) + return 0; + else if (blkcnt == 1) + cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; + else + cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; + + if (Capacity == High) + cmd.cmdarg = start; + else + cmd.cmdarg = start * write_bl_len; + + cmd.resp_type = MMC_RSP_R1; + + data.src = src; + data.blocks = blkcnt; + data.blocksize = write_bl_len; + data.flags = MMC_DATA_WRITE; + + if (mmc_send_cmd(&cmd, &data)) { + SendUartString("mmc write failed\n"); + return 0; + } + + /* SPI multiblock writes terminate using a special + * token, not a STOP_TRANSMISSION request. + */ + if (blkcnt > 1) { + cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + if (mmc_send_cmd(&cmd, NULL)) { + SendUartString("mmc fail to send stop cmd\n"); + return 0; + } + } + + /* Waiting for the ready status */ + if (mmc_send_status(timeout)) + return 0; + + return blkcnt; +} + +ulong mmc_bwrite(lbaint_t start, lbaint_t blkcnt, + const void *src) +{ + lbaint_t cur, blocks_todo = blkcnt; + unsigned char *buf = (unsigned char*)src; + + + if (mmc_set_blocklen(read_bl_len)) + return 0; + + do { + cur = (blocks_todo > CONFIG_SYS_MMC_MAX_BLK_COUNT) ? + CONFIG_SYS_MMC_MAX_BLK_COUNT : blocks_todo; + if (mmc_write_blocks(start, cur, buf) != cur) + return 0; + blocks_todo -= cur; + start += cur; + buf += cur * write_bl_len; + } while (blocks_todo > 0); + + return blkcnt; +} + +unsigned int mmc_write(void *buf, unsigned int offset, unsigned int size, int show_progress) +{ + int blkstart, blkcnt; + unsigned int *pbuf = (unsigned int *)buf; + + if(offset % write_bl_len) + blkstart = offset / write_bl_len + 1; + else + blkstart = offset / write_bl_len; + + if(size % write_bl_len) + blkcnt = size / write_bl_len + 1; + else + blkcnt = size / write_bl_len; + + mmc_bwrite(blkstart,blkcnt, pbuf); + + if (show_progress) + update_progress_set(100); + + return 0; +} + +ulong mmc_bread(lbaint_t start, lbaint_t blkcnt, void *dst) +{ + lbaint_t cur, blocks_todo = blkcnt; + unsigned char *buf = (unsigned char*)dst; + + if (blkcnt == 0) + return 0; + + if (mmc_set_blocklen(read_bl_len)) { + SendUartString("mmc_bread: Failed to set blocklen\n"); + return 0; + } + + do { + cur = (blocks_todo > CONFIG_SYS_MMC_MAX_BLK_COUNT) ? + CONFIG_SYS_MMC_MAX_BLK_COUNT : blocks_todo; + + if (mmc_read_blocks(buf, start, cur) != cur) { + SendUartString("mmc_bread: Failed to read blocks\n"); + return 0; + } + blocks_todo -= cur; + start += cur; + buf += cur * read_bl_len; + } while (blocks_todo > 0); + + return blkcnt; +} + +unsigned int mmc_read(void *buf, unsigned int offset, unsigned int size) +{ + int blkstart, blkcnt; + unsigned char *pbuf = (unsigned char *)buf; + unsigned char *tempbuf = (unsigned char *)(0x21000000); + unsigned int inoffset = 0; + unsigned int readsize = 0; + + blkstart = offset/read_bl_len; + inoffset = offset - blkstart*read_bl_len; + readsize = size + inoffset; + if(readsize%read_bl_len) + blkcnt = (readsize/read_bl_len) +1; + else + blkcnt = readsize/read_bl_len; + mmc_bread(blkstart,blkcnt, tempbuf); + memcpy(pbuf,tempbuf+inoffset,size); + + return 0; +} + +void EmmcClkinit(void) +{ + unsigned int regval = 0; + regval = rSYS_SDMMC_CLK_CFG; + regval &= ~(0x1FF << 0); + regval |= (1 << 7) | (1 << 6) | (4 << 0); + rSYS_SDMMC_CLK_CFG = regval; +} + +void Emmcinit(int chipid) +{ + lg_ulChip = chipid; + g_MatchSdVcc = 1; + EmmcClkinit(); + select_sd_pad(lg_ulChip); + if(InitSDMMCCard()) + { + SendUartString("InitSDMMCCard fail.\r\n"); + return; + } +} + +void bootFromEmmc(int chipid) +{ + void (*funPtr)(void); + UINT32 *buf = (UINT32*)IMAGE_ENTRY; + UpFileHeader *header; + UpFileInfo *appfile; + UINT32 startoffset; +#ifdef MMU_ENABLE + UINT32 appsize; +#endif + + SysInfo *sysinfo = GetSysInfo(); + + PrintVariableValueHex("image_offset", sysinfo->image_offset); + startoffset = sysinfo->image_offset; + mmc_read(buf, startoffset, 512); + header = (UpFileHeader*)buf; + appfile = &header->files[0]; + if (appfile->offset & (0x400 - 1)) { + SendUartString("\nImage positon is not align to flash pagesize, can't load.\r\n"); + while(1); + } + + if (sysinfo->app_size) + appsize = sysinfo->app_size; + else + appsize = appfile->size; + + mmc_read(buf, appfile->offset + sysinfo->image_offset, appsize); + +#ifdef MMU_ENABLE + CP15_clean_dcache_for_dma(IMAGE_ENTRY, IMAGE_ENTRY + appsize); +#endif + + funPtr = (void (*)(void))IMAGE_ENTRY; + funPtr(); + +} + +int EmmcBurn(void *buf, unsigned int offset, unsigned int size, int show_progress) +{ + int blkstart, blkcnt; + unsigned int *pbuf = (unsigned int *)buf; + + if(offset % write_bl_len) + blkstart = offset / write_bl_len + 1; + else + blkstart = offset / write_bl_len; + + if(size % write_bl_len) + blkcnt = size / write_bl_len + 1; + else + blkcnt = size / write_bl_len; + + //mmc_berase(blkstart, blkcnt); + mmc_bwrite(blkstart, blkcnt, pbuf); + + if (show_progress) + update_progress_set(100); + + return 0; +} + +void EmmcWriteSysInfo(SysInfo *info) +{ + EmmcBurn(info, SYSINFOB_OFFSET, sizeof(SysInfo), 0); + EmmcBurn(info, SYSINFOA_OFFSET, sizeof(SysInfo), 0); +} + +int EmmcReadSysInfo(SysInfo *info) +{ + UINT32 *buf = (UINT32*)IMAGE_ENTRY; + int startoffset; + UINT32 checksum; + UINT32 calc_checksum; + + startoffset = SYSINFOA_OFFSET; + + mmc_read(buf,startoffset, sizeof(SysInfo)); + checksum = *(UINT32*)(IMAGE_ENTRY + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, (void*)IMAGE_ENTRY, sizeof(SysInfo)); + return 0; + } + + buf = (UINT32*)IMAGE_ENTRY; + startoffset = SYSINFOB_OFFSET; + + mmc_read(buf,startoffset, sizeof(SysInfo)); + + checksum = *(UINT32*)(IMAGE_ENTRY + sizeof(SysInfo) - 4); + calc_checksum = xcrc32((unsigned char*)IMAGE_ENTRY, sizeof(SysInfo) - 4, 0xffffffff); + if (calc_checksum == checksum) { + memcpy(info, (void*)IMAGE_ENTRY, sizeof(SysInfo)); + return 0; + } + + return -1; +} + +#if DEVICE_TYPE_SELECT == EMMC_FLASH +unsigned int EmmcGetUpfileOffset(int type) +{ + SysInfo *sysinfo = GetSysInfo(); + + if (type == UPFILE_TYPE_WHOLE) { + if (sysinfo->image_offset == IMAGE_OFFSET) + sysinfo->image_offset = IMAGEB_OFFSET; + else + sysinfo->image_offset = IMAGE_OFFSET; + return sysinfo->image_offset; + } else if (type == UPFILE_TYPE_FIRSTLDR) { + if (sysinfo->loader_offset == LOADER_OFFSET) + sysinfo->loader_offset = LOADERB_OFFSET; + else + sysinfo->loader_offset = LOADER_OFFSET; + return sysinfo->loader_offset; + } else if (type == UPFILE_TYPE_STEPLDR) { + if (sysinfo->stepldr_offset == STEPLDRA_OFFSET) + sysinfo->stepldr_offset = STEPLDRB_OFFSET; + else + sysinfo->stepldr_offset = STEPLDRA_OFFSET; + return sysinfo->stepldr_offset; + } else { + unsigned int buf[512]; + UpFileHeader *header; + UpFileInfo *appfile; + unsigned int offset; + int i; + + mmc_read(buf, sysinfo->image_offset, 512); + header = (UpFileHeader*)buf; + if (header->magic != MKTAG('U', 'P', 'D', 'F')) { + SendUartString("old update file isn't found in flash, can't support module update.\n"); + return 0xffffffff; + } + for (i = 0; i < header->filenum; i++) { + appfile = &header->files[i]; + if ((appfile->magic == UPFILE_APP_MAGIC && type == UPFILE_TYPE_APP) || + (appfile->magic == MKTAG('R', 'O', 'M', 'A') && type == UPFILE_TYPE_RESOURCE) || + (appfile->magic == MKTAG('B', 'A', 'N', 'I') && type == UPFILE_TYPE_ANIMATION)) { + offset = appfile->offset; + if (offset & (512 - 1)) { + SendUartString("offset isn't align to sector erase size, can't support module update.\n"); + return 0xffffffff; + } + return offset + sysinfo->image_offset; + } + } + } + + return 0xffffffff; +} +#endif diff --git a/A58-STEPLDR/Src/sdmmc.h b/A58-STEPLDR/Src/sdmmc.h new file mode 100644 index 00000000..ac8eb928 --- /dev/null +++ b/A58-STEPLDR/Src/sdmmc.h @@ -0,0 +1,303 @@ +/* +********************************************************************** +Copyright (c)2007 Arkmicro Technologies Inc. All Rights Reserved +Filename: sdmmc.h +Version : 1.1 +Date : 2008.01.08 +Author : wx(Modify by Salem) +Abstract: ark1610 soc sd driver +History : +*********************************************************************** +*/ +#ifndef SDMMC_H +#define SDMMC_H + + +#define SD_DEBUG 0 + + +typedef unsigned long ulong; +typedef ulong lbaint_t; + +#define SDMMC_RW_SUCCES 0 +#define SDMMC_RW_TIMEOUT -1 +#define SDMMC_RW_DMAREAD_FAIL -2 +#define SDMMC_RW_DMAWRITE_FAIL -3 +#define SDMMC_RW_CMDTIMEROUT -4 + + +#define PWREN_ON 0x00000000 //turn on all card power +#define PWREN_OFF 0xFFFFFFFF //turn off all card power +#define CLK_CLKEN 0x0000ffff // +#define CLK_CLKDIS 0x00000000 // disable clk +#define CLK_DIV_INITIAL 0x00000010 //initial choose frequency +#define CLK_DIV_NORMAL 0x00000000 //data transfers clk frequency +#define CLK_SRC 0x00000000 // +#define CMD_CHANG_CLK 0x80202000 //chang clk +#define CMD_INITIAL_CLK 0x80008000 //initial clk before work +#define CMD0_GO_IDLE 0x80000000 //go idle +#define CMD1_MATCH_VCC 0x80000041 //turn on for match vcc +#define CMD2_CID 0x800001c2 //initial card get CID +#define CMD3_RCA 0x80000143 //comfire RCA to card +#define CMD6_SWTICH 0x80000346 //switch function +#define CMD7_SELECT_CARD 0x80000147 //select card +#define CMD8_SPEC 0x80000048 //confire specfic +#define CMD9_CSD 0x800001c9 //get CSD +#define CMD10_CID 0x800001ca //get CID at transfers +#define CMD12_STOP_STEARM 0x8000004c //stop block transfers +#define CMD13_STATUS_CARD 0x8000014D //get card status +#define CMD15_INACTIVE 0x8000000F //make card to inactive +#define CMD16_SET_BLOCKLEN 0x80000150 //set card block length +#define CMD17_READ_SINGLE 0x80000351 //single block read +#define CMD18_READ_MUL 0x80001352 //multipe block read +#define CMD23_PRE_ERASE 0x80000157 //pre erase for write +#define CMD24_WRITE_SINGLE 0x80000758 //single block write +#define CMD25_WRITE_MUL 0x80000759 //multipe block write +#define CMD27_PROG_CSD 0x8000065b //programme csd +#define CMD28_SET_PROTECT 0x8000015c //set protect +#define CMD29_CLR_PROTECT 0x8000015d //clearn protect +#define CMD30_SEND_WRITE 0x8000025e //get the status about protect +#define CMD32_ERASESD_START 0x80000160 //set start erase SD card address +#define CMD33_ERASESD_END 0x80000161 //set end erase SD card address +#define CMD38_ERASE 0x80000166 //confirm erase +#define CMD41_MATCH_VCC 0x80000169 //FOR SD +#define CMD55_APP 0x80000177 //APP CMD +#define ACMD6_WID 0x80000146 //set bus width +#define ACMD13_GET_STATUS 0x8000024d //get status 512 bit +#define ACMD42_DISCON_DATA3 0x8000016a //make data3 disconnect +#define ACMD51_GET_CSR 0x80000273 //get card csr +//=======================MMC set bus========================== +#define CMD6_SWITH 0x80000446 //set bus width +//================================================ + +#define MMC_ERASE_ARG 0x00000000 + +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SWITCH 6 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_EXT_CSD 8 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_SEND_TUNING_BLOCK 19 +#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21 +#define MMC_CMD_SET_BLOCK_COUNT 23 +#define MMC_CMD_WRITE_SINGLE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_ERASE_GROUP_START 35 +#define MMC_CMD_ERASE_GROUP_END 36 +#define MMC_CMD_ERASE 38 +#define MMC_CMD_APP_CMD 55 +#define MMC_CMD_SPI_READ_OCR 58 +#define MMC_CMD_SPI_CRC_ON_OFF 59 +#define MMC_CMD_RES_MAN 62 + +#define MMC_CMD62_ARG1 0xefac62ec +#define MMC_CMD62_ARG2 0xcbaea7 + + +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH_FUNC 6 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_SWITCH_UHS18V 11 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_SD_STATUS 13 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ + MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + +#define OCR_BUSY 0x80000000 +#define OCR_HCS 0x40000000 +#define OCR_S18R 0x1000000 +#define OCR_VOLTAGE_MASK 0x007FFF80 +#define OCR_ACCESS_MODE 0x60000000 + +#define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_SWITCH_ERROR (1 << 7) +#define MMC_STATUS_RDY_FOR_DATA (1 << 8) +#define MMC_STATUS_CURR_STATE (0xf << 9) +#define MMC_STATUS_ERROR (1 << 19) + +#define MMC_STATE_PRG (7 << 9) + +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte + addressed by index which are + 1 in value field */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte + addressed by index, which are + 1 in value field */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ + +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SWITCH 1 + +/* + * EXT_CSD fields + */ +#define EXT_CSD_ENH_START_ADDR 136 /* R/W */ +#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ +#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ +#define EXT_CSD_PARTITION_SETTING 155 /* R/W */ +#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ +#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ +#define EXT_CSD_WR_REL_PARAM 166 /* R */ +#define EXT_CSD_WR_REL_SET 167 /* R/W */ +#define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_BOOT_BUS_WIDTH 177 +#define EXT_CSD_PART_CONF 179 /* R/W */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ + +/* + * EXT_CSD field definitions + */ + +#define EXT_CSD_CMD_SET_NORMAL (1 << 0) +#define EXT_CSD_CMD_SET_SECURE (1 << 1) +#define EXT_CSD_CMD_SET_CPSECURE (1 << 2) + +#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) + +#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ + /* SDR mode @1.8V I/O */ +#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ + /* SDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ + EXT_CSD_CARD_TYPE_HS200_1_2V) + +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ +#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ +#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ + +#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ +#define EXT_CSD_TIMING_HS 1 /* HS */ +#define EXT_CSD_TIMING_HS200 2 /* HS200 */ + +#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) +#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) +#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) +#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) + +#define EXT_CSD_BOOT_ACK(x) (x << 6) +#define EXT_CSD_BOOT_PART_NUM(x) (x << 3) +#define EXT_CSD_PARTITION_ACCESS(x) (x << 0) + +#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) +#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) +#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) + +#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) + +#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) + +#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ +#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ + +#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ + +#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ +#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ + + +#define MMC_DATA_READ 1 +#define MMC_DATA_WRITE 2 + +/* Maximum block size for MMC */ +#define MMC_MAX_BLOCK_LEN 512 + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 + + +struct mmc_cmd { + USHORT cmdidx; + UINT resp_type; + UINT cmdarg; + UINT response[4]; +}; + +struct mmc_data { + union { + char *dest; + const char *src; /* src buffers don't get written to */ + }; + UINT flags; + UINT blocks; + UINT blocksize; +}; + +int EmmcBurn(void *buf, unsigned int offset, unsigned int size, int show_progress); +ulong mmc_berase( lbaint_t start, lbaint_t blkcnt); +unsigned int mmc_write(void *buf, unsigned int offset, unsigned int size, int show_progress); +void Emmcinit(int chipid); +void bootFromEmmc(int chipid); +unsigned int EmmcGetUpfileOffset(int type); + +#endif + diff --git a/A58-STEPLDR/Src/spi.h b/A58-STEPLDR/Src/spi.h new file mode 100644 index 00000000..be72c946 --- /dev/null +++ b/A58-STEPLDR/Src/spi.h @@ -0,0 +1,82 @@ +#ifndef __SPI_H__ +#define __SPI_H__ + +#include "update.h" + +#define MAX_WAIT_LOOP_COUNT 100000 + +#define SPI_WRITE_ENABLE 0x06 +#define SPI_WRITE_DISABLE 0x04 +#define SPI_READ_STATUS 0x05 +#define SPI_READ_STATUS2 0x35 +#define SPI_READ_STATUS3 0x15 +#define SPI_WRITE_STATUS 0x01 +#define SPI_WRITE_STATUS2 0x31 +#define SPI_READ_DATA 0x03 + +#define SPI_4BYTEADDR_READ_DATA 0x13 + +#define SPI_FAST_READ 0x0B +#define SPI_PAGE_PROGRAM 0x02 +#define SPI_4BYTEADD_PAGE_PROGRAM 0x12 +#define SPI_SECTOR_ERASE 0x20 +#define SPI_4BYTEADD_SECTOR_ERASE 0x21 +#define SPI_SECTOR_ERASE_1 0xD7 +#define SPI_BLOCK_ERASE 0xD8 +#define SPI_4BYTEADD_BLOCK_ERASE 0xDC +#define SPI_BLOCK_ERASE_1 0x52 +#define SPI_CHIP_ERASE 0xC7 +#define SPI_CHIP_ERASE_1 0x60 +#define SPI_POWER_DOWN 0xB9 +#define SPI_READ_JEDEC_ID 0x9F +#define SPI_READ_ID_1 0xAB +#define SPI_MF_DEVICE_ID 0x90 +#define SPI_MF_DEVICE_ID_1 0x15 +#define SPI_READ_ELECTRON_SIGN 0xAB + +#define SPI_MF_WINBOND 0xEF +#define SPI_MF_EON 0x1C +#define SPI_MF_AMIC 0x37 +#define SPI_MF_ATMEL 0x1F +#define SPI_MF_SST 0xBF +#define SPI_MF_MXIC 0xC2 + +#define SPI_ENABLE_4BYTE_MODE 0xB7 +#define SPI_DISABLE_4BYTE_MODE 0xE9 +#define SPI_QUAD_IO_READ_DATA 0xEB + + + +#define SPI_BUSY (1<<0) +#define SPIFLASH_WRITEENABLE (1<<1) + +#define SPI_QE (1 << 1) +#define SPI_SSI_QE (1 << 6) +#define SPI_MIC_QE (1 << 6) + +#define SPI_WRITE_DMA +#define SPI_READ_DMA + +#define WORDSPERPAGE 64 +#define BYTESPERPAGE 256 +#define PAGESPERSECTORS 16 +#define SECTORSPERBLOCK 16 +#define BLOCKSPERFLASH 64 + + +#define BYTESPERBLOCK (BYTESPERPAGE*PAGESPERSECTORS*SECTORSPERBLOCK) +#define BYTESPERSECTOR (BYTESPERPAGE*PAGESPERSECTORS) + + +#define PAGES_PER_BLOCK 64 +#define BYTES_PER_PAGE 2048 + +void SpiSelectPad(void); +int SpiInit(void); +void SpiBurnLoad(void); +void SpiReadId(void); +int FlashBurn(void *buf, unsigned int offset, unsigned int size, int show_progress); +unsigned int SpiGetUpfileOffset(int type); + +#endif + diff --git a/A58-STEPLDR/Src/st7701s.c b/A58-STEPLDR/Src/st7701s.c new file mode 100644 index 00000000..23412868 --- /dev/null +++ b/A58-STEPLDR/Src/st7701s.c @@ -0,0 +1,376 @@ +/* + * ST7701S LCD Display. + * + * LCD Type: AMT TFT + * Display Format: 320(RGB)*960 + * Input Data: RGB 16bits(RGB565) + */ + +#include "board.h" +#include "gpio.h" +#include "timer.h" + + +//3 lines mode spi. +#define ST7701S_GPIO_SPI_CS 23 +#define ST7701S_GPIO_SPI_SCL 24 +#define ST7701S_GPIO_SPI_SDA 25 +#define ST7701S_GPIO_SPI_RST 26 + +#define ST7701S_DELAY udelay(5) + + +static void SPI_SendData(unsigned char value) +{ + int i; + + for(i=0; i<8; i++) + { + if(value & 0x80) + gpio_direction_output(ST7701S_GPIO_SPI_SDA, 1); //SDA=1 + else + gpio_direction_output(ST7701S_GPIO_SPI_SDA, 0); //SDA=0 + + value<<= 1; + + gpio_direction_output(ST7701S_GPIO_SPI_SCL, 0); //SCL=0 + ST7701S_DELAY; + gpio_direction_output(ST7701S_GPIO_SPI_SCL, 1); //SCL=1 + ST7701S_DELAY; + } +} + +static void SPI_WriteComm(unsigned char value) +{ + gpio_direction_output(ST7701S_GPIO_SPI_CS, 0); //CS=0 + + //D/CX = 0 + gpio_direction_output(ST7701S_GPIO_SPI_SDA, 0); //SDA=0 + gpio_direction_output(ST7701S_GPIO_SPI_SCL, 0); //SCL=0 + ST7701S_DELAY; + gpio_direction_output(ST7701S_GPIO_SPI_SCL, 1); //SCL=1 + ST7701S_DELAY; + + //Command data. + SPI_SendData(value); + + gpio_direction_output(ST7701S_GPIO_SPI_CS, 1); //CS=1 + ST7701S_DELAY; +} + +static void SPI_WriteData(unsigned char value) +{ + gpio_direction_output(ST7701S_GPIO_SPI_CS, 0); //CS=0 + + //D/CX = 1 + gpio_direction_output(ST7701S_GPIO_SPI_SDA, 1); //SDA=1 + gpio_direction_output(ST7701S_GPIO_SPI_SCL, 0); //SCL=0 + ST7701S_DELAY; + gpio_direction_output(ST7701S_GPIO_SPI_SCL, 1); //SCL=1 + ST7701S_DELAY; + + //Parameter data. + SPI_SendData(value); + + gpio_direction_output(ST7701S_GPIO_SPI_CS, 1); //CS=1 + ST7701S_DELAY; +} + +static void st7701s_reg_init(void) +{ + SPI_WriteComm (0xFF); + SPI_WriteData (0x77); + SPI_WriteData (0x01); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x13); + + SPI_WriteComm (0xEF); + SPI_WriteData (0x08); + + SPI_WriteComm (0xFF); + SPI_WriteData (0x77); + SPI_WriteData (0x01); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x10); + + SPI_WriteComm (0xC0); + SPI_WriteData (0x77); + SPI_WriteData (0x00); + + SPI_WriteComm (0xC1); //proch control. + SPI_WriteData (0x09); //vbp + SPI_WriteData (0x08); //vfp + + SPI_WriteComm (0xC2); //inv +#if 0 + SPI_WriteData (0x01); +#else + SPI_WriteData (0x07); +#endif + SPI_WriteData (0x02); + + //default:0x00, DE mode. + SPI_WriteComm (0xC3); //RGB control. + SPI_WriteData (0x02); //82 HVmode 02 DEmode + +#if 0 //default:0x00 + SPI_WriteComm (0xC7); //add. Source direction control. + SPI_WriteData (0x04); //0x00:Source form 0 to 479, 0x04:from 479 to 0. +#endif + + SPI_WriteComm (0xCC); + SPI_WriteData (0x10); + + SPI_WriteComm (0xB0); + SPI_WriteData (0x40); + SPI_WriteData (0x14); + SPI_WriteData (0x59); + SPI_WriteData (0x10); + SPI_WriteData (0x12); + SPI_WriteData (0x08); + SPI_WriteData (0x03); + SPI_WriteData (0x09); + SPI_WriteData (0x05); + SPI_WriteData (0x1E); + SPI_WriteData (0x05); + SPI_WriteData (0x14); + SPI_WriteData (0x10); + SPI_WriteData (0x68); + SPI_WriteData (0x33); + SPI_WriteData (0x15); + + SPI_WriteComm (0xB1); + SPI_WriteData (0x40); + SPI_WriteData (0x08); + SPI_WriteData (0x53); + SPI_WriteData (0x09); + SPI_WriteData (0x11); + SPI_WriteData (0x09); + SPI_WriteData (0x02); + SPI_WriteData (0x07); + SPI_WriteData (0x09); + SPI_WriteData (0x1A); + SPI_WriteData (0x04); + SPI_WriteData (0x12); + SPI_WriteData (0x12); + SPI_WriteData (0x64); + SPI_WriteData (0x29); + SPI_WriteData (0x29); + + SPI_WriteComm (0xFF); + SPI_WriteData (0x77); + SPI_WriteData (0x01); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x11); + + SPI_WriteComm (0xB0); + SPI_WriteData (0x6D); //6D + + SPI_WriteComm (0xB1); //vcom + SPI_WriteData (0x1D); + + SPI_WriteComm (0xB2); + SPI_WriteData (0x87); + + SPI_WriteComm (0xB3); + SPI_WriteData (0x80); + + SPI_WriteComm (0xB5); + SPI_WriteData (0x49); + + SPI_WriteComm (0xB7); + SPI_WriteData (0x85); + + SPI_WriteComm (0xB8); + SPI_WriteData (0x20); + + SPI_WriteComm (0xC1); + SPI_WriteData (0x78); + + SPI_WriteComm (0xC2); + SPI_WriteData (0x78); + + SPI_WriteComm (0xD0); + SPI_WriteData (0x88); + + SPI_WriteComm (0xE0); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x02); + + SPI_WriteComm (0xE1); + SPI_WriteData (0x02); + SPI_WriteData (0x8C); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x03); + SPI_WriteData (0x8C); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x33); + SPI_WriteData (0x33); + + SPI_WriteComm (0xE2); + SPI_WriteData (0x33); + SPI_WriteData (0x33); + SPI_WriteData (0x33); + SPI_WriteData (0x33); + SPI_WriteData (0xC9); + SPI_WriteData (0x3C); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0xCA); + SPI_WriteData (0x3C); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + + SPI_WriteComm (0xE3); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x33); + SPI_WriteData (0x33); + + SPI_WriteComm (0xE4); + SPI_WriteData (0x44); + SPI_WriteData (0x44); + + SPI_WriteComm (0xE5); + SPI_WriteData (0x05); + SPI_WriteData (0xCD); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + SPI_WriteData (0x01); + SPI_WriteData (0xC9); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + SPI_WriteData (0x07); + SPI_WriteData (0xCF); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + SPI_WriteData (0x03); + SPI_WriteData (0xCB); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + + SPI_WriteComm (0xE6); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x33); + SPI_WriteData (0x33); + + SPI_WriteComm (0xE7); + SPI_WriteData (0x44); + SPI_WriteData (0x44); + + SPI_WriteComm (0xE8); + SPI_WriteData (0x06); + SPI_WriteData (0xCE); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + SPI_WriteData (0x02); + SPI_WriteData (0xCA); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + SPI_WriteData (0x08); + SPI_WriteData (0xD0); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + SPI_WriteData (0x04); + SPI_WriteData (0xCC); + SPI_WriteData (0x82); + SPI_WriteData (0x82); + + SPI_WriteComm (0xEB); + SPI_WriteData (0x08); + SPI_WriteData (0x01); + SPI_WriteData (0xE4); + SPI_WriteData (0xE4); + SPI_WriteData (0x88); + SPI_WriteData (0x00); + SPI_WriteData (0x40); + + SPI_WriteComm (0xEC); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + + SPI_WriteComm (0xED); + SPI_WriteData (0xFF); + SPI_WriteData (0xF0); + SPI_WriteData (0x07); + SPI_WriteData (0x65); + SPI_WriteData (0x4F); + SPI_WriteData (0xFC); + SPI_WriteData (0xC2); + SPI_WriteData (0x2F); + SPI_WriteData (0xF2); + SPI_WriteData (0x2C); + SPI_WriteData (0xCF); + SPI_WriteData (0xF4); + SPI_WriteData (0x56); + SPI_WriteData (0x70); + SPI_WriteData (0x0F); + SPI_WriteData (0xFF); + + SPI_WriteComm (0xEF); + SPI_WriteData (0x10); + SPI_WriteData (0x0D); + SPI_WriteData (0x04); + SPI_WriteData (0x08); + SPI_WriteData (0x3F); + SPI_WriteData (0x1F); + + SPI_WriteComm (0xFF); + SPI_WriteData (0x77); + SPI_WriteData (0x01); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + SPI_WriteData (0x00); + + mdelay(114); //Sleep out cmd cannot be send after hw-reset for 120ms. + SPI_WriteComm (0x11); //sleep out. + + SPI_WriteComm (0x35); + SPI_WriteData (0x00); + +#if 0 + SPI_WriteComm (0x36); // + SPI_WriteData (0x10); //bit4(0:normal scan, 1:inverse scan); bit3(0:RGB, 1:BGR), default:0x00 +#endif + + SPI_WriteComm (0x3A); //RGB Interface pixel format. + SPI_WriteData (0x77); //bit[4-6](101:16-bit/pixel; 110:18-bit/pixel;111:24-bit/pixel), default:0x70 + + //SPI_WriteComm (0x11); + //Delay(120); + + SPI_WriteComm (0x29); //display on. +} + +static void st7701s_hw_reset(void) +{ + gpio_direction_output(ST7701S_GPIO_SPI_RST, 1); + mdelay(10); + gpio_direction_output(ST7701S_GPIO_SPI_RST, 0); + mdelay(1); //>=9us + gpio_direction_output(ST7701S_GPIO_SPI_RST, 1); + mdelay(6); //>=5ms +} + +int st7701s_init(void) +{ + gpio_direction_output(ST7701S_GPIO_SPI_CS, 1); //CS=1 + gpio_direction_output(ST7701S_GPIO_SPI_SCL, 1); //SCL=1 + gpio_direction_output(ST7701S_GPIO_SPI_SDA, 0); //SDA=0 + + st7701s_hw_reset(); + + st7701s_reg_init(); + + return 0; +} diff --git a/A58-STEPLDR/Src/sysctl.c b/A58-STEPLDR/Src/sysctl.c new file mode 100644 index 00000000..402db8c1 --- /dev/null +++ b/A58-STEPLDR/Src/sysctl.c @@ -0,0 +1,10 @@ +#include "amt630h.h" + +void vSysctlConfigure(uint32_t regoffset, uint32_t bitoffset, uint32_t mask, uint32_t val) +{ + uint32_t tmp = readl(REGS_SYSCTL_BASE + regoffset); + + tmp &= ~(mask << bitoffset); + tmp |= val << bitoffset; + writel(tmp, REGS_SYSCTL_BASE + regoffset); +} diff --git a/A58-STEPLDR/Src/sysctl.h b/A58-STEPLDR/Src/sysctl.h new file mode 100644 index 00000000..b31961a4 --- /dev/null +++ b/A58-STEPLDR/Src/sysctl.h @@ -0,0 +1,59 @@ +#ifndef _SYSCTL_H +#define _SYSCTL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define SYS_BOOT_SAMPLE 0x0 +#define SYS_BUS_CLK_CFG 0x40 +#define SYS_PER_CLK_CFG 0x44 +#define SYS_SDMMC_CLK_CFG 0x48 +#define SYS_VOU_CLK_CFG 0x4c +#define SYS_BUS_CLK_EN 0x50 +#define SYS_BUS1_CLK_EN 0x54 +#define SYS_PER_CLK_EN 0x58 +#define SYS_SOFT_RST 0x5c +#define SYS_SOFT1_RST 0x60 +#define SYS_SSP_CLK_CFG 0x64 +#define SYS_TIMER_CLK_CFG 0x68 +#define SYS_I2S_NCO_CFG 0x6c +#define SYS_DDRCTL_CFG 0x70 +#define SYS_PERCTL_CFG 0x78 +#define SYS_TIMER1_CLK_CFG 0x7c +#define SYS_ANA_CFG 0x80 +#define SYS_ANA1_CFG 0x84 +#define SYS_CPUPLL_CFG 0x88 +#define SYS_SYSPLL_CFG 0x8c +#define SYS_ANA2_CFG 0x98 +#define SYS_ANA3_CFG 0x9c +#define SYS_ANA4_CFG 0xa0 + +#define SYS_PAD_CTRL00 0xc0 +#define SYS_PAD_CTRL01 0xc4 +#define SYS_PAD_CTRL02 0xc8 +#define SYS_PAD_CTRL03 0xcc +#define SYS_PAD_CTRL04 0xd0 +#define SYS_PAD_CTRL05 0xd4 +#define SYS_PAD_CTRL06 0xd8 +#define SYS_PAD_CTRL07 0xdc + +#define SYS_IO_DRIVER00 0xe0 +#define SYS_IO_DRIVER01 0xe4 +#define SYS_IO_DRIVER02 0xe8 +#define SYS_IO_DRIVER03 0xec +#define SYS_IO_DRIVER04 0xf0 +#define SYS_IO_DRIVER05 0xf4 +#define SYS_IO_DRIVER06 0xf8 +#define SYS_IO_DRIVER07 0xfc + + +extern void vSysctlConfigure(uint32_t regoffset, uint32_t bitoffset, uint32_t mask, uint32_t val); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/A58-STEPLDR/Src/sysinfo.c b/A58-STEPLDR/Src/sysinfo.c new file mode 100644 index 00000000..536c205e --- /dev/null +++ b/A58-STEPLDR/Src/sysinfo.c @@ -0,0 +1,52 @@ +#include "amt630h.h" +#include "sysinfo.h" +#include "crc32.h" + +extern int SpiReadSysInfo(SysInfo *info); +extern void SpiWriteSysInfo(SysInfo *info); +extern int EmmcReadSysInfo(SysInfo *info); +extern void EmmcWriteSysInfo(SysInfo *info); + +static SysInfo sysinfo = {0}; + +SysInfo *GetSysInfo(void) +{ + return &sysinfo; +} + +void SetDefaultSysInfo(void) +{ +#if DEVICE_TYPE_SELECT != EMMC_FLASH + sysinfo.update_media_type = UPDATE_MEDIA_SD; +#else + sysinfo.update_media_type = UPDATE_MEDIA_USB; + sysinfo.loader_offset = LOADERB_OFFSET; + sysinfo.loader_size = LOADER_MAX_SIZE; + sysinfo.image_offset = IMAGEB_OFFSET; +#endif + sysinfo.image_offset = IMAGE_OFFSET; + sysinfo.update_status = UPDATE_STATUS_START; + sysinfo.stepldr_offset = STEPLDRB_OFFSET; + sysinfo.stepldr_size = STEPLDR_MAX_SIZE; +} + +int ReadSysInfo(void) +{ +#if DEVICE_TYPE_SELECT != EMMC_FLASH + return SpiReadSysInfo(&sysinfo); +#else + return EmmcReadSysInfo(&sysinfo); +#endif +} + +void SaveSysInfo(SysInfo *info) +{ + if (!info) + info = &sysinfo; + info->checksum = xcrc32((unsigned char*)info, sizeof(SysInfo) - 4, 0xffffffff); +#if DEVICE_TYPE_SELECT != EMMC_FLASH + SpiWriteSysInfo(info); +#else + EmmcWriteSysInfo(info); +#endif +} \ No newline at end of file diff --git a/A58-STEPLDR/Src/sysinfo.h b/A58-STEPLDR/Src/sysinfo.h new file mode 100644 index 00000000..d59759a3 --- /dev/null +++ b/A58-STEPLDR/Src/sysinfo.h @@ -0,0 +1,32 @@ +#ifndef _SYSINFO_H_ +#define _SYSINFO_H_ + +#define UPDATE_MEDIA_SD 0 +#define UPDATE_MEDIA_USB 1 +#define UPDATE_MEDIA_UART 2 + +#define UPDATE_STATUS_START 0 +#define UPDATE_STATUS_END 1 + +typedef struct { + unsigned int app_checksum; + unsigned int stepldr_offset; + unsigned int stepldr_size; + unsigned int update_media_type; + unsigned int update_status; + unsigned int app_size; + unsigned int image_offset; + unsigned int loader_offset; + unsigned int loader_size; + unsigned int reserved[10]; + unsigned int upgrade_flag; + unsigned int upgrade_appsize; + unsigned int checksum; +} SysInfo; + +SysInfo *GetSysInfo(void); +void SetDefaultSysInfo(void); +int ReadSysInfo(void); +void SaveSysInfo(SysInfo *info); + +#endif \ No newline at end of file diff --git a/A58-STEPLDR/Src/timer.c b/A58-STEPLDR/Src/timer.c new file mode 100644 index 00000000..326f6b93 --- /dev/null +++ b/A58-STEPLDR/Src/timer.c @@ -0,0 +1,78 @@ +#include "amt630h.h" +#include "timer.h" + +#define APBTMR_CONTROL_ENABLE (1 << 0) +/* 1: periodic, 0:free running. */ +#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1) +#define APBTMR_CONTROL_INT_DISABLE (1 << 2) + +#define TIMER_CLK CLK_24MHZ +#define TIMER_PERIOD 1000000 +#define TIMER_LOAD_VAL 0xffffffff + +static unsigned long timestamp; +static unsigned long lastdec; + +void timer_init(void) +{ + rTIMER0_CONTROL = 0; + rTIMER0_LOAD_COUNT = TIMER_LOAD_VAL; + /* No timer interrupt */ + rTIMER0_CONTROL = APBTMR_CONTROL_INT_DISABLE | + APBTMR_CONTROL_MODE_PERIODIC | APBTMR_CONTROL_ENABLE; +} + +void udelay(unsigned long usec) +{ + long tmo = usec * (TIMER_CLK / TIMER_PERIOD); + unsigned long last = rTIMER0_CURRENT_VALUE; + unsigned long now; + + while (tmo > 0) { + now = rTIMER0_CURRENT_VALUE; + if (last >= now) + tmo -= last - now; + else + tmo -= last + (TIMER_LOAD_VAL - now); + last = now; + } +} + +void mdelay(unsigned long msec) +{ + udelay(1000*msec); +} + +#if 0 +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = rTIMER0_CURRENT_VALUE; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} +#endif + +ULONG get_timer_masked (void) +{ + unsigned long now = rTIMER0_CURRENT_VALUE; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + (TIMER_LOAD_VAL - now); + } + lastdec = now; + + return timestamp / DIV_ROUND_UP(TIMER_CLK, TIMER_PERIOD) / 1000; +} + +ULONG get_timer(ULONG base) +{ + return get_timer_masked () - base; +} \ No newline at end of file diff --git a/A58-STEPLDR/Src/timer.h b/A58-STEPLDR/Src/timer.h new file mode 100644 index 00000000..39c8cbef --- /dev/null +++ b/A58-STEPLDR/Src/timer.h @@ -0,0 +1,12 @@ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "typedef.h" + +extern void timer_init(void); +//extern void reset_timer_masked (void); +extern void udelay(unsigned long usec); +extern void mdelay(unsigned long msec); +extern ULONG get_timer(ULONG base); + +#endif diff --git a/A58-STEPLDR/Src/trace.h b/A58-STEPLDR/Src/trace.h new file mode 100644 index 00000000..fa1aa071 --- /dev/null +++ b/A58-STEPLDR/Src/trace.h @@ -0,0 +1,204 @@ +/** + * \file + * + * \par Purpose + * + * Standard output methods for reporting debug information, warnings and + * errors, which can be easily be turned on/off. + * + * \par Usage + * -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually + * disable ALL traces; otherwise use DBGU_Configure(). + * -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() + * TRACE_FATAL() macros to output traces throughout the program. + * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 + * and Fatal 1. Disable a group of traces by changing the value of + * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL + * are not generated. To generate no trace, use the reserved value 0. + * -# Trace disabling can be static or dynamic. If dynamic disabling is selected + * the trace level can be modified in runtime. If static disabling is selected + * the disabled traces are not compiled. + * + * \par traceLevels Trace level description + * -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, + * and which do not produce meaningful information otherwise. + * -# TRACE_INFO (4): Informational trace about the program execution. Should + * enable the user to see the execution flow. + * -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case + * it can be discarded safely; it may even be expected. + * -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, + * but which indicates there is a problem with the code. + * -# TRACE_FATAL (1): Indicates a major error which prevents the program from going + * any further. + */ + +#ifndef _TRACE_ +#define _TRACE_ + +/* + * Headers + */ + +//#include "pio.h" + +#include +#include "uart.h" + +/* + * Global Definitions + */ + +/** Softpack Version */ +#define SOFTPACK_VERSION "1.1" + +#define TRACE_LEVEL_DEBUG 5 +#define TRACE_LEVEL_INFO 4 +#define TRACE_LEVEL_WARNING 3 +#define TRACE_LEVEL_ERROR 2 +#define TRACE_LEVEL_FATAL 1 +#define TRACE_LEVEL_NO_TRACE 0 + +#define TRACE_LEVEL TRACE_LEVEL_NO_TRACE + +/* By default, all traces are output except the debug one. */ +#if !defined(TRACE_LEVEL) +#define TRACE_LEVEL TRACE_LEVEL_INFO +#endif + +/* By default, trace level is static (not dynamic) */ +#if !defined(DYN_TRACES) +#define DYN_TRACES 0 +#endif + +#if defined(NOTRACE) +#error "Error: NOTRACE has to be not defined !" +#endif + +#undef NOTRACE +#if (DYN_TRACES==0) + #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) + #define NOTRACE + #endif +#endif + + + +/* ------------------------------------------------------------------------------ + * Global Macros + * ------------------------------------------------------------------------------ + */ + +extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) ; + +/** + * Initializes the DBGU for ISP project + * + * \param mode DBGU mode. + * \param baudrate DBGU baudrate. + * \param mck Master clock frequency. + */ +#ifndef DYNTRACE +#define DYNTRACE 0 +#endif + +#if (TRACE_LEVEL==0) && (DYNTRACE==0) +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} +#else +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ + const Pin pinsDBGU[] = {PINS_DBGU}; \ + PIO_Configure(pinsDBGU, PIO_LISTSIZE(pinsDBGU)); \ + DBGU_Configure( baudrate, mck ) ; \ + } +#endif + +/** + * Outputs a formatted string using 'printf' if the log level is high + * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. + * \param ... Additional parameters depending on formatted string. + */ +#if defined(NOTRACE) + +/* Empty macro */ +#define TRACE_DEBUG(...) { } +#define TRACE_INFO(...) { } +#define TRACE_WARNING(...) { } +#define TRACE_ERROR(...) { } +#define TRACE_FATAL(...) { while(1); } + +#define TRACE_DEBUG_WP(...) { } +#define TRACE_INFO_WP(...) { } +#define TRACE_WARNING_WP(...) { } +#define TRACE_ERROR_WP(...) { } +#define TRACE_FATAL_WP(...) { while(1); } + +#elif (DYN_TRACES == 1) + +/* Trace output depends on dwTraceLevel value */ +#define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } +#define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } +#define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } +#define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } +#define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } } + +#define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } +#define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } +#define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } +#define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } +#define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } } + +#else + +/* Trace compilation depends on TRACE_LEVEL value */ +#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) +#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } +#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_DEBUG(...) { } +#define TRACE_DEBUG_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_INFO) +#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } +#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_INFO(...) { } +#define TRACE_INFO_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) +#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } +#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_WARNING(...) { } +#define TRACE_WARNING_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) +#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } +#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_ERROR(...) { } +#define TRACE_ERROR_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) +#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } +#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); } +#else +#define TRACE_FATAL(...) { while(1); } +#define TRACE_FATAL_WP(...) { while(1); } +#endif + +#endif + + +/** + * Exported variables + */ +/** Depending on DYN_TRACES, dwTraceLevel is a modifable runtime variable or a define */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) + extern uint32_t dwTraceLevel ; +#endif + +#endif //#ifndef TRACE_H + diff --git a/A58-STEPLDR/Src/typedef.h b/A58-STEPLDR/Src/typedef.h new file mode 100644 index 00000000..a2c38a3d --- /dev/null +++ b/A58-STEPLDR/Src/typedef.h @@ -0,0 +1,126 @@ +#ifndef TYPEDEF_HEAD_H__ +#define TYPEDEF_HEAD_H__ + +#ifndef _INTEGER + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef signed char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +#define _INTEGER +#endif + + +typedef char INT8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef unsigned short HWORD; +typedef signed int INT32; +typedef unsigned int UINT32; +typedef unsigned long COLORREF; +typedef unsigned long long UINT64; + +typedef void VOID; +typedef void * P_VOID; + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; + +//typedef unsigned char uint8_t; +//typedef unsigned short uint16_t; +//typedef unsigned int uint32_t; + +#define true 1 +#define false 0 + +#if 0 +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ + +#define ENOSYS 38 /* Invalid system call number */ + +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ +#endif + +#define EAGAIN 11 /* Try again */ +#define ETIMEDOUT 110 /* Connection timed out */ + + +typedef struct { + char Present; //1 - card is in the socket + char Changed; //1 - card changed(card is in socket) + unsigned int SecNum; // the whole setctor number +} FS_CARD; + +#endif diff --git a/A58-STEPLDR/Src/uart.c b/A58-STEPLDR/Src/uart.c new file mode 100644 index 00000000..17ab3122 --- /dev/null +++ b/A58-STEPLDR/Src/uart.c @@ -0,0 +1,761 @@ +#include + +#include "amt630h.h" +#include "typedef.h" +#include "uart.h" +#include "aic.h" +#include "update.h" +#include "spi.h" +#include "crc32.h" +#include "sysinfo.h" +#include "board.h" +#include "sysctl.h" +#include "sdmmc.h" + +#define UART_CLK CLK_24MHZ +#define UART_ISR_PASS_LIMIT 1 + +static unsigned int ulUartBase[UART_NUM] = {REGS_UART0_BASE, REGS_UART1_BASE, REGS_UART2_BASE, REGS_UART3_BASE}; + +void InitUart(unsigned int baud) +{ + unsigned int Baud_Rate_Divisor; + unsigned int val; + + //select pad + val = rSYS_PAD_CTRL02; + val &= ~(0xF<<12); + val |=(0x1<<14)|(0x1<<12); + rSYS_PAD_CTRL02 = val; + + Baud_Rate_Divisor = ((CLK_24MHZ<<3) + baud)/(baud<<1); + rUART_IBRD = Baud_Rate_Divisor >> 6; + rUART_FBRD = Baud_Rate_Divisor & 0x3f; + + rUART_LCR_H = 0x70;//data len:8 bit,parity checking disable + rUART_IFLS = 0x19; + rUART_CR = 0x301; +} + +static char HexToChar(unsigned char value) +{ + value &= 0x0f; + + if ( value < 10 ) + return(0x30 + value); + else + return(0x60 + value - 9); +} + + +static void ShortToStr(unsigned short value, char *str) +{ + str[0] = HexToChar(value >> 12); + str[1] = HexToChar((value >> 8) & 0x0f); + str[2] = HexToChar((value >> 4) & 0x0f); + str[3] = HexToChar(value & 0x0f); + str[4] = 0; +} + +void IntToStr(unsigned int value, char *str) +{ + ShortToStr(value >> 16, str); + ShortToStr(value & 0xffff, str + 4); + str[8] = 0; +} + +void SendUartString(char * buf) +{ + int i = 0; + while ( buf[i] != 0) + { + while ( !(rUART_FR & 0x20) ) + { + rUART_DR = buf[i++]; + if ( buf[i] == 0 ) + return; + } + while ( (rUART_FR & 0x20)); + } +} + +void SendUartChar(char ch) +{ + while ( (rUART_FR & 0x20) ); + rUART_DR = ch; +} + + +void PrintVariableValueHex(char * variable, unsigned int value) +{ + char buf[10]; + + SendUartString(variable); + SendUartString(": 0x"); + IntToStr(value, buf); + SendUartString(buf); + SendUartString("\r\n"); +} + +void SendUartWord(unsigned int data) +{ + char buf[10]; + + SendUartString("0x"); + IntToStr(data, buf); + SendUartString(buf); + SendUartString("\r\n"); +} +void uart_puts(const UINT8*buf) +{ + INT32 i = 0; + while ( buf[i] != 0) + { + while( !(rUART_FR & 0x20) ) + { + if ( buf[i] == '\n' ) + { + rUART_DR = '\r'; + while( (rUART_FR & 0x20) ); + } + + rUART_DR = buf[i++]; + if ( buf[i] == 0 ) + return; + } + while( (rUART_FR & 0x20) ); + } +} + +/* retarget printf function */ +int putchar(int ch) +{ + while (readl(REGS_UART0_BASE + UART_FR) & UART_FR_TXFF); + writel(ch, REGS_UART0_BASE + UART_DR); + + return ch; +} + +typedef enum { + UART_FRAME_START, + UART_FRAME_FILEINFO, + UART_FRAME_FILEXFER, + UART_FRAME_FINISH, +} eUartFrameType; + +#define UUP_STATE_IDLE 0 +#define UUP_STATE_START 1 +#define UUP_STATE_END 2 + +#define UUP_ACK_OK 1 +#define UUP_ACK_FAIL 0 + +#define UUP_MAX_FILE_SIZE 0x1000000 +#define UUP_BUF_SIZE (BYTESPERPAGE * PAGESPERSECTORS) +#define UUP_PACKET_SIZE 128 +#define UUP_MAX_FRAME_LEN (UUP_PACKET_SIZE + 16) +#define UUP_RX_FRAME_NUM 16 +#define UUP_MAX_LOADER_SIZE STEPLDR_MAX_SIZE//0x10000 + + +typedef struct { + int type; + unsigned char *buf; + unsigned int len; + int ack; +} UartFrame; + +#pragma data_alignment=16 +static unsigned char uup_rx_buf[UUP_RX_FRAME_NUM][UUP_MAX_FRAME_LEN]; +static unsigned char *uup_rx_ptr; +static int uup_rx_rev_len = 0; +static int uup_rx_head = 0; +static int uup_rx_tail = 0; +static int uup_rx_state = 0; +static int uup_rx_data_len = 0; +static int uup_status = UUP_STATE_IDLE; +static int uup_file_type = 0; +static unsigned int uup_file_offset; +static int uup_file_size = 0; +static int uup_packet_num = 0; +static int uup_rev_packet = 0; +static int uup_rev_len = 0; + +#pragma data_alignment=16 +static unsigned char uup_buf[UUP_MAX_LOADER_SIZE]; +static unsigned int uup_buf_len = 0; + +static void uart_select_pad(int id) +{ + switch (id) { + case UART_ID0: + vSysctlConfigure(SYS_PAD_CTRL02, 12, 0xf, 0x5); + break; + case UART_ID1: + vSysctlConfigure(SYS_PAD_CTRL02, 16, 0xf, 0x5); + break; + case UART_ID2: + vSysctlConfigure(SYS_PAD_CTRL02, 20, 0xf, 0x5); + break; + case UART_ID3: + vSysctlConfigure(SYS_PAD_CTRL02, 24, 0xf, 0x5); + break; + } +} + +void uart_init(int id, unsigned int baud, unsigned int flags) +{ + unsigned int lcr_h, quot, cr; + unsigned int regbase; + int count = 0; + + //uart_select_pad(id); + + regbase = ulUartBase[id]; + + if (id == UART_ID0 || id == UART_ID2) { + if (baud > UART_CLK / 16) + quot = (UART_CLK * 8 + baud / 2) / baud; + else + quot = (UART_CLK * 4 + baud / 2) / baud; + + switch (flags & CSIZE) { + case CS5: + lcr_h = UART_LCRH_WLEN_5; + break; + case CS6: + lcr_h = UART_LCRH_WLEN_6; + break; + case CS7: + lcr_h = UART_LCRH_WLEN_7; + break; + default: // CS8 + lcr_h = UART_LCRH_WLEN_8; + break; + } + if (flags & CSTOPB) + lcr_h |= UART_LCRH_STP2; + if (flags & PARENB) { + lcr_h |= UART_LCRH_PEN; + if (!(flags & PARODD)) + lcr_h |= UART_LCRH_EPS; + if (flags & CMSPAR) + lcr_h |= UART_LCRH_SPS; + } + lcr_h |= UART_LCRH_FEN; + + /* Provoke TX FIFO interrupt into asserting */ + cr = UART_CR_UARTEN | UART_CR_TXE | UART_CR_LBE; + reconfig: + writel(cr, regbase + UART_CR); + writel(0, regbase + UART_FBRD); + writel(1, regbase + UART_IBRD); + writel(0, regbase + UART_LCRH); + writel(0, regbase + UART_DR); + while (readl(regbase + UART_FR) & UART_FR_BUSY); + if (count++ < 10 && !(readl(regbase + UART_RIS) & UART_TXIS)) { + SendUartString("ERROR! Uart status wrong.\n"); + goto reconfig; + } + + /* first, disable everything */ + writel(0, regbase + UART_CR); + + cr = UART_CR_RXE | UART_CR_TXE; + if (flags & CRTSCTS) + cr |= UART_CR_CTSEN | UART_CR_RTSEN; + + /* Set baud rate */ + writel(quot & 0x3f, regbase + UART_FBRD); + writel(quot >> 6, regbase + UART_IBRD); + + writel(UART_RTIM | UART_RXIM, regbase + UART_IMSC); + writel(UART_IFLS_RX4_8 | UART_IFLS_TX4_8, regbase + UART_IFLS); + writel(lcr_h, regbase + UART_LCRH); + writel(cr | UART_CR_UARTEN, regbase + UART_CR); + } else { + //set modem + writel(0, regbase + UART485_MCR); + + // baud = clk/(16*U_DLL) + //set baud rate + writel(readl(regbase + UART485_LCR) | (1 << 7), regbase + UART485_LCR); + writel(UART_CLK / (16 * baud), regbase + UART485_DLL); + writel(0, regbase + UART485_DLH); + //Set fractional baud rate + //Fractional baud divisor = ((uart_clk%(16*baud))/(16*baud)) * 16 = (uart_clk%(16*baud)) * 16 / (16*baud); + writel((UART_CLK % (16*baud)) * 16 / (16*baud), regbase + UART485_DLF); + + writel(readl(regbase + UART485_LCR) & ~(1 << 7), regbase + UART485_LCR); + + cr = readl(regbase + UART485_LCR); + //校验 + cr &= ~(7 << 3); + if (flags & PARENB) { + cr |= (1 << 3); + if (!(flags & PARODD)) + cr |= (1 << 4); + if (flags & CMSPAR) + cr |= (1 << 5); + } + //停止位 + if (flags & CSTOPB) + cr |= (1 << 2); + else + cr &= ~(1 << 2); + //数据位 + cr &= ~(3 << 0); + switch (flags & CSIZE) { + case CS5: + break; + case CS6: + cr |= 1; + break; + case CS7: + cr |= 2; + break; + default: // CS8 + cr |= 3; + break; + } + writel(cr, regbase + UART485_LCR); + + //set fifo + writel((2 << 6) | (3 << 4) | 7, regbase + UART485_FCR); + + //enable rx and err interrupt + writel((1 << 4) | 1, regbase + UART485_IER); + + //设置通信模式全双工还是半双工 + //485mode disable + writel(0, regbase + UART485_TCR); + } + + uart_select_pad(id); +} + + +static int uart_rx_chars(int id) +{ + unsigned int regbase = ulUartBase[id]; + unsigned int status; + unsigned int ch, max_count = 256; + int fifotaken = 0; + + while (max_count--) { + if (id == UART_ID0 || id == UART_ID2) { + status = readl(regbase + UART_FR); + if (status & UART_FR_RXFE) + break; + + /* Take chars from the FIFO and update status */ + ch = readl(regbase + UART_DR); + } else { + status = readl(regbase + UART485_LSR); + if (!(status & UART485_LSR_DR)) + break; + + /* Take chars from the FIFO and update status */ + ch = readl(regbase + UART485_RBR); + } + + fifotaken++; + switch (uup_rx_state) { + case 0: + if (ch == 0x55) { + uup_rx_state++; + uup_rx_rev_len = 0; + uup_rx_ptr = &uup_rx_buf[uup_rx_head][0]; + } + break; + case 1: + if (ch == 0x81) + uup_rx_state++; + else + uup_rx_state = 0; + *uup_rx_ptr++ = ch; + break; + case 2: + if (ch == 0xc6) + uup_rx_state++; + else + uup_rx_state = 0; + *uup_rx_ptr++ = ch; + break; + case 3: + uup_rx_data_len = ch; + if (uup_rx_data_len <= 0 || uup_rx_data_len > UUP_PACKET_SIZE + 2) { + SendUartString("Invalid uart frame len.\n"); + uup_rx_state = 0; + } else { + uup_rx_state++; + *uup_rx_ptr++ = ch; + } + break; + case 4: + *uup_rx_ptr++ = ch; + if (++uup_rx_rev_len == uup_rx_data_len) + uup_rx_state++; + break; + case 5: + *uup_rx_ptr++ = ch; + uup_rx_head = (uup_rx_head + 1) % UUP_RX_FRAME_NUM; + uup_rx_state = 0; + break; + } + + /* discard when rx buf is full */ + + } + + return fifotaken; +} + +void uart_tx_chars(int id, unsigned char *buf, int len) +{ + unsigned int regbase = ulUartBase[id]; + int i; + + for (i = 0; i < len; i++) { + if (id == UART_ID0 || id == UART_ID2) { + while (readl(regbase + UART_FR) & UART_FR_TXFF); + writel(buf[i], regbase + UART_DR); + } else { + while (!(readl(regbase + UART485_LSR) & UART485_LSR_TEMT)); + writel(buf[i], regbase + UART485_THR); + } + } +} + +void uart_update_int_handler(void *param) +{ + int id = (int)param; + unsigned int regbase = ulUartBase[id]; + unsigned int status; + unsigned int imsc; + uint32_t pass_counter = UART_ISR_PASS_LIMIT; + + imsc = readl(regbase + UART_IMSC); + status = readl(regbase + UART_RIS) & imsc; + if (status) { + do { + writel(status & ~(/*UART_TXIS | */UART_RTIS | UART_RXIS), + regbase + UART_ICR); + + if (status & (UART_RTIS | UART_RXIS)) { + uart_rx_chars(id); + } + /* if (status & UART_TXIS) + xUartTxChars(uap, pdTRUE); */ + + if (pass_counter-- == 0) + break; + + status = readl(regbase + UART_RIS) & imsc; + } while (status != 0); + } +} + +void uart485_update_int_handler(void *param) +{ + int id = (int)param; + unsigned int regbase = ulUartBase[id]; + uint32_t iir; + + iir = readl(regbase + UART485_IIR); + switch (iir & UART485_IIR_IID_MASK) { + case UART485_IIR_IID_REV_DATA_AVAIL: + case UART485_IIR_IID_REV_LINE_STATUS: + case UART485_IIR_IID_CHAR_TIMEOUT: + uart_rx_chars(id); + } +} + +static void uart_send_ack(int type, int ret) +{ + unsigned char buf[7] = {0x55, 0x80, 0xc5, 0x02, 0x00, 0x00, 0x00}; + int i; + + buf[4] = type; + buf[5] = ret; + for (i = 1; i < 6; i++) + buf[6] ^= buf[i]; + + uart_tx_chars(UART_MCU_PORT, buf, 7); +} + +static int uart_rev_frame(UartFrame *frame) +{ + unsigned char *buf; + int len; + unsigned char checksum = 0; + int i; + + if (uup_rx_tail == uup_rx_head) { + return 0; + } + buf = &uup_rx_buf[uup_rx_tail][0]; + uup_rx_tail = (uup_rx_tail + 1) % UUP_RX_FRAME_NUM; + len = buf[2]; + for (i = 0; i < len + 3; i++) + checksum ^= buf[i]; + if (checksum == buf[len + 3]) { + frame->buf = &buf[4]; + frame->len = len - 1; + frame->type = buf[3]; + } else { + SendUartString("rev frame checksum err.\n"); + /* for (int i = 0; i < len + 4; i++) { + if (i && i % 16 == 0) + printf("\n"); + printf("%.2x, ", buf[i]); + } + printf("\n0x%x, 0x%x.\n", checksum, buf[len + 3]); */ + uart_send_ack(buf[3], UUP_ACK_FAIL); + return 0; + } + + return 1; +} + + +void updateFromUart(int id) +{ + UartFrame rx_frame; + unsigned char *buf; + unsigned int checksum = 0, calc_checksum = 0xffffffff; + unsigned int framelen; + unsigned int packetnum; + SysInfo *sysinfo = GetSysInfo(); + + uart_init(id, 115200, 0); + if (id == UART_ID0 || id == UART_ID2) + request_irq(UART0_IRQn + id, 0, uart_update_int_handler, (void*)id); + else + request_irq(UART0_IRQn + id, 0, uart485_update_int_handler, (void*)id); + + do { + if (!uart_rev_frame(&rx_frame)) + continue; + + switch (rx_frame.type) { + case UART_FRAME_START: + uart_send_ack(rx_frame.type, UUP_ACK_OK); + uup_status = UUP_STATE_START; + update_logo_init(); + break; + case UART_FRAME_FILEINFO: + if (uup_status != UUP_STATE_START) + break; + buf = rx_frame.buf; + uup_file_type = buf[0]; + if (uup_file_type > UPFILE_TYPE_STEPLDR) { + PrintVariableValueHex("Rev wrong file type", uup_file_type); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } +#if DEVICE_TYPE_SELECT != EMMC_FLASH + uup_file_offset = SpiGetUpfileOffset(uup_file_type); +#else + uup_file_offset = EmmcGetUpfileOffset(uup_file_type); +#endif + if (uup_file_offset == 0xffffffff) { + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + uup_packet_num = (buf[1] << 16) | (buf[2] << 8) | buf[3]; + uup_file_size = UUP_PACKET_SIZE * uup_packet_num; + if (uup_file_size > UUP_MAX_FILE_SIZE - uup_file_offset) { + SendUartString("Rev wrong file size.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + uart_send_ack(rx_frame.type, UUP_ACK_OK); + break; + case UART_FRAME_FILEXFER: + if (uup_status != UUP_STATE_START) + break; + buf = rx_frame.buf; + packetnum = buf[0]; + PrintVariableValueHex("uup_rev_packet", uup_rev_packet); + if ((uup_rev_packet & 0xff) != packetnum) { + SendUartString("Wrong packet number.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + if (uup_rev_packet == 0) { + if (uup_file_type == UPFILE_TYPE_WHOLE) { + UpFileHeader *header = (UpFileHeader *)&buf[1]; + if (header->magic != MKTAG('U', 'P', 'D', 'F')) { + SendUartString("Wrong whole file magic.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + checksum = header->checksum; + sysinfo->app_size = header->files[0].size; + PrintVariableValueHex("sysinfo->appsize ", sysinfo->app_size); + } else if (uup_file_type == UPFILE_TYPE_RESOURCE) { + RomHeader *header = (RomHeader *)&buf[1]; + if (header->magic != MKTAG('R', 'O', 'M', 'A')) { + SendUartString("Wrong resource file magic.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + checksum = header->checksum; + } else if (uup_file_type == UPFILE_TYPE_ANIMATION) { + BANIHEADER *header = (BANIHEADER *)&buf[1]; + if (header->magic != MKTAG('B', 'A', 'N', 'I')) { + SendUartString("Wrong animation file magic.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + checksum = header->checksum; + } else if (uup_file_type == UPFILE_TYPE_APP) { + unsigned int magic = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + if (magic != UPFILE_APP_MAGIC) { + SendUartString("Wrong app file magic.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + unsigned char *tmp = buf + 1 + APPLDR_CHECKSUM_OFFSET; + checksum = tmp[0] | (tmp[1] <<8) | (tmp[2] << 16) | (tmp[3] << 24); + } + } + framelen = rx_frame.len - 1; + /* only last frame size is less than UUP_PACKET_SIZE */ + if (framelen > UUP_PACKET_SIZE || + (framelen < UUP_PACKET_SIZE && uup_rev_packet != uup_packet_num - 1)) { + SendUartString("Wrong packet len.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + memcpy(uup_buf + uup_buf_len, buf + 1, framelen); + uup_buf_len += framelen; + if (uup_buf_len > UUP_MAX_LOADER_SIZE) { + SendUartString("loader file is too large.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + uup_rev_packet++; + //loader程序如果升级错误会导致系统起不来并且不能再继续升级，因此需要 + //等数据校验成功后再烧录(loader程序通常并不需要升级) + if (uup_file_type < UPFILE_TYPE_FIRSTLDR && uup_buf_len == UUP_BUF_SIZE) { +#if DEVICE_TYPE_SELECT != EMMC_FLASH + if(!FlashBurn(uup_buf, uup_file_offset, UUP_BUF_SIZE, 0)) +#else + if(!EmmcBurn(uup_buf, uup_file_offset, UUP_BUF_SIZE, 0)) +#endif + { + uart_send_ack(rx_frame.type, UUP_ACK_OK); + } else { + SendUartString("Burn failed.\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + break; + } + //文件起始部分需要先将头信息里的checksum清0来计算checksum + if (uup_rev_packet == UUP_BUF_SIZE / UUP_PACKET_SIZE) { + if (uup_file_type == UPFILE_TYPE_WHOLE) { + UpFileHeader *pheader = (UpFileHeader *)uup_buf; + pheader->checksum = 0; + } else if (uup_file_type == UPFILE_TYPE_RESOURCE) { + RomHeader *pheader = (RomHeader *)uup_buf; + pheader->checksum = 0; + } else if (uup_file_type == UPFILE_TYPE_ANIMATION) { + BANIHEADER *pheader = (BANIHEADER *)uup_buf; + pheader->checksum = 0; + } else if (uup_file_type == UPFILE_TYPE_APP) { + unsigned int *tmp = (unsigned int *)(uup_buf + APPLDR_CHECKSUM_OFFSET); + *tmp = 0; + } + } + calc_checksum = xcrc32(uup_buf, UUP_BUF_SIZE, calc_checksum); + uup_buf_len = 0; + uup_file_offset += UUP_BUF_SIZE; + uup_rev_len += UUP_BUF_SIZE; + update_progress_set(uup_rev_len * 100 / uup_file_size); + } else { + uart_send_ack(rx_frame.type, UUP_ACK_OK); + } + break; + case UART_FRAME_FINISH: + buf = rx_frame.buf; + if (!buf[0]) { + SendUartString("update end with error!\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + uup_status = UUP_STATE_END; + break; + } + if (uup_file_type < UPFILE_TYPE_FIRSTLDR) { + if (uup_buf_len) { +#if DEVICE_TYPE_SELECT != EMMC_FLASH + if(FlashBurn(uup_buf, uup_file_offset, uup_buf_len, 0)) +#else + if(EmmcBurn(uup_buf, uup_file_offset, uup_buf_len, 0)) +#endif + { + SendUartString("update fail with burn failed.!\n"); + calc_checksum = 0xFFFFFFFF; + } else { + //如果升级文件小于UUP_BUF_SIZE，此时收到的是文件起始部分 + if (uup_rev_packet < UUP_BUF_SIZE / UUP_PACKET_SIZE) { + if (uup_file_type == UPFILE_TYPE_WHOLE) { + UpFileHeader *pheader = (UpFileHeader *)uup_buf; + pheader->checksum = 0; + } else if (uup_file_type == UPFILE_TYPE_RESOURCE) { + RomHeader *pheader = (RomHeader *)uup_buf; + pheader->checksum = 0; + } else if (uup_file_type == UPFILE_TYPE_ANIMATION) { + BANIHEADER *pheader = (BANIHEADER *)uup_buf; + pheader->checksum = 0; + } else if (uup_file_type == UPFILE_TYPE_APP) { + unsigned int *checksum = (unsigned int *)(uup_buf + APPLDR_CHECKSUM_OFFSET); + *checksum = 0; + } + } + calc_checksum = xcrc32(uup_buf, uup_buf_len, calc_checksum); + } + } + if (calc_checksum == checksum) { + SendUartString("update finish!\n"); + update_progress_set(100); + if (uup_file_type == UPFILE_TYPE_APP) + sysinfo->app_size = uup_file_size; + sysinfo->update_status = UPDATE_STATUS_END; + SaveSysInfo(sysinfo); + uart_send_ack(rx_frame.type, UUP_ACK_OK); + } else { + SendUartString("update checksum fail!\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + } + } else { + unsigned int *tmp = (unsigned int *)(uup_buf + APPLDR_CHECKSUM_OFFSET); + checksum = *tmp; + *tmp = 0; + calc_checksum = xcrc32(uup_buf, uup_buf_len, calc_checksum); + if (calc_checksum == checksum) { +#if DEVICE_TYPE_SELECT != EMMC_FLASH + if (!FlashBurn(uup_buf, uup_file_offset, uup_buf_len, 1)) +#else + if (!EmmcBurn(uup_buf, uup_file_offset, uup_buf_len, 1)) +#endif + { + if (uup_file_type == UPFILE_TYPE_STEPLDR) + sysinfo->stepldr_size = uup_buf_len; + sysinfo->update_status = UPDATE_STATUS_END; + SaveSysInfo(sysinfo); + uart_send_ack(rx_frame.type, UUP_ACK_OK); + } else { + SendUartString("burn loader fail!\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + } + } else { + SendUartString("update checksum fail!\n"); + uart_send_ack(rx_frame.type, UUP_ACK_FAIL); + } + } + uup_status = UUP_STATE_END; + break; + } + } while (uup_status != UUP_STATE_END); +} + diff --git a/A58-STEPLDR/Src/uart.h b/A58-STEPLDR/Src/uart.h new file mode 100644 index 00000000..4e57e960 --- /dev/null +++ b/A58-STEPLDR/Src/uart.h @@ -0,0 +1,205 @@ +#ifndef UART_PRINT_H__ +#define UART_PRINT_H__ + +/* UART Register Offsets. */ +#define UART_DR 0x00 /* Data read or written from the interface. */ +#define UART_RSR 0x04 /* Receive status register (Read). */ +#define UART_FR 0x18 /* Flag register (Read only). */ +#define UART_ILPR 0x20 /* IrDA low power counter register. */ +#define UART_IBRD 0x24 /* Integer baud rate divisor register. */ +#define UART_FBRD 0x28 /* Fractional baud rate divisor register. */ +#define UART_LCRH 0x2c /* Line control register. */ +#define UART_CR 0x30 /* Control register. */ +#define UART_IFLS 0x34 /* Interrupt fifo level select. */ +#define UART_IMSC 0x38 /* Interrupt mask. */ +#define UART_RIS 0x3c /* Raw interrupt status. */ +#define UART_MIS 0x40 /* Masked interrupt status. */ +#define UART_ICR 0x44 /* Interrupt clear register. */ +#define UART_DMACR 0x48 /* DMA control register. */ + + +#define UART_DR_OE (1 << 11) +#define UART_DR_BE (1 << 10) +#define UART_DR_PE (1 << 9) +#define UART_DR_FE (1 << 8) + +#define UART_RSR_OE 0x08 +#define UART_RSR_BE 0x04 +#define UART_RSR_PE 0x02 +#define UART_RSR_FE 0x01 + +#define UART_FR_RI 0x100 +#define UART_FR_TXFE 0x080 +#define UART_FR_RXFF 0x040 +#define UART_FR_TXFF 0x020 +#define UART_FR_RXFE 0x010 +#define UART_FR_BUSY 0x008 +#define UART_FR_DCD 0x004 +#define UART_FR_DSR 0x002 +#define UART_FR_CTS 0x001 +#define UART_FR_TMSK (UART_FR_TXFF + UART_FR_BUSY) + +#define UART_CR_CTSEN 0x8000 /* CTS hardware flow control */ +#define UART_CR_RTSEN 0x4000 /* RTS hardware flow control */ +#define UART_CR_OUT2 0x2000 /* OUT2 */ +#define UART_CR_OUT1 0x1000 /* OUT1 */ +#define UART_CR_RTS 0x0800 /* RTS */ +#define UART_CR_DTR 0x0400 /* DTR */ +#define UART_CR_RXE 0x0200 /* receive enable */ +#define UART_CR_TXE 0x0100 /* transmit enable */ +#define UART_CR_LBE 0x0080 /* loopback enable */ +#define UART_CR_RTIE 0x0040 +#define UART_CR_TIE 0x0020 +#define UART_CR_RIE 0x0010 +#define UART_CR_MSIE 0x0008 +#define UART_CR_IIRLP 0x0004 /* SIR low power mode */ +#define UART_CR_SIREN 0x0002 /* SIR enable */ +#define UART_CR_UARTEN 0x0001 /* UART enable */ + +#define UART_LCRH_SPS 0x80 +#define UART_LCRH_WLEN_8 0x60 +#define UART_LCRH_WLEN_7 0x40 +#define UART_LCRH_WLEN_6 0x20 +#define UART_LCRH_WLEN_5 0x00 +#define UART_LCRH_FEN 0x10 +#define UART_LCRH_STP2 0x08 +#define UART_LCRH_EPS 0x04 +#define UART_LCRH_PEN 0x02 +#define UART_LCRH_BRK 0x01 + + +#define UART_IFLS_RX1_8 (0 << 3) +#define UART_IFLS_RX2_8 (1 << 3) +#define UART_IFLS_RX4_8 (2 << 3) +#define UART_IFLS_RX6_8 (3 << 3) +#define UART_IFLS_RX7_8 (4 << 3) +#define UART_IFLS_TX1_8 (0 << 0) +#define UART_IFLS_TX2_8 (1 << 0) +#define UART_IFLS_TX4_8 (2 << 0) +#define UART_IFLS_TX6_8 (3 << 0) +#define UART_IFLS_TX7_8 (4 << 0) + +#define UART_OEIM (1 << 10) /* overrun error interrupt mask */ +#define UART_BEIM (1 << 9) /* break error interrupt mask */ +#define UART_PEIM (1 << 8) /* parity error interrupt mask */ +#define UART_FEIM (1 << 7) /* framing error interrupt mask */ +#define UART_RTIM (1 << 6) /* receive timeout interrupt mask */ +#define UART_TXIM (1 << 5) /* transmit interrupt mask */ +#define UART_RXIM (1 << 4) /* receive interrupt mask */ +#define UART_DSRMIM (1 << 3) /* DSR interrupt mask */ +#define UART_DCDMIM (1 << 2) /* DCD interrupt mask */ +#define UART_CTSMIM (1 << 1) /* CTS interrupt mask */ +#define UART_RIMIM (1 << 0) /* RI interrupt mask */ + +#define UART_OEIS (1 << 10) /* overrun error interrupt status */ +#define UART_BEIS (1 << 9) /* break error interrupt status */ +#define UART_PEIS (1 << 8) /* parity error interrupt status */ +#define UART_FEIS (1 << 7) /* framing error interrupt status */ +#define UART_RTIS (1 << 6) /* receive timeout interrupt status */ +#define UART_TXIS (1 << 5) /* transmit interrupt status */ +#define UART_RXIS (1 << 4) /* receive interrupt status */ +#define UART_DSRMIS (1 << 3) /* DSR interrupt status */ +#define UART_DCDMIS (1 << 2) /* DCD interrupt status */ +#define UART_CTSMIS (1 << 1) /* CTS interrupt status */ +#define UART_RIMIS (1 << 0) /* RI interrupt status */ + + + +#define UART485_RBR_THR_DLL 0x000 +#define UART485_DLH_IER 0x004 +#define UART485_IIR_FCR 0x008 +#define UART485_RBR 0x000 +#define UART485_THR 0x000 +#define UART485_DLL 0x000 +#define UART485_DLH 0x004 +#define UART485_IER 0x004 +#define UART485_IIR 0x008 +#define UART485_FCR 0x008 +#define UART485_LCR 0x00C +#define UART485_MCR 0x010 +#define UART485_LSR 0x014 +#define UART485_MSR 0x018 +#define UART485_SCR 0x01C +#define UART485_LPDLL 0x020 +#define UART485_LPDLH 0x024 +#define UART485_RESERVED 0x028 +#define UART485_SRBR 0x030 +#define UART485_STHR 0x06C +#define UART485_FAR 0x070 +#define UART485_TFR 0x074 +#define UART485_RFW 0x078 +#define UART485_USR 0x07C +#define UART485_TFL 0x080 +#define UART485_RFL 0x084 +#define UART485_SRR 0x088 +#define UART485_SRTS 0x08C +#define UART485_SBCR 0x090 +#define UART485_SDMAM 0x094 +#define UART485_SFE 0x098 +#define UART485_SRT 0x09C +#define UART485_STET 0x0A0 +#define UART485_HTX 0x0A4 +#define UART485_DMASA 0x0A8 +#define UART485_TCR 0x0AC +#define UART485_DE_EN 0x0B0 +#define UART485_RE_EN 0x0B4 +#define UART485_DET 0x0B8 +#define UART485_TAT 0x0BC +#define UART485_DLF 0x0C0 +#define UART485_RAR 0x0C4 +#define UART485_TAR 0x0C8 +#define UART485_LCR_EXT 0x0CC +#define UART485_CPR 0x0F4 +#define UART485_UCV 0x0F8 +#define UART485_CTR 0x0FC + +#define UART485_LSR_RFE (1 << 7) +#define UART485_LSR_TEMT (1 << 6) +#define UART485_LSR_THRE (1 << 5) +#define UART485_LSR_BI (1 << 4) +#define UART485_LSR_FE (1 << 3) +#define UART485_LSR_PE (1 << 2) +#define UART485_LSR_OE (1 << 1) +#define UART485_LSR_DR (1 << 0) + +#define UART485_IIR_IID_MASK (0xf << 0) +#define UART485_IIR_IID_MODEM_STATUS 0x0 +#define UART485_IIR_IID_NO_INT_PENDING 0x1 +#define UART485_IIR_IID_THR_EMPTY 0x2 +#define UART485_IIR_IID_REV_DATA_AVAIL 0x4 +#define UART485_IIR_IID_REV_LINE_STATUS 0x6 +#define UART485_IIR_IID_BUSY_DETECT 0x7 +#define UART485_IIR_IID_CHAR_TIMEOUT 0xc + + + +#define CSIZE 0x0003 +#define CS8 0x0000 +#define CS6 0x0001 +#define CS7 0x0002 +#define CS5 0x0003 +#define CSTOPB 0x0004 +#define PARENB 0x0010 +#define PARODD 0x0020 +#define CMSPAR 0x0100 /* mark or space (stick) parity */ +#define CRTSCTS 0x0200 /* flow control */ + +typedef enum { + UART_ID0 = 0, + UART_ID1, + UART_ID2, + UART_ID3, + UART_NUM, +} eUartID; + +void InitUart(unsigned int baud); +void SendUartString(char * buf); +void SendUartChar(char ch); +void PrintVariableValueHex(char * variable, unsigned int value); +void SendUartWord(unsigned int data); +void IntToStr(unsigned int value, char *str); +void uart_init(int id, unsigned int baud, unsigned int flags); +void updateFromUart(int id); + +#endif + diff --git a/A58-STEPLDR/Src/update.c b/A58-STEPLDR/Src/update.c new file mode 100644 index 00000000..8ecdc6a3 --- /dev/null +++ b/A58-STEPLDR/Src/update.c @@ -0,0 +1,227 @@ +#include "amt630h.h" +#include "board.h" +#include "lcd.h" +#include "update.h" +#include "cp15.h" +#include "pxp.h" + +#if LCD_INTERFACE_TYPE == LCD_INTERFACE_MIPI +#define UPDATING_WIDTH 200 +#define UPDATING_HEIGHT 20 + +#define PROGRESS_WIDTH 200 +#define PROGRESS_HEIGHT 36 +#else +#define UPDATING_WIDTH 200 +#define UPDATING_HEIGHT 20 + +#define PROGRESS_WIDTH 200 +#define PROGRESS_HEIGHT 32 +#endif + + + +#define UPDATE_LOGO_WIDTH PROGRESS_WIDTH +#define UPDATE_LOGO_HEIGHT (UPDATING_HEIGHT + PROGRESS_HEIGHT) + +#define UPDATELOGO_DISPLAY_ADDR 0x20ff0000 + +#define PXP_DISPLAY_ADDR 0x21000000 + +#if LCD_BPP == 32 +typedef unsigned int Upcolor; +#define UPDATE_TEXT_COLOR 0xffffffff; //white +#define UPDATE_RECT_COLOR 0xffffffff //white +#define UPDATE_BAR_COLOR 0xff00ff00; //green +#elif LCD_BPP == 16 +typedef unsigned short Upcolor; +#define UPDATE_TEXT_COLOR 0xffff; //white +#define UPDATE_RECT_COLOR 0xffff; //white +#define UPDATE_BAR_COLOR 0x07e0; //green +#endif + +#define UPDATE_LAN_CHINESE +#ifndef UPDATE_LAN_CHINESE +#define UPDATE_LAN_ENGLISH +#endif + +#ifdef UPDATE_LAN_CHINESE +//chinese +#define UPDATING_POINT_COUNT 397 +static unsigned short updating[UPDATING_POINT_COUNT] = +{ + 810, 821, 828, 840, 866, 878, 883, 894, 900, 1008, 1009, 1010, 1021, 1024, 1025, 1026, + 1027, 1028, 1040, 1060, 1066, 1076, 1077, 1078, 1079, 1080, 1083, 1086, 1093, 1094, 1096, 1097, + 1098, 1099, 1100, 1206, 1207, 1210, 1220, 1223, 1224, 1225, 1227, 1228, 1240, 1260, 1261, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1275, 1276, 1277, 1280, 1281, 1283, 1285, 1293, 1299, 1404, + 1405, 1406, 1407, 1410, 1420, 1422, 1425, 1427, 1436, 1440, 1441, 1442, 1443, 1444, 1445, 1461, + 1466, 1467, 1468, 1477, 1481, 1483, 1484, 1492, 1494, 1498, 1499, 1500, 1501, 1502, 1603, 1606, + 1610, 1619, 1621, 1622, 1624, 1627, 1628, 1629, 1636, 1637, 1638, 1639, 1640, 1641, 1644, 1645, + 1664, 1665, 1666, 1667, 1669, 1677, 1678, 1679, 1680, 1683, 1684, 1685, 1686, 1692, 1694, 1695, + 1696, 1697, 1698, 1702, 1806, 1810, 1812, 1813, 1814, 1818, 1819, 1820, 1821, 1824, 1825, 1826, + 1827, 1828, 1829, 1836, 1840, 1844, 1859, 1860, 1861, 1862, 1863, 1864, 1865, 1866, 1867, 1868, + 1869, 1870, 1874, 1875, 1876, 1877, 1880, 1881, 1882, 1883, 1884, 1885, 1891, 1892, 1894, 1896, + 1897, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2014, 2020, 2024, 2025, 2028, + 2036, 2040, 2044, 2058, 2059, 2060, 2063, 2068, 2076, 2077, 2078, 2080, 2085, 2090, 2092, 2094, + 2096, 2097, 2098, 2099, 2100, 2101, 2206, 2210, 2219, 2220, 2221, 2222, 2223, 2224, 2226, 2227, + 2228, 2236, 2237, 2238, 2239, 2240, 2241, 2242, 2243, 2244, 2245, 2260, 2264, 2265, 2266, 2267, + 2268, 2276, 2277, 2279, 2280, 2281, 2282, 2283, 2284, 2285, 2292, 2294, 2295, 2296, 2298, 2406, + 2410, 2419, 2420, 2423, 2426, 2427, 2436, 2440, 2460, 2464, 2465, 2466, 2467, 2468, 2475, 2477, + 2480, 2485, 2492, 2494, 2498, 2499, 2500, 2501, 2502, 2606, 2610, 2621, 2622, 2623, 2626, 2627, + 2640, 2660, 2662, 2663, 2664, 2668, 2674, 2675, 2677, 2680, 2681, 2682, 2683, 2684, 2685, 2692, + 2694, 2695, 2696, 2697, 2698, 2805, 2810, 2820, 2821, 2822, 2825, 2826, 2827, 2840, 2851, 2852, + 2860, 2861, 2862, 2864, 2865, 2866, 2867, 2868, 2874, 2877, 2880, 2885, 2892, 2897, 2899, 3004, + 3005, 3010, 3018, 3019, 3021, 3022, 3024, 3025, 3028, 3040, 3051, 3052, 3060, 3061, 3064, 3068, + 3077, 3080, 3083, 3085, 3092, 3096, 3100, 3106, 3107, 3114, 3115, 3122, 3123, 3203, 3204, 3210, + 3221, 3223, 3224, 3228, 3229, 3230, 3240, 3252, 3264, 3266, 3267, 3268, 3277, 3280, 3284, 3285, + 3292, 3295, 3296, 3300, 3301, 3403, 3422, 3423, 3451, 3464, 3494, 3495, 3502, +}; +#else +//english +#define UPDATING_POINT_COUNT 237 +static unsigned short updating[UPDATING_POINT_COUNT] = +{ + 1021, 1022, 1023, 1044, 1045, 1222, 1223, 1235, 1236, 1422, 1423, 1435, 1436, 1601, 1602, 1603, + 1605, 1606, 1607, 1609, 1610, 1611, 1612, 1613, 1614, 1619, 1620, 1621, 1622, 1623, 1627, 1628, + 1629, 1630, 1633, 1634, 1635, 1636, 1637, 1638, 1642, 1643, 1644, 1645, 1649, 1650, 1652, 1653, + 1654, 1659, 1660, 1661, 1662, 1663, 1802, 1803, 1806, 1807, 1810, 1811, 1814, 1815, 1818, 1819, + 1822, 1823, 1826, 1827, 1830, 1831, 1835, 1836, 1844, 1845, 1850, 1851, 1852, 1854, 1855, 1858, + 1859, 1861, 1862, 2002, 2003, 2006, 2007, 2010, 2011, 2014, 2015, 2018, 2019, 2022, 2023, 2028, + 2029, 2030, 2031, 2035, 2036, 2044, 2045, 2050, 2054, 2055, 2058, 2059, 2061, 2062, 2202, 2203, + 2206, 2207, 2210, 2211, 2214, 2215, 2218, 2219, 2222, 2223, 2227, 2228, 2230, 2231, 2235, 2236, + 2244, 2245, 2250, 2254, 2255, 2259, 2260, 2261, 2402, 2403, 2406, 2407, 2410, 2411, 2414, 2415, + 2418, 2419, 2422, 2423, 2426, 2427, 2430, 2431, 2435, 2436, 2444, 2445, 2450, 2454, 2455, 2458, + 2459, 2466, 2467, 2468, 2474, 2475, 2476, 2482, 2483, 2484, 2603, 2604, 2605, 2606, 2607, 2608, + 2610, 2611, 2612, 2613, 2614, 2619, 2620, 2621, 2622, 2623, 2624, 2627, 2628, 2629, 2630, 2631, + 2632, 2636, 2637, 2638, 2642, 2643, 2644, 2645, 2646, 2647, 2649, 2650, 2651, 2652, 2654, 2655, + 2656, 2658, 2659, 2660, 2661, 2662, 2666, 2667, 2668, 2674, 2675, 2676, 2682, 2683, 2684, 2810, + 2811, 2858, 2859, 2862, 2863, 3009, 3010, 3011, 3012, 3059, 3060, 3061, 3062, +}; +#endif + +static int update_start = 0; +static int update_percent = -1; + +static void updating_init(void) +{ + int i; + Upcolor *p = (Upcolor *)(UPDATELOGO_DISPLAY_ADDR); + Upcolor color = UPDATE_TEXT_COLOR; + int pos = 0; + + for(i = 0; i < UPDATING_WIDTH * UPDATING_HEIGHT; i++) { + if(updating[pos] == i) { + *p = color; + pos++; + } + p++; + } +} + +void update_progress_init(void) +{ + int i, j; + Upcolor *p = (Upcolor *)(UPDATELOGO_DISPLAY_ADDR + + UPDATING_HEIGHT * PROGRESS_WIDTH * LCD_BPP / 8); + int height = UPDATE_LOGO_HEIGHT; + Upcolor color = UPDATE_RECT_COLOR; + + for(j = UPDATING_HEIGHT; j < height; j++) { + for(i = 0; i < PROGRESS_WIDTH; i++) { + if(j < (UPDATING_HEIGHT + 2) || j > (height -3) || \ + i < 2 || i > (PROGRESS_WIDTH -3)) { + *p = color; + } + p++; + } + } +} + +void update_progress_set(int percent) +{ + int i, j, end; + unsigned int memstart = UPDATELOGO_DISPLAY_ADDR + + UPDATING_WIDTH * UPDATING_HEIGHT * LCD_BPP / 8; + Upcolor *p = (Upcolor *)memstart; + int height = UPDATE_LOGO_HEIGHT; + Upcolor color = UPDATE_BAR_COLOR; + + if(percent < 0 || percent > 100) { + return; + } + + if (!update_start || percent == update_percent) + return; + + update_percent = percent; + + end = percent * (PROGRESS_WIDTH - 3) / 100; + + for(j = UPDATING_HEIGHT; j < height; j++) { + for(i = 0; i < PROGRESS_WIDTH; i++) { + if(j > (UPDATING_HEIGHT + 2) && j < (height -3) \ + && i > 2 && i < end) { + *p = color; + } + p++; + } + } + + CP15_clean_dcache_for_dma((unsigned int)memstart, + (unsigned int)memstart + PROGRESS_WIDTH *PROGRESS_HEIGHT * LCD_BPP / 8); + +#if LCD_ROTATE_ANGLE != LCD_ROTATE_ANGLE_0 + pxp_scaler_rotate(UPDATELOGO_DISPLAY_ADDR, 0, 0, + PXP_SRC_FMT_RGB565, UPDATE_LOGO_WIDTH, UPDATE_LOGO_HEIGHT, + PXP_DISPLAY_ADDR, 0, PXP_OUT_FMT_RGB565, UPDATE_LOGO_HEIGHT, UPDATE_LOGO_WIDTH, LCD_ROTATE_ANGLE); +#endif + + +} + +void update_logo_init(void) +{ + int x, y; + unsigned int width = UPDATE_LOGO_WIDTH; + unsigned int height = UPDATE_LOGO_HEIGHT; +#if LCD_ROTATE_ANGLE != LCD_ROTATE_ANGLE_0 + unsigned int display_addr = PXP_DISPLAY_ADDR; + unsigned int out_width; + unsigned int out_height; +#endif + + if (update_start) + return; + + memset((void *)UPDATELOGO_DISPLAY_ADDR, 0 , width *height * LCD_BPP / 8); + updating_init(); + update_progress_init(); + CP15_clean_dcache_for_dma(UPDATELOGO_DISPLAY_ADDR, + UPDATELOGO_DISPLAY_ADDR + width *height * LCD_BPP / 8); + +#if LCD_ROTATE_ANGLE != LCD_ROTATE_ANGLE_0 +#if LCD_ROTATE_ANGLE == LCD_ROTATE_ANGLE_180 + out_width = width; + out_height = height; +#else + out_width = height; + out_height = width; +#endif + ark_lcd_set_osd_size(LCD_OSD1, out_width, out_height); + pxp_scaler_rotate(UPDATELOGO_DISPLAY_ADDR, 0, 0, PXP_SRC_FMT_RGB565, width, height, + display_addr, 0, PXP_OUT_FMT_RGB565, out_width, out_height, LCD_ROTATE_ANGLE); + ark_lcd_set_osd_yaddr(LCD_OSD1, display_addr); + y = (LCD_HEIGHT - out_height) / 2; + x = (LCD_WIDTH - out_width) / 2; +#else + ark_lcd_set_osd_yaddr(LCD_OSD1, UPDATELOGO_DISPLAY_ADDR); + ark_lcd_set_osd_size(LCD_OSD1, width, height); + x = (LCD_WIDTH - width) / 2; + y = (LCD_HEIGHT - height) / 2; +#endif + ark_lcd_set_osd_possition(LCD_OSD1, x, y); + ark_lcd_osd_enable(LCD_OSD1, 1); + ark_lcd_set_osd_sync(LCD_OSD1); + + update_start = 1; +} diff --git a/A58-STEPLDR/Src/update.h b/A58-STEPLDR/Src/update.h new file mode 100644 index 00000000..28a0a227 --- /dev/null +++ b/A58-STEPLDR/Src/update.h @@ -0,0 +1,52 @@ +#ifndef _UPDATE_H_ +#define _UPDATE_H_ + +#define UPFILE_APP_MAGIC 0xe59ff030 +#define APPLDR_CHECKSUM_OFFSET 20 + +#define ROMFILE_NAME_MAX_LEN 64 + +typedef struct { + char name[ROMFILE_NAME_MAX_LEN]; + unsigned int offset; + unsigned int size; +} RomFileInfo; + +typedef struct { + unsigned int magic; + unsigned int filenum; + unsigned int romsize; + unsigned int checksum; + RomFileInfo files[]; +} RomHeader; + +typedef struct { + unsigned int magic; + int hasBootlogo; + int bootlogoDisplayTime; + int aniCount; + int aniWidth; + int aniHeight; + int aniFps; + int aniDelayHideTime; + unsigned int aniSize; + unsigned int checksum; + unsigned int reserved[2]; +}BANIHEADER; + +typedef enum { + UPFILE_TYPE_WHOLE, + UPFILE_TYPE_RESOURCE, + UPFILE_TYPE_ANIMATION, + UPFILE_TYPE_APP, + UPFILE_TYPE_FIRSTLDR, + UPFILE_TYPE_STEPLDR, + UPFILE_TYPE_LNCHEMMC, +} eUpfileType; + +#define MKTAG(a,b,c,d) ((a) | ((b) << 8) | ((c) << 16) | ((unsigned)(d) << 24)) + +void update_logo_init(void); +void update_progress_set(int percent); + +#endif diff --git a/A58-STEPLDR/Src/usb/ark_dwc2.c b/A58-STEPLDR/Src/usb/ark_dwc2.c new file mode 100644 index 00000000..283751a6 --- /dev/null +++ b/A58-STEPLDR/Src/usb/ark_dwc2.c @@ -0,0 +1,619 @@ +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include +#include "core.h" +#include "hcd.h" +#include "ark_dwc2.h" +#include "usbroothubdes.h" +#include "sysctl.h" + +struct dwc2_host_data { + struct dwc2_hsotg *host; + struct usb_hcd hcd; + enum usb_device_speed host_speed; + int root_hub_devnum; + //struct usb_host_endpoint hep; + struct urb urb_in[16]; + struct urb urb_out[16]; + struct usb_host_endpoint hep_in[16]; + struct usb_host_endpoint hep_out[16]; + struct hc_driver *dw2_hc_driver; + List_t free_urb_list; + spinlock_t lock; +}; + +int dwc2_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); +int dwc2_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); +extern int dwc2_driver_init(struct dwc2_hsotg **dev, struct usb_hcd *hcd); +extern int dwc2_driver_uninit(struct dwc2_hsotg *hsotg); +extern struct hc_driver* dwc2_get_driver(); +static int dwc_otg_submit_rh_msg(struct usb_device *dev, + unsigned long pipe, void *buffer, int txlen, + struct devrequest *cmd); + + + +struct dwc2_host_data dwc2_host; + +static void dwc2_host_complete_urb(struct urb *urb) +{ + urb->dev->status &= ~USB_ST_NOT_PROC; + urb->dev->act_len = urb->actual_length; + //printf("actual_length:%d\r\n", urb->actual_length); + urb->urb_complete = 1; +} + +static void usb_urb_release(struct urb *urb) +{ + if (NULL == urb) + return; + spin_lock(&dwc2_host.lock); + list_add_tail(&urb->urb_list, &dwc2_host.free_urb_list); + spin_unlock(&dwc2_host.lock); +} + +static struct urb *usb_urb_alloc(struct dwc2_host_data *ctx, + int iso_desc_count, + gfp_t mem_flags) +{ + struct urb *urb = NULL; + u32 size = sizeof(*urb); + + ListItem_t *pxListItem = NULL; + int found = 0, flags; + spin_lock_irqsave(&ctx->lock, flags); + list_for_each_entry(pxListItem, urb, &ctx->free_urb_list) { + if (urb->number_of_packets == iso_desc_count) { + found = 1; + break; + } + } + if (found) { + list_del_init(&urb->urb_list); + spin_unlock_irqrestore(&ctx->lock, flags); + memset(urb, 0, sizeof(struct urb)); + INIT_LIST_ITEM(&urb->urb_list); + listSET_LIST_ITEM_OWNER(&urb->urb_list, urb); + urb->urb_complete = 0; + return urb; + } + spin_unlock_irqrestore(&ctx->lock, flags); + + urb = (struct urb *)kzalloc(size, mem_flags); + if (urb) { + urb->number_of_packets = iso_desc_count; + INIT_LIST_ITEM(&urb->urb_list); + listSET_LIST_ITEM_OWNER(&urb->urb_list, urb); + urb->urb_complete = 0; + } + + return urb; +} + + +static void construct_urb(struct urb *urb, struct usb_host_endpoint *hep, + struct usb_device *dev, int endpoint_type, + unsigned long pipe, void *buffer, int len, + struct devrequest *setup, int interval) +{ + int epnum = usb_pipeendpoint(pipe); + int is_in = usb_pipein(pipe); + + INIT_LIST_HEAD(&hep->urb_list); + INIT_LIST_ITEM(&urb->urb_list); + urb->urb_list.pvOwner = (void *)urb; + urb->ep = hep; + urb->complete = dwc2_host_complete_urb; + urb->status = -EINPROGRESS; + urb->dev = dev; + urb->pipe = pipe; + urb->transfer_buffer = buffer; + urb->transfer_dma = (dma_addr_t)buffer; + urb->transfer_buffer_length = len; + urb->setup_packet = (unsigned char *)setup; + urb->setup_dma = (dma_addr_t)setup; + urb->transfer_flags &= ~(URB_DIR_MASK | URB_DMA_MAP_SINGLE | + URB_DMA_MAP_PAGE | URB_DMA_MAP_SG | URB_MAP_LOCAL | + URB_SETUP_MAP_SINGLE | URB_SETUP_MAP_LOCAL | + URB_DMA_SG_COMBINED); + urb->transfer_flags |= (is_in ? URB_DIR_IN : URB_DIR_OUT); + + urb->ep->desc.wMaxPacketSize = + __cpu_to_le16(is_in ? dev->epmaxpacketin[epnum] : + dev->epmaxpacketout[epnum]); + urb->ep->desc.bmAttributes = endpoint_type; + urb->ep->desc.bEndpointAddress = + (is_in ? USB_DIR_IN : USB_DIR_OUT) | epnum; + urb->ep->desc.bInterval = interval; +} + +static int submit_urb(struct usb_hcd *hcd, struct urb *urb) +{ + int ret; + + ret = dwc2_urb_enqueue(hcd, urb, 0); + if (ret < 0) { + PrintVariableValueHex("Failed to enqueue URB to controller ret", ret); + return ret; + } + + return ret; +} + +static int _dwc2_submit_control_msg(struct dwc2_host_data *host, + struct usb_device *dev, unsigned long pipe, + void *buffer, int len, struct devrequest *setup, int timeout) +{ + struct urb *urb = NULL; + struct usb_host_endpoint *hep = NULL; + int epnum = usb_pipeendpoint(pipe); + int is_in = usb_pipein(pipe); + int ret = 0; + unsigned int start_time; + + if (epnum > 8 || epnum < 0) + return -EINVAL; + + if (is_in) { + hep = &host->hep_in[epnum]; + } else { + hep = &host->hep_out[epnum]; + } + urb = usb_urb_alloc(host, 0, IRQ_NONE); + if (urb == NULL) + return -ENOMEM; + + construct_urb(urb, hep, dev, USB_ENDPOINT_XFER_CONTROL, + pipe, buffer, len, setup, 0); + + /* Fix speed for non hub-attached devices */ + if (!usb_dev_get_parent(dev)) + dev->speed = host->host_speed; + //unsigned char *a = urb->setup_packet; + //if (a) + //printf("setup-->%02x %02x %02x %02x %02x %02x %02x %02x\r\n", a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7]); + ret = submit_urb(&host->hcd, urb); + if (ret < 0) { + dwc2_urb_dequeue(&host->hcd, urb, 0); + goto exit; + } + + start_time = get_timer(0); + ret = pdTRUE; + do { + if (get_timer(start_time) > timeout) { + ret = pdFALSE; + break; + } + } while(!urb->urb_complete); + if (ret != pdTRUE || 0 != urb->status) {//timeout + dwc2_urb_dequeue(&host->hcd, urb, 0); + if (0 != urb->status) + PrintVariableValueHex("usb control urb error", urb->status); + ret = urb->status; + } else { + ret = urb->actual_length; + } +exit: + usb_urb_release(urb); + return ret; +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int *actual_length, int timeout) +{ + struct urb *urb = NULL; + struct usb_host_endpoint *hep = NULL; + int epnum = usb_pipeendpoint(pipe); + int is_in = usb_pipein(pipe); + int ret = 0; + struct dwc2_host_data *host = &dwc2_host; + unsigned int start_time; + + if (epnum > 8 || epnum < 0) + return -EINVAL; + if (is_in) { + hep = &host->hep_in[epnum]; + } else { + hep = &host->hep_out[epnum]; + } + + urb = usb_urb_alloc(host, 0, IRQ_NONE); + if (urb == NULL) + return -ENOMEM; + + construct_urb(urb, hep, dev, USB_ENDPOINT_XFER_BULK, + pipe, buffer, transfer_len, NULL, 0); + ret = submit_urb(&host->hcd, urb); + if (ret < 0) { + dwc2_urb_dequeue(&host->hcd, urb, 0); + goto exit; + } + + start_time = get_timer(0); + ret = pdTRUE; + do { + if (get_timer(start_time) > timeout) { + ret = pdFALSE; + break; + } + } while(!urb->urb_complete); + if (ret != pdTRUE || 0 != urb->status) {//timeout + dwc2_urb_dequeue(&host->hcd, urb, 0); + if (actual_length) + *actual_length = 0; + if (0 != urb->status) + PrintVariableValueHex("usb bulk urb error", urb->status); + ret = urb->status; + } else { + if (actual_length) + *actual_length = urb->actual_length; + } + +exit: + usb_urb_release(urb); + + return ret; +} + +void usb_reset_endpoint() +{ + int i; + struct dwc2_host_data *host = &dwc2_host; + + if ((NULL == host->dw2_hc_driver) || (NULL == host->dw2_hc_driver->endpoint_reset)) + return; + for (i = 0; i < 16; i++) { + host->dw2_hc_driver->endpoint_reset(&(host->hcd), &host->hep_in[i]); + host->dw2_hc_driver->endpoint_reset(&(host->hcd), &host->hep_out[i]); + } +} + +void usb_disable_endpoint() +{ + int i; + struct dwc2_host_data *host = &dwc2_host; + + if ((NULL == host->dw2_hc_driver) || (NULL == host->dw2_hc_driver->endpoint_disable)) + return; + for (i = 0; i < 16; i++) { + host->dw2_hc_driver->endpoint_disable(&(host->hcd), &host->hep_in[i]); + host->dw2_hc_driver->endpoint_disable(&(host->hcd), &host->hep_out[i]); + } +} + +void reset_usb_phy() +{ + vSysctlConfigure(SYS_SOFT_RST, 30, 1, 0);//phy reset + mdelay(10); + vSysctlConfigure(SYS_SOFT_RST, 30, 1, 1);//phy reset +} + +void usb_sysctrl_init() +{ + vSysctlConfigure(SYS_ANA_CFG, 8, 0xff, 4); + + vSysctlConfigure(SYS_SOFT_RST, 30, 1, 0);//phy reset + vSysctlConfigure(SYS_SOFT_RST, 3, 1, 0); + mdelay(10); + vSysctlConfigure(SYS_SOFT_RST, 30, 1, 1);//phy reset + vSysctlConfigure(SYS_SOFT_RST, 3, 1, 1); + vSysctlConfigure(SYS_ANA_CFG, 24, 3, 1); + mdelay(10); +} + + + +int hub_status_data(char buf[8]) +{ + int ret = 1; + struct dwc2_host_data *host = &dwc2_host; + //printf("prvUsbPortScanTimerCallback\r\n"); + ret = host->dw2_hc_driver->hub_status_data(&(host->hcd), buf); + if (ret != 0) { + //printf("state:%d usb state changed now!\r\n", buf[0]); + } + return ret; +} + +void usb_dwc2_lowlevel_restart() +{ + struct dwc2_host_data *host = &dwc2_host; + + if (host->dw2_hc_driver && host->dw2_hc_driver->stop) { + host->dw2_hc_driver->stop(&(host->hcd)); + } + msleep(50); + if (host->dw2_hc_driver && host->dw2_hc_driver->start) { + host->dw2_hc_driver->start(&(host->hcd)); + } +} + + +//#define mainTIMER_SCAN_FREQUENCY_MS pdMS_TO_TICKS( 1000UL ) + +int usb_dwc2_lowlevel_init() +{ + struct dwc2_host_data *host = &dwc2_host; + int ret; + + INIT_LIST_HEAD(&host->free_urb_list); + spin_lock_init(&host->lock); + + ret = dwc2_driver_init(&host->host, &(host->hcd)); + if (!host->host) { + SendUartString("MUSB host is not registered\n"); + return -ENODEV; + } + host->dw2_hc_driver = dwc2_get_driver(); + + + return ret; +} + +int usb_dwc2_lowlevel_uninit() +{ + if (!dwc2_host.host) { + SendUartString("MUSB host is not registered\n"); + return -ENODEV; + } + + dwc2_driver_uninit(dwc2_host.host); + return 0; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int length, struct devrequest *setup, int timeout) +{ + if (dev->parent == NULL) { + return dwc_otg_submit_rh_msg(dev, pipe, buffer, length, setup); + } else { + return _dwc2_submit_control_msg(&dwc2_host, dev, pipe, buffer, length, setup, timeout); + } +} + +/* + * DWC2 to USB API interface + */ +/* Direction: In ; Request: Status */ +static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer, + int txlen, struct devrequest *cmd) +{ + int len = 0; + int stat = 0; + + switch (cmd->requesttype & ~USB_DIR_IN) { + case 0: + *(uint16_t *)buffer = cpu_to_le16(1); + len = 2; + break; + case USB_RECIP_INTERFACE: + case USB_RECIP_ENDPOINT: + *(uint16_t *)buffer = cpu_to_le16(0); + len = 2; + break; + case USB_TYPE_CLASS: + *(uint32_t *)buffer = cpu_to_le32(0); + len = 4; + break; + case USB_RECIP_OTHER | USB_TYPE_CLASS: + len = 4; + stat = dwc2_host.dw2_hc_driver->hub_control(&dwc2_host.hcd, (cmd->requesttype << 8) | (cmd->request), + cmd->value, cmd->index, (char*)buffer, len); + + break; + default: + //puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + dev->act_len = min(len, txlen); + dev->status = stat; + + return stat; +} + +/* Direction: In ; Request: Descriptor */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xffUL << 24) /* power on to power good time */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, + void *buffer, int txlen, + struct devrequest *cmd) +{ + + unsigned char data[32]; + uint32_t dsc; + int len = 0; + int stat = 0; + uint16_t wValue = cpu_to_le16(cmd->value); + uint16_t wLength = cpu_to_le16(cmd->length); + + switch (cmd->requesttype & ~USB_DIR_IN) { + case 0: + { + switch (wValue & 0xff00) { + case 0x0100: /* device descriptor */ + len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); + memcpy(buffer, root_hub_dev_des, len); + break; + case 0x0200: /* configuration descriptor */ + len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); + memcpy(buffer, root_hub_config_des, len); + break; + case 0x0300: /* string descriptors */ + switch (wValue & 0xff) { + case 0x00: + len = min3(txlen, (int)sizeof(root_hub_str_index0), + (int)wLength); + memcpy(buffer, root_hub_str_index0, len); + break; + case 0x01: + len = min3(txlen, (int)sizeof(root_hub_str_index1), + (int)wLength); + memcpy(buffer, root_hub_str_index1, len); + break; + } + break; + default: + stat = USB_ST_STALLED; + } + break; + } + case USB_TYPE_CLASS: + /* Root port config, set 1 port and nothing else. */ + dsc = 0x00000001; + + data[0] = 9; /* min length; */ + data[1] = 0x29; + data[2] = dsc & RH_A_NDP; + data[3] = 0; + if (dsc & RH_A_PSM) + data[3] |= 0x1; + if (dsc & RH_A_NOCP) + data[3] |= 0x10; + else if (dsc & RH_A_OCPM) + data[3] |= 0x8; + + /* corresponds to data[4-7] */ + data[5] = (dsc & RH_A_POTPGT) >> 24; + data[7] = dsc & RH_B_DR; + if (data[2] < 7) { + data[8] = 0xff; + } else { + data[0] += 2; + data[8] = (dsc & RH_B_DR) >> 8; + data[9] = 0xff; + data[10] = data[9]; + } + + len = min3(txlen, (int)data[0], (int)wLength); + memcpy(buffer, data, len); + break; + default: + //puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + dev->act_len = min(len, txlen); + dev->status = stat; + + return stat; +} + +/* Direction: In ; Request: Configuration */ +static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, + void *buffer, int txlen, + struct devrequest *cmd) +{ + int len = 0; + int stat = 0; + + switch (cmd->requesttype & ~USB_DIR_IN) { + case 0: + *(uint8_t *)buffer = 0x01; + len = 1; + break; + default: + //puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + dev->act_len = min(len, txlen); + dev->status = stat; + + return stat; +} + +/* Direction: In */ +static int dwc_otg_submit_rh_msg_in( + struct usb_device *dev, void *buffer, + int txlen, struct devrequest *cmd) +{ + switch (cmd->request) { + case USB_REQ_GET_STATUS: + return dwc_otg_submit_rh_msg_in_status(dev, buffer, + txlen, cmd); + case USB_REQ_GET_DESCRIPTOR: + return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, + txlen, cmd); + case USB_REQ_GET_CONFIGURATION: + return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, + txlen, cmd); + default: + //puts("unsupported root hub command\n"); + return USB_ST_STALLED; + } +} + +/* Direction: Out */ +static int dwc_otg_submit_rh_msg_out( + struct usb_device *dev, + void *buffer, int txlen, + struct devrequest *cmd) +{ + int len = 0; + int stat = 0; + uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); + uint16_t wValue = cpu_to_le16(cmd->value); + switch (bmrtype_breq & ~USB_DIR_IN) { + case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: + case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: + break; + + case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: + case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: + dwc2_host.dw2_hc_driver->hub_control(&dwc2_host.hcd, (cmd->requesttype << 8) | (cmd->request), + cmd->value, cmd->index, (char*)buffer, txlen); + break; + case (USB_REQ_SET_ADDRESS << 8): + dwc2_host.root_hub_devnum = wValue; + dwc2_host.dw2_hc_driver->hub_control(&dwc2_host.hcd, (cmd->requesttype << 8) | (cmd->request), + cmd->value, cmd->index, (char*)buffer, txlen); + break; + case (USB_REQ_SET_CONFIGURATION << 8): + break; + default: + //puts("unsupported root hub command\n"); + stat = USB_ST_STALLED; + } + + len = min(len, txlen); + + dev->act_len = len; + dev->status = stat; + + return stat; +} + +static int dwc_otg_submit_rh_msg(struct usb_device *dev, + unsigned long pipe, void *buffer, int txlen, + struct devrequest *cmd) +{ + int stat = 0; + if (usb_pipeint(pipe)) { + //puts("Root-Hub submit IRQ: NOT implemented\n"); + return 0; + } + + if (cmd->requesttype & USB_DIR_IN) + stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd); + else + stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd); + + stat = dev->act_len; + return stat; +} + diff --git a/A58-STEPLDR/Src/usb/ark_dwc2.h b/A58-STEPLDR/Src/usb/ark_dwc2.h new file mode 100644 index 00000000..60161d21 --- /dev/null +++ b/A58-STEPLDR/Src/usb/ark_dwc2.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * MUSB OTG driver u-boot specific functions + * + * Copyright © 2015 Hans de Goede + */ +#ifndef __ARK_USB_DWC2_H__ +#define __ARK_USB_DWC2_H__ + +int usb_dwc2_lowlevel_init(); +int usb_dwc2_lowlevel_uninit(); +void usb_sysctrl_init(); +void reset_usb_phy(); +void usb_disable_endpoint(); +void usb_reset_endpoint(); +void usb_dwc2_lowlevel_restart(); + + +#endif diff --git a/A58-STEPLDR/Src/usb/core.c b/A58-STEPLDR/Src/usb/core.c new file mode 100644 index 00000000..0baf205e --- /dev/null +++ b/A58-STEPLDR/Src/usb/core.c @@ -0,0 +1,296 @@ +/* + * core.c - DesignWare HS OTG Controller common routines + * + * Copyright (C) 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * The Core code provides basic services for accessing and managing the + * DWC_otg hardware. These services are used by both the Host Controller + * Driver and the Peripheral Controller Driver. + */ +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include + +#include "core.h" +#include "hcd.h" + +/** + * dwc2_wait_for_mode() - Waits for the controller mode. + * @hsotg: Programming view of the DWC_otg controller. + * @host_mode: If true, waits for host mode, otherwise device mode. + */ +static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, + bool host_mode) +{ + uint32_t tick = get_timer(0); + unsigned int timeout = 110;//ms + + dev_vdbg(hsotg->dev, "Waiting for %s mode\n", + host_mode ? "host" : "device"); + + while (1) { + __s64 ms; + + if (dwc2_is_host_mode(hsotg) == host_mode) { + dev_vdbg(hsotg->dev, "%s mode set\n", + host_mode ? "Host" : "Device"); + break; + } + + ms = get_timer(tick); + if (ms >= (__s64)timeout) { + dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", + __func__, host_mode ? "host" : "device"); + break; + } + //vTaskDelay(2000 / portTICK_RATE_MS); + mdelay(10); + } +} + +/* + * Do core a soft reset of the core. Be careful with this because it + * resets all the internal state machines of the core. + */ +int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) +{ + u32 greset; + int count = 0; + bool wait_for_host_mode = false; + + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + /* + * If the current mode is host, either due to the force mode + * bit being set (which persists after core reset) or the + * connector id pin, a core soft reset will temporarily reset + * the mode to device. A delay from the IDDIG debounce filter + * will occur before going back to host mode. + * + * Determine whether we will go back into host mode after a + * reset and account for this delay after the reset. + */ + + /* Core Soft Reset */ + greset = dwc2_readl(hsotg->regs + GRSTCTL); + greset |= GRSTCTL_CSFTRST; + dwc2_writel(greset, hsotg->regs + GRSTCTL); + do { + udelay(1); + greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! Soft Reset GRSTCTL=%0x\n", + __func__, greset); + return -EBUSY; + } + } while (greset & GRSTCTL_CSFTRST); + + /* Wait for AHB master IDLE state */ + count = 0; + do { + udelay(1); + greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! AHB Idle GRSTCTL=%0x\n", + __func__, greset); + return -EBUSY; + } + } while (!(greset & GRSTCTL_AHBIDLE)); + + if (wait_for_host_mode && !skip_wait) + dwc2_wait_for_mode(hsotg, true); + + return 0; +} + +/* + * Sets or clears force mode based on the dr_mode parameter. + */ +void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) +{ + switch (hsotg->dr_mode) { + case USB_DR_MODE_HOST: + /* + * NOTE: This is required for some rockchip soc based + * platforms on their host-only dwc2. + */ + msleep(50); + + break; + default: + dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", + __func__, hsotg->dr_mode); + break; + } +} + +/* + * Do core a soft reset of the core. Be careful with this because it + * resets all the internal state machines of the core. + * + * Additionally this will apply force mode as per the hsotg->dr_mode + * parameter. + */ +int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg) +{ + int retval; + + retval = dwc2_core_reset(hsotg, false); + if (retval) + return retval; + + dwc2_force_dr_mode(hsotg); + return 0; +} + +/** + * dwc2_flush_tx_fifo() - Flushes a Tx FIFO + * + * @hsotg: Programming view of DWC_otg controller + * @num: Tx FIFO to flush + */ +void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) +{ + u32 greset; + int count = 0; + + dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); + + greset = GRSTCTL_TXFFLSH; + greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; + dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { + greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, + "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset, + dwc2_readl(hsotg->regs + GNPTXSTS)); + break; + } + udelay(1); + } while (greset & GRSTCTL_TXFFLSH); + + /* Wait for at least 3 PHY Clocks */ + udelay(1); +} + +/** + * dwc2_flush_rx_fifo() - Flushes the Rx FIFO + * + * @hsotg: Programming view of DWC_otg controller + */ +void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) +{ + u32 greset; + int count = 0; + + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + greset = GRSTCTL_RXFFLSH; + dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { + greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", + __func__, greset); + break; + } + udelay(1); + } while (greset & GRSTCTL_RXFFLSH); + + /* Wait for at least 3 PHY Clocks */ + udelay(1); +} + +bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) +{ + if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) + return false; + else + return true; +} + +/** + * dwc2_enable_global_interrupts() - Enables the controller's Global + * Interrupt in the AHB Config register + * + * @hsotg: Programming view of DWC_otg controller + */ +void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) +{ + u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg |= GAHBCFG_GLBL_INTR_EN; + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); +} + +/** + * dwc2_disable_global_interrupts() - Disables the controller's Global + * Interrupt in the AHB Config register + * + * @hsotg: Programming view of DWC_otg controller + */ +void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) +{ + u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); +} + +/* Returns the controller's GHWCFG2.OTG_MODE. */ +unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) +{ + u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); + + return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> + GHWCFG2_OP_MODE_SHIFT; +} + +/* Returns true if the controller is host-only. */ +bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) +{ + unsigned int op_mode = dwc2_op_mode(hsotg); + + return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || + (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); +} \ No newline at end of file diff --git a/A58-STEPLDR/Src/usb/core.h b/A58-STEPLDR/Src/usb/core.h new file mode 100644 index 00000000..bf1fb319 --- /dev/null +++ b/A58-STEPLDR/Src/usb/core.h @@ -0,0 +1,1032 @@ +/* + * core.h - DesignWare HS OTG Controller common declarations + * + * Copyright (C) 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DWC2_CORE_H__ +#define __DWC2_CORE_H__ + +#include "board.h" + +#include "dwc2_compat.h" +//#include +#include "usb_os_adapter.h" + +#include "hw.h" + +/* + * Suggested defines for tracers: + * - no_printk: Disable tracing + * - pr_info: Print this info to the console + * - trace_printk: Print this info to trace buffer (good for verbose logging) + */ +#define dwc2_sch_dbg(hsotg, fmt, ...) +#define dwc2_sch_vdbg(hsotg, fmt, ...) + +#ifdef CONFIG_MIPS +/* + * There are some MIPS machines that can run in either big-endian + * or little-endian mode and that use the dwc2 register without + * a byteswap in both ways. + * Unlike other architectures, MIPS apparently does not require a + * barrier before the __raw_writel() to synchronize with DMA but does + * require the barrier after the __raw_writel() to serialize a set of + * writes. This set of operations was added specifically for MIPS and + * should only be used there. + */ +static inline u32 dwc2_readl(const void __iomem *addr) +{ + u32 value = __raw_readl(addr); + + /* In order to preserve endianness __raw_* operation is used. Therefore + * a barrier is needed to ensure IO access is not re-ordered across + * reads or writes + */ + mb(); + return value; +} + +static inline void dwc2_writel(u32 value, void __iomem *addr) +{ + __raw_writel(value, addr); + + /* + * In order to preserve endianness __raw_* operation is used. Therefore + * a barrier is needed to ensure IO access is not re-ordered across + * reads or writes + */ + mb(); +#ifdef DWC2_LOG_WRITES + pr_info("INFO:: wrote %08x to %p\n", value, addr); +#endif +} +#else +/* Normal architectures just use readl/write */ +static inline u32 dwc2_readl(u32 addr) +{ + return readl(addr); +} + +static inline void dwc2_writel(u32 value, u32 addr) +{ + writel(value, addr); + +#ifdef DWC2_LOG_WRITES + pr_info("info:: wrote %08x to %p\n", value, addr); +#endif +} +#endif + +/* Maximum number of Endpoints/HostChannels */ +#define MAX_EPS_CHANNELS 4 + +/* dwc2-hsotg declarations */ +static const char * const dwc2_hsotg_supply_names[] = { + "vusb_d", /* digital USB supply, 1.2V */ + "vusb_a", /* analog USB supply, 1.1V */ +}; + +#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) + +/* + * EP0_MPS_LIMIT + * + * Unfortunately there seems to be a limit of the amount of data that can + * be transferred by IN transactions on EP0. This is either 127 bytes or 3 + * packets (which practically means 1 packet and 63 bytes of data) when the + * MPS is set to 64. + * + * This means if we are wanting to move >127 bytes of data, we need to + * split the transactions up, but just doing one packet at a time does + * not work (this may be an implicit DATA0 PID on first packet of the + * transaction) and doing 2 packets is outside the controller's limits. + * + * If we try to lower the MPS size for EP0, then no transfers work properly + * for EP0, and the system will fail basic enumeration. As no cause for this + * has currently been found, we cannot support any large IN transfers for + * EP0. + */ +#define EP0_MPS_LIMIT 64 + +struct dwc2_hsotg; +struct dwc2_hsotg_req; + +/** + * struct dwc2_hsotg_ep - driver endpoint definition. + * @ep: The gadget layer representation of the endpoint. + * @name: The driver generated name for the endpoint. + * @queue: Queue of requests for this endpoint. + * @parent: Reference back to the parent device structure. + * @req: The current request that the endpoint is processing. This is + * used to indicate an request has been loaded onto the endpoint + * and has yet to be completed (maybe due to data move, or simply + * awaiting an ack from the core all the data has been completed). + * @debugfs: File entry for debugfs file for this endpoint. + * @lock: State lock to protect contents of endpoint. + * @dir_in: Set to true if this endpoint is of the IN direction, which + * means that it is sending data to the Host. + * @index: The index for the endpoint registers. + * @mc: Multi Count - number of transactions per microframe + * @interval - Interval for periodic endpoints, in frames or microframes. + * @name: The name array passed to the USB core. + * @halted: Set if the endpoint has been halted. + * @periodic: Set if this is a periodic ep, such as Interrupt + * @isochronous: Set if this is a isochronous ep + * @send_zlp: Set if we need to send a zero-length packet. + * @desc_list_dma: The DMA address of descriptor chain currently in use. + * @desc_list: Pointer to descriptor DMA chain head currently in use. + * @desc_count: Count of entries within the DMA descriptor chain of EP. + * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1. + * @next_desc: index of next free descriptor in the ISOC chain under SW control. + * @total_data: The total number of data bytes done. + * @fifo_size: The size of the FIFO (for periodic IN endpoints) + * @fifo_load: The amount of data loaded into the FIFO (periodic IN) + * @last_load: The offset of data for the last start of request. + * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN + * @target_frame: Targeted frame num to setup next ISOC transfer + * @frame_overrun: Indicates SOF number overrun in DSTS + * + * This is the driver's state for each registered enpoint, allowing it + * to keep track of transactions that need doing. Each endpoint has a + * lock to protect the state, to try and avoid using an overall lock + * for the host controller as much as possible. + * + * For periodic IN endpoints, we have fifo_size and fifo_load to try + * and keep track of the amount of data in the periodic FIFO for each + * of these as we don't have a status register that tells us how much + * is in each of them. (note, this may actually be useless information + * as in shared-fifo mode periodic in acts like a single-frame packet + * buffer than a fifo) + */ +struct dwc2_hsotg_ep { + struct usb_ep ep; + List_t queue; + struct dwc2_hsotg *parent; + struct dwc2_hsotg_req *req; + struct dentry *debugfs; + + unsigned long total_data; + unsigned int size_loaded; + unsigned int last_load; + unsigned int fifo_load; + unsigned short fifo_size; + unsigned short fifo_index; + + unsigned char dir_in; + unsigned char index; + unsigned char mc; + u16 interval; + + unsigned int halted:1; + unsigned int periodic:1; + unsigned int isochronous:1; + unsigned int send_zlp:1; + unsigned int target_frame; +#define TARGET_FRAME_INITIAL 0xFFFFFFFF + bool frame_overrun; + + u8 desc_count; + unsigned char isoc_chain_num; + unsigned int next_desc; + + char name[10]; +}; + +/** + * struct dwc2_hsotg_req - data transfer request + * @req: The USB gadget request + * @queue: The list of requests for the endpoint this is queued for. + * @saved_req_buf: variable to save req.buf when bounce buffers are used. + */ +struct dwc2_hsotg_req { + struct usb_request req; + ListItem_t queue; + void *saved_req_buf; +}; + +struct dwc2_hsotg; +struct dwc2_host_chan; + +/* Device States */ +enum dwc2_lx_state { + DWC2_L0, /* On state */ + DWC2_L1, /* LPM sleep state */ + DWC2_L2, /* USB suspend state */ + DWC2_L3, /* Off state */ +}; + +/* Gadget ep0 states */ +enum dwc2_ep0_state { + DWC2_EP0_SETUP, + DWC2_EP0_DATA_IN, + DWC2_EP0_DATA_OUT, + DWC2_EP0_STATUS_IN, + DWC2_EP0_STATUS_OUT, +}; + +/** + * struct dwc2_core_params - Parameters for configuring the core + * + * @otg_cap: Specifies the OTG capabilities. + * 0 - HNP and SRP capable + * 1 - SRP Only capable + * 2 - No HNP/SRP capable (always available) + * Defaults to best available option (0, 1, then 2) + * @host_dma: Specifies whether to use slave or DMA mode for accessing + * the data FIFOs. The driver will automatically detect the + * value for this parameter if none is specified. + * 0 - Slave (always available) + * 1 - DMA (default, if available) + * @dma_desc_enable: When DMA mode is enabled, specifies whether to use + * address DMA mode or descriptor DMA mode for accessing + * the data FIFOs. The driver will automatically detect the + * value for this if none is specified. + * 0 - Address DMA + * 1 - Descriptor DMA (default, if available) + * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use + * address DMA mode or descriptor DMA mode for accessing + * the data FIFOs in Full Speed mode only. The driver + * will automatically detect the value for this if none is + * specified. + * 0 - Address DMA + * 1 - Descriptor DMA in FS (default, if available) + * @speed: Specifies the maximum speed of operation in host and + * device mode. The actual speed depends on the speed of + * the attached device and the value of phy_type. + * 0 - High Speed + * (default when phy_type is UTMI+ or ULPI) + * 1 - Full Speed + * (default when phy_type is Full Speed) + * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters + * 1 - Allow dynamic FIFO sizing (default, if available) + * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs + * are enabled for non-periodic IN endpoints in device + * mode. + * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when + * dynamic FIFO sizing is enabled + * 16 to 32768 + * Actual maximum value is autodetected and also + * the default. + * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO + * in host mode when dynamic FIFO sizing is enabled + * 16 to 32768 + * Actual maximum value is autodetected and also + * the default. + * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in + * host mode when dynamic FIFO sizing is enabled + * 16 to 32768 + * Actual maximum value is autodetected and also + * the default. + * @max_transfer_size: The maximum transfer size supported, in bytes + * 2047 to 65,535 + * Actual maximum value is autodetected and also + * the default. + * @max_packet_count: The maximum number of packets in a transfer + * 15 to 511 + * Actual maximum value is autodetected and also + * the default. + * @host_channels: The number of host channel registers to use + * 1 to 16 + * Actual maximum value is autodetected and also + * the default. + * @phy_type: Specifies the type of PHY interface to use. By default, + * the driver will automatically detect the phy_type. + * 0 - Full Speed Phy + * 1 - UTMI+ Phy + * 2 - ULPI Phy + * Defaults to best available option (2, 1, then 0) + * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter + * is applicable for a phy_type of UTMI+ or ULPI. (For a + * ULPI phy_type, this parameter indicates the data width + * between the MAC and the ULPI Wrapper.) Also, this + * parameter is applicable only if the OTG_HSPHY_WIDTH cC + * parameter was set to "8 and 16 bits", meaning that the + * core has been configured to work at either data path + * width. + * 8 or 16 (default 16 if available) + * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single + * data rate. This parameter is only applicable if phy_type + * is ULPI. + * 0 - single data rate ULPI interface with 8 bit wide + * data bus (default) + * 1 - double data rate ULPI interface with 4 bit wide + * data bus + * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or + * external supply to drive the VBus + * 0 - Internal supply (default) + * 1 - External supply + * @i2c_enable: Specifies whether to use the I2Cinterface for a full + * speed PHY. This parameter is only applicable if phy_type + * is FS. + * 0 - No (default) + * 1 - Yes + * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only + * 0 - No (default) + * 1 - Yes + * @host_support_fs_ls_low_power: Specifies whether low power mode is supported + * when attached to a Full Speed or Low Speed device in + * host mode. + * 0 - Don't support low power mode (default) + * 1 - Support low power mode + * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode + * when connected to a Low Speed device in host + * mode. This parameter is applicable only if + * host_support_fs_ls_low_power is enabled. + * 0 - 48 MHz + * (default when phy_type is UTMI+ or ULPI) + * 1 - 6 MHz + * (default when phy_type is Full Speed) + * @ts_dline: Enable Term Select Dline pulsing + * 0 - No (default) + * 1 - Yes + * @reload_ctl: Allow dynamic reloading of HFIR register during runtime + * 0 - No (default for core < 2.92a) + * 1 - Yes (default for core >= 2.92a) + * @ahbcfg: This field allows the default value of the GAHBCFG + * register to be overridden + * -1 - GAHBCFG value will be set to 0x06 + * (INCR4, default) + * all others - GAHBCFG value will be overridden with + * this value + * Not all bits can be controlled like this, the + * bits defined by GAHBCFG_CTRL_MASK are controlled + * by the driver and are ignored in this + * configuration value. + * @uframe_sched: True to enable the microframe scheduler + * @external_id_pin_ctl: Specifies whether ID pin is handled externally. + * Disable CONIDSTSCHNG controller interrupt in such + * case. + * 0 - No (default) + * 1 - Yes + * @hibernation: Specifies whether the controller support hibernation. + * If hibernation is enabled, the controller will enter + * hibernation in both peripheral and host mode when + * needed. + * 0 - No (default) + * 1 - Yes + * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO + * register. + * 0 - Deactivate the transceiver (default) + * 1 - Activate the transceiver + * @g_dma: Enables gadget dma usage (default: autodetect). + * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). + * @g_rx_fifo_size: The periodic rx fifo size for the device, in + * DWORDS from 16-32768 (default: 2048 if + * possible, otherwise autodetect). + * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in + * DWORDS from 16-32768 (default: 1024 if + * possible, otherwise autodetect). + * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo + * mode. Each value corresponds to one EP + * starting from EP1 (max 15 values). Sizes are + * in DWORDS with possible values from from + * 16-32768 (default: 256, 256, 256, 256, 768, + * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). + * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL + * while full&low speed device connect. And change speed + * back to DWC2_SPEED_PARAM_HIGH while device is gone. + * 0 - No (default) + * 1 - Yes + * + * The following parameters may be specified when starting the module. These + * parameters define how the DWC_otg controller should be configured. A + * value of -1 (or any other out of range value) for any parameter means + * to read the value from hardware (if possible) or use the builtin + * default described above. + */ +struct dwc2_core_params { + u8 otg_cap; +#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 +#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 +#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 + + u8 phy_type; +#define DWC2_PHY_TYPE_PARAM_FS 0 +#define DWC2_PHY_TYPE_PARAM_UTMI 1 +#define DWC2_PHY_TYPE_PARAM_ULPI 2 + + u8 speed; +#define DWC2_SPEED_PARAM_HIGH 0 +#define DWC2_SPEED_PARAM_FULL 1 +#define DWC2_SPEED_PARAM_LOW 2 + + u8 phy_utmi_width; + bool enable_dynamic_fifo; + bool en_multiple_tx_fifo; + bool reload_ctl; + bool activate_stm_fs_transceiver; + u16 max_packet_count; + u32 max_transfer_size; + u32 ahbcfg; + + u8 host_channels; + u16 host_rx_fifo_size; + u16 host_nperio_tx_fifo_size; + u16 host_perio_tx_fifo_size; + + bool change_speed_quirk; +}; + +/** + * struct dwc2_hw_params - Autodetected parameters. + * + * These parameters are the various parameters read from hardware + * registers during initialization. They typically contain the best + * supported or maximum value that can be configured in the + * corresponding dwc2_core_params value. + * + * The values that are not in dwc2_core_params are documented below. + * + * @op_mode Mode of Operation + * 0 - HNP- and SRP-Capable OTG (Host & Device) + * 1 - SRP-Capable OTG (Host & Device) + * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) + * 3 - SRP-Capable Device + * 4 - Non-OTG Device + * 5 - SRP-Capable Host + * 6 - Non-OTG Host + * @arch Architecture + * 0 - Slave only + * 1 - External DMA + * 2 - Internal DMA + * @power_optimized Are power optimizations enabled? + * @num_dev_ep Number of device endpoints available + * @num_dev_perio_in_ep Number of device periodic IN endpoints + * available + * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue + * Depth + * 0 to 30 + * @host_perio_tx_q_depth + * Host Mode Periodic Request Queue Depth + * 2, 4 or 8 + * @nperio_tx_q_depth + * Non-Periodic Request Queue Depth + * 2, 4 or 8 + * @hs_phy_type High-speed PHY interface type + * 0 - High-speed interface not supported + * 1 - UTMI+ + * 2 - ULPI + * 3 - UTMI+ and ULPI + * @fs_phy_type Full-speed PHY interface type + * 0 - Full speed interface not supported + * 1 - Dedicated full speed interface + * 2 - FS pins shared with UTMI+ pins + * 3 - FS pins shared with ULPI pins + * @total_fifo_size: Total internal RAM for FIFOs (bytes) + * @utmi_phy_data_width UTMI+ PHY data width + * 0 - 8 bits + * 1 - 16 bits + * 2 - 8 or 16 bits + * @snpsid: Value from SNPSID register + * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) + */ +struct dwc2_hw_params { + unsigned op_mode:3; + unsigned arch:2; + unsigned enable_dynamic_fifo:1; + unsigned en_multiple_tx_fifo:1; + unsigned rx_fifo_size:16; + unsigned host_nperio_tx_fifo_size:16; + unsigned dev_nperio_tx_fifo_size:16; + unsigned host_perio_tx_fifo_size:16; + unsigned nperio_tx_q_depth:3; + unsigned host_perio_tx_q_depth:3; + unsigned dev_token_q_depth:5; + unsigned max_transfer_size:26; + unsigned max_packet_count:11; + unsigned host_channels:5; + unsigned hs_phy_type:2; + unsigned fs_phy_type:2; + unsigned num_dev_ep:4; + unsigned num_dev_perio_in_ep:4; + unsigned total_fifo_size:16; + unsigned power_optimized:1; + unsigned utmi_phy_data_width:2; + u32 snpsid; + u32 dev_ep_dirs; +}; + +/* Size of control and EP0 buffers */ +#define DWC2_CTRL_BUFF_SIZE 8 + +/** + * struct dwc2_gregs_backup - Holds global registers state before + * entering partial power down + * @gotgctl: Backup of GOTGCTL register + * @gintmsk: Backup of GINTMSK register + * @gahbcfg: Backup of GAHBCFG register + * @gusbcfg: Backup of GUSBCFG register + * @grxfsiz: Backup of GRXFSIZ register + * @gnptxfsiz: Backup of GNPTXFSIZ register + * @gi2cctl: Backup of GI2CCTL register + * @hptxfsiz: Backup of HPTXFSIZ register + * @gdfifocfg: Backup of GDFIFOCFG register + * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint + * @gpwrdn: Backup of GPWRDN register + */ +struct dwc2_gregs_backup { + u32 gotgctl; + u32 gintmsk; + u32 gahbcfg; + u32 gusbcfg; + u32 grxfsiz; + u32 gnptxfsiz; + u32 gi2cctl; + u32 hptxfsiz; + u32 pcgcctl; + u32 gdfifocfg; + u32 dtxfsiz[MAX_EPS_CHANNELS]; + u32 gpwrdn; + bool valid; +}; + +/** + * struct dwc2_dregs_backup - Holds device registers state before + * entering partial power down + * @dcfg: Backup of DCFG register + * @dctl: Backup of DCTL register + * @daintmsk: Backup of DAINTMSK register + * @diepmsk: Backup of DIEPMSK register + * @doepmsk: Backup of DOEPMSK register + * @diepctl: Backup of DIEPCTL register + * @dieptsiz: Backup of DIEPTSIZ register + * @diepdma: Backup of DIEPDMA register + * @doepctl: Backup of DOEPCTL register + * @doeptsiz: Backup of DOEPTSIZ register + * @doepdma: Backup of DOEPDMA register + */ +struct dwc2_dregs_backup { + u32 dcfg; + u32 dctl; + u32 daintmsk; + u32 diepmsk; + u32 doepmsk; + u32 diepctl[MAX_EPS_CHANNELS]; + u32 dieptsiz[MAX_EPS_CHANNELS]; + u32 diepdma[MAX_EPS_CHANNELS]; + u32 doepctl[MAX_EPS_CHANNELS]; + u32 doeptsiz[MAX_EPS_CHANNELS]; + u32 doepdma[MAX_EPS_CHANNELS]; + bool valid; +}; + +/** + * struct dwc2_hregs_backup - Holds host registers state before + * entering partial power down + * @hcfg: Backup of HCFG register + * @haintmsk: Backup of HAINTMSK register + * @hcintmsk: Backup of HCINTMSK register + * @hptr0: Backup of HPTR0 register + * @hfir: Backup of HFIR register + */ +struct dwc2_hregs_backup { + u32 hcfg; + u32 haintmsk; + u32 hcintmsk[MAX_EPS_CHANNELS]; + u32 hprt0; + u32 hfir; + bool valid; +}; + +/* + * Constants related to high speed periodic scheduling + * + * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a + * reservation point of view it's assumed that the schedule goes right back to + * the beginning after the end of the schedule. + * + * What does that mean for scheduling things with a long interval? It means + * we'll reserve time for them in every possible microframe that they could + * ever be scheduled in. ...but we'll still only actually schedule them as + * often as they were requested. + * + * We keep our schedule in a "bitmap" structure. This simplifies having + * to keep track of and merge intervals: we just let the bitmap code do most + * of the heavy lifting. In a way scheduling is much like memory allocation. + * + * We schedule 100us per uframe or 80% of 125us (the maximum amount you're + * supposed to schedule for periodic transfers). That's according to spec. + * + * Note that though we only schedule 80% of each microframe, the bitmap that we + * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of + * space for each uFrame). + * + * Requirements: + * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) + * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably + * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might + * be bugs). The 8 comes from the USB spec: number of microframes per frame. + */ +#define DWC2_US_PER_UFRAME 125 +#define DWC2_HS_PERIODIC_US_PER_UFRAME 100 + +#define DWC2_HS_SCHEDULE_UFRAMES 8 +#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ + DWC2_HS_PERIODIC_US_PER_UFRAME) + +/* + * Constants related to low speed scheduling + * + * For high speed we schedule every 1us. For low speed that's a bit overkill, + * so we make up a unit called a "slice" that's worth 25us. There are 40 + * slices in a full frame and we can schedule 36 of those (90%) for periodic + * transfers. + * + * Our low speed schedule can be as short as 1 frame or could be longer. When + * we only schedule 1 frame it means that we'll need to reserve a time every + * frame even for things that only transfer very rarely, so something that runs + * every 2048 frames will get time reserved in every frame. Our low speed + * schedule can be longer and we'll be able to handle more overlap, but that + * will come at increased memory cost and increased time to schedule. + * + * Note: one other advantage of a short low speed schedule is that if we mess + * up and miss scheduling we can jump in and use any of the slots that we + * happened to reserve. + * + * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for + * the schedule. There will be one schedule per TT. + * + * Requirements: + * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. + */ +#define DWC2_US_PER_SLICE 25 +#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) + +#define DWC2_ROUND_US_TO_SLICE(us) \ + (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ + DWC2_US_PER_SLICE) + +#define DWC2_LS_PERIODIC_US_PER_FRAME \ + 900 +#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ + (DWC2_LS_PERIODIC_US_PER_FRAME / \ + DWC2_US_PER_SLICE) + +#define DWC2_LS_SCHEDULE_FRAMES 1 +#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ + DWC2_LS_PERIODIC_SLICES_PER_FRAME) + +/** + * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic + * and periodic schedules + * + * These are common for both host and peripheral modes: + * + * @dev: The struct device pointer + * @regs: Pointer to controller regs + * @hw_params: Parameters that were autodetected from the + * hardware registers + * @core_params: Parameters that define how the core should be configured + * @op_state: The operational State, during transitions (a_host=> + * a_peripheral and b_device=>b_host) this may not match + * the core, but allows the software to determine + * transitions + * @dr_mode: Requested mode of operation, one of following: + * - USB_DR_MODE_PERIPHERAL + * - USB_DR_MODE_HOST + * - USB_DR_MODE_OTG + * @hcd_enabled Host mode sub-driver initialization indicator. + * @gadget_enabled Peripheral mode sub-driver initialization indicator. + * @ll_hw_enabled Status of low-level hardware resources. + * @phy: The otg phy transceiver structure for phy control. + * @uphy: The otg phy transceiver structure for old USB phy + * control. + * @plat: The platform specific configuration data. This can be + * removed once all SoCs support usb transceiver. + * @supplies: Definition of USB power supplies + * @phyif: PHY interface width + * @lock: Spinlock that protects all the driver data structures + * @priv: Stores a pointer to the struct usb_hcd + * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth + * transfer are in process of being queued + * @srp_success: Stores status of SRP request in the case of a FS PHY + * with an I2C interface + * @wq_otg: Workqueue object used for handling of some interrupts + * @wf_otg: Work object for handling Connector ID Status Change + * interrupt + * @wkp_timer: Timer object for handling Wakeup Detected interrupt + * @lx_state: Lx state of connected device + * @gregs_backup: Backup of global registers during suspend + * @dregs_backup: Backup of device registers during suspend + * @hregs_backup: Backup of host registers during suspend + * + * These are for host mode: + * + * @flags: Flags for handling root port state changes + * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. + * Transfers associated with these QHs are not currently + * assigned to a host channel. + * @non_periodic_sched_active: Active QHs in the non-periodic schedule. + * Transfers associated with these QHs are currently + * assigned to a host channel. + * @non_periodic_qh_ptr: Pointer to next QH to process in the active + * non-periodic schedule + * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a + * list of QHs for periodic transfers that are _not_ + * scheduled for the next frame. Each QH in the list has an + * interval counter that determines when it needs to be + * scheduled for execution. This scheduling mechanism + * allows only a simple calculation for periodic bandwidth + * used (i.e. must assume that all periodic transfers may + * need to execute in the same frame). However, it greatly + * simplifies scheduling and should be sufficient for the + * vast majority of OTG hosts, which need to connect to a + * small number of peripherals at one time. Items move from + * this list to periodic_sched_ready when the QH interval + * counter is 0 at SOF. + * @periodic_sched_ready: List of periodic QHs that are ready for execution in + * the next frame, but have not yet been assigned to host + * channels. Items move from this list to + * periodic_sched_assigned as host channels become + * available during the current frame. + * @periodic_sched_assigned: List of periodic QHs to be executed in the next + * frame that are assigned to host channels. Items move + * from this list to periodic_sched_queued as the + * transactions for the QH are queued to the DWC_otg + * controller. + * @periodic_sched_queued: List of periodic QHs that have been queued for + * execution. Items move from this list to either + * periodic_sched_inactive or periodic_sched_ready when the + * channel associated with the transfer is released. If the + * interval for the QH is 1, the item moves to + * periodic_sched_ready because it must be rescheduled for + * the next frame. Otherwise, the item moves to + * periodic_sched_inactive. + * @split_order: List keeping track of channels doing splits, in order. + * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. + * This value is in microseconds per (micro)frame. The + * assumption is that all periodic transfers may occur in + * the same (micro)frame. + * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the + * host is in high speed mode; low speed schedules are + * stored elsewhere since we need one per TT. + * @frame_number: Frame number read from the core at SOF. The value ranges + * from 0 to HFNUM_MAX_FRNUM. + * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for + * SOF enable/disable. + * @free_hc_list: Free host channels in the controller. This is a list of + * struct dwc2_host_chan items. + * @periodic_channels: Number of host channels assigned to periodic transfers. + * Currently assuming that there is a dedicated host + * channel for each periodic transaction and at least one + * host channel is available for non-periodic transactions. + * @non_periodic_channels: Number of host channels assigned to non-periodic + * transfers + * @available_host_channels Number of host channels available for the microframe + * scheduler to use + * @hc_ptr_array: Array of pointers to the host channel descriptors. + * Allows accessing a host channel descriptor given the + * host channel number. This is useful in interrupt + * handlers. + * @status_buf: Buffer used for data received during the status phase of + * a control transfer. + * @status_buf_dma: DMA address for status_buf + * @start_work: Delayed work for handling host A-cable connection + * @reset_work: Delayed work for handling a port reset + * @otg_port: OTG port number + * @frame_list: Frame list + * @frame_list_dma: Frame list DMA address + * @frame_list_sz: Frame list size + * @desc_gen_cache: Kmem cache for generic descriptors + * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors + * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf + * + * These are for peripheral mode: + * + * @driver: USB gadget driver + * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. + * @num_of_eps: Number of available EPs (excluding EP0) + * @debug_root: Root directrory for debugfs. + * @debug_file: Main status file for debugfs. + * @debug_testmode: Testmode status file for debugfs. + * @debug_fifo: FIFO status file for debugfs. + * @ep0_reply: Request used for ep0 reply. + * @ep0_buff: Buffer for EP0 reply data, if needed. + * @ctrl_buff: Buffer for EP0 control requests. + * @ctrl_req: Request for EP0 control packets. + * @ep0_state: EP0 control transfers state + * @test_mode: USB test mode requested by the host + * @setup_desc_dma: EP0 setup stage desc chain DMA address + * @setup_desc: EP0 setup stage desc chain pointer + * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address + * @ctrl_in_desc: EP0 IN data phase desc chain pointer + * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address + * @ctrl_out_desc: EP0 OUT data phase desc chain pointer + * @eps: The endpoints being supplied to the gadget framework + */ + +#define OTG_WQ_MSG_RESET 0 +#define OTG_WQ_MSG_START 1 +#define OTG_WQ_MSG_ID_STATE_CHANGE 2 + +struct dwc2_hsotg { + struct device *dev; + u32 regs; //addr + /** Params detected from hardware */ + struct dwc2_hw_params hw_params; + /** Params to actually use */ + struct dwc2_core_params params; + enum usb_otg_state op_state; + enum usb_dr_mode dr_mode; + unsigned int hcd_enabled:1; + u32 phyif; + + spinlock_t lock; + void *priv; + int irq; + struct clk *clk; + struct reset_control *reset; + + unsigned int queuing_high_bandwidth:1; + unsigned int srp_success:1; + struct work_struct wf_otg; + struct timer_list wkp_timer; + enum dwc2_lx_state lx_state; + struct dwc2_gregs_backup gr_backup; + struct dwc2_dregs_backup dr_backup; + struct dwc2_hregs_backup hr_backup; + + /* DWC OTG HW Release versions */ +#define DWC2_CORE_REV_2_71a 0x4f54271a +#define DWC2_CORE_REV_2_90a 0x4f54290a +#define DWC2_CORE_REV_2_91a 0x4f54291a +#define DWC2_CORE_REV_2_92a 0x4f54292a +#define DWC2_CORE_REV_2_94a 0x4f54294a +#define DWC2_CORE_REV_3_00a 0x4f54300a +#define DWC2_CORE_REV_3_10a 0x4f54310a +#define DWC2_FS_IOT_REV_1_00a 0x5531100a +#define DWC2_HS_IOT_REV_1_00a 0x5532100a + +#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) || IS_ENABLED(CONFIG_USB_NEW_DWC2_HOST) + + union dwc2_hcd_internal_flags { + u32 d32; + struct { + unsigned port_connect_status_change:1; + unsigned port_connect_status:1; + unsigned port_reset_change:1; + unsigned port_enable_change:1; + unsigned port_suspend_change:1; + unsigned port_over_current_change:1; + unsigned port_l1_change:1; + unsigned reserved:25; + } b; + } flags; + + List_t non_periodic_sched_inactive; + List_t non_periodic_sched_active; + ListItem_t *non_periodic_qh_ptr; + List_t split_order; + + unsigned long hs_periodic_bitmap[ + DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; + u16 frame_number; + bool bus_suspended; + bool new_connection; + + u16 last_frame_num; + + List_t free_hc_list; + + List_t free_qtd_list; + List_t free_urb_list; + + int non_periodic_channels; + int available_host_channels; + struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; + u8 *status_buf; + u32 status_offset; + +#define DWC2_HCD_STATUS_BUF_SIZE 6 + u8 otg_port; + u32 *frame_list; + dma_addr_t frame_list_dma; + u32 frame_list_sz; +#define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 + +#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ +}; + +/* Reasons for halting a host channel */ +enum dwc2_halt_status { + DWC2_HC_XFER_NO_HALT_STATUS, + DWC2_HC_XFER_COMPLETE, + DWC2_HC_XFER_URB_COMPLETE, + DWC2_HC_XFER_ACK, + DWC2_HC_XFER_NAK, + DWC2_HC_XFER_NYET, + DWC2_HC_XFER_STALL, + DWC2_HC_XFER_XACT_ERR, + DWC2_HC_XFER_FRAME_OVERRUN, + DWC2_HC_XFER_BABBLE_ERR, + DWC2_HC_XFER_DATA_TOGGLE_ERR, + DWC2_HC_XFER_AHB_ERR, + DWC2_HC_XFER_PERIODIC_INCOMPLETE, + DWC2_HC_XFER_URB_DEQUEUE, +}; + +/* Core version information */ +static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) +{ + return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; +} + +static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) +{ + return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; +} + +static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) +{ + return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; +} + +/* + * The following functions support initialization of the core driver component + * and the DWC_otg controller + */ +int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); +int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); +void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); + +bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); + +/* + * Common core Functions. + * The following functions support managing the DWC_otg controller in either + * device or host mode. + */ +void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); +void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); +void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); + +void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); +void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); + +/* This function should be called on every hardware interrupt. */ +irqreturn_t dwc2_handle_common_intr(int irq, void *dev); + +/* Parameters */ +int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); +int dwc2_init_params(struct dwc2_hsotg *hsotg); + +/* + * The following functions check the controller's OTG operation mode + * capability (GHWCFG2.OTG_MODE). + * + * These functions can be used before the internal hsotg->hw_params + * are read in and cached so they always read directly from the + * GHWCFG2 register. + */ +unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); +bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); + +/* + * Returns the mode of operation, host or device + */ +static inline bool dwc2_is_host_mode(struct dwc2_hsotg *hsotg) +{ + return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; +} + +/* + * Dump core registers and SPRAM + */ +int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); +int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); +void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); +void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); +void dwc2_hcd_start(struct dwc2_hsotg *hsotg); + +#endif /* __DWC2_CORE_H__ */ diff --git a/A58-STEPLDR/Src/usb/core_intr.c b/A58-STEPLDR/Src/usb/core_intr.c new file mode 100644 index 00000000..be8aac86 --- /dev/null +++ b/A58-STEPLDR/Src/usb/core_intr.c @@ -0,0 +1,269 @@ +/* + * core_intr.c - DesignWare HS OTG Controller common interrupt handling + * + * Copyright (C) 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file contains the common interrupt handlers + */ + +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include + +#include "core.h" +#include "hcd.h" + +const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) +{ + switch (hsotg->op_state) { + case OTG_STATE_A_HOST: + return "a_host"; + case OTG_STATE_A_SUSPEND: + return "a_suspend"; + case OTG_STATE_A_PERIPHERAL: + return "a_peripheral"; + case OTG_STATE_B_PERIPHERAL: + return "b_peripheral"; + case OTG_STATE_B_HOST: + return "b_host"; + default: + return "unknown"; + } +} + +/** + * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message + * + * @hsotg: Programming view of DWC_otg controller + */ +static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) +{ + /* Clear interrupt */ + dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); + + dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); +} + +/** + * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG + * Interrupt Register (GOTGINT) to determine what interrupt has occurred. + * + * @hsotg: Programming view of DWC_otg controller + */ +static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) +{ + u32 gotgint; + + gotgint = dwc2_readl(hsotg->regs + GOTGINT); + + /* Clear GOTGINT */ + dwc2_writel(gotgint, hsotg->regs + GOTGINT); +} + +/** + * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status + * Change Interrupt + * + * @hsotg: Programming view of DWC_otg controller + * + * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a + * Device to Host Mode transition or a Host to Device Mode transition. This only + * occurs when the cable is connected/removed from the PHY connector. + */ +static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) +{ + u32 gintmsk; + + /* Clear interrupt */ + dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); + + /* Need to disable SOF interrupt immediately */ + gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_SOF; + dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + + dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); +} + +/** + * dwc2_handle_session_req_intr() - This interrupt indicates that a device is + * initiating the Session Request Protocol to request the host to turn on bus + * power so a new session can begin + * + * @hsotg: Programming view of DWC_otg controller + * + * This handler responds by turning on bus power. If the DWC_otg controller is + * in low power mode, this handler brings the controller out of low power mode + * before turning on bus power. + */ +static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) +{ + /* Clear interrupt */ + dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); + + dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", + hsotg->lx_state); +} + +/* + * This interrupt indicates that a device has been disconnected from the + * root port + */ +static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) +{ + dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); + + dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", + dwc2_is_host_mode(hsotg) ? "Host" : "Device", + dwc2_op_state_str(hsotg)); + + if (hsotg->op_state == OTG_STATE_A_HOST) + dwc2_hcd_disconnect(hsotg, false); +} + +/* + * This interrupt indicates that SUSPEND state has been detected on the USB. + * + * For HNP the USB Suspend interrupt signals the change from "a_peripheral" + * to "a_host". + * + * When power management is enabled the core will be put in low power mode. + */ +static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) +{ + /* Clear interrupt */ + dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); + + dev_dbg(hsotg->dev, "USB SUSPEND\n"); + + if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) { + dev_dbg(hsotg->dev, "a_peripheral->a_host\n"); + + /* Change to L2 (suspend) state */ + hsotg->lx_state = DWC2_L2; + /* Clear the a_peripheral flag, back to a_host */ + spin_unlock(&hsotg->lock); + dwc2_hcd_start_isr(hsotg); + spin_lock(&hsotg->lock); + hsotg->op_state = OTG_STATE_A_HOST; + } +} + +#define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ + GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \ + GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \ + GINTSTS_USBSUSP | GINTSTS_PRTINT) + +/* + * This function returns the Core Interrupt register + */ +static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) +{ + u32 gintsts; + u32 gintmsk; + u32 gahbcfg; + u32 gintmsk_common = GINTMSK_COMMON; + + gintsts = dwc2_readl(hsotg->regs + GINTSTS); + gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* If any common interrupts set */ + if (gintsts & gintmsk_common) + dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n", + gintsts, gintmsk); + + if (gahbcfg & GAHBCFG_GLBL_INTR_EN) + return gintsts & gintmsk & gintmsk_common; + else + return 0; +} + +/* + * Common interrupt handler + * + * The common interrupts are those that occur in both Host and Device mode. + * This handler handles the following interrupts: + * - Mode Mismatch Interrupt + * - OTG Interrupt + * - Connector ID Status Change Interrupt + * - Disconnect Interrupt + * - Session Request Interrupt + * - Resume / Remote Wakeup Detected Interrupt + * - Suspend Interrupt + */ +irqreturn_t dwc2_handle_common_intr(int irq, void *dev) +{ + struct dwc2_hsotg *hsotg = dev; + u32 gintsts; + irqreturn_t retval = IRQ_NONE; + + if (!dwc2_is_controller_alive(hsotg)) { + dev_warn(hsotg->dev, "Controller is dead\n"); + goto out; + } + + gintsts = dwc2_read_common_intr(hsotg); + if (gintsts & ~GINTSTS_PRTINT) + retval = IRQ_HANDLED; + + if (gintsts & GINTSTS_MODEMIS) + dwc2_handle_mode_mismatch_intr(hsotg); + if (gintsts & GINTSTS_OTGINT) + dwc2_handle_otg_intr(hsotg); + if (gintsts & GINTSTS_CONIDSTSCHNG) + dwc2_handle_conn_id_status_change_intr(hsotg); + if (gintsts & GINTSTS_DISCONNINT) + dwc2_handle_disconnect_intr(hsotg); + if (gintsts & GINTSTS_SESSREQINT) + dwc2_handle_session_req_intr(hsotg); + + if (gintsts & GINTSTS_USBSUSP) + dwc2_handle_usb_suspend_intr(hsotg); + + if (gintsts & GINTSTS_PRTINT) { + /* + * The port interrupt occurs while in device mode with HPRT0 + * Port Enable/Disable + */ + } + +out: + return retval; +} diff --git a/A58-STEPLDR/Src/usb/dwc2_compat.h b/A58-STEPLDR/Src/usb/dwc2_compat.h new file mode 100644 index 00000000..073ed9d7 --- /dev/null +++ b/A58-STEPLDR/Src/usb/dwc2_compat.h @@ -0,0 +1,138 @@ +#ifndef _DWC2_COMPAT_H +#define _DWC2_COMPAT_H + + +/* OTG defines lots of enumeration states before device reset */ +enum usb_otg_state { + OTG_STATE_UNDEFINED = 0, + + /* single-role peripheral, and dual-role default-b */ + OTG_STATE_B_IDLE, + OTG_STATE_B_SRP_INIT, + OTG_STATE_B_PERIPHERAL, + + /* extra dual-role default-b states */ + OTG_STATE_B_WAIT_ACON, + OTG_STATE_B_HOST, + + /* dual-role default-a */ + OTG_STATE_A_IDLE, + OTG_STATE_A_WAIT_VRISE, + OTG_STATE_A_WAIT_BCON, + OTG_STATE_A_HOST, + OTG_STATE_A_SUSPEND, + OTG_STATE_A_PERIPHERAL, + OTG_STATE_A_WAIT_VFALL, + OTG_STATE_A_VBUS_ERR, +}; + + +enum usb_dr_mode { + USB_DR_MODE_UNKNOWN, + USB_DR_MODE_HOST, + USB_DR_MODE_PERIPHERAL, + USB_DR_MODE_OTG, +}; + +#define URB_DIR_IN 0x0200 /* Transfer from device to host */ +#define URB_DIR_OUT 0 +#define URB_DIR_MASK URB_DIR_IN + +#define URB_DMA_MAP_SINGLE 0x00010000 /* Non-scatter-gather mapping */ +#define URB_DMA_MAP_PAGE 0x00020000 /* HCD-unsupported S-G */ +#define URB_DMA_MAP_SG 0x00040000 /* HCD-supported S-G */ +#define URB_MAP_LOCAL 0x00080000 /* HCD-local-memory mapping */ +#define URB_SETUP_MAP_SINGLE 0x00100000 /* Setup packet DMA mapped */ +#define URB_SETUP_MAP_LOCAL 0x00200000 /* HCD-local setup packet */ +#define URB_DMA_SG_COMBINED 0x00400000 /* S-G entries were combined */ +#define URB_ALIGNED_TEMP_BUFFER 0x00800000 /* Temp buffer was alloc'd */ + + +#define USB_RESUME_TIMEOUT 40 /* ms */ + + + +/* class requests from the USB 2.0 hub spec, table 11-15 */ +#define HUB_CLASS_REQ(dir, type, request) ((((dir) | (type)) << 8) | (request)) +/* GetBusState and SetHubDescriptor are optional, omitted */ +#define ClearHubFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, USB_REQ_CLEAR_FEATURE) +#define ClearPortFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, USB_REQ_CLEAR_FEATURE) +#define GetHubDescriptor HUB_CLASS_REQ(USB_DIR_IN, USB_RT_HUB, USB_REQ_GET_DESCRIPTOR) +#define GetHubStatus HUB_CLASS_REQ(USB_DIR_IN, USB_RT_HUB, USB_REQ_GET_STATUS) +#define GetPortStatus HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, USB_REQ_GET_STATUS) +#define SetHubFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, USB_REQ_SET_FEATURE) +#define SetPortFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, USB_REQ_SET_FEATURE) + + +/* + * Port feature numbers + * See USB 2.0 spec Table 11-17 + */ +#define USB_PORT_FEAT_CONNECTION 0 +#define USB_PORT_FEAT_ENABLE 1 +#define USB_PORT_FEAT_SUSPEND 2 /* L2 suspend */ +#define USB_PORT_FEAT_OVER_CURRENT 3 +#define USB_PORT_FEAT_RESET 4 +#define USB_PORT_FEAT_L1 5 /* L1 suspend */ +#define USB_PORT_FEAT_POWER 8 +#define USB_PORT_FEAT_LOWSPEED 9 /* Should never be used */ +#define USB_PORT_FEAT_C_CONNECTION 16 +#define USB_PORT_FEAT_C_ENABLE 17 +#define USB_PORT_FEAT_C_SUSPEND 18 +#define USB_PORT_FEAT_C_OVER_CURRENT 19 +#define USB_PORT_FEAT_C_RESET 20 +#define USB_PORT_FEAT_TEST 21 +#define USB_PORT_FEAT_INDICATOR 22 +#define USB_PORT_FEAT_C_PORT_L1 23 + +/* + * wPortChange bit field + * See USB 2.0 spec Table 11-22 and USB 2.0 LPM ECN Table-4.10 + * Bits 0 to 5 shown, bits 6 to 15 are reserved + */ +#define USB_PORT_STAT_C_CONNECTION 0x0001 +#define USB_PORT_STAT_C_ENABLE 0x0002 +#define USB_PORT_STAT_C_SUSPEND 0x0004 +#define USB_PORT_STAT_C_OVERCURRENT 0x0008 +#define USB_PORT_STAT_C_RESET 0x0010 +#define USB_PORT_STAT_C_L1 0x0020 + +/* + * wPortStatus bit field + * See USB 2.0 spec Table 11-21 + */ +#define USB_PORT_STAT_CONNECTION 0x0001 +#define USB_PORT_STAT_ENABLE 0x0002 +#define USB_PORT_STAT_SUSPEND 0x0004 +#define USB_PORT_STAT_OVERCURRENT 0x0008 +#define USB_PORT_STAT_RESET 0x0010 +#define USB_PORT_STAT_L1 0x0020 +/* bits 6 to 7 are reserved */ +#define USB_PORT_STAT_POWER 0x0100 +#define USB_PORT_STAT_LOW_SPEED 0x0200 +#define USB_PORT_STAT_HIGH_SPEED 0x0400 +#define USB_PORT_STAT_TEST 0x0800 +#define USB_PORT_STAT_INDICATOR 0x1000 +/* bits 13 to 15 are reserved */ + +/* + * wHubCharacteristics (masks) + * See USB 2.0 spec Table 11-13, offset 3 + */ +#define HUB_CHAR_LPSM 0x0003 /* Logical Power Switching Mode mask */ +#define HUB_CHAR_COMMON_LPSM 0x0000 /* All ports power control at once */ +#define HUB_CHAR_INDV_PORT_LPSM 0x0001 /* per-port power control */ +#define HUB_CHAR_NO_LPSM 0x0002 /* no power switching */ + +#define HUB_CHAR_COMPOUND 0x0004 /* hub is part of a compound device */ + +#define HUB_CHAR_OCPM 0x0018 /* Over-Current Protection Mode mask */ +#define HUB_CHAR_COMMON_OCPM 0x0000 /* All ports Over-Current reporting */ +#define HUB_CHAR_INDV_PORT_OCPM 0x0008 /* per-port Over-current reporting */ +#define HUB_CHAR_NO_OCPM 0x0010 /* No Over-current Protection support */ + +#define HUB_CHAR_TTTT 0x0060 /* TT Think Time mask */ +#define HUB_CHAR_PORTIND 0x0080 /* per-port indicators (LEDs) */ + + +#endif diff --git a/A58-STEPLDR/Src/usb/hcd.c b/A58-STEPLDR/Src/usb/hcd.c new file mode 100644 index 00000000..5b19b2ac --- /dev/null +++ b/A58-STEPLDR/Src/usb/hcd.c @@ -0,0 +1,3703 @@ +/* + * hcd.c - DesignWare HS OTG Controller host-mode routines + * + * Copyright (C) 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file contains the core HCD code, and implements the Linux hc_driver + * API + */ +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include +#include "cp15.h" + +#include "core.h" +#include "hcd.h" + +int usb_urb_dir_in(struct urb *urb) +{ + return (urb->transfer_flags & URB_DIR_MASK) == URB_DIR_IN; +} + +static void dwc2_port_resume(struct dwc2_hsotg *hsotg); + +/* + * ========================================================================= + * Host Core Layer Functions + * ========================================================================= + */ + +/** + * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, + * used in both device and host modes + * + * @hsotg: Programming view of the DWC_otg controller + */ +static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) +{ + u32 intmsk; + + /* Clear any pending OTG Interrupts */ + dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + + /* Clear any pending interrupts */ + dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + + /* Enable the interrupts in the GINTMSK */ + intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; + + intmsk |= GINTSTS_RXFLVL; + intmsk |= GINTSTS_CONIDSTSCHNG; + + intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | + GINTSTS_SESSREQINT; + + dwc2_writel(intmsk, hsotg->regs + GINTMSK); +} + +/* + * Initializes the FSLSPClkSel field of the HCFG register depending on the + * PHY type + */ +static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) +{ + u32 hcfg, val; + + /* High speed PHY running at full speed or high speed */ + val = HCFG_FSLSPCLKSEL_30_60_MHZ; + + dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); + hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; + dwc2_writel(hcfg, hsotg->regs + HCFG); +} + +static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +{ + u32 usbcfg, ggpio; + int retval = 0; + + /* + * core_init() is now called on every switch so only call the + * following for the first time through + */ + if (select_phy) { + dev_dbg(hsotg->dev, "FS PHY selected\n"); + + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + if (!(usbcfg & GUSBCFG_PHYSEL)) { + usbcfg |= GUSBCFG_PHYSEL; + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after a PHY select */ + retval = dwc2_core_reset_and_force_dr_mode(hsotg); + + if (retval) { + dev_err(hsotg->dev, + "%s: Reset failed, aborting", __func__); + return retval; + } + } + + if (hsotg->params.activate_stm_fs_transceiver) { + ggpio = dwc2_readl(hsotg->regs + GGPIO); + if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { + dev_dbg(hsotg->dev, "Activating transceiver\n"); + /* + * STM32F4x9 uses the GGPIO register as general + * core configuration register. + */ + ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; + dwc2_writel(ggpio, hsotg->regs + GGPIO); + } + } + } + + /* + * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also + * do this on HNP Dev/Host mode switches (done in dev_init and + * host_init). + */ + if (dwc2_is_host_mode(hsotg)) + dwc2_init_fs_ls_pclk_sel(hsotg); + + return retval; +} + +static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +{ + u32 usbcfg, usbcfg_old; + int retval = 0; + + if (!select_phy) + return 0; + + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg_old = usbcfg; + + /* + * HS PHY parameters. These parameters are preserved during soft reset + * so only program the first time. Do a soft reset immediately after + * setting phyif. + */ + switch (hsotg->params.phy_type) { + case DWC2_PHY_TYPE_PARAM_ULPI: + /* ULPI interface */ + dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); + usbcfg |= GUSBCFG_ULPI_UTMI_SEL; + usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); + break; + case DWC2_PHY_TYPE_PARAM_UTMI: + /* UTMI+ interface */ + dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); + usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); + if (hsotg->params.phy_utmi_width == 16) + usbcfg |= GUSBCFG_PHYIF16; + break; + default: + dev_err(hsotg->dev, "FS PHY selected at HS!\n"); + break; + } + + if (usbcfg != usbcfg_old) { + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after setting the PHY parameters */ + retval = dwc2_core_reset_and_force_dr_mode(hsotg); + if (retval) { + dev_err(hsotg->dev, + "%s: Reset failed, aborting", __func__); + return retval; + } + } + + return retval; +} + +static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) +{ + u32 usbcfg; + int retval = 0; + + if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || + hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && + hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { + /* If FS/LS mode with FS/LS PHY */ + retval = dwc2_fs_phy_init(hsotg, select_phy); + if (retval) + return retval; + } else { + /* High speed PHY */ + retval = dwc2_hs_phy_init(hsotg, select_phy); + if (retval) + return retval; + } + + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~GUSBCFG_ULPI_FS_LS; + usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + return retval; +} + +static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) +{ + u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + if (hsotg->params.ahbcfg != -1) { + ahbcfg &= GAHBCFG_CTRL_MASK; + ahbcfg |= hsotg->params.ahbcfg & + ~GAHBCFG_CTRL_MASK; + } + + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + + return 0; +} + +static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) +{ + u32 usbcfg; + + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); + + switch (hsotg->hw_params.op_mode) { + case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: + if (hsotg->params.otg_cap == + DWC2_CAP_PARAM_HNP_SRP_CAPABLE) + usbcfg |= GUSBCFG_HNPCAP; + if (hsotg->params.otg_cap != + DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) + usbcfg |= GUSBCFG_SRPCAP; + break; + + case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: + case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: + case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: + if (hsotg->params.otg_cap != + DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) + usbcfg |= GUSBCFG_SRPCAP; + break; + + case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: + case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: + case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: + default: + break; + } + + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); +} + +/** + * dwc2_enable_host_interrupts() - Enables the Host mode interrupts + * + * @hsotg: Programming view of DWC_otg controller + */ +static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) +{ + u32 intmsk; + + dev_dbg(hsotg->dev, "%s()\n", __func__); + + /* Disable all interrupts */ + dwc2_writel(0, hsotg->regs + GINTMSK); + dwc2_writel(0, hsotg->regs + HAINTMSK); + + /* Enable the common interrupts */ + dwc2_enable_common_interrupts(hsotg); + + /* Enable host mode interrupts without disturbing common interrupts */ + intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; + dwc2_writel(intmsk, hsotg->regs + GINTMSK); +} + +/** + * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts + * + * @hsotg: Programming view of DWC_otg controller + */ +static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) +{ + u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); + + /* Disable host mode interrupts without disturbing common interrupts */ + intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | + GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); + dwc2_writel(intmsk, hsotg->regs + GINTMSK); +} + +/* + * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size + * For system that have a total fifo depth that is smaller than the default + * RX + TX fifo size. + * + * @hsotg: Programming view of DWC_otg controller + */ +static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *params = &hsotg->params; + struct dwc2_hw_params *hw = &hsotg->hw_params; + u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; + + total_fifo_size = hw->total_fifo_size; + rxfsiz = params->host_rx_fifo_size; + nptxfsiz = params->host_nperio_tx_fifo_size; + ptxfsiz = params->host_perio_tx_fifo_size; + + /* + * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth + * allocation with support for high bandwidth endpoints. Synopsys + * defines MPS(Max Packet size) for a periodic EP=1024, and for + * non-periodic as 512. + */ + if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { + /* + * For Buffer DMA mode/Scatter Gather DMA mode + * 2 * ((Largest Packet size / 4) + 1 + 1) + n + * with n = number of host channel. + * 2 * ((1024/4) + 2) = 516 + */ + rxfsiz = 516 + hw->host_channels; + + /* + * min non-periodic tx fifo depth + * 2 * (largest non-periodic USB packet used / 4) + * 2 * (512/4) = 256 + */ + nptxfsiz = 256; + + /* + * min periodic tx fifo depth + * (largest packet size*MC)/4 + * (1024 * 3)/4 = 768 + */ + ptxfsiz = 768; + + params->host_rx_fifo_size = rxfsiz; + params->host_nperio_tx_fifo_size = nptxfsiz; + params->host_perio_tx_fifo_size = ptxfsiz; + } + + /* + * If the summation of RX, NPTX and PTX fifo sizes is still + * bigger than the total_fifo_size, then we have a problem. + * + * We won't be able to allocate as many endpoints. Right now, + * we're just printing an error message, but ideally this FIFO + * allocation algorithm would be improved in the future. + * + * FIXME improve this FIFO allocation algorithm. + */ + if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) + dev_err(hsotg->dev, "invalid fifo sizes\n"); +} + +static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *params = &hsotg->params; + u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; + + if (!params->enable_dynamic_fifo) + return; + + dwc2_calculate_dynamic_fifo(hsotg); + + /* Rx FIFO */ + grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); + grxfsiz &= ~GRXFSIZ_DEPTH_MASK; + grxfsiz |= params->host_rx_fifo_size << + GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; + dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); + dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", + dwc2_readl(hsotg->regs + GRXFSIZ)); + + /* Non-periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", + dwc2_readl(hsotg->regs + GNPTXFSIZ)); + nptxfsiz = params->host_nperio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + nptxfsiz |= params->host_rx_fifo_size << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; + dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); + dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", + dwc2_readl(hsotg->regs + GNPTXFSIZ)); + + /* Periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", + dwc2_readl(hsotg->regs + HPTXFSIZ)); + hptxfsiz = params->host_perio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + hptxfsiz |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size) << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; + dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); + dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", + dwc2_readl(hsotg->regs + HPTXFSIZ)); + + if (hsotg->params.en_multiple_tx_fifo && + hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { + /* + * This feature was implemented in 2.91a version + * Global DFIFOCFG calculation for Host mode - + * include RxFIFO, NPTXFIFO and HPTXFIFO + */ + dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); + dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; + dfifocfg |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size + + params->host_perio_tx_fifo_size) << + GDFIFOCFG_EPINFOBASE_SHIFT & + GDFIFOCFG_EPINFOBASE_MASK; + dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); + } +} + +/** + * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for + * the HFIR register according to PHY type and speed + * + * @hsotg: Programming view of DWC_otg controller + * + * NOTE: The caller can modify the value of the HFIR register only after the + * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) + * has been set + */ +u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) +{ + u32 usbcfg; + u32 hprt0; + int clock = 60; /* default value */ + + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && + !(usbcfg & GUSBCFG_PHYIF16)) + clock = 60; + if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == + GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) + clock = 48; + if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && + !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) + clock = 30; + if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && + !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) + clock = 60; + if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && + !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) + clock = 48; + if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && + hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) + clock = 48; + if ((usbcfg & GUSBCFG_PHYSEL) && + hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) + clock = 48; + + if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) + /* High speed case */ + return 125 * clock - 1; + + /* FS/LS case */ + return 1000 * clock - 1; +} + +/** + * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination + * buffer + * + * @core_if: Programming view of DWC_otg controller + * @dest: Destination buffer for the packet + * @bytes: Number of bytes to copy to the destination + */ +void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) +{ + u32 __iomem *fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(0)); + u32 *data_buf = (u32 *)dest; + int word_count = (bytes + 3) / 4; + int i; + + /* + * Todo: Account for the case where dest is not dword aligned. This + * requires reading data from the FIFO into a u32 temp buffer, then + * moving it into the data buffer. + */ + + dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); + + for (i = 0; i < word_count; i++, data_buf++) + *data_buf = dwc2_readl((u32)fifo); +} + +static int _dwc2_hcd_start(struct usb_hcd *hcd); + +void dwc2_host_start(struct dwc2_hsotg *hsotg) +{ + struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); + + hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); + _dwc2_hcd_start(hcd); +} + +static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) +{ + struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); + + hcd->self.is_b_host = 0; +} + +static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, + int *hub_addr, int *hub_port) +{ + +} + +/* + * ========================================================================= + * Low Level Host Channel Access Functions + * ========================================================================= + */ + +static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan) +{ + u32 hcintmsk = HCINTMSK_CHHLTD; + + switch (chan->ep_type) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + dev_vdbg(hsotg->dev, "control/bulk\n"); + hcintmsk |= HCINTMSK_XFERCOMPL; + hcintmsk |= HCINTMSK_STALL; + hcintmsk |= HCINTMSK_XACTERR; + hcintmsk |= HCINTMSK_DATATGLERR; + if (chan->ep_is_in) { + hcintmsk |= HCINTMSK_BBLERR; + } else { + hcintmsk |= HCINTMSK_NAK; + hcintmsk |= HCINTMSK_NYET; + if (chan->do_ping) + hcintmsk |= HCINTMSK_ACK; + } + + if (chan->do_split) { + hcintmsk |= HCINTMSK_NAK; + if (chan->complete_split) + hcintmsk |= HCINTMSK_NYET; + else + hcintmsk |= HCINTMSK_ACK; + } + + if (chan->error_state) + hcintmsk |= HCINTMSK_ACK; + break; + + default: + dev_err(hsotg->dev, "## Unknown EP type ##\n"); + break; + } + + dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); +} + +static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan) +{ + u32 intmsk; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "DMA disabled\n"); + dwc2_hc_enable_slave_ints(hsotg, chan); + + /* Enable the top level host channel interrupt */ + intmsk = dwc2_readl(hsotg->regs + HAINTMSK); + intmsk |= 1 << chan->hc_num; + dwc2_writel(intmsk, hsotg->regs + HAINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); + + /* Make sure host channel interrupts are enabled */ + intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_HCHINT; + dwc2_writel(intmsk, hsotg->regs + GINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); +} + +/** + * dwc2_hc_init() - Prepares a host channel for transferring packets to/from + * a specific endpoint + * + * @hsotg: Programming view of DWC_otg controller + * @chan: Information needed to initialize the host channel + * + * The HCCHARn register is set up with the characteristics specified in chan. + * Host channel interrupts that may need to be serviced while this transfer is + * in progress are enabled. + */ +static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) +{ + u8 hc_num = chan->hc_num; + u32 hcintmsk; + u32 hcchar; + u32 hcsplt = 0; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + /* Clear old interrupt conditions for this host channel */ + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; + dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); + + /* Enable channel interrupts required for this transfer */ + dwc2_hc_enable_ints(hsotg, chan); + + /* + * Program the HCCHARn register with the endpoint characteristics for + * the current transfer + */ + hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; + hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; + if (chan->ep_is_in) + hcchar |= HCCHAR_EPDIR; + if (chan->speed == USB_SPEED_LOW) + hcchar |= HCCHAR_LSPDDEV; + hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; + hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", + hc_num, hcchar); + + dev_vdbg(hsotg->dev, "%s: Channel %d\n", + __func__, hc_num); + dev_vdbg(hsotg->dev, " Dev Addr: %d\n", + chan->dev_addr); + dev_vdbg(hsotg->dev, " Ep Num: %d\n", + chan->ep_num); + dev_vdbg(hsotg->dev, " Is In: %d\n", + chan->ep_is_in); + dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", + chan->speed == USB_SPEED_LOW); + dev_vdbg(hsotg->dev, " Ep Type: %d\n", + chan->ep_type); + dev_vdbg(hsotg->dev, " Max Pkt: %d\n", + chan->max_packet); + } + + /* Program the HCSPLT register for SPLITs */ + if (chan->do_split) { + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, + "Programming HC %d with split --> %s\n", + hc_num, + chan->complete_split ? "CSPLIT" : "SSPLIT"); + if (chan->complete_split) + hcsplt |= HCSPLT_COMPSPLT; + hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & + HCSPLT_XACTPOS_MASK; + hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & + HCSPLT_HUBADDR_MASK; + hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & + HCSPLT_PRTADDR_MASK; + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, " comp split %d\n", + chan->complete_split); + dev_vdbg(hsotg->dev, " xact pos %d\n", + chan->xact_pos); + dev_vdbg(hsotg->dev, " hub addr %d\n", + chan->hub_addr); + dev_vdbg(hsotg->dev, " hub port %d\n", + chan->hub_port); + dev_vdbg(hsotg->dev, " is_in %d\n", + chan->ep_is_in); + dev_vdbg(hsotg->dev, " Max Pkt %d\n", + chan->max_packet); + dev_vdbg(hsotg->dev, " xferlen %d\n", + chan->xfer_len); + } + } + + dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); +} + +/** + * dwc2_hc_halt() - Attempts to halt a host channel + * + * @hsotg: Controller register interface + * @chan: Host channel to halt + * @halt_status: Reason for halting the channel + * + * This function should only be called in Slave mode or to abort a transfer in + * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the + * controller halts the channel when the transfer is complete or a condition + * occurs that requires application intervention. + * + * In slave mode, checks for a free request queue entry, then sets the Channel + * Enable and Channel Disable bits of the Host Channel Characteristics + * register of the specified channel to intiate the halt. If there is no free + * request queue entry, sets only the Channel Disable bit of the HCCHARn + * register to flush requests for this channel. In the latter case, sets a + * flag to indicate that the host channel needs to be halted when a request + * queue slot is open. + * + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the + * HCCHARn register. The controller ensures there is space in the request + * queue before submitting the halt request. + * + * Some time may elapse before the core flushes any posted requests for this + * host channel and halts. The Channel Halted interrupt handler completes the + * deactivation of the host channel. + */ +void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, + enum dwc2_halt_status halt_status) +{ + u32 nptxsts, hcchar; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) + dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); + + if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || + halt_status == DWC2_HC_XFER_AHB_ERR) { + /* + * Disable all channel interrupts except Ch Halted. The QTD + * and QH state associated with this transfer has been cleared + * (in the case of URB_DEQUEUE), so the channel needs to be + * shut down carefully to prevent crashes. + */ + u32 hcintmsk = HCINTMSK_CHHLTD; + + dev_vdbg(hsotg->dev, "dequeue/error\n"); + dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the QTD and QH state. + */ + dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR + * even if the channel was already halted for some other + * reason + */ + chan->halt_status = halt_status; + + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + if (!(hcchar & HCCHAR_CHENA)) { + /* + * The channel is either already halted or it hasn't + * started yet. In DMA mode, the transfer may halt if + * it finishes normally or a condition occurs that + * requires driver intervention. Don't want to halt + * the channel again. In either Slave or DMA mode, + * it's possible that the transfer has been assigned + * to a channel, but not started yet when an URB is + * dequeued. Don't want to halt a channel that hasn't + * started yet. + */ + return; + } + } + if (chan->halt_pending) { + /* + * A halt has already been issued for this channel. This might + * happen when a transfer is aborted by a higher level in + * the stack. + */ + dev_vdbg(hsotg->dev, + "*** %s: Channel %d, chan->halt_pending already set ***\n", + __func__, chan->hc_num); + return; + } + + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + /* No need to set the bit in DDMA for disabling the channel */ + /* TODO check it everywhere channel is disabled */ + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "desc DMA disabled\n"); + hcchar |= HCCHAR_CHENA; + + hcchar |= HCCHAR_CHDIS; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "DMA not enabled\n"); + hcchar |= HCCHAR_CHENA; + + /* Check for space in the request queue to issue the halt */ + if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || + chan->ep_type == USB_ENDPOINT_XFER_BULK) { + dev_vdbg(hsotg->dev, "control/bulk\n"); + nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { + dev_vdbg(hsotg->dev, "Disabling channel\n"); + hcchar &= ~HCCHAR_CHENA; + } + } + + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->halt_status = halt_status; + + if (hcchar & HCCHAR_CHENA) { + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Channel enabled\n"); + chan->halt_pending = 1; + chan->halt_on_queue = 0; + } else { + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Channel disabled\n"); + chan->halt_on_queue = 1; + } + + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, + chan->hc_num); + dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", + hcchar); + dev_vdbg(hsotg->dev, " halt_pending: %d\n", + chan->halt_pending); + dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", + chan->halt_on_queue); + dev_vdbg(hsotg->dev, " halt_status: %d\n", + chan->halt_status); + } +} + +/** + * dwc2_hc_cleanup() - Clears the transfer state for a host channel + * + * @hsotg: Programming view of DWC_otg controller + * @chan: Identifies the host channel to clean up + * + * This function is normally called after a transfer is done and the host + * channel is being released + */ +void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) +{ + u32 hcintmsk; + + chan->xfer_started = 0; + + list_del_init(&chan->split_order_list_entry); + + /* + * Clear channel interrupt enables and any unhandled channel interrupt + * conditions + */ + dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; + dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); +} + +/** + * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in + * which frame a periodic transfer should occur + * + * @hsotg: Programming view of DWC_otg controller + * @chan: Identifies the host channel to set up and its properties + * @hcchar: Current value of the HCCHAR register for the specified host channel + * + * This function has no effect on non-periodic transfers + */ +static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, u32 *hcchar) +{ + +} + +/** + * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with + * the Host Channel + * + * @hsotg: Programming view of DWC_otg controller + * @chan: Information needed to initialize the host channel + * + * This function should only be called in Slave mode. For a channel associated + * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel + * associated with a periodic EP, the periodic Tx FIFO is written. + * + * Upon return the xfer_buf and xfer_count fields in chan are incremented by + * the number of bytes written to the Tx FIFO. + */ +static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan) +{ + u32 i; + u32 remaining_count; + u32 byte_count; + u32 dword_count; + u32 __iomem *data_fifo; + u32 *data_buf = (u32 *)chan->xfer_buf; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); + + remaining_count = chan->xfer_len - chan->xfer_count; + if (remaining_count > chan->max_packet) + byte_count = chan->max_packet; + else + byte_count = remaining_count; + + dword_count = (byte_count + 3) / 4; + + if (((unsigned long)data_buf & 0x3) == 0) { + /* xfer_buf is DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) + dwc2_writel(*data_buf, (u32)data_fifo); + } else { + /* xfer_buf is not DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) { + u32 data = data_buf[0] | data_buf[1] << 8 | + data_buf[2] << 16 | data_buf[3] << 24; + dwc2_writel(data, (u32)data_fifo); + } + } + + chan->xfer_count += byte_count; + chan->xfer_buf += byte_count; +} + +/** + * dwc2_hc_do_ping() - Starts a PING transfer + * + * @hsotg: Programming view of DWC_otg controller + * @chan: Information needed to initialize the host channel + * + * This function should only be called in Slave mode. The Do Ping bit is set in + * the HCTSIZ register, then the channel is enabled. + */ +static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan) +{ + u32 hcchar; + u32 hctsiz; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, + chan->hc_num); + + hctsiz = TSIZ_DOPNG; + hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; + dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar |= HCCHAR_CHENA; + hcchar &= ~HCCHAR_CHDIS; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); +} + +/** + * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host + * channel and starts the transfer + * + * @hsotg: Programming view of DWC_otg controller + * @chan: Information needed to initialize the host channel. The xfer_len value + * may be reduced to accommodate the max widths of the XferSize and + * PktCnt fields in the HCTSIZn register. The multi_count value may be + * changed to reflect the final xfer_len value. + * + * This function may be called in either Slave mode or DMA mode. In Slave mode, + * the caller must ensure that there is sufficient space in the request queue + * and Tx Data FIFO. + * + * For an OUT transfer in Slave mode, it loads a data packet into the + * appropriate FIFO. If necessary, additional data packets are loaded in the + * Host ISR. + * + * For an IN transfer in Slave mode, a data packet is requested. The data + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, + * additional data packets are requested in the Host ISR. + * + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ + * register along with a packet count of 1 and the channel is enabled. This + * causes a single PING transaction to occur. Other fields in HCTSIZ are + * simply set to 0 since no data transfer occurs in this case. + * + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with + * all the information required to perform the subsequent data transfer. In + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the + * controller performs the entire PING protocol, then starts the data + * transfer. + */ +static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan) +{ + u32 max_hc_xfer_size = hsotg->params.max_transfer_size; + u16 max_hc_pkt_count = hsotg->params.max_packet_count; + u32 hcchar; + u32 hctsiz = 0; + u16 num_packets; + u32 ec_mc; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + if (chan->do_ping) { + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "ping, no DMA\n"); + dwc2_hc_do_ping(hsotg, chan); + chan->xfer_started = 1; + return; + } + + if (chan->do_split) { + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "split\n"); + num_packets = 1; + + if (chan->complete_split && !chan->ep_is_in) + /* + * For CSPLIT OUT Transfer, set the size to 0 so the + * core doesn't expect any data written to the FIFO + */ + chan->xfer_len = 0; + else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) + chan->xfer_len = chan->max_packet; + else if (!chan->ep_is_in && chan->xfer_len > 188) + chan->xfer_len = 188; + + hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & + TSIZ_XFERSIZE_MASK; + + /* For split set ec_mc for immediate retries */ + ec_mc = 1; + } else { + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "no split\n"); + /* + * Ensure that the transfer length and packet count will fit + * in the widths allocated for them in the HCTSIZn register + */ + if (chan->xfer_len > max_hc_xfer_size) { + /* + * Make sure that xfer_len is a multiple of max packet + * size + */ + chan->xfer_len = + max_hc_xfer_size - chan->max_packet + 1; + } + + if (chan->xfer_len > 0) { + num_packets = (chan->xfer_len + chan->max_packet - 1) / + chan->max_packet; + if (num_packets > max_hc_pkt_count) { + num_packets = max_hc_pkt_count; + chan->xfer_len = num_packets * chan->max_packet; + } + } else { + /* Need 1 packet for transfer length of 0 */ + num_packets = 1; + } + + if (chan->ep_is_in) + /* + * Always program an integral # of max packets for IN + * transfers + */ + chan->xfer_len = num_packets * chan->max_packet; + + hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & + TSIZ_XFERSIZE_MASK; + + /* The ec_mc gets the multi_count for non-split */ + ec_mc = chan->multi_count; + } + + chan->start_pkt_count = num_packets; + hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; + hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & + TSIZ_SC_MC_PID_MASK; + dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", + hctsiz, chan->hc_num); + + dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, + chan->hc_num); + dev_vdbg(hsotg->dev, " Xfer Size: %d\n", + (hctsiz & TSIZ_XFERSIZE_MASK) >> + TSIZ_XFERSIZE_SHIFT); + dev_vdbg(hsotg->dev, " Num Pkts: %d\n", + (hctsiz & TSIZ_PKTCNT_MASK) >> + TSIZ_PKTCNT_SHIFT); + dev_vdbg(hsotg->dev, " Start PID: %d\n", + (hctsiz & TSIZ_SC_MC_PID_MASK) >> + TSIZ_SC_MC_PID_SHIFT); + } + + /* Start the split */ + if (chan->do_split) { + u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); + + hcsplt |= HCSPLT_SPLTENA; + dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); + } + + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar &= ~HCCHAR_MULTICNT_MASK; + hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; + dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); + + if (hcchar & HCCHAR_CHDIS) + dev_warn(hsotg->dev, + "%s: chdis set, channel %d, hcchar 0x%08x\n", + __func__, chan->hc_num, hcchar); + + /* Set host channel enable after all other setup is complete */ + hcchar |= HCCHAR_CHENA; + hcchar &= ~HCCHAR_CHDIS; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", + (hcchar & HCCHAR_MULTICNT_MASK) >> + HCCHAR_MULTICNT_SHIFT); + + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, + chan->hc_num); + + chan->xfer_started = 1; + chan->requests++; + + if (!chan->ep_is_in && chan->xfer_len > 0) + /* Load OUT packet into the appropriate Tx FIFO */ + dwc2_hc_write_packet(hsotg, chan); +} + +/** + * dwc2_hc_continue_transfer() - Continues a data transfer that was started by + * a previous call to dwc2_hc_start_transfer() + * + * @hsotg: Programming view of DWC_otg controller + * @chan: Information needed to initialize the host channel + * + * The caller must ensure there is sufficient space in the request queue and Tx + * Data FIFO. This function should only be called in Slave mode. In DMA mode, + * the controller acts autonomously to complete transfers programmed to a host + * channel. + * + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO + * if there is any data remaining to be queued. For an IN transfer, another + * data packet is always requested. For the SETUP phase of a control transfer, + * this function does nothing. + * + * Return: 1 if a new request is queued, 0 if no more requests are required + * for this transfer + */ +static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan) +{ + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, + chan->hc_num); + + if (chan->do_split) + /* SPLITs always queue just once per channel */ + return 0; + + if (chan->data_pid_start == DWC2_HC_PID_SETUP) + /* SETUPs are queued only once since they can't be NAK'd */ + return 0; + + if (chan->ep_is_in) { + /* + * Always queue another request for other IN transfers. If + * back-to-back INs are issued and NAKs are received for both, + * the driver may still be processing the first NAK when the + * second NAK is received. When the interrupt handler clears + * the NAK interrupt for the first NAK, the second NAK will + * not be seen. So we can't depend on the NAK interrupt + * handler to requeue a NAK'd request. Instead, IN requests + * are issued each time this function is called. When the + * transfer completes, the extra requests for the channel will + * be flushed. + */ + u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); + hcchar |= HCCHAR_CHENA; + hcchar &= ~HCCHAR_CHDIS; + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", + hcchar); + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->requests++; + return 1; + } + + /* OUT transfers */ + + if (chan->xfer_count < chan->xfer_len) { + /* Load OUT packet into the appropriate Tx FIFO */ + dwc2_hc_write_packet(hsotg, chan); + chan->requests++; + return 1; + } + + return 0; +} + +/* + * ========================================================================= + * HCD + * ========================================================================= + */ + +/* + * Processes all the URBs in a single list of QHs. Completes them with + * -ETIMEDOUT and frees the QTD. + * + * Must be called with interrupt disabled and spinlock held + */ +static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, + List_t *qh_list) +{ + struct dwc2_qh *qh; + struct dwc2_qtd *qtd; + ListItem_t *pxListItem, *nListItem; + + list_for_each_entry_safe(pxListItem, nListItem, qh, qh_list) { + ListItem_t *pxListItem1, *nListItem1; + + list_for_each_entry_safe(pxListItem1, nListItem1, qtd, &qh->qtd_list) { + dwc2_host_complete(hsotg, qtd, -ECONNRESET); + dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); + } + } +} + +static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, + List_t *qh_list) +{ + struct dwc2_qtd *qtd; + struct dwc2_qh *qh; + unsigned long flags; + + if (!listLIST_IS_INITIALISED(qh_list)) + /* The list hasn't been initialized yet */ + return; + + spin_lock_irqsave(&hsotg->lock, flags); + + /* Ensure there are no QTDs or URBs left */ + dwc2_kill_urbs_in_qh_list(hsotg, qh_list); + + ListItem_t *pxListItem, *nListItem; + list_for_each_entry_safe(pxListItem, nListItem, qh, qh_list) { + dwc2_hcd_qh_unlink(hsotg, qh); + + /* Free each QTD in the QH's QTD list */ + ListItem_t *pxListItem1, *nListItem1; + list_for_each_entry_safe(pxListItem1, nListItem1, qtd, &qh->qtd_list) + dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); + + if (qh->channel && qh->channel->qh == qh) + qh->channel->qh = NULL; + + spin_unlock_irqrestore(&hsotg->lock, flags); + dwc2_hcd_qh_free(hsotg, qh); + spin_lock_irqsave(&hsotg->lock, flags); + } + + spin_unlock_irqrestore(&hsotg->lock, flags); +} + +/* + * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic + * and periodic schedules. The QTD associated with each URB is removed from + * the schedule and freed. This function may be called when a disconnect is + * detected or when the HCD is being stopped. + * + * Must be called with interrupt disabled and spinlock held + */ +static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) +{ + dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); + dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); +} + +/** + * dwc2_hcd_start() - Starts the HCD when switching to Host mode + * + * @hsotg: Pointer to struct dwc2_hsotg + */ +void dwc2_hcd_start(struct dwc2_hsotg *hsotg) +{ + u32 hprt0; + + if (hsotg->op_state == OTG_STATE_B_HOST) { + /* + * Reset the port. During a HNP mode switch the reset + * needs to occur within 1ms and have a duration of at + * least 50ms. + */ + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RST; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + } +} + +void dwc2_hcd_start_isr(struct dwc2_hsotg *hsotg) +{ + u32 hprt0; + + if (hsotg->op_state == OTG_STATE_B_HOST) { + /* + * Reset the port. During a HNP mode switch the reset + * needs to occur within 1ms and have a duration of at + * least 50ms. + */ + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RST; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + } +} + + +/* Must be called with interrupt disabled and spinlock held */ +static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) +{ + int num_channels = hsotg->params.host_channels; + struct dwc2_host_chan *channel; + u32 hcchar; + int i; + + /* Flush out any channel requests in slave mode */ + for (i = 0; i < num_channels; i++) { + channel = hsotg->hc_ptr_array[i]; + //if (!list_empty(&channel->hc_list_entry)) + if (!list_item_empty(&channel->hc_list_entry)) + continue; + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); + hcchar |= HCCHAR_CHDIS; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + } + + for (i = 0; i < num_channels; i++) { + channel = hsotg->hc_ptr_array[i]; + //if (!list_empty(&channel->hc_list_entry)) + if (!list_item_empty(&channel->hc_list_entry)) + continue; + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + /* Halt the channel */ + hcchar |= HCCHAR_CHDIS; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + dwc2_hc_cleanup(hsotg, channel); + list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); + /* + * Added for Descriptor DMA to prevent channel double cleanup in + * release_channel_ddma(), which is called from ep_disable when + * device disconnects + */ + channel->qh = NULL; + } + /* All channels have been freed, mark them available */ + hsotg->non_periodic_channels = 0; + +} + +/** + * dwc2_hcd_connect() - Handles connect of the HCD + * + * @hsotg: Pointer to struct dwc2_hsotg + * + * Must be called with interrupt disabled and spinlock held + */ +void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) +{ + if (hsotg->lx_state != DWC2_L0) + usb_hcd_resume_root_hub(hsotg->priv); + + hsotg->flags.b.port_connect_status_change = 1; + hsotg->flags.b.port_connect_status = 1; +} + +/** + * dwc2_hcd_disconnect() - Handles disconnect of the HCD + * + * @hsotg: Pointer to struct dwc2_hsotg + * @force: If true, we won't try to reconnect even if we see device connected. + * + * Must be called with interrupt disabled and spinlock held + */ +void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) +{ + u32 intr; + u32 hprt0; + + /* Set status flags for the hub driver */ + hsotg->flags.b.port_connect_status_change = 1; + hsotg->flags.b.port_connect_status = 0; + + /* + * Shutdown any transfers in process by clearing the Tx FIFO Empty + * interrupt mask and status bits and disabling subsequent host + * channel interrupts. + */ + intr = dwc2_readl(hsotg->regs + GINTMSK); + intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); + dwc2_writel(intr, hsotg->regs + GINTMSK); + intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; + dwc2_writel(intr, hsotg->regs + GINTSTS); + + /* + * Turn off the vbus power only if the core has transitioned to device + * mode. If still in host mode, need to keep power on to detect a + * reconnection. + */ + + /* Respond with an error status to all URBs in the schedule */ + dwc2_kill_all_urbs(hsotg); + + if (dwc2_is_host_mode(hsotg)) + /* Clean up any host channels that were in use */ + dwc2_hcd_cleanup_channels(hsotg); + + dwc2_host_disconnect(hsotg); + + /* + * Add an extra check here to see if we're actually connected but + * we don't have a detection interrupt pending. This can happen if: + * 1. hardware sees connect + * 2. hardware sees disconnect + * 3. hardware sees connect + * 4. dwc2_port_intr() - clears connect interrupt + * 5. dwc2_handle_common_intr() - calls here + * + * Without the extra check here we will end calling disconnect + * and won't get any future interrupts to handle the connect. + */ + if (!force) { + hprt0 = dwc2_readl(hsotg->regs + HPRT0); + if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) + dwc2_hcd_connect(hsotg); + } +} + +#if 0 +/** + * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup + * + * @hsotg: Pointer to struct dwc2_hsotg + */ +static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) +{ + if (hsotg->bus_suspended) { + hsotg->flags.b.port_suspend_change = 1; + usb_hcd_resume_root_hub(hsotg->priv); + } + + if (hsotg->lx_state == DWC2_L1) + hsotg->flags.b.port_l1_change = 1; +} +#endif + +/** + * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner + * + * @hsotg: Pointer to struct dwc2_hsotg + * + * Must be called with interrupt disabled and spinlock held + */ +void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) +{ + dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); + + /* + * The root hub should be disconnected before this function is called. + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) + * and the QH lists (via ..._hcd_endpoint_disable). + */ + + /* Turn off all host-specific interrupts */ + dwc2_disable_host_interrupts(hsotg); + + /* Turn off the vbus power */ + dev_dbg(hsotg->dev, "PortPower off\n"); + dwc2_writel(0, hsotg->regs + HPRT0); +} + +/* Caller must hold driver lock */ +static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, + struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, + struct dwc2_qtd *qtd) +{ + u32 intr_mask; + int retval; + int dev_speed; + + if (!hsotg->flags.b.port_connect_status) { + /* No longer connected */ + dev_err(hsotg->dev, "Not connected\n"); + return -ENODEV; + } + + dev_speed = dwc2_host_get_speed(hsotg, urb->priv); + + /* Some configurations cannot support LS traffic on a FS root port */ + if ((dev_speed == USB_SPEED_LOW) && + (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && + (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { + u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + + if (prtspd == HPRT0_SPD_FULL_SPEED) + return -ENODEV; + } + + if (!qtd) + return -EINVAL; + + dwc2_hcd_qtd_init(qtd, urb); + retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); + if (retval) { + dev_err(hsotg->dev, + "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", + retval); + return retval; + } + + intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + if (!(intr_mask & GINTSTS_SOF)) { + enum dwc2_transaction_type tr_type; + + if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && + !(qtd->urb->flags & URB_GIVEBACK_ASAP)) + /* + * Do not schedule SG transactions until qtd has + * URB_GIVEBACK_ASAP set + */ + return 0; + + tr_type = dwc2_hcd_select_transactions(hsotg); + if (tr_type != DWC2_TRANSACTION_NONE) + dwc2_hcd_queue_transactions(hsotg, tr_type); + } + + return 0; +} + +/* Must be called with interrupt disabled and spinlock held */ +static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, + struct dwc2_hcd_urb *urb) +{ + struct dwc2_qh *qh; + struct dwc2_qtd *urb_qtd; + + urb_qtd = urb->qtd; + if (!urb_qtd) { + dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); + return -EINVAL; + } + + qh = urb_qtd->qh; + if (!qh) { + dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); + return -EINVAL; + } + + urb->priv = NULL; + + if (urb_qtd->in_process && qh->channel) { + /* The QTD is in process (it has been assigned to a channel) */ + if (hsotg->flags.b.port_connect_status) + /* + * If still connected (i.e. in host mode), halt the + * channel so it can be used for other transfers. If + * no longer connected, the host registers can't be + * written to halt the channel since the core is in + * device mode. + */ + dwc2_hc_halt(hsotg, qh->channel, + DWC2_HC_XFER_URB_DEQUEUE); + } + + /* + * Free the QTD and clean up the associated QH. Leave the QH in the + * schedule if it has any remaining QTDs. + */ + u8 in_process = urb_qtd->in_process; + + dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); + if (in_process) { + dwc2_hcd_qh_deactivate(hsotg, qh, 0); + qh->channel = NULL; + } else if (list_empty(&qh->qtd_list)) { + dwc2_hcd_qh_unlink(hsotg, qh); + } + + return 0; +} + +/* Must NOT be called with interrupt disabled or spinlock held */ +static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, + struct usb_host_endpoint *ep, int retry) +{ + struct dwc2_qtd *qtd;//, *qtd_tmp; + struct dwc2_qh *qh; + unsigned long flags; + int rc; + + spin_lock_irqsave(&hsotg->lock, flags); + + qh = ep->hcpriv; + if (!qh) { + rc = -EINVAL; + goto err; + } + + while (!list_empty(&qh->qtd_list) && retry--) { + if (retry == 0) { + dev_err(hsotg->dev, + "## timeout in dwc2_hcd_endpoint_disable() ##\n"); + rc = -EBUSY; + goto err; + } + + spin_unlock_irqrestore(&hsotg->lock, flags); + msleep(20); + spin_lock_irqsave(&hsotg->lock, flags); + qh = ep->hcpriv; + if (!qh) { + rc = -EINVAL; + goto err; + } + } + + dwc2_hcd_qh_unlink(hsotg, qh); + + /* Free each QTD in the QH's QTD list */ + //list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) + ListItem_t *pxListItem, *nListItem; + list_for_each_entry_safe(pxListItem, nListItem, qtd, &qh->qtd_list) + dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); + + ep->hcpriv = NULL; + + if (qh->channel && qh->channel->qh == qh) + qh->channel->qh = NULL; + + spin_unlock_irqrestore(&hsotg->lock, flags); + + dwc2_hcd_qh_free(hsotg, qh); + + return 0; + +err: + ep->hcpriv = NULL; + spin_unlock_irqrestore(&hsotg->lock, flags); + + return rc; +} + +/* Must be called with interrupt disabled and spinlock held */ +static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, + struct usb_host_endpoint *ep) +{ + struct dwc2_qh *qh = ep->hcpriv; + + if (!qh) + return -EINVAL; + + qh->data_toggle = DWC2_HC_PID_DATA0; + + return 0; +} + +/** + * dwc2_core_init() - Initializes the DWC_otg controller registers and + * prepares the core for device mode or host mode operation + * + * @hsotg: Programming view of the DWC_otg controller + * @initial_setup: If true then this is the first init for this instance. + */ +static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) +{ + u32 usbcfg, otgctl; + int retval; + + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + + /* Set ULPI External VBUS bit if needed */ + usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; + + /* Set external TS Dline pulsing bit if needed */ + usbcfg &= ~GUSBCFG_TERMSELDLPULSE; + + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* + * Reset the Controller + * + * We only need to reset the controller if this is a re-init. + * For the first init we know for sure that earlier code reset us (it + * needed to in order to properly detect various parameters). + */ + if (!initial_setup) { + retval = dwc2_core_reset_and_force_dr_mode(hsotg); + if (retval) { + dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", + __func__); + return retval; + } + } + + /* + * This needs to happen in FS mode before any other programming occurs + */ + retval = dwc2_phy_init(hsotg, initial_setup); + if (retval) + return retval; + + /* Program the GAHBCFG Register */ + retval = dwc2_gahbcfg_init(hsotg); + if (retval) + return retval; + + /* Program the GUSBCFG register */ + dwc2_gusbcfg_init(hsotg); + + /* Program the GOTGCTL register */ + otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_OTGVER; + dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + /* Clear the SRP success bit for FS-I2c */ + hsotg->srp_success = 0; + + /* Enable common interrupts */ + dwc2_enable_common_interrupts(hsotg); + + /* + * Do device or host initialization based on mode during PCD and + * HCD initialization + */ + if (dwc2_is_host_mode(hsotg)) { + dev_dbg(hsotg->dev, "Host Mode\n"); + hsotg->op_state = OTG_STATE_A_HOST; + } + + return 0; +} + +/** + * dwc2_core_host_init() - Initializes the DWC_otg controller registers for + * Host mode + * + * @hsotg: Programming view of DWC_otg controller + * + * This function flushes the Tx and Rx FIFOs and flushes any entries in the + * request queues. Host channels are reset to ensure that they are ready for + * performing transfers. + */ +static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) +{ + u32 hcfg, hfir, otgctl, usbcfg; + + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Set HS/FS Timeout Calibration to 7 (max available value). + * The number of PHY clocks that the application programs in + * this field is added to the high/full speed interpacket timeout + * duration in the core to account for any additional delays + * introduced by the PHY. This can be required, because the delay + * introduced by the PHY in generating the linestate condition + * can vary from one PHY to another. + */ + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_TOUTCAL(7); + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Restart the Phy Clock */ + dwc2_writel(0, hsotg->regs + PCGCTL); + + /* Initialize Host Configuration Register */ + dwc2_init_fs_ls_pclk_sel(hsotg); + if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || + hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { + hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg |= HCFG_FSLSSUPP; + dwc2_writel(hcfg, hsotg->regs + HCFG); + } + + /* + * This bit allows dynamic reloading of the HFIR register during + * runtime. This bit needs to be programmed during initial configuration + * and its value must not be changed during runtime. + */ + if (hsotg->params.reload_ctl) { + hfir = dwc2_readl(hsotg->regs + HFIR); + hfir |= HFIR_RLDCTRL; + dwc2_writel(hfir, hsotg->regs + HFIR); + } + + /* Configure data FIFO sizes */ + dwc2_config_fifos(hsotg); + + /* TODO - check this */ + /* Clear Host Set HNP Enable in the OTG Control Register */ + otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; + dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + /* Make sure the FIFOs are flushed */ + dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); + dwc2_flush_rx_fifo(hsotg); + + /* Clear Host Set HNP Enable in the OTG Control Register */ + otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; + dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + { + int num_channels, i; + u32 hcchar; + + /* Flush out any leftover queued requests */ + num_channels = hsotg->params.host_channels; + for (i = 0; i < num_channels; i++) { + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar &= ~HCCHAR_CHENA; + hcchar |= HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + /* Halt all channels to put them into a known state */ + for (i = 0; i < num_channels; i++) { + int count = 0; + + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dev_dbg(hsotg->dev, "%s: Halt channel %d\n", + __func__, i); + do { + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (++count > 1000) { + dev_err(hsotg->dev, + "Unable to clear enable on channel %d\n", + i); + break; + } + udelay(1); + } while (hcchar & HCCHAR_CHENA); + } + } + + /* Turn on the vbus power */ + dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); + if (hsotg->op_state == OTG_STATE_A_HOST) { + u32 hprt0 = dwc2_read_hprt0(hsotg); + + dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", + !!(hprt0 & HPRT0_PWR)); + if (!(hprt0 & HPRT0_PWR)) { + hprt0 |= HPRT0_PWR; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + } + + dwc2_enable_host_interrupts(hsotg); +} + +/* + * Initializes dynamic portions of the DWC_otg HCD state + * + * Must be called with interrupt disabled and spinlock held + */ +static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) +{ + struct dwc2_host_chan *chan;//, *chan_tmp; + int num_channels; + int i; +#if 1 + hsotg->flags.d32 = 0; + hsotg->non_periodic_qh_ptr = (ListItem_t *)listGET_END_MARKER(&hsotg->non_periodic_sched_active); + //hsotg->non_periodic_qh_ptr = listGET_HEAD_ENTRY(&hsotg->non_periodic_sched_active); + hsotg->non_periodic_channels = 0; + + /* + * Put all channels in the free channel list and clean up channel + * states + */ + /*list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, + hc_list_entry)*/ + ListItem_t *pxListItem, *nListItem; + list_for_each_entry_safe(pxListItem, nListItem, chan, &hsotg->free_hc_list) + list_del_init(&chan->hc_list_entry); + + num_channels = hsotg->params.host_channels; + for (i = 0; i < num_channels; i++) { + chan = hsotg->hc_ptr_array[i]; + list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); + dwc2_hc_cleanup(hsotg, chan); + } +#endif + /* Initialize the DWC core for host mode operation */ + dwc2_core_host_init(hsotg); +} + +static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, + struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) +{ + int hub_addr, hub_port; + + chan->do_split = 1; + chan->xact_pos = qtd->isoc_split_pos; + chan->complete_split = qtd->complete_split; + dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); + chan->hub_addr = (u8)hub_addr; + chan->hub_port = (u8)hub_port; +} + +static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, + struct dwc2_qtd *qtd) +{ + struct dwc2_hcd_urb *urb = qtd->urb; + + switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { + case USB_ENDPOINT_XFER_CONTROL: + chan->ep_type = USB_ENDPOINT_XFER_CONTROL; + + switch (qtd->control_phase) { + case DWC2_CONTROL_SETUP: + dev_vdbg(hsotg->dev, " ##Control setup transaction\n"); + chan->do_ping = 0; + chan->ep_is_in = 0; + chan->data_pid_start = DWC2_HC_PID_SETUP; + chan->xfer_buf = urb->setup_packet; + chan->xfer_len = 8; + //unsigned char *a = urb->setup_packet; + //if (a) + //printf("xfer setup-->%02x %02x %02x %02x %02x %02x %02x %02x\r\n", a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7]); + break; + + case DWC2_CONTROL_DATA: + dev_vdbg(hsotg->dev, " Control data transaction\n"); + chan->data_pid_start = qtd->data_toggle; + break; + + case DWC2_CONTROL_STATUS: + /* + * Direction is opposite of data direction or IN if no + * data + */ + dev_vdbg(hsotg->dev, " Control status transaction\n"); + if (urb->length == 0) + chan->ep_is_in = 1; + else + chan->ep_is_in = + dwc2_hcd_is_pipe_out(&urb->pipe_info); + if (chan->ep_is_in) + chan->do_ping = 0; + chan->data_pid_start = DWC2_HC_PID_DATA1; + chan->xfer_len = 0; + chan->xfer_buf = hsotg->status_buf; + break; + } + break; + + case USB_ENDPOINT_XFER_BULK: + chan->ep_type = USB_ENDPOINT_XFER_BULK; + break; + } +} + +/** + * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host + * channel and initializes the host channel to perform the transactions. The + * host channel is removed from the free list. + * + * @hsotg: The HCD state structure + * @qh: Transactions from the first QTD for this QH are selected and assigned + * to a free host channel + */ +static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) +{ + struct dwc2_host_chan *chan; + struct dwc2_hcd_urb *urb; + struct dwc2_qtd *qtd; + + if (dbg_qh(qh)) + dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); + + if (list_empty(&qh->qtd_list)) { + dev_dbg(hsotg->dev, "No QTDs in QH list\n"); + return -ENOMEM; + } + + if (list_empty(&hsotg->free_hc_list)) { + dev_dbg(hsotg->dev, "No free channel to assign\n"); + return -ENOMEM; + } + + chan = list_first_entry(&hsotg->free_hc_list); + + /* Remove host channel from free list */ + list_del_init(&chan->hc_list_entry); + qtd = list_first_entry(&qh->qtd_list); + urb = qtd->urb; + qh->channel = chan; + qtd->in_process = 1; + + /* + * Use usb_pipedevice to determine device address. This address is + * 0 before the SET_ADDRESS command and the correct address afterward. + */ + chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); + chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); + chan->speed = qh->dev_speed; + chan->max_packet = dwc2_max_packet(qh->maxp); + + chan->xfer_started = 0; + chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; + chan->error_state = (qtd->error_count > 0); + chan->halt_on_queue = 0; + chan->halt_pending = 0; + chan->requests = 0; + + /* + * The following values may be modified in the transfer type section + * below. The xfer_len value may be reduced when the transfer is + * started to accommodate the max widths of the XferSize and PktCnt + * fields in the HCTSIZn register. + */ + + chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); + if (chan->ep_is_in) + chan->do_ping = 0; + else + chan->do_ping = qh->ping_state; + + chan->data_pid_start = qh->data_toggle; + chan->multi_count = 1; + + if (urb->actual_length > urb->length && + !dwc2_hcd_is_pipe_in(&urb->pipe_info)) + urb->actual_length = urb->length; + + chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; + chan->xfer_len = urb->length - urb->actual_length; + chan->xfer_count = 0; + + /* Set the split attributes if required */ + if (qh->do_split) + dwc2_hc_init_split(hsotg, chan, qtd, urb); + else + chan->do_split = 0; + + /* Set the transfer attributes */ + dwc2_hc_init_xfer(hsotg, chan, qtd); + + /* For non-dword aligned buffers */ + /* + * We assume that DMA is always aligned in non-split + * case or split out case. Warn if not. + */ + chan->align_buf = 0; + + dwc2_hc_init(hsotg, chan); + chan->qh = qh; + + return 0; +} + +/** + * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer + * schedule and assigns them to available host channels. Called from the HCD + * interrupt handler functions. + * + * @hsotg: The HCD state structure + * + * Return: The types of new transactions that were assigned to host channels + */ +enum dwc2_transaction_type dwc2_hcd_select_transactions( + struct dwc2_hsotg *hsotg) +{ + enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; + ListItem_t* qh_ptr; + struct dwc2_qh *qh; + int num_channels; + +#ifdef DWC2_DEBUG_SOF + dev_vdbg(hsotg->dev, " Select Transactions\n"); +#endif + + /* + * Process entries in the inactive portion of the non-periodic + * schedule. Some free host channels may not be used if they are + * reserved for periodic transfers. + */ + num_channels = hsotg->params.host_channels; + qh_ptr = listGET_HEAD_ENTRY(&hsotg->non_periodic_sched_inactive); + while (qh_ptr != listGET_END_MARKER(&hsotg->non_periodic_sched_inactive)) { + if (hsotg->non_periodic_channels >= num_channels) + break; + if (list_empty(&hsotg->free_hc_list)) + break; + qh = list_entry(qh_ptr); + + if (dwc2_assign_and_init_hc(hsotg, qh)) + break; + //printf("dwc2_hcd_select_transactions:2949\r\n"); + /* + * Move the QH from the non-periodic inactive schedule to the + * non-periodic active schedule + */ + qh_ptr = listGET_NEXT(qh_ptr); + list_move_tail(&qh->qh_list_entry, + &hsotg->non_periodic_sched_active); + + if (ret_val == DWC2_TRANSACTION_NONE) + ret_val = DWC2_TRANSACTION_NON_PERIODIC; + else + ret_val = DWC2_TRANSACTION_ALL; + } + + return ret_val; +} + +/** + * dwc2_queue_transaction() - Attempts to queue a single transaction request for + * a host channel associated with either a periodic or non-periodic transfer + * + * @hsotg: The HCD state structure + * @chan: Host channel descriptor associated with either a periodic or + * non-periodic transfer + * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO + * for periodic transfers or the non-periodic Tx FIFO + * for non-periodic transfers + * + * Return: 1 if a request is queued and more requests may be needed to + * complete the transfer, 0 if no more requests are required for this + * transfer, -1 if there is insufficient space in the Tx FIFO + * + * This function assumes that there is space available in the appropriate + * request queue. For an OUT transfer or SETUP transaction in Slave mode, + * it checks whether space is available in the appropriate Tx FIFO. + * + * Must be called with interrupt disabled and spinlock held + */ +static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, + u16 fifo_dwords_avail) +{ + int retval = 0; + + if (chan->do_split) + /* Put ourselves on the list to keep order straight */ + list_move_tail(&chan->split_order_list_entry, + &hsotg->split_order); + + if (chan->halt_pending) { + /* Don't queue a request if the channel has been halted */ + } else if (chan->halt_on_queue) { + dwc2_hc_halt(hsotg, chan, chan->halt_status); + } else if (chan->do_ping) { + if (!chan->xfer_started) + dwc2_hc_start_transfer(hsotg, chan); + } else if (!chan->ep_is_in || + chan->data_pid_start == DWC2_HC_PID_SETUP) { + if ((fifo_dwords_avail * 4) >= chan->max_packet) { + if (!chan->xfer_started) { + dwc2_hc_start_transfer(hsotg, chan); + retval = 1; + } else { + retval = dwc2_hc_continue_transfer(hsotg, chan); + } + } else { + retval = -1; + } + } else { + if (!chan->xfer_started) { + dwc2_hc_start_transfer(hsotg, chan); + retval = 1; + } else { + retval = dwc2_hc_continue_transfer(hsotg, chan); + } + } + + return retval; +} + +/* + * Processes active non-periodic channels and queues transactions for these + * channels to the DWC_otg controller. After queueing transactions, the NP Tx + * FIFO Empty interrupt is enabled if there are more transactions to queue as + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx + * FIFO Empty interrupt is disabled. + * + * Must be called with interrupt disabled and spinlock held + */ +static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) +{ + ListItem_t *orig_qh_ptr = NULL; + struct dwc2_qh *qh; + u32 tx_status; + u32 qspcavail; + u32 fspcavail; + u32 gintmsk; + int status; + int no_queue_space = 0; + int no_fifo_space = 0; + int more_to_do = 0; + + dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); + + tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> + TXSTS_FSPCAVAIL_SHIFT; + dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", + qspcavail); + dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", + fspcavail); + + /* + * Keep track of the starting point. Skip over the start-of-list + * entry. + */ + if (hsotg->non_periodic_qh_ptr == listGET_END_MARKER(&hsotg->non_periodic_sched_active)) { + hsotg->non_periodic_qh_ptr = listGET_HEAD_ENTRY(&hsotg->non_periodic_sched_active); + } + //orig_qh_ptr = hsotg->non_periodic_qh_ptr; + orig_qh_ptr = hsotg->non_periodic_qh_ptr; + + /* + * Process once through the active list or until no more space is + * available in the request queue or the Tx FIFO + */ + do { + tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + if (qspcavail == 0) { + no_queue_space = 1; + break; + } + + qh = list_entry(hsotg->non_periodic_qh_ptr); + if (!qh->channel) + goto next; + + /* Make sure EP's TT buffer is clean before queueing qtds */ + if (qh->tt_buffer_dirty) + goto next; + + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> + TXSTS_FSPCAVAIL_SHIFT;//printf("%s:%d\r\n", __func__, __LINE__); + status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); + //printf("%s:%d\r\n", __func__, __LINE__); + if (status > 0) { + more_to_do = 1; + } else if (status < 0) { + no_fifo_space = 1; + break; + } +next: + /* Advance to next QH, skipping start-of-list entry */ + hsotg->non_periodic_qh_ptr = listGET_NEXT(hsotg->non_periodic_qh_ptr); + if (hsotg->non_periodic_qh_ptr == + listGET_END_MARKER(&hsotg->non_periodic_sched_active)) + hsotg->non_periodic_qh_ptr = listGET_NEXT(hsotg->non_periodic_qh_ptr); + } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); + + tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> + TXSTS_FSPCAVAIL_SHIFT; + dev_vdbg(hsotg->dev, + " NP Tx Req Queue Space Avail (after queue): %d\n", + qspcavail); + dev_vdbg(hsotg->dev, + " NP Tx FIFO Space Avail (after queue): %d\n", + fspcavail); + + if (more_to_do || no_queue_space || no_fifo_space) { + /* + * May need to queue more transactions as the request + * queue or Tx FIFO empties. Enable the non-periodic + * Tx FIFO empty interrupt. (Always use the half-empty + * level to ensure that new requests are loaded as + * soon as possible.) + */ + gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; + dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are + * no more transactions that need to be queued right + * now. This function is called from interrupt + * handlers to queue more transactions as transfer + * states change. + */ + gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_NPTXFEMP; + dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } +} + +/** + * dwc2_hcd_queue_transactions() - Processes the currently active host channels + * and queues transactions for these channels to the DWC_otg controller. Called + * from the HCD interrupt handler functions. + * + * @hsotg: The HCD state structure + * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, + * or both) + * + * Must be called with interrupt disabled and spinlock held + */ +void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, + enum dwc2_transaction_type tr_type) +{ +#ifdef DWC2_DEBUG_SOF + dev_vdbg(hsotg->dev, "Queue Transactions\n"); +#endif + /* Process host channels associated with non-periodic transfers */ + if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || + tr_type == DWC2_TRANSACTION_ALL) { + if (!list_empty(&hsotg->non_periodic_sched_active)) { + dwc2_process_non_periodic_channels(hsotg); + } else { + /* + * Ensure NP Tx FIFO empty interrupt is disabled when + * there are no non-periodic transfers to process + */ + u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + gintmsk &= ~GINTSTS_NPTXFEMP; + dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } +} + +static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) +{ + struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); + + return hcd->self.b_hnp_enable; +} + +/* Must NOT be called with interrupt disabled or spinlock held */ +static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) +{ + unsigned long flags; + u32 hprt0; + u32 pcgctl; + u32 gotgctl; + + dev_dbg(hsotg->dev, "%s()\n", __func__); + + spin_lock_irqsave(&hsotg->lock, flags); + + if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl |= GOTGCTL_HSTSETHNPEN; + dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + hsotg->op_state = OTG_STATE_A_SUSPEND; + } + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_SUSP; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + + hsotg->bus_suspended = true; + + /* + * If hibernation is supported, Phy clock will be suspended + * after registers are backuped. + */ + /* Suspend the Phy Clock */ + pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl |= PCGCTL_STOPPCLK; + dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + udelay(10); + + /* For HNP the bus must be suspended for at least 200ms */ + if (dwc2_host_is_b_hnp_enabled(hsotg)) { + pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~PCGCTL_STOPPCLK; + dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + + spin_unlock_irqrestore(&hsotg->lock, flags); + + msleep(200); + } else { + spin_unlock_irqrestore(&hsotg->lock, flags); + } +} + +/* Must NOT be called with interrupt disabled or spinlock held */ +static void dwc2_port_resume(struct dwc2_hsotg *hsotg) +{ + unsigned long flags; + u32 hprt0; + u32 pcgctl; + + spin_lock_irqsave(&hsotg->lock, flags); + + /* + * If hibernation is supported, Phy clock is already resumed + * after registers restore. + */ + pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~PCGCTL_STOPPCLK; + dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + spin_unlock_irqrestore(&hsotg->lock, flags); + msleep(20); + spin_lock_irqsave(&hsotg->lock, flags); + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RES; + hprt0 &= ~HPRT0_SUSP; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + spin_unlock_irqrestore(&hsotg->lock, flags); + + msleep(USB_RESUME_TIMEOUT); + + spin_lock_irqsave(&hsotg->lock, flags); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); + dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->bus_suspended = false; + spin_unlock_irqrestore(&hsotg->lock, flags); +} + +/* Handles hub class-specific requests */ +static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, + u16 wvalue, u16 windex, char *buf, u16 wlength) +{ + struct usb_hub_descriptor *hub_desc; + int retval = 0; + u32 hprt0; + u32 port_status; + u32 speed; + u32 pcgctl;//printf("GetPortStatus:%x\n", GetPortStatus); + + switch (typereq) { + case ClearHubFeature: + dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); + + switch (wvalue) { + case C_HUB_LOCAL_POWER: + case C_HUB_OVER_CURRENT: + /* Nothing required here */ + break; + + default: + retval = -EINVAL; + dev_err(hsotg->dev, + "ClearHubFeature request %1xh unknown\n", + wvalue); + } + break; + + case ClearPortFeature: + if (wvalue != USB_PORT_FEAT_L1) + if (!windex || windex > 1) + goto error; + switch (wvalue) { + case USB_PORT_FEAT_ENABLE: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_ENA; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_SUSPEND: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); + + if (hsotg->bus_suspended) + dwc2_port_resume(hsotg); + break; + + case USB_PORT_FEAT_POWER: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~HPRT0_PWR; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_INDICATOR: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); + /* Port indicator not supported */ + break; + + case USB_PORT_FEAT_C_CONNECTION: + /* + * Clears driver's internal Connect Status Change flag + */ + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); + hsotg->flags.b.port_connect_status_change = 0; + break; + + case USB_PORT_FEAT_C_RESET: + /* Clears driver's internal Port Reset Change flag */ + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); + hsotg->flags.b.port_reset_change = 0; + break; + + case USB_PORT_FEAT_C_ENABLE: + /* + * Clears the driver's internal Port Enable/Disable + * Change flag + */ + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); + hsotg->flags.b.port_enable_change = 0; + break; + + case USB_PORT_FEAT_C_SUSPEND: + /* + * Clears the driver's internal Port Suspend Change + * flag, which is set when resume signaling on the host + * port is complete + */ + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); + hsotg->flags.b.port_suspend_change = 0; + break; + + case USB_PORT_FEAT_C_PORT_L1: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); + hsotg->flags.b.port_l1_change = 0; + break; + + case USB_PORT_FEAT_C_OVER_CURRENT: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); + hsotg->flags.b.port_over_current_change = 0; + break; + + default: + retval = -EINVAL; + dev_err(hsotg->dev, + "ClearPortFeature request %1xh unknown or unsupported\n", + wvalue); + } + break; + + case GetHubDescriptor: + dev_dbg(hsotg->dev, "GetHubDescriptor\n"); + hub_desc = (struct usb_hub_descriptor *)buf; + + hub_desc->bLength = 9; + hub_desc->bDescriptorType = USB_DT_HUB; + hub_desc->bNbrPorts = 1; + hub_desc->wHubCharacteristics = + cpu_to_le16(HUB_CHAR_COMMON_LPSM | + HUB_CHAR_INDV_PORT_OCPM); + hub_desc->bPwrOn2PwrGood = 1; + hub_desc->bHubContrCurrent = 0; + hub_desc->u.hs.DeviceRemovable[0] = 0; + hub_desc->u.hs.DeviceRemovable[1] = 0xff; + break; + + case GetHubStatus: + dev_dbg(hsotg->dev, "GetHubStatus\n"); + memset(buf, 0, 4); + break; + + case GetPortStatus: + dev_vdbg(hsotg->dev, + "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, + hsotg->flags.d32); + if (!windex || windex > 1) + goto error; + + port_status = 0; + if (hsotg->flags.b.port_connect_status_change) + port_status |= USB_PORT_STAT_C_CONNECTION << 16; + if (hsotg->flags.b.port_enable_change) + port_status |= USB_PORT_STAT_C_ENABLE << 16; + if (hsotg->flags.b.port_suspend_change) + port_status |= USB_PORT_STAT_C_SUSPEND << 16; + if (hsotg->flags.b.port_l1_change) + port_status |= USB_PORT_STAT_C_L1 << 16; + if (hsotg->flags.b.port_reset_change) + port_status |= USB_PORT_STAT_C_RESET << 16; + if (hsotg->flags.b.port_over_current_change) { + dev_warn(hsotg->dev, "Overcurrent change detected\n"); + port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; + } + + if (!hsotg->flags.b.port_connect_status) { + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return 0's for the remainder of the port status + * since the port register can't be read if the core + * is in device mode. + */ + *(__le32 *)buf = cpu_to_le32(port_status); + break; + } + + hprt0 = dwc2_readl(hsotg->regs + HPRT0); + dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); + + if (hprt0 & HPRT0_CONNSTS) + port_status |= USB_PORT_STAT_CONNECTION; + if (hprt0 & HPRT0_ENA) + port_status |= USB_PORT_STAT_ENABLE; + if (hprt0 & HPRT0_SUSP) + port_status |= USB_PORT_STAT_SUSPEND; + if (hprt0 & HPRT0_OVRCURRACT) + port_status |= USB_PORT_STAT_OVERCURRENT; + if (hprt0 & HPRT0_RST) + port_status |= USB_PORT_STAT_RESET; + if (hprt0 & HPRT0_PWR) + port_status |= USB_PORT_STAT_POWER; + + speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + if (speed == HPRT0_SPD_HIGH_SPEED) + port_status |= USB_PORT_STAT_HIGH_SPEED; + else if (speed == HPRT0_SPD_LOW_SPEED) + port_status |= USB_PORT_STAT_LOW_SPEED; + + if (hprt0 & HPRT0_TSTCTL_MASK) + port_status |= USB_PORT_STAT_TEST; + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ + + dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); + *(__le32 *)buf = cpu_to_le32(port_status); + break; + + case SetHubFeature: + dev_dbg(hsotg->dev, "SetHubFeature\n"); + /* No HUB features supported */ + break; + + case SetPortFeature: + dev_dbg(hsotg->dev, "SetPortFeature\n"); + if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) + goto error; + + if (!hsotg->flags.b.port_connect_status) { + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return without doing anything since the port + * register can't be written if the core is in device + * mode. + */ + break; + } + + switch (wvalue) { + case USB_PORT_FEAT_SUSPEND: + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); + if (windex != hsotg->otg_port) + goto error; + dwc2_port_suspend(hsotg, windex); + break; + + case USB_PORT_FEAT_POWER: + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_PWR; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_RESET: + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_RESET\n"); + pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); + dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + /* ??? Original driver does this */ + dwc2_writel(0, hsotg->regs + PCGCTL); + + hprt0 = dwc2_read_hprt0(hsotg); + /* Clear suspend bit if resetting from suspend state */ + hprt0 &= ~HPRT0_SUSP; + + /* + * When B-Host the Port reset bit is set in the Start + * HCD Callback function, so that the reset is started + * within 1ms of the HNP success interrupt + */ + if (!dwc2_hcd_is_b_host(hsotg)) { + hprt0 |= HPRT0_PWR | HPRT0_RST; + dev_dbg(hsotg->dev, + "In host mode, hprt0=%08x\n", hprt0); + dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ + msleep(50); + hprt0 &= ~HPRT0_RST; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->lx_state = DWC2_L0; /* Now back to On state */ + break; + + case USB_PORT_FEAT_INDICATOR: + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); + /* Not supported */ + break; + + case USB_PORT_FEAT_TEST: + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_TEST\n"); + hprt0 &= ~HPRT0_TSTCTL_MASK; + hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; + dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + default: + retval = -EINVAL; + dev_err(hsotg->dev, + "SetPortFeature %1xh unknown or unsupported\n", + wvalue); + break; + } + break; + + default: +error: + retval = -EINVAL; + dev_dbg(hsotg->dev, + "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", + typereq, windex, wvalue); + break; + } + + return retval; +} + +static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) +{ + int retval; + + if (port != 1) + return -EINVAL; + + retval = (hsotg->flags.b.port_connect_status_change || + hsotg->flags.b.port_reset_change || + hsotg->flags.b.port_enable_change || + hsotg->flags.b.port_suspend_change || + hsotg->flags.b.port_over_current_change); +/*printf("%d %d %d %d %d\r\n", hsotg->flags.b.port_connect_status_change, + hsotg->flags.b.port_reset_change , + hsotg->flags.b.port_enable_change , + hsotg->flags.b.port_suspend_change , + hsotg->flags.b.port_over_current_change);*/ + if (retval) { + dev_dbg(hsotg->dev, + "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); + dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", + hsotg->flags.b.port_connect_status_change); + dev_dbg(hsotg->dev, " port_reset_change: %d\n", + hsotg->flags.b.port_reset_change); + dev_dbg(hsotg->dev, " port_enable_change: %d\n", + hsotg->flags.b.port_enable_change); + dev_dbg(hsotg->dev, " port_suspend_change: %d\n", + hsotg->flags.b.port_suspend_change); + dev_dbg(hsotg->dev, " port_over_current_change: %d\n", + hsotg->flags.b.port_over_current_change); + } + + return retval; +} + +int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) +{ + u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); + +#ifdef DWC2_DEBUG_SOF + dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", + (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); +#endif + return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; +} + +int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) +{ + u32 hprt = dwc2_readl(hsotg->regs + HPRT0); + u32 hfir = dwc2_readl(hsotg->regs + HFIR); + u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); + unsigned int us_per_frame; + unsigned int frame_number; + unsigned int remaining; + unsigned int interval; + unsigned int phy_clks; + + /* High speed has 125 us per (micro) frame; others are 1 ms per */ + us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; + + /* Extract fields */ + frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; + remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; + interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; + + /* + * Number of phy clocks since the last tick of the frame number after + * "us" has passed. + */ + phy_clks = (interval - remaining) + + DIV_ROUND_UP(interval * us, us_per_frame); + + return dwc2_frame_num_inc(frame_number, phy_clks / interval); +} + +int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) +{ + return hsotg->op_state == OTG_STATE_B_HOST; +} + +static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, + int iso_desc_count, + gfp_t mem_flags) +{ + struct dwc2_hcd_urb *urb; + u32 size = sizeof(*urb) + iso_desc_count; + + ListItem_t *pxListItem = NULL; + int found = 0, flags; + spin_lock_irqsave(&hsotg->lock, flags); + list_for_each_entry(pxListItem, urb, &hsotg->free_urb_list) { + if (urb && urb->packet_count == iso_desc_count) { + found = 1; + break; + } + } + if (found) { + list_del_init(&urb->free_list_entry); + spin_unlock_irqrestore(&hsotg->lock, flags); + memset(urb, 0, sizeof(struct dwc2_hcd_urb)); + INIT_LIST_ITEM(&urb->free_list_entry); + listSET_LIST_ITEM_OWNER(&urb->free_list_entry, urb); + return urb; + } + spin_unlock_irqrestore(&hsotg->lock, flags); + + urb = (struct dwc2_hcd_urb *)kzalloc(size, mem_flags); + if (urb) + urb->packet_count = iso_desc_count; + + if (urb) { + INIT_LIST_ITEM(&urb->free_list_entry); + listSET_LIST_ITEM_OWNER(&urb->free_list_entry, urb); + } + + return urb; +} + +static struct dwc2_qtd *dwc2_hcd_qtd_alloc(struct dwc2_hsotg *hsotg, + gfp_t mem_flags) +{ + struct dwc2_qtd *qtd = NULL; + + if (!list_empty(&hsotg->free_qtd_list)) { + qtd = listGET_OWNER_OF_HEAD_ENTRY(&hsotg->free_qtd_list); + memset(qtd, 0, sizeof(struct dwc2_qtd)); + list_del_init(&qtd->qtd_list_entry); + listSET_LIST_ITEM_OWNER(&qtd->qtd_list_entry, qtd); + return qtd; + } + + qtd = (struct dwc2_qtd *)kzalloc(sizeof(*qtd), mem_flags); + if (qtd) { + listSET_LIST_ITEM_OWNER(&qtd->qtd_list_entry, qtd); + } + + return qtd; +} + + +static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, + struct dwc2_hcd_urb *urb, u8 dev_addr, + u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) +{ + if (dbg_perio() || + ep_type == USB_ENDPOINT_XFER_BULK || + ep_type == USB_ENDPOINT_XFER_CONTROL) + dev_vdbg(hsotg->dev, + "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", + dev_addr, ep_num, ep_dir, ep_type, mps); + urb->pipe_info.dev_addr = dev_addr; + urb->pipe_info.ep_num = ep_num; + urb->pipe_info.pipe_type = ep_type; + urb->pipe_info.pipe_dir = ep_dir; + urb->pipe_info.mps = mps; +} + +struct wrapper_priv_data { + struct dwc2_hsotg *hsotg; +}; + +/* Gets the dwc2_hsotg from a usb_hcd */ +static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) +{ + struct wrapper_priv_data *p; + + p = (struct wrapper_priv_data *)hcd->hcd_priv; + + return p->hsotg; +} + +/** + * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context + * + * This will get the dwc2_tt structure (and ttport) associated with the given + * context (which is really just a struct urb pointer). + * + * The first time this is called for a given TT we allocate memory for our + * structure. When everyone is done and has called dwc2_host_put_tt_info() + * then the refcount for the structure will go to 0 and we'll free it. + * + * @hsotg: The HCD state structure for the DWC OTG controller. + * @qh: The QH structure. + * @context: The priv pointer from a struct dwc2_hcd_urb. + * @mem_flags: Flags for allocating memory. + * @ttport: We'll return this device's port number here. That's used to + * reference into the bitmap if we're on a multi_tt hub. + * + * Return: a pointer to a struct dwc2_tt. Don't forget to call + * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. + */ + +struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, + gfp_t mem_flags, int *ttport) +{ + struct urb *urb = context; + struct dwc2_tt *dwc_tt = NULL; + + if (urb->dev->tt) { + *ttport = urb->dev->ttport; + + dwc_tt = urb->dev->tt->hcpriv; + if (!dwc_tt) { + size_t bitmap_size; + + /* + * For single_tt we need one schedule. For multi_tt + * we need one per port. + */ + bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * + sizeof(dwc_tt->periodic_bitmaps[0]); + if (urb->dev->tt->multi) + bitmap_size *= urb->dev->tt->hub->maxchild; + + dwc_tt = (struct dwc2_tt *)kzalloc(sizeof(*dwc_tt) + bitmap_size, + mem_flags); + if (!dwc_tt) + return NULL; + + dwc_tt->usb_tt = urb->dev->tt; + dwc_tt->usb_tt->hcpriv = dwc_tt; + } + + dwc_tt->refcount++; + } + + return dwc_tt; +} + +/** + * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() + * + * Frees resources allocated by dwc2_host_get_tt_info() if all current holders + * of the structure are done. + * + * It's OK to call this with NULL. + * + * @hsotg: The HCD state structure for the DWC OTG controller. + * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. + */ +void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) +{ + /* Model kfree and make put of NULL a no-op */ + if (!dwc_tt) + return; + + WARN_ON(dwc_tt->refcount < 1); + + dwc_tt->refcount--; + if (!dwc_tt->refcount) { + dwc_tt->usb_tt->hcpriv = NULL; + kfree(dwc_tt); + } +} + +int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) +{ + struct urb *urb = context; + + return urb->dev->speed; +} + +static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, + struct urb *urb) +{ + struct usb_bus *bus = hcd_to_bus(hcd); + + if (urb->interval) + bus->bandwidth_allocated += bw / urb->interval; + + bus->bandwidth_int_reqs++; +} + +/* + * Sets the final status of an URB and returns it to the upper layer. Any + * required cleanup of the URB is performed. + * + * Must be called with interrupt disabled and spinlock held + */ +void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, + int status) +{ + struct urb *urb; + + if (!qtd) { + dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); + return; + } + + if (!qtd->urb) { + dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); + return; + } + + urb = qtd->urb->priv; + if (!urb) { + dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); + return; + } + + urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); + + if (dbg_urb(urb)) + dev_vdbg(hsotg->dev, + "%s: urb %p device %d ep %d-%s status %d actual %d\n", + __func__, urb, usb_pipedevice(urb->pipe), + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "IN" : "OUT", status, + urb->actual_length); + + urb->status = status; + if (!status) { + if ((urb->transfer_flags & URB_SHORT_NOT_OK) && + urb->actual_length < urb->transfer_buffer_length) + urb->status = -EREMOTEIO; + } + + usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); + urb->hcpriv = NULL; + list_add_tail(&qtd->urb->free_list_entry, &hsotg->free_urb_list); + qtd->urb = NULL; + + usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); +} + +/* + * ========================================================================= + * Linux HC Driver Functions + * ========================================================================= + */ + +/* + * Initializes the DWC_otg controller and its root hub and prepares it for host + * mode operation. Activates the root port. Returns 0 on success and a negative + * error code on failure. + */ +static int _dwc2_hcd_start(struct usb_hcd *hcd) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + struct usb_bus *bus = hcd_to_bus(hcd); + unsigned long flags; + + dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); + + spin_lock_irqsave(&hsotg->lock, flags); + hsotg->lx_state = DWC2_L0; + + dwc2_hcd_reinit(hsotg); + + spin_unlock_irqrestore(&hsotg->lock, flags); + return 0; +} + +/* + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are + * stopped. + */ +static void _dwc2_hcd_stop(struct usb_hcd *hcd) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + unsigned long flags; + + /* Turn off all host-specific interrupts */ + dwc2_disable_host_interrupts(hsotg); + + spin_lock_irqsave(&hsotg->lock, flags); + /* Ensure hcd is disconnected */ + dwc2_hcd_disconnect(hsotg, true); + dwc2_hcd_stop(hsotg); + hsotg->lx_state = DWC2_L3; + + spin_unlock_irqrestore(&hsotg->lock, flags); + + udelay(2000); +} + +/* Returns the current frame number */ +static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + + return dwc2_hcd_get_frame_number(hsotg); +} + +/* + * Starts processing a USB transfer request specified by a USB Request Block + * (URB). mem_flags indicates the type of memory allocation to use while + * processing this URB. + */ +int dwc2_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, + gfp_t mem_flags) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + struct usb_host_endpoint *ep = urb->ep; + struct dwc2_hcd_urb *dwc2_urb; + int retval; + int alloc_bandwidth = 0; + u8 ep_type = 0; + u32 tflags = 0; + void *buf; + unsigned long flags; + struct dwc2_qh *qh; + bool qh_allocated = false; + struct dwc2_qtd *qtd; + + if (dbg_urb(urb)) { + dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); + } + + if (!ep) + return -EINVAL; + + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: + ep_type = USB_ENDPOINT_XFER_CONTROL; + break; + case PIPE_BULK: + ep_type = USB_ENDPOINT_XFER_BULK; + break; + } + + /*if (usb_pipetype(urb->pipe) == PIPE_BULK && urb->transfer_buffer) {//dev_dbg(hsotg->dev, "data_toggle:%d\n", qh->data_toggle); + char *tmpbuf = urb->transfer_buffer; + for(i = 0; i < urb->transfer_buffer_length; i++) { + printf("%02x ", tmpbuf[i]); + }printf("\n"); + }*/ + + dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, + mem_flags); + if (!dwc2_urb) + return -ENOMEM; + + dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), + usb_pipeendpoint(urb->pipe), ep_type, + usb_pipein(urb->pipe), + usb_maxpacket(urb->dev, urb->pipe)); + + buf = urb->transfer_buffer; + + if (hcd->self.uses_dma) { + if (!buf && (urb->transfer_dma & 3)) { + dev_err(hsotg->dev, + "%s: unaligned transfer with no transfer_buffer", + __func__); + retval = -EINVAL; + goto fail0; + } + } + + if (!(urb->transfer_flags & URB_NO_INTERRUPT)) + tflags |= URB_GIVEBACK_ASAP; + if (urb->transfer_flags & URB_ZERO_PACKET) + tflags |= URB_SEND_ZERO_PACKET; + + dwc2_urb->priv = urb; + dwc2_urb->buf = buf; + dwc2_urb->dma = urb->transfer_dma; + dwc2_urb->length = urb->transfer_buffer_length; + dwc2_urb->setup_packet = urb->setup_packet; + dwc2_urb->setup_dma = urb->setup_dma; + dwc2_urb->flags = tflags; + dwc2_urb->interval = urb->interval; + dwc2_urb->status = -EINPROGRESS; + + urb->hcpriv = dwc2_urb; + qh = (struct dwc2_qh *)ep->hcpriv; + /* Create QH for the endpoint if it doesn't exist */ + if (!qh) { + qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); + if (!qh) { + retval = -ENOMEM; + goto fail0; + } + ep->hcpriv = qh; + qh_allocated = true; + }//dev_dbg(hsotg->dev, "data_toggle:%d qh:%x\n", qh->data_toggle, qh); + + spin_lock_irqsave(&hsotg->lock, flags); + qtd = dwc2_hcd_qtd_alloc(hsotg, mem_flags); + if (!qtd) { + retval = -ENOMEM; + goto fail1; + } + + usb_hcd_link_urb_to_ep(hcd, urb); + + retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); + if (retval) + goto fail3; + + if (alloc_bandwidth) { + dwc2_allocate_bus_bandwidth(hcd, + dwc2_hcd_get_ep_bandwidth(hsotg, ep), + urb); + } + + spin_unlock_irqrestore(&hsotg->lock, flags); + + return 0; + +fail3: + dwc2_urb->priv = NULL; + usb_hcd_unlink_urb_from_ep(hcd, urb); + if (qh_allocated && qh->channel && qh->channel->qh == qh) + qh->channel->qh = NULL; + list_add_tail(&qtd->qtd_list_entry, &hsotg->free_qtd_list); + spin_unlock_irqrestore(&hsotg->lock, flags); + urb->hcpriv = NULL; +fail1: + if (qh_allocated) { + struct dwc2_qtd *qtd2;//, *qtd2_tmp; + + ep->hcpriv = NULL; + dwc2_hcd_qh_unlink(hsotg, qh); + /* Free each QTD in the QH's QTD list */ + /*list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, + qtd_list_entry)*/ + ListItem_t *pxListItem, *nListItem; + list_for_each_entry_safe(pxListItem, nListItem, qtd2, &qh->qtd_list) + dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); + dwc2_hcd_qh_free(hsotg, qh); + } +fail0: + spin_lock_irqsave(&hsotg->lock, flags); + list_add_tail(&dwc2_urb->free_list_entry, &hsotg->free_urb_list); + spin_unlock_irqrestore(&hsotg->lock, flags); + + return retval; +} + +/* + * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. + */ +int dwc2_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, + int status) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + int rc; + unsigned long flags; + + dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); + + spin_lock_irqsave(&hsotg->lock, flags); + + rc = usb_hcd_check_unlink_urb(hcd, urb, status); + if (rc) + goto out; + + if (!urb->hcpriv) { + dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); + goto out; + } + + rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); + + usb_hcd_unlink_urb_from_ep(hcd, urb); + + kfree(urb->hcpriv); + urb->hcpriv = NULL; + + /* Higher layer software sets URB status */ + spin_unlock(&hsotg->lock); + usb_hcd_giveback_urb(hcd, urb, status); + spin_lock(&hsotg->lock); + + dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); + dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); +out: + spin_unlock_irqrestore(&hsotg->lock, flags); + + return rc; +} + +/* + * Frees resources in the DWC_otg controller related to a given endpoint. Also + * clears state in the HCD related to the endpoint. Any URBs for the endpoint + * must already be dequeued. + */ +static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, + struct usb_host_endpoint *ep) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + + dev_dbg(hsotg->dev, + "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", + ep->desc.bEndpointAddress, ep->hcpriv); + dwc2_hcd_endpoint_disable(hsotg, ep, 250); +} + +/* + * Resets endpoint specific parameter values, in current version used to reset + * the data toggle (as a WA). This function can be called from usb_clear_halt + * routine. + */ +static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, + struct usb_host_endpoint *ep) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + unsigned long flags; + + dev_dbg(hsotg->dev, + "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", + ep->desc.bEndpointAddress); + + spin_lock_irqsave(&hsotg->lock, flags); + dwc2_hcd_endpoint_reset(hsotg, ep); + spin_unlock_irqrestore(&hsotg->lock, flags); +} + +/* + * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid + * interrupt. + * + * This function is called by the USB core when an interrupt occurs + */ +static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + + return dwc2_handle_hcd_intr(hsotg); +} + +void dwc2_hcd_irq(struct dwc2_hsotg *hsotg) +{ + dwc2_handle_hcd_intr(hsotg); +} + + +/* + * Creates Status Change bitmap for the root hub and root port. The bitmap is + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 + * is the status change indicator for the single root port. Returns 1 if either + * change indicator is 1, otherwise returns 0. + */ +static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) +{ + struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); + + int ret; + + ret = (dwc2_hcd_is_status_changed(hsotg, 1) << 1); + memcpy(buf, &hsotg->flags, sizeof(hsotg->flags)); + + return ret; +} + +/* Handles hub class-specific requests */ +static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, + u16 windex, char *buf, u16 wlength) +{ + int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, + wvalue, windex, buf, wlength); + return retval; +} + +static struct hc_driver dwc2_hc_driver = { + .description = "dwc2_hsotg", + .product_desc = "DWC OTG Controller", + .hcd_priv_size = sizeof(struct wrapper_priv_data), + + .irq = _dwc2_hcd_irq, + .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, + + .start = _dwc2_hcd_start, + .stop = _dwc2_hcd_stop, + .urb_enqueue = dwc2_urb_enqueue, + .urb_dequeue = dwc2_urb_dequeue, + .endpoint_disable = _dwc2_hcd_endpoint_disable, + .endpoint_reset = _dwc2_hcd_endpoint_reset, + .get_frame_number = _dwc2_hcd_get_frame_number, + + .hub_status_data = _dwc2_hcd_hub_status_data, + .hub_control = _dwc2_hcd_hub_control, +}; + +struct hc_driver* dwc2_get_driver() +{ + return &dwc2_hc_driver; +} + + +/* + * Frees secondary storage associated with the dwc2_hsotg structure contained + * in the struct usb_hcd field + */ +static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) +{ + u32 ahbcfg; + u32 dctl; + int i; + + dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); + + /* Free memory for QH/QTD lists */ + dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); + dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); + + /* Free memory for the host channels */ + for (i = 0; i < MAX_EPS_CHANNELS; i++) { + struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; + + if (chan) { + dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", + i, chan); + hsotg->hc_ptr_array[i] = NULL; + kfree(chan); + } + } + + kfree(hsotg->status_buf); + hsotg->status_buf = NULL; + + ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* Disable all interrupts */ + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + dwc2_writel(0, hsotg->regs + GINTMSK); + + if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { + dctl = dwc2_readl(hsotg->regs + DCTL); + dctl |= DCTL_SFTDISCON; + dwc2_writel(dctl, hsotg->regs + DCTL); + } +} + +static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) +{ + /* Turn off all host-specific interrupts */ + dwc2_disable_host_interrupts(hsotg); + + dwc2_hcd_free(hsotg); +} + +void reset_hcd_reg(struct dwc2_hsotg *hsotg) +{ + dwc2_writel(0x0024863E, hsotg->regs + 0x000); + dwc2_writel(0x006086a3, hsotg->regs + 0x008); + dwc2_writel(0x3a40170f, hsotg->regs + 0x00c); + dwc2_writel(0x80000400, hsotg->regs + 0x010); + dwc2_writel(0xFFFFFFFF, hsotg->regs + 0x018); + dwc2_writel(0x00000634, hsotg->regs + 0x024); + dwc2_writel(0x01800634, hsotg->regs + 0x028); + dwc2_writel(0x00000000, hsotg->regs + 0x054); + dwc2_writel(0x030007B4, hsotg->regs + 0x100); + dwc2_writel(0x80008000, hsotg->regs + 0x400); + dwc2_writel(0x0001EA60, hsotg->regs + 0x404); + dwc2_writel(0x0000FFFF, hsotg->regs + 0x418); + dwc2_writel(0x00001000, hsotg->regs + 0x440); + dwc2_writel(0x00000000, hsotg->regs + 0x500); +} + +/* + * Initializes the HCD. This function allocates memory for and initializes the + * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the + * USB bus with the core and calls the hc_driver->start() function. It returns + * a negative error on failure. + */ +int dwc2_hcd_init(struct dwc2_hsotg *hsotg, struct usb_hcd *hcd) +{ + //struct usb_hcd *hcd; + struct dwc2_host_chan *channel; + u32 hcfg; + int i, num_channels; + int retval; + + dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); + + retval = -ENOMEM; + + hcfg = dwc2_readl(hsotg->regs + HCFG); + USB_UNUSED(hcfg); + dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); + + hsotg->last_frame_num = HFNUM_MAX_FRNUM; + hcd->self.uses_dma = 0; + + hcd->has_tt = 1; + struct wrapper_priv_data *hcd_pri = (struct wrapper_priv_data *)kmalloc(sizeof(struct wrapper_priv_data), __GFP_ZERO); + hcd_pri->hsotg = hsotg; + hcd->hcd_priv = hcd_pri; + hsotg->priv = (void*)hcd; + + /* + * Disable the global interrupt until all the interrupt handlers are + * installed + */ + dwc2_disable_global_interrupts(hsotg); + + /* Initialize the DWC_otg core, and select the Phy type */ + retval = dwc2_core_init(hsotg, true); + if (retval) + goto error2; + + /* Create new workqueue and init work */ + retval = -ENOMEM; + + /* Initialize the non-periodic schedule */ + INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); + INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); + + INIT_LIST_HEAD(&hsotg->split_order); + + /* + * Create a host channel descriptor for each host channel implemented + * in the controller. Initialize the channel descriptor array. + */ + INIT_LIST_HEAD(&hsotg->free_hc_list); + num_channels = hsotg->params.host_channels; + memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); + + for (i = 0; i < num_channels; i++) { + channel = kzalloc(sizeof(*channel), GFP_KERNEL); + if (!channel) + goto error3; + channel->hc_num = i; + + INIT_LIST_ITEM(&channel->split_order_list_entry); + //channel->split_order_list_entry.pvOwner = (void *)channel; + listSET_LIST_ITEM_OWNER(&channel->split_order_list_entry, channel); + //channel->hc_list_entry.pvOwner = (void *)channel; + listSET_LIST_ITEM_OWNER(&channel->hc_list_entry, channel); + hsotg->hc_ptr_array[i] = channel; + } + + INIT_LIST_HEAD(&hsotg->free_qtd_list); + INIT_LIST_HEAD(&hsotg->free_urb_list); + + /* + * Allocate space for storing data on status transactions. Normally no + * data is sent, but this space acts as a bit bucket. This must be + * done after usb_add_hcd since that function allocates the DMA buffer + * pool. + */ + hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, + GFP_KERNEL); + + if (!hsotg->status_buf) + goto error3; + + hsotg->otg_port = 1; + hsotg->frame_list = NULL; + hsotg->frame_list_dma = 0; + + /* Initiate lx_state to L3 disconnected state */ + hsotg->lx_state = DWC2_L3; + + hcd->self.otg_port = hsotg->otg_port; + + /* Don't support SG list at this point */ + hcd->self.sg_tablesize = 0; + + //_dwc2_hcd_start(hcd); + dwc2_host_start(hsotg); + + //reset_hcd_reg(hsotg); + + dwc2_enable_global_interrupts(hsotg); + + return 0; + +/* error4: + kmem_cache_destroy(hsotg->unaligned_cache); + kmem_cache_destroy(hsotg->desc_hsisoc_cache); + kmem_cache_destroy(hsotg->desc_gen_cache); */ +error3: + dwc2_hcd_release(hsotg); +error2: +//error1: + dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); + return retval; +} + +/* + * Removes the HCD. + * Frees memory and resources associated with the HCD and deregisters the bus. + */ +void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) +{ + struct usb_hcd *hcd; + + dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); + + hcd = dwc2_hsotg_to_hcd(hsotg); + dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); + + if (!hcd) { + dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", + __func__); + return; + } + + hsotg->priv = NULL; + dwc2_hcd_release(hsotg); +} diff --git a/A58-STEPLDR/Src/usb/hcd.h b/A58-STEPLDR/Src/usb/hcd.h new file mode 100644 index 00000000..c5bd55d9 --- /dev/null +++ b/A58-STEPLDR/Src/usb/hcd.h @@ -0,0 +1,793 @@ +/* + * hcd.h - DesignWare HS OTG Controller host-mode declarations + * + * Copyright (C) 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __DWC2_HCD_H__ +#define __DWC2_HCD_H__ + +#include "usb-compat.h" + +/* + * This file contains the structures, constants, and interfaces for the + * Host Contoller Driver (HCD) + * + * The Host Controller Driver (HCD) is responsible for translating requests + * from the USB Driver into the appropriate actions on the DWC_otg controller. + * It isolates the USBD from the specifics of the controller by providing an + * API to the USBD. + */ + +struct dwc2_qh; + +/** + * struct dwc2_host_chan - Software host channel descriptor + * + * @hc_num: Host channel number, used for register address lookup + * @dev_addr: Address of the device + * @ep_num: Endpoint of the device + * @ep_is_in: Endpoint direction + * @speed: Device speed. One of the following values: + * - USB_SPEED_LOW + * - USB_SPEED_FULL + * - USB_SPEED_HIGH + * @ep_type: Endpoint type. One of the following values: + * - USB_ENDPOINT_XFER_CONTROL: 0 + * - USB_ENDPOINT_XFER_ISOC: 1 + * - USB_ENDPOINT_XFER_BULK: 2 + * - USB_ENDPOINT_XFER_INTR: 3 + * @max_packet: Max packet size in bytes + * @data_pid_start: PID for initial transaction. + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control EP), + * SETUP (Control EP) + * @multi_count: Number of additional periodic transactions per + * (micro)frame + * @xfer_buf: Pointer to current transfer buffer position + * @xfer_dma: DMA address of xfer_buf + * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not + * DWORD aligned + * @xfer_len: Total number of bytes to transfer + * @xfer_count: Number of bytes transferred so far + * @start_pkt_count: Packet count at start of transfer + * @xfer_started: True if the transfer has been started + * @ping: True if a PING request should be issued on this channel + * @error_state: True if the error count for this transaction is non-zero + * @halt_on_queue: True if this channel should be halted the next time a + * request is queued for the channel. This is necessary in + * slave mode if no request queue space is available when + * an attempt is made to halt the channel. + * @halt_pending: True if the host channel has been halted, but the core + * is not finished flushing queued requests + * @do_split: Enable split for the channel + * @complete_split: Enable complete split + * @hub_addr: Address of high speed hub for the split + * @hub_port: Port of the low/full speed device for the split + * @xact_pos: Split transaction position. One of the following values: + * - DWC2_HCSPLT_XACTPOS_MID + * - DWC2_HCSPLT_XACTPOS_BEGIN + * - DWC2_HCSPLT_XACTPOS_END + * - DWC2_HCSPLT_XACTPOS_ALL + * @requests: Number of requests issued for this channel since it was + * assigned to the current transfer (not counting PINGs) + * @schinfo: Scheduling micro-frame bitmap + * @ntd: Number of transfer descriptors for the transfer + * @halt_status: Reason for halting the host channel + * @hcint Contents of the HCINT register when the interrupt came + * @qh: QH for the transfer being processed by this channel + * @hc_list_entry: For linking to list of host channels + * @desc_list_addr: Current QH's descriptor list DMA address + * @desc_list_sz: Current QH's descriptor list size + * @split_order_list_entry: List entry for keeping track of the order of splits + * + * This structure represents the state of a single host channel when acting in + * host mode. It contains the data items needed to transfer packets to an + * endpoint via a host channel. + */ +struct dwc2_host_chan { + u8 hc_num; + + unsigned dev_addr:7; + unsigned ep_num:4; + unsigned ep_is_in:1; + unsigned speed:4; + unsigned ep_type:2; + unsigned max_packet:11; + unsigned data_pid_start:2; +#define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 +#define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 +#define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 +#define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA +#define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP + + unsigned multi_count:2; + + u8 *xfer_buf; + dma_addr_t xfer_dma; + dma_addr_t align_buf; + u32 xfer_len; + u32 xfer_count; + u16 start_pkt_count; + u8 xfer_started; + u8 do_ping; + u8 error_state; + u8 halt_on_queue; + u8 halt_pending; + u8 do_split; + u8 complete_split; + u8 hub_addr; + u8 hub_port; + u8 xact_pos; +#define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID +#define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END +#define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN +#define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL + + u8 requests; + u8 schinfo; + u16 ntd; + enum dwc2_halt_status halt_status; + u32 hcint; + struct dwc2_qh *qh; + ListItem_t hc_list_entry; + ListItem_t split_order_list_entry; +}; + +struct dwc2_hcd_pipe_info { + u8 dev_addr; + u8 ep_num; + u8 pipe_type; + u8 pipe_dir; + u16 mps; +}; + +struct dwc2_qtd; + +struct dwc2_hcd_urb { + void *priv; + struct dwc2_qtd *qtd; + void *buf; + dma_addr_t dma; + void *setup_packet; + dma_addr_t setup_dma; + u32 length; + u32 actual_length; + int status; + u32 error_count; + u32 packet_count; + u32 flags; + u16 interval; + ListItem_t free_list_entry; + struct dwc2_hcd_pipe_info pipe_info; +}; + +/* Phases for control transfers */ +enum dwc2_control_phase { + DWC2_CONTROL_SETUP, + DWC2_CONTROL_DATA, + DWC2_CONTROL_STATUS, +}; + +/* Transaction types */ +enum dwc2_transaction_type { + DWC2_TRANSACTION_NONE, + DWC2_TRANSACTION_PERIODIC, + DWC2_TRANSACTION_NON_PERIODIC, + DWC2_TRANSACTION_ALL, +}; + +/* The number of elements per LS bitmap (per port on multi_tt) */ +#define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \ + BITS_PER_LONG) + +/** + * struct dwc2_tt - dwc2 data associated with a usb_tt + * + * @refcount: Number of Queue Heads (QHs) holding a reference. + * @usb_tt: Pointer back to the official usb_tt. + * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted + * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP + * elements (so sizeof(long) times that in bytes). + * + * This structure is stored in the hcpriv of the official usb_tt. + */ +struct dwc2_tt { + int refcount; + struct usb_tt *usb_tt; + unsigned long periodic_bitmaps[]; +}; + +/** + * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus. + * + * @start_schedule_usecs: The start time on the main bus schedule. Note that + * the main bus schedule is tightly packed and this + * time should be interpreted as tightly packed (so + * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us + * instead of 125 us). + * @duration_us: How long this transfer goes. + */ + +struct dwc2_hs_transfer_time { + u32 start_schedule_us; + u16 duration_us; +}; + +/** + * struct dwc2_qh - Software queue head structure + * + * @hsotg: The HCD state structure for the DWC OTG controller + * @ep_type: Endpoint type. One of the following values: + * - USB_ENDPOINT_XFER_CONTROL + * - USB_ENDPOINT_XFER_BULK + * - USB_ENDPOINT_XFER_INT + * - USB_ENDPOINT_XFER_ISOC + * @ep_is_in: Endpoint direction + * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor + * @dev_speed: Device speed. One of the following values: + * - USB_SPEED_LOW + * - USB_SPEED_FULL + * - USB_SPEED_HIGH + * @data_toggle: Determines the PID of the next data packet for + * non-controltransfers. Ignored for control transfers. + * One of the following values: + * - DWC2_HC_PID_DATA0 + * - DWC2_HC_PID_DATA1 + * @ping_state: Ping state + * @do_split: Full/low speed endpoint on high-speed hub requires split + * @td_first: Index of first activated isochronous transfer descriptor + * @td_last: Index of last activated isochronous transfer descriptor + * @host_us: Bandwidth in microseconds per transfer as seen by host + * @device_us: Bandwidth in microseconds per transfer as seen by device + * @host_interval: Interval between transfers as seen by the host. If + * the host is high speed and the device is low speed this + * will be 8 times device interval. + * @device_interval: Interval between transfers as seen by the device. + * interval. + * @next_active_frame: (Micro)frame _before_ we next need to put something on + * the bus. We'll move the qh to active here. If the + * host is in high speed mode this will be a uframe. If + * the host is in low speed mode this will be a full frame. + * @start_active_frame: If we are partway through a split transfer, this will be + * what next_active_frame was when we started. Otherwise + * it should always be the same as next_active_frame. + * @num_hs_transfers: Number of transfers in hs_transfers. + * Normally this is 1 but can be more than one for splits. + * Always >= 1 unless the host is in low/full speed mode. + * @hs_transfers: Transfers that are scheduled as seen by the high speed + * bus. Not used if host is in low or full speed mode (but + * note that it IS USED if the device is low or full speed + * as long as the HOST is in high speed mode). + * @ls_start_schedule_slice: Start time (in slices) on the low speed bus + * schedule that's being used by this device. This + * will be on the periodic_bitmap in a + * "struct dwc2_tt". Not used if this device is high + * speed. Note that this is in "schedule slice" which + * is tightly packed. + * @ls_duration_us: Duration on the low speed bus schedule. + * @ntd: Actual number of transfer descriptors in a list + * @dw_align_buf: Used instead of original buffer if its physical address + * is not dword-aligned + * @dw_align_buf_dma: DMA address for dw_align_buf + * @qtd_list: List of QTDs for this QH + * @channel: Host channel currently processing transfers for this QH + * @qh_list_entry: Entry for QH in either the periodic or non-periodic + * schedule + * @desc_list: List of transfer descriptors + * @desc_list_dma: Physical address of desc_list + * @desc_list_sz: Size of descriptors list + * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer + * descriptor and indicates original XferSize value for the + * descriptor + * @unreserve_timer: Timer for releasing periodic reservation. + * @dwc2_tt: Pointer to our tt info (or NULL if no tt). + * @ttport: Port number within our tt. + * @tt_buffer_dirty True if clear_tt_buffer_complete is pending + * @unreserve_pending: True if we planned to unreserve but haven't yet. + * @schedule_low_speed: True if we have a low/full speed component (either the + * host is in low/full speed mode or do_split). + * + * A Queue Head (QH) holds the static characteristics of an endpoint and + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may + * be entered in either the non-periodic or periodic schedule. + */ +struct dwc2_qh { + struct dwc2_hsotg *hsotg; + u8 ep_type; + u8 ep_is_in; + u16 maxp; + u8 dev_speed; + u8 data_toggle; + u8 ping_state; + u8 do_split; + u8 td_first; + u8 td_last; + u16 host_us; + u16 device_us; + u16 host_interval; + u16 device_interval; + u16 next_active_frame; + u16 start_active_frame; + s16 num_hs_transfers; + struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES]; + u32 ls_start_schedule_slice; + u16 ntd; + u8 *dw_align_buf; + dma_addr_t dw_align_buf_dma; + List_t qtd_list; + struct dwc2_host_chan *channel; + ListItem_t qh_list_entry; + u32 *n_bytes; + struct timer_list unreserve_timer; + struct dwc2_tt *dwc_tt; + int ttport; + unsigned tt_buffer_dirty:1; + unsigned unreserve_pending:1; + unsigned schedule_low_speed:1; +}; + +/** + * struct dwc2_qtd - Software queue transfer descriptor (QTD) + * + * @control_phase: Current phase for control transfers (Setup, Data, or + * Status) + * @in_process: Indicates if this QTD is currently processed by HW + * @data_toggle: Determines the PID of the next data packet for the + * data phase of control transfers. Ignored for other + * transfer types. One of the following values: + * - DWC2_HC_PID_DATA0 + * - DWC2_HC_PID_DATA1 + * @complete_split: Keeps track of the current split type for FS/LS + * endpoints on a HS Hub + * @isoc_split_pos: Position of the ISOC split in full/low speed + * @isoc_frame_index: Index of the next frame descriptor for an isochronous + * transfer. A frame descriptor describes the buffer + * position and length of the data to be transferred in the + * next scheduled (micro)frame of an isochronous transfer. + * It also holds status for that transaction. The frame + * index starts at 0. + * @isoc_split_offset: Position of the ISOC split in the buffer for the + * current frame + * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT + * @error_count: Holds the number of bus errors that have occurred for + * a transaction within this transfer + * @n_desc: Number of DMA descriptors for this QTD + * @isoc_frame_index_last: Last activated frame (packet) index, used in + * descriptor DMA mode only + * @urb: URB for this transfer + * @qh: Queue head for this QTD + * @qtd_list_entry: For linking to the QH's list of QTDs + * + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, + * interrupt, or isochronous transfer. A single QTD is created for each URB + * (of one of these types) submitted to the HCD. The transfer associated with + * a QTD may require one or multiple transactions. + * + * A QTD is linked to a Queue Head, which is entered in either the + * non-periodic or periodic schedule for execution. When a QTD is chosen for + * execution, some or all of its transactions may be executed. After + * execution, the state of the QTD is updated. The QTD may be retired if all + * its transactions are complete or if an error occurred. Otherwise, it + * remains in the schedule so more transactions can be executed later. + */ +struct dwc2_qtd { + enum dwc2_control_phase control_phase; + u8 in_process; + u8 data_toggle; + u8 complete_split; + u8 isoc_split_pos; + u32 ssplit_out_xfer_count; + u8 error_count; + u8 n_desc; + struct dwc2_hcd_urb *urb; + struct dwc2_qh *qh; + ListItem_t qtd_list_entry; +}; + +#ifdef DEBUG +struct hc_xfer_info { + struct dwc2_hsotg *hsotg; + struct dwc2_host_chan *chan; +}; +#endif + +u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); + +/* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ +static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) +{ + return (struct usb_hcd *)hsotg->priv; +} + +/* + * Inline used to disable one channel interrupt. Channel interrupts are + * disabled when the channel is halted or released by the interrupt handler. + * There is no need to handle further interrupts of that type until the + * channel is re-assigned. In fact, subsequent handling may cause crashes + * because the channel structures are cleaned up when the channel is released. + */ +static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) +{ + u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + + mask &= ~intr; + dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); +} + +void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); +void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, + enum dwc2_halt_status halt_status); +void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan); + +/* + * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they + * are read as 1, they won't clear when written back. + */ +static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) +{ + u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); + return hprt0; +} + +static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) +{ + return pipe->ep_num; +} + +static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) +{ + return pipe->pipe_type; +} + +static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) +{ + return pipe->mps; +} + +static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) +{ + return pipe->dev_addr; +} + +static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) +{ + return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; +} + +static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) +{ + return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; +} + +static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) +{ + return pipe->pipe_dir == USB_DIR_IN; +} + +static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) +{ + return !dwc2_hcd_is_pipe_in(pipe); +} +void dwc2_hcd_irq(struct dwc2_hsotg *hsotg); +int dwc2_hcd_init(struct dwc2_hsotg *hsotg, struct usb_hcd *hcd); +void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); + +/* Transaction Execution Functions */ +enum dwc2_transaction_type dwc2_hcd_select_transactions( + struct dwc2_hsotg *hsotg); +void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, + enum dwc2_transaction_type tr_type); + +/* Schedule Queue Functions */ +/* Implemented in hcd_queue.c */ +struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, + struct dwc2_hcd_urb *urb, + gfp_t mem_flags); +void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); +int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); +void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); +void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, + int sched_csplit); + +void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); +int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, + struct dwc2_qh *qh); + +/* Unlinks and frees a QTD */ +static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, + struct dwc2_qtd *qtd, + struct dwc2_qh *qh) +{ + list_del(&qtd->qtd_list_entry); + list_add_tail(&qtd->qtd_list_entry, &hsotg->free_qtd_list); + + qtd = NULL; +} + +/* Descriptor DMA support functions */ +void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, + struct dwc2_qh *qh); +void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + enum dwc2_halt_status halt_status); + +int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, + gfp_t mem_flags); +void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); + +/* Check if QH is non-periodic */ +#define dwc2_qh_is_non_per(_qh_ptr_) \ + ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ + (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) + +#ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC +static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } +static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } +static inline bool dbg_urb(struct urb *urb) { return true; } +static inline bool dbg_perio(void) { return true; } +#else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ +static inline bool dbg_hc(struct dwc2_host_chan *hc) +{ + return hc->ep_type == USB_ENDPOINT_XFER_BULK || + hc->ep_type == USB_ENDPOINT_XFER_CONTROL; +} + +static inline bool dbg_qh(struct dwc2_qh *qh) +{ + return qh->ep_type == USB_ENDPOINT_XFER_BULK || + qh->ep_type == USB_ENDPOINT_XFER_CONTROL; +} + +static inline bool dbg_urb(struct urb *urb) +{ + return true; + /*return usb_pipetype(urb->pipe) == PIPE_BULK || + usb_pipetype(urb->pipe) == PIPE_CONTROL;*/ +} + +static inline bool dbg_perio(void) { return false; } +#endif + +/* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ +#define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) + +/* Packet size for any kind of endpoint descriptor */ +#define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) + +/* + * Returns true if frame1 index is greater than frame2 index. The comparison + * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the + * frame number when the max index frame number is reached. + */ +static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) +{ + u16 diff = fr_idx1 - fr_idx2; + u16 sign = diff & (FRLISTEN_64_SIZE >> 1); + + return diff && !sign; +} + +/* + * Returns true if frame1 is less than or equal to frame2. The comparison is + * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the + * frame number when the max frame number is reached. + */ +static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) +{ + return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); +} + +/* + * Returns true if frame1 is greater than frame2. The comparison is done + * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame + * number when the max frame number is reached. + */ +static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) +{ + return (frame1 != frame2) && + ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); +} + +/* + * Increments frame by the amount specified by inc. The addition is done + * modulo HFNUM_MAX_FRNUM. Returns the incremented value. + */ +static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) +{ + return (frame + inc) & HFNUM_MAX_FRNUM; +} + +static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec) +{ + return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; +} + +static inline u16 dwc2_full_frame_num(u16 frame) +{ + return (frame & HFNUM_MAX_FRNUM) >> 3; +} + +static inline u16 dwc2_micro_frame_num(u16 frame) +{ + return frame & 0x7; +} + +/* + * Returns the Core Interrupt Status register contents, ANDed with the Core + * Interrupt Mask register contents + */ +static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) +{ + return dwc2_readl(hsotg->regs + GINTSTS) & + dwc2_readl(hsotg->regs + GINTMSK); +} + +static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) +{ + return dwc2_urb->status; +} + +static inline u32 dwc2_hcd_urb_get_actual_length( + struct dwc2_hcd_urb *dwc2_urb) +{ + return dwc2_urb->actual_length; +} + +static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) +{ + return dwc2_urb->error_count; +} + +static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, + struct usb_host_endpoint *ep) +{ + struct dwc2_qh *qh = (struct dwc2_qh *)ep->hcpriv; + + if (qh && !list_item_empty(&qh->qh_list_entry)) + return 1; + + return 0; +} + +static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, + struct usb_host_endpoint *ep) +{ + struct dwc2_qh *qh = (struct dwc2_qh *)ep->hcpriv; + + if (!qh) { + WARN_ON(1); + return 0; + } + + return qh->host_us; +} + +void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd); + +/* HCD Core API */ + +/** + * dwc2_handle_hcd_intr() - Called on every hardware interrupt + * + * @hsotg: The DWC2 HCD + * + * Returns IRQ_HANDLED if interrupt is handled + * Return IRQ_NONE if interrupt is not handled + */ +irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); + +/** + * dwc2_hcd_stop() - Halts the DWC_otg host mode operation + * + * @hsotg: The DWC2 HCD + */ +void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); + +/** + * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, + * and 0 otherwise + * + * @hsotg: The DWC2 HCD + */ +int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); + +/* URB interface */ + +/* Transfer flags */ +#define URB_GIVEBACK_ASAP 0x1 +#define URB_SEND_ZERO_PACKET 0x2 + +/* Host driver callbacks */ +struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, + void *context, gfp_t mem_flags, + int *ttport); + +void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, + struct dwc2_tt *dwc_tt); +int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); +void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, + int status); + +#ifdef DEBUG +/* + * Macro to sample the remaining PHY clocks left in the current frame. This + * may be used during debugging to determine the average time it takes to + * execute sections of code. There are two possible sample points, "a" and + * "b", so the _letter_ argument must be one of these values. + * + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For + * example, "cat /sys/devices/lm0/hcd_frrem". + */ +#define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ +do { \ + struct hfnum_data _hfnum_; \ + struct dwc2_qtd *_qtd_; \ + \ + _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ + qtd_list_entry); \ + if (usb_pipeint(_qtd_->urb->pipe) && \ + (_qh_)->start_active_frame != 0 && !_qtd_->complete_split) { \ + _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \ + switch (_hfnum_.b.frnum & 0x7) { \ + case 7: \ + (_hcd_)->hfnum_7_samples_##_letter_++; \ + (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ + _hfnum_.b.frrem; \ + break; \ + case 0: \ + (_hcd_)->hfnum_0_samples_##_letter_++; \ + (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ + _hfnum_.b.frrem; \ + break; \ + default: \ + (_hcd_)->hfnum_other_samples_##_letter_++; \ + (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ + _hfnum_.b.frrem; \ + break; \ + } \ + } \ +} while (0) +#else +#define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) +#endif + +void dwc2_hcd_start_isr(struct dwc2_hsotg *hsotg); + +#endif /* __DWC2_HCD_H__ */ diff --git a/A58-STEPLDR/Src/usb/hcd_intr.c b/A58-STEPLDR/Src/usb/hcd_intr.c new file mode 100644 index 00000000..2767b252 --- /dev/null +++ b/A58-STEPLDR/Src/usb/hcd_intr.c @@ -0,0 +1,1523 @@ +/* + * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling + * + * Copyright (C) 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file contains the interrupt handlers for Host mode + */ +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include +#include "cp15.h" + +#include "core.h" +#include "hcd.h" + + +/* This function is for debug only */ +static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg) +{ + u16 curr_frame_number = hsotg->frame_number; + u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1); + + if (expected != curr_frame_number) + dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n", + expected, curr_frame_number); + + hsotg->last_frame_num = curr_frame_number; +} + +static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, + struct dwc2_qtd *qtd) +{ +} + +/* + * Handles the start-of-frame interrupt in host mode. Non-periodic + * transactions may be queued to the DWC_otg controller for the current + * (micro)frame. Periodic transactions may be queued to the controller + * for the next (micro)frame. + */ +static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) +{ + //struct list_head *qh_entry; + enum dwc2_transaction_type tr_type; + + /* Clear interrupt */ + dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); + +#ifdef DEBUG_SOF + dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); +#endif + + hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); + + dwc2_track_missed_sofs(hsotg); + + tr_type = dwc2_hcd_select_transactions(hsotg); + if (tr_type != DWC2_TRANSACTION_NONE) + dwc2_hcd_queue_transactions(hsotg, tr_type); +} + +/* + * Handles the Rx FIFO Level Interrupt, which indicates that there is + * at least one packet in the Rx FIFO. The packets are moved from the FIFO to + * memory if the DWC_otg controller is operating in Slave mode. + */ +static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) +{ + u32 grxsts, chnum, bcnt, dpid, pktsts; + struct dwc2_host_chan *chan; + + if (dbg_perio()) + dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); + + grxsts = dwc2_readl(hsotg->regs + GRXSTSP); + chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; + chan = hsotg->hc_ptr_array[chnum]; + if (!chan) { + dev_err(hsotg->dev, "Unable to get corresponding channel\n"); + return; + } + + bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT; + dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT; + pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT; + + USB_UNUSED(dpid); + + /* Packet Status */ + if (dbg_perio()) { + dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum); + dev_vdbg(hsotg->dev, " Count = %d\n", bcnt); + dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid, + chan->data_pid_start); + dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts); + } + + switch (pktsts) { + case GRXSTS_PKTSTS_HCHIN: + /* Read the data into the host buffer */ + if (bcnt > 0) { + dwc2_read_packet(hsotg, chan->xfer_buf, bcnt); + + /* Update the HC fields for the next packet received */ + chan->xfer_count += bcnt; + chan->xfer_buf += bcnt; + } + break; + case GRXSTS_PKTSTS_HCHIN_XFER_COMP: + case GRXSTS_PKTSTS_DATATOGGLEERR: + case GRXSTS_PKTSTS_HCHHALTED: + /* Handled in interrupt, just ignore data */ + break; + default: + dev_err(hsotg->dev, + "RxFIFO Level Interrupt: Unknown status %d\n", pktsts); + break; + } +} + +/* + * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More + * data packets may be written to the FIFO for OUT transfers. More requests + * may be written to the non-periodic request queue for IN transfers. This + * interrupt is enabled only in Slave mode. + */ +static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) +{ + dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n"); + dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC); +} + +static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, + u32 *hprt0_modify) +{ + u32 hfir; + + dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Every time when port enables calculate HFIR.FrInterval */ + hfir = dwc2_readl(hsotg->regs + HFIR); + hfir &= ~HFIR_FRINT_MASK; + hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & + HFIR_FRINT_MASK; + dwc2_writel(hfir, hsotg->regs + HFIR); + + /* Check if we need to adjust the PHY clock speed for low power */ + /* Port has been enabled, set the reset change flag */ + hsotg->flags.b.port_reset_change = 1; + + return; +} + +/* + * There are multiple conditions that can cause a port interrupt. This function + * determines which interrupt conditions have occurred and handles them + * appropriately. + */ +static void dwc2_port_intr(struct dwc2_hsotg *hsotg) +{ + u32 hprt0; + u32 hprt0_modify; + + dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); + + hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0_modify = hprt0; + + /* + * Clear appropriate bits in HPRT0 to clear the interrupt bit in + * GINTSTS + */ + hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | + HPRT0_OVRCURRCHG); + + /* + * Port Connect Detected + * Set flag and clear if detected + */ + if (hprt0 & HPRT0_CONNDET) { + dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0); + + dev_vdbg(hsotg->dev, + "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", + hprt0); + dwc2_hcd_connect(hsotg); + + /* + * The Hub driver asserts a reset when it sees port connect + * status change flag + */ + } + + /* + * Port Enable Changed + * Clear if detected - Set internal flag if disabled + */ + if (hprt0 & HPRT0_ENACHG) { + dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0); + dev_vdbg(hsotg->dev, + " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", + hprt0, !!(hprt0 & HPRT0_ENA)); + if (hprt0 & HPRT0_ENA) { + hsotg->new_connection = true; + dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify); + } else { + hsotg->flags.b.port_enable_change = 1; + } + } + + /* Overcurrent Change Interrupt */ + if (hprt0 & HPRT0_OVRCURRCHG) { + dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG, + hsotg->regs + HPRT0); + dev_vdbg(hsotg->dev, + " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", + hprt0); + hsotg->flags.b.port_over_current_change = 1; + } +} + +/* + * Gets the actual length of a transfer after the transfer halts. halt_status + * holds the reason for the halt. + * + * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read + * is set to 1 upon return if less than the requested number of bytes were + * transferred. short_read may also be NULL on entry, in which case it remains + * unchanged. + */ +static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status, + int *short_read) +{ + u32 hctsiz, count, length; + + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + + if (halt_status == DWC2_HC_XFER_COMPLETE) { + if (chan->ep_is_in) { + count = (hctsiz & TSIZ_XFERSIZE_MASK) >> + TSIZ_XFERSIZE_SHIFT; + length = chan->xfer_len - count; + if (short_read) + *short_read = (count != 0); + } else if (chan->qh->do_split) { + length = qtd->ssplit_out_xfer_count; + } else { + length = chan->xfer_len; + } + } else { + /* + * Must use the hctsiz.pktcnt field to determine how much data + * has been transferred. This field reflects the number of + * packets that have been transferred via the USB. This is + * always an integral number of packets if the transfer was + * halted before its normal completion. (Can't use the + * hctsiz.xfersize field because that reflects the number of + * bytes transferred via the AHB, not the USB). + */ + count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT; + length = (chan->start_pkt_count - count) * chan->max_packet; + } + + return length; +} + +/** + * dwc2_update_urb_state() - Updates the state of the URB after a Transfer + * Complete interrupt on the host channel. Updates the actual_length field + * of the URB based on the number of bytes transferred via the host channel. + * Sets the URB status if the data transfer is finished. + * + * Return: 1 if the data transfer specified by the URB is completely finished, + * 0 otherwise + */ +static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_hcd_urb *urb, + struct dwc2_qtd *qtd) +{ + u32 hctsiz; + int xfer_done = 0; + int short_read = 0; + int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, + DWC2_HC_XFER_COMPLETE, + &short_read); + + if (urb->actual_length + xfer_length > urb->length) { + dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); + xfer_length = urb->length - urb->actual_length; + } + + dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n", + urb->actual_length, xfer_length); + urb->actual_length += xfer_length; + + if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK && + (urb->flags & URB_SEND_ZERO_PACKET) && + urb->actual_length >= urb->length && + !(urb->length % chan->max_packet)) { + xfer_done = 0; + } else if (short_read || urb->actual_length >= urb->length) { + xfer_done = 1; + urb->status = 0; + } + + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + USB_UNUSED(hctsiz); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); + dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n", + (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT); + dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length); + dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length); + dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read, + xfer_done); + + return xfer_done; +} + +/* + * Save the starting data toggle for the next transfer. The data toggle is + * saved in the QH for non-control transfers and it's saved in the QTD for + * control transfers. + */ +#ifndef WARN +#define WARN(condition, format...) (condition) +#endif +void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; + + if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { + if (WARN(!chan || !chan->qh, + "chan->qh must be specified for non-control eps\n")) + return; + //dev_dbg(hsotg->dev, "dwc2_hcd_save_data_toggle pid:%d qh:%x\n", pid, chan->qh); + if (pid == TSIZ_SC_MC_PID_DATA0) + chan->qh->data_toggle = DWC2_HC_PID_DATA0; + else + chan->qh->data_toggle = DWC2_HC_PID_DATA1; + } else { + if (WARN(!qtd, + "qtd must be specified for control eps\n")) + return; + + if (pid == TSIZ_SC_MC_PID_DATA0) + qtd->data_toggle = DWC2_HC_PID_DATA0; + else + qtd->data_toggle = DWC2_HC_PID_DATA1; + } +} + +/* + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are + * still linked to the QH, the QH is added to the end of the inactive + * non-periodic schedule. For periodic QHs, removes the QH from the periodic + * schedule if no more QTDs are linked to the QH. + */ +static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, + int free_qtd) +{ + int continue_split = 0; + struct dwc2_qtd *qtd; + + if (dbg_qh(qh)) + dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__, + hsotg, qh, free_qtd); + + if (list_empty(&qh->qtd_list)) { + dev_dbg(hsotg->dev, "## QTD list empty ##\n"); + goto no_qtd; + } + + //qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); + qtd = list_first_entry(&qh->qtd_list); + + if (qtd->complete_split) + continue_split = 1; + else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID || + qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END) + continue_split = 1; + + if (free_qtd) { + dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); + continue_split = 0; + } + +no_qtd: + qh->channel = NULL; + dwc2_hcd_qh_deactivate(hsotg, qh, continue_split); +} + +/** + * dwc2_release_channel() - Releases a host channel for use by other transfers + * + * @hsotg: The HCD state structure + * @chan: The host channel to release + * @qtd: The QTD associated with the host channel. This QTD may be + * freed if the transfer is complete or an error has occurred. + * @halt_status: Reason the channel is being released. This status + * determines the actions taken by this function. + * + * Also attempts to select and queue more transactions since at least one host + * channel is available. + */ +static void dwc2_release_channel(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, + struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status) +{ + enum dwc2_transaction_type tr_type; + u32 haintmsk; + int free_qtd = 0; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n", + __func__, chan->hc_num, halt_status); + + switch (halt_status) { + case DWC2_HC_XFER_URB_COMPLETE: + free_qtd = 1; + break; + case DWC2_HC_XFER_AHB_ERR: + case DWC2_HC_XFER_STALL: + case DWC2_HC_XFER_BABBLE_ERR: + free_qtd = 1; + break; + case DWC2_HC_XFER_XACT_ERR: + if (qtd && qtd->error_count >= 3) { + SendUartString("Complete URB with transaction error\n"); + free_qtd = 1; + dwc2_host_complete(hsotg, qtd, -EPROTO); + } + break; + case DWC2_HC_XFER_URB_DEQUEUE: + /* + * The QTD has already been removed and the QH has been + * deactivated. Don't want to do anything except release the + * host channel and try to queue more transfers. + */ + goto cleanup; + case DWC2_HC_XFER_PERIODIC_INCOMPLETE: + dev_vdbg(hsotg->dev, " Complete URB with I/O error\n"); + free_qtd = 1; + dwc2_host_complete(hsotg, qtd, -EIO); + break; + case DWC2_HC_XFER_NO_HALT_STATUS: + default: + break; + } + + dwc2_deactivate_qh(hsotg, chan->qh, free_qtd); + +cleanup: + /* + * Release the host channel for use by other transfers. The cleanup + * function clears the channel interrupt enables and conditions, so + * there's no need to clear the Channel Halted interrupt separately. + */ + if (!list_item_empty(&chan->hc_list_entry)) + list_del(&chan->hc_list_entry); + + dwc2_hc_cleanup(hsotg, chan); + list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); + + switch (chan->ep_type) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + hsotg->non_periodic_channels--; + break; + default: + /* + * Don't release reservations for periodic channels + * here. That's done when a periodic transfer is + * descheduled (i.e. when the QH is removed from the + * periodic schedule). + */ + break; + } + + haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); + haintmsk &= ~(1 << chan->hc_num); + dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); + + /* Try to queue more transfers now that there's a free channel */ + tr_type = dwc2_hcd_select_transactions(hsotg); + if (tr_type != DWC2_TRANSACTION_NONE) + dwc2_hcd_queue_transactions(hsotg, tr_type); +} + +/* + * Halts a host channel. If the channel cannot be halted immediately because + * the request queue is full, this function ensures that the FIFO empty + * interrupt for the appropriate queue is enabled so that the halt request can + * be queued when there is space in the request queue. + * + * This function may also be called in DMA mode. In that case, the channel is + * simply released since the core always halts the channel automatically in + * DMA mode. + */ +static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status) +{ + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + /* Slave mode processing */ + dwc2_hc_halt(hsotg, chan, halt_status); + + if (chan->halt_on_queue) { + u32 gintmsk; + + dev_vdbg(hsotg->dev, "Halt on queue\n"); + if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || + chan->ep_type == USB_ENDPOINT_XFER_BULK) { + dev_vdbg(hsotg->dev, "control/bulk\n"); + /* + * Make sure the Non-periodic Tx FIFO empty interrupt + * is enabled so that the non-periodic schedule will + * be processed + */ + gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; + dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } +} + +/* + * Performs common cleanup for non-periodic transfers after a Transfer + * Complete interrupt. This function should be called after any endpoint type + * specific handling is finished to release the host channel. + */ +static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, + int chnum, struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status) +{ + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + qtd->error_count = 0; + + if (chan->hcint & HCINTMSK_NYET) { + /* + * Got a NYET on the last transaction of the transfer. This + * means that the endpoint should be in the PING state at the + * beginning of the next transfer. + */ + dev_vdbg(hsotg->dev, "got NYET\n"); + chan->qh->ping_state = 1; + } + + /* + * Always halt and release the host channel to make it available for + * more transfers. There may still be more phases for a control + * transfer or more data packets for a bulk transfer at this point, + * but the host channel is still halted. A channel will be reassigned + * to the transfer when the non-periodic schedule is processed after + * the channel is released. This allows transactions to be queued + * properly via dwc2_hcd_queue_transactions, which also enables the + * Tx FIFO Empty interrupt if necessary. + */ + if (chan->ep_is_in) { + /* + * IN transfers in Slave mode require an explicit disable to + * halt the channel. (In DMA mode, this call simply releases + * the channel.) + */ + dwc2_halt_channel(hsotg, chan, qtd, halt_status); + } else { + /* + * The channel is automatically disabled by the core for OUT + * transfers in Slave mode + */ + dwc2_release_channel(hsotg, chan, qtd, halt_status); + } +} + +/* + * Handles a host channel Transfer Complete interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + struct dwc2_hcd_urb *urb = qtd->urb; + enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE; + int pipe_type; + int urb_xfer_done; + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, + "--Host Channel %d Interrupt: Transfer Complete--\n", + chnum); + + if (!urb) + goto handle_xfercomp_done; + + pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); + + /* Handle xfer complete on CSPLIT */ + if (chan->qh->do_split) { + qtd->complete_split = 0; + } + + /* Update the QTD and URB states */ + switch (pipe_type) { + case USB_ENDPOINT_XFER_CONTROL: + switch (qtd->control_phase) { + case DWC2_CONTROL_SETUP: + if (urb->length > 0) + qtd->control_phase = DWC2_CONTROL_DATA; + else + qtd->control_phase = DWC2_CONTROL_STATUS; + dev_vdbg(hsotg->dev, + " Control setup transaction done\n"); + halt_status = DWC2_HC_XFER_COMPLETE; + break; + case DWC2_CONTROL_DATA: + urb_xfer_done = dwc2_update_urb_state(hsotg, chan, + chnum, urb, qtd); + if (urb_xfer_done) { + qtd->control_phase = DWC2_CONTROL_STATUS; + dev_vdbg(hsotg->dev, + " Control data transfer done\n"); + } else { + dwc2_hcd_save_data_toggle(hsotg, chan, chnum, + qtd); + } + halt_status = DWC2_HC_XFER_COMPLETE; + break; + case DWC2_CONTROL_STATUS: + dev_vdbg(hsotg->dev, " Control transfer complete\n"); + if (urb->status == -EINPROGRESS) + urb->status = 0; + dwc2_host_complete(hsotg, qtd, urb->status); + halt_status = DWC2_HC_XFER_URB_COMPLETE; + break; + } + + dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, + halt_status); + break; + case USB_ENDPOINT_XFER_BULK: + dev_vdbg(hsotg->dev, " Bulk transfer complete\n"); + urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, + qtd); + if (urb_xfer_done) { + dwc2_host_complete(hsotg, qtd, urb->status); + halt_status = DWC2_HC_XFER_URB_COMPLETE; + } else { + halt_status = DWC2_HC_XFER_COMPLETE; + } + + dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); + dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, + halt_status); + break; + } + +handle_xfercomp_done: + disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL); +} + +/* + * Handles a host channel STALL interrupt. This handler may be called in + * either DMA mode or Slave mode. + */ +static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + struct dwc2_hcd_urb *urb = qtd->urb; + int pipe_type; + + dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n", + chnum); + + /* if (hsotg->params.dma_desc_enable) { + dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, + DWC2_HC_XFER_STALL); + goto handle_stall_done; + } */ + + if (!urb) + goto handle_stall_halt; + + pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); + + if (pipe_type == USB_ENDPOINT_XFER_CONTROL) + dwc2_host_complete(hsotg, qtd, -EPIPE); + + if (pipe_type == USB_ENDPOINT_XFER_BULK || + pipe_type == USB_ENDPOINT_XFER_INT) { + dwc2_host_complete(hsotg, qtd, -EPIPE); + /* + * USB protocol requires resetting the data toggle for bulk + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) + * setup command is issued to the endpoint. Anticipate the + * CLEAR_FEATURE command since a STALL has occurred and reset + * the data toggle now. + */ + chan->qh->data_toggle = 0; + } + +handle_stall_halt: + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL); + +//handle_stall_done: + disable_hc_int(hsotg, chnum, HCINTMSK_STALL); +} + +/* + * Updates the state of the URB when a transfer has been stopped due to an + * abnormal condition before the transfer completes. Modifies the + * actual_length field of the URB to reflect the number of bytes that have + * actually been transferred via the host channel. + */ +static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_hcd_urb *urb, + struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status) +{ + u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, + qtd, halt_status, NULL); + u32 hctsiz; + + if (urb->actual_length + xfer_length > urb->length) { + dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); + xfer_length = urb->length - urb->actual_length; + } + + urb->actual_length += xfer_length; + + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + USB_UNUSED(hctsiz); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", + chan->start_pkt_count); + dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n", + (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT); + dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet); + dev_vdbg(hsotg->dev, " bytes_transferred %d\n", + xfer_length); + dev_vdbg(hsotg->dev, " urb->actual_length %d\n", + urb->actual_length); + dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", + urb->length); +} + +/* + * Handles a host channel NAK interrupt. This handler may be called in either + * DMA mode or Slave mode. + */ +static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + if (!qtd) { + dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__); + return; + } + + if (!qtd->urb) { + dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__); + return; + } + + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n", + chnum); + + /* + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and + * interrupt. Re-start the SSPLIT transfer. + */ + if (chan->do_split) { + if (chan->complete_split) + qtd->error_count = 0; + qtd->complete_split = 0; + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); + goto handle_nak_done; + } + + switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + /* + * NAK interrupts normally occur during OUT transfers in DMA + * or Slave mode. For IN transfers, more requests will be + * queued as request queue space is available. + */ + qtd->error_count = 0; + + if (!chan->qh->ping_state) { + dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, + qtd, DWC2_HC_XFER_NAK); + dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); + + if (chan->speed == USB_SPEED_HIGH) + chan->qh->ping_state = 1; + } + + /* + * Halt the channel so the transfer can be re-started from + * the appropriate point or the PING protocol will + * start/continue + */ + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); + break; + } + +handle_nak_done: + disable_hc_int(hsotg, chnum, HCINTMSK_NAK); +} + +/* + * Handles a host channel ACK interrupt. This interrupt is enabled when + * performing the PING protocol in Slave mode, when errors occur during + * either Slave mode or DMA mode, and during Start Split transactions. + */ +static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n", + chnum); + + if (chan->do_split) { + /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */ + if (!chan->ep_is_in && + chan->data_pid_start != DWC2_HC_PID_SETUP) + qtd->ssplit_out_xfer_count = chan->xfer_len; + + if (chan->ep_is_in) { + qtd->complete_split = 1; + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); + } + } else { + qtd->error_count = 0; + + if (chan->qh->ping_state) { + chan->qh->ping_state = 0; + /* + * Halt the channel so the transfer can be re-started + * from the appropriate point. This only happens in + * Slave mode. In DMA mode, the ping_state is cleared + * when the transfer is started because the core + * automatically executes the PING, then the transfer. + */ + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); + } + } + + /* + * If the ACK occurred when _not_ in the PING state, let the channel + * continue transferring data after clearing the error count + */ + disable_hc_int(hsotg, chnum, HCINTMSK_ACK); +} + +/* + * Handles a host channel NYET interrupt. This interrupt should only occur on + * Bulk and Control OUT endpoints and for complete split transactions. If a + * NYET occurs at the same time as a Transfer Complete interrupt, it is + * handled in the xfercomp interrupt handler, not here. This handler may be + * called in either DMA mode or Slave mode. + */ +static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n", + chnum); + + /* + * NYET on CSPLIT + * re-do the CSPLIT immediately on non-periodic + */ + if (chan->do_split && chan->complete_split) { + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); + goto handle_nyet_done; + } + + chan->qh->ping_state = 1; + qtd->error_count = 0; + + dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd, + DWC2_HC_XFER_NYET); + dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); + + /* + * Halt the channel and re-start the transfer so the PING protocol + * will start + */ + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); + +handle_nyet_done: + disable_hc_int(hsotg, chnum, HCINTMSK_NYET); +} + +/* + * Handles a host channel babble interrupt. This handler may be called in + * either DMA mode or Slave mode. + */ +static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n", + chnum); + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + + /* if (hsotg->params.dma_desc_enable) { + dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, + DWC2_HC_XFER_BABBLE_ERR); + goto disable_int; + } */ + + dwc2_host_complete(hsotg, qtd, -EOVERFLOW); + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR); + +//disable_int: + disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR); +} + +/* + * Handles a host channel AHB error interrupt. This handler is only called in + * DMA mode. + */ +static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + struct dwc2_hcd_urb *urb = qtd->urb; + char *pipetype, *speed; + u32 hcchar; + u32 hcsplt; + u32 hctsiz; + u32 hc_dma; + + dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n", + chnum); + + if (!urb) + goto handle_ahberr_halt; + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); + hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); + + dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); + dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); + dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma); + dev_err(hsotg->dev, " Device address: %d\n", + dwc2_hcd_get_dev_addr(&urb->pipe_info)); + dev_err(hsotg->dev, " Endpoint: %d, %s\n", + dwc2_hcd_get_ep_num(&urb->pipe_info), + dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); + + switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { + case USB_ENDPOINT_XFER_CONTROL: + pipetype = "CONTROL"; + break; + case USB_ENDPOINT_XFER_BULK: + pipetype = "BULK"; + break; + default: + pipetype = "UNKNOWN"; + break; + } + + dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype); + + switch (chan->speed) { + case USB_SPEED_HIGH: + speed = "HIGH"; + break; + case USB_SPEED_FULL: + speed = "FULL"; + break; + case USB_SPEED_LOW: + speed = "LOW"; + break; + default: + speed = "UNKNOWN"; + break; + } + + dev_err(hsotg->dev, " Speed: %s\n", speed); + + dev_err(hsotg->dev, " Max packet size: %d\n", + dwc2_hcd_get_mps(&urb->pipe_info)); + dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length); + dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", + urb->buf, (unsigned long)urb->dma); + dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", + urb->setup_packet, (unsigned long)urb->setup_dma); + dev_err(hsotg->dev, " Interval: %d\n", urb->interval); + + /* Core halts the channel for Descriptor DMA mode */ + /* if (hsotg->params.dma_desc_enable) { + dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, + DWC2_HC_XFER_AHB_ERR); + goto handle_ahberr_done; + } */ + + dwc2_host_complete(hsotg, qtd, -EIO); + +handle_ahberr_halt: + /* + * Force a channel halt. Don't call dwc2_halt_channel because that won't + * write to the HCCHARn register in DMA mode to force the halt. + */ + dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR); + +//handle_ahberr_done: + disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR); + + (void)pipetype; + (void)speed; + (void)hcchar; + (void)hcsplt; + (void)hctsiz; + (void)hc_dma; +} + +/* + * Handles a host channel transaction error interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + dev_dbg(hsotg->dev, + "--Host Channel %d Interrupt: Transaction Error--\n", chnum); + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + + /* if (hsotg->params.dma_desc_enable) { + dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, + DWC2_HC_XFER_XACT_ERR); + goto handle_xacterr_done; + } */ + + switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + qtd->error_count++; + if (!chan->qh->ping_state) { + dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, + qtd, DWC2_HC_XFER_XACT_ERR); + dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); + if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH) + chan->qh->ping_state = 1; + } + + /* + * Halt the channel so the transfer can be re-started from + * the appropriate point or the PING protocol will start + */ + dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); + break; + } + +//handle_xacterr_done: + disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR); +} + +/* + * Handles a host channel frame overrun interrupt. This handler may be called + * in either DMA mode or Slave mode. + */ +static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + if (dbg_hc(chan)) + dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n", + chnum); + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + + switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + break; + } + + disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN); +} + +/* + * Handles a host channel data toggle error interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + dev_dbg(hsotg->dev, + "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum); + + if (chan->ep_is_in) + qtd->error_count = 0; + else + dev_err(hsotg->dev, + "Data Toggle Error on OUT transfer, channel %d\n", + chnum); + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR); +} + +/* + * For debug only. It checks that a valid halt status is set and that + * HCCHARn.chdis is clear. If there's a problem, corrective action is + * taken and a warning is issued. + * + * Return: true if halt status is ok, false otherwise + */ +static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ +#ifdef DEBUG + u32 hcchar; + u32 hctsiz; + u32 hcintmsk; + u32 hcsplt; + + if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) { + /* + * This code is here only as a check. This condition should + * never happen. Ignore the halt if it does occur. + */ + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); + dev_dbg(hsotg->dev, + "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", + __func__); + dev_dbg(hsotg->dev, + "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n", + chnum, hcchar, hctsiz); + dev_dbg(hsotg->dev, + "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n", + chan->hcint, hcintmsk, hcsplt); + if (qtd) + dev_dbg(hsotg->dev, "qtd->complete_split %d\n", + qtd->complete_split); + dev_warn(hsotg->dev, + "%s: no halt status, channel %d, ignoring interrupt\n", + __func__, chnum); + return false; + } + + /* + * This code is here only as a check. hcchar.chdis should never be set + * when the halt interrupt occurs. Halt the channel again if it does + * occur. + */ + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); + if (hcchar & HCCHAR_CHDIS) { + dev_warn(hsotg->dev, + "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", + __func__, hcchar); + chan->halt_pending = 0; + dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status); + return false; + } +#endif + + return true; +} + +/* + * Handles a host channel Channel Halted interrupt + * + * In slave mode, this handler is called only when the driver specifically + * requests a halt. This occurs during handling other host channel interrupts + * (e.g. nak, xacterr, stall, nyet, etc.). + * + * In DMA mode, this is the interrupt that occurs when the core has finished + * processing a transfer on a channel. Other host channel interrupts (except + * ahberr) are disabled in DMA mode. + */ +static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg, + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) +{ + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n", + chnum); + + if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd)) + return; + dwc2_release_channel(hsotg, chan, qtd, chan->halt_status); +} + +/* + * Check if the given qtd is still the top of the list (and thus valid). + * + * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed + * the qtd from the top of the list, this will return false (otherwise true). + */ +static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh) +{ + struct dwc2_qtd *cur_head; + + if (!qh) + return false; + + /*cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd, + qtd_list_entry);*/ + cur_head = list_first_entry(&qh->qtd_list); + return (cur_head == qtd); +} + +/* Handles interrupt for a specific Host Channel */ +static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) +{ + struct dwc2_qtd *qtd; + struct dwc2_host_chan *chan; + u32 hcint, hcintmsk; + + chan = hsotg->hc_ptr_array[chnum]; + + hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); + hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + if (!chan) { + dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); + dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + return; + } + + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n", + chnum); + dev_vdbg(hsotg->dev, + " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", + hcint, hcintmsk, hcint & hcintmsk); + } + + dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + + /* + * If we got an interrupt after someone called + * dwc2_hcd_endpoint_disable() we don't want to crash below + */ + if (!chan->qh) { + dev_warn(hsotg->dev, "Interrupt on disabled channel\n"); + return; + } + + chan->hcint = hcint; + hcint &= hcintmsk; + + /* + * If the channel was halted due to a dequeue, the qtd list might + * be empty or at least the first entry will not be the active qtd. + * In this case, take a shortcut and just release the channel. + */ + if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { + /* + * If the channel was halted, this should be the only + * interrupt unmasked + */ + WARN_ON(hcint != HCINTMSK_CHHLTD); + if (0/*hsotg->params.dma_desc_enable*/) + ;/* dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, + chan->halt_status); */ + else + dwc2_release_channel(hsotg, chan, NULL, + chan->halt_status); + return; + } + + if (list_empty(&chan->qh->qtd_list)) { + /* + * TODO: Will this ever happen with the + * DWC2_HC_XFER_URB_DEQUEUE handling above? + */ + dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n", + chnum); + dev_dbg(hsotg->dev, + " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", + chan->hcint, hcintmsk, hcint); + chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; + disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD); + chan->hcint = 0; + return; + } + + /*qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd, + qtd_list_entry);*/ + qtd = list_first_entry(&chan->qh->qtd_list); + + if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD) + hcint &= ~HCINTMSK_CHHLTD; + + if (hcint & HCINTMSK_XFERCOMPL) { + dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); + /* + * If NYET occurred at same time as Xfer Complete, the NYET is + * handled by the Xfer Complete interrupt handler. Don't want + * to call the NYET interrupt handler in this case. + */ + hcint &= ~HCINTMSK_NYET; + } + + if (hcint & HCINTMSK_CHHLTD) { + dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_AHBERR) { + dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_STALL) { + dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_NAK) { + dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_ACK) { + dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_NYET) { + dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_XACTERR) { + dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_BBLERR) { + dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_FRMOVRUN) { + dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + if (hcint & HCINTMSK_DATATGLERR) { + dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd); + if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) + goto exit; + } + +exit: + chan->hcint = 0; +} + +/* + * This interrupt indicates that one or more host channels has a pending + * interrupt. There are multiple conditions that can cause each host channel + * interrupt. This function determines which conditions have occurred for each + * host channel interrupt and handles them appropriately. + */ +static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) +{ + u32 haint; + int i; + struct dwc2_host_chan *chan;//, *chan_tmp; + + haint = dwc2_readl(hsotg->regs + HAINT); + if (dbg_perio()) { + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint); + } + + /* + * According to USB 2.0 spec section 11.18.8, a host must + * issue complete-split transactions in a microframe for a + * set of full-/low-speed endpoints in the same relative + * order as the start-splits were issued in a microframe for. + */ + /*list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order, + split_order_list_entry) {*/ + ListItem_t *pxListItem, *nListItem; + list_for_each_entry_safe(pxListItem, nListItem, chan, &hsotg->split_order) { + int hc_num = chan->hc_num; + + if (haint & (1 << hc_num)) { + dwc2_hc_n_intr(hsotg, hc_num); + haint &= ~(1 << hc_num); + } + } + + for (i = 0; i < hsotg->params.host_channels; i++) { + if (haint & (1 << i)) + dwc2_hc_n_intr(hsotg, i); + } +} + +/* This function handles interrupts for the HCD */ +irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) +{ + u32 gintsts, dbg_gintsts; + irqreturn_t retval = IRQ_NONE; + + if (!dwc2_is_controller_alive(hsotg)) { + dev_warn(hsotg->dev, "Controller is dead\n"); + return retval; + } + + /* Check if HOST Mode */ + if (dwc2_is_host_mode(hsotg)) { + gintsts = dwc2_read_core_intr(hsotg); + if (!gintsts) { + spin_unlock(&hsotg->lock); + return retval; + } + + retval = IRQ_HANDLED; + + dbg_gintsts = gintsts; +#ifndef DEBUG_SOF + dbg_gintsts &= ~GINTSTS_SOF; +#endif + if (!dbg_perio()) + dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL | + GINTSTS_PTXFEMP); + + /* Only print if there are any non-suppressed interrupts left */ + if (dbg_gintsts) + dev_vdbg(hsotg->dev, + "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", + gintsts); + + if (gintsts & GINTSTS_SOF) + dwc2_sof_intr(hsotg); + if (gintsts & GINTSTS_RXFLVL) + dwc2_rx_fifo_level_intr(hsotg); + if (gintsts & GINTSTS_NPTXFEMP) + dwc2_np_tx_fifo_empty_intr(hsotg); + if (gintsts & GINTSTS_PRTINT) + dwc2_port_intr(hsotg); + if (gintsts & GINTSTS_HCHINT) + dwc2_hc_intr(hsotg); + + if (dbg_gintsts) { + dev_vdbg(hsotg->dev, + "DWC OTG HCD Finished Servicing Interrupts\n"); + dev_vdbg(hsotg->dev, + "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", + dwc2_readl(hsotg->regs + GINTSTS), + dwc2_readl(hsotg->regs + GINTMSK)); + } + } + + return retval; +} diff --git a/A58-STEPLDR/Src/usb/hcd_queue.c b/A58-STEPLDR/Src/usb/hcd_queue.c new file mode 100644 index 00000000..f7f8cec8 --- /dev/null +++ b/A58-STEPLDR/Src/usb/hcd_queue.c @@ -0,0 +1,429 @@ +/* + * hcd_queue.c - DesignWare HS OTG Controller host queuing routines + * + * Copyright (C) 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file contains the functions to manage Queue Heads and Queue + * Transfer Descriptors for Host mode + */ +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include + +#include "core.h" +#include "hcd.h" + +/* Wait this long before releasing periodic reservation */ +#define DWC2_UNRESERVE_DELAY (5) + +#define swap(a, b) do {unsigned long tmp = (a); (a) = (b); (b) = tmp;} while(0) +unsigned long gcd(unsigned long a, unsigned long b) +{ + unsigned long r = a | b; + + if (!a || !b) + return r; + + /* Isolate lsbit of r */ + r &= -r; + + while (!(b & r)) + b >>= 1; + if (b == r) + return r; + + for (;;) { + while (!(a & r)) + a >>= 1; + if (a == r) + return r; + if (a == b) + return a; + + if (a < b) + swap(a, b); + a -= b; + a >>= 1; + if (a & r) + a += b; + a >>= 1; + } +} + +/** + * dwc2_do_unreserve() - Actually release the periodic reservation + * + * This function actually releases the periodic bandwidth that was reserved + * by the given qh. + * + * @hsotg: The HCD state structure for the DWC OTG controller + * @qh: QH for the periodic transfer. + */ +static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) +{ + assert_spin_locked(&hsotg->lock); + + WARN_ON(!qh->unreserve_pending); + + /* No more unreserve pending--we're doing it */ + qh->unreserve_pending = false; + if (!list_item_empty(&qh->qh_list_entry)) { + WARN_ON(!list_item_empty(&qh->qh_list_entry)); + list_del_init(&qh->qh_list_entry); + } +} + +/** + * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation + * + * According to the kernel doc for usb_submit_urb() (specifically the part about + * "Reserved Bandwidth Transfers"), we need to keep a reservation active as + * long as a device driver keeps submitting. Since we're using HCD_BH to give + * back the URB we need to give the driver a little bit of time before we + * release the reservation. This worker is called after the appropriate + * delay. + * + * @work: Pointer to a qh unreserve_work. + */ +/* static void dwc2_unreserve_timer_fn(unsigned long data) +{ +} */ + + +/** + * dwc2_qh_init() - Initializes a QH structure + * + * @hsotg: The HCD state structure for the DWC OTG controller + * @qh: The QH to init + * @urb: Holds the information about the device/endpoint needed to initialize + * the QH + * @mem_flags: Flags for allocating memory. + */ +static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, + struct dwc2_hcd_urb *urb, gfp_t mem_flags) +{ + int dev_speed = dwc2_host_get_speed(hsotg, urb->priv); + u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); + bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info); + u32 hprt = dwc2_readl(hsotg->regs + HPRT0); + u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED && + dev_speed != USB_SPEED_HIGH); + int maxp = dwc2_hcd_get_mps(&urb->pipe_info); + int bytecount = dwc2_hb_mult(maxp) * dwc2_max_packet(maxp); + char *speed, *type; + + /* Initialize QH */ + qh->hsotg = hsotg; + qh->ep_type = ep_type; + qh->ep_is_in = ep_is_in; + + qh->data_toggle = DWC2_HC_PID_DATA0; + qh->maxp = maxp; + INIT_LIST_HEAD(&qh->qtd_list); + INIT_LIST_ITEM(&qh->qh_list_entry); + qh->qh_list_entry.pvOwner = (void *)qh; + qh->do_split = do_split; + qh->dev_speed = dev_speed; + + switch (dev_speed) { + case USB_SPEED_LOW: + speed = "low"; + break; + case USB_SPEED_FULL: + speed = "full"; + break; + case USB_SPEED_HIGH: + speed = "high"; + break; + default: + speed = "?"; + break; + } + + switch (qh->ep_type) { + case USB_ENDPOINT_XFER_CONTROL: + type = "control"; + break; + case USB_ENDPOINT_XFER_BULK: + type = "bulk"; + break; + default: + type = "?"; + break; + } + + USB_UNUSED(bytecount); + USB_UNUSED(speed); + USB_UNUSED(type); + dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type, + speed, bytecount); + dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh, + dwc2_hcd_get_dev_addr(&urb->pipe_info), + dwc2_hcd_get_ep_num(&urb->pipe_info), + ep_is_in ? "IN" : "OUT"); +} + +/** + * dwc2_hcd_qh_create() - Allocates and initializes a QH + * + * @hsotg: The HCD state structure for the DWC OTG controller + * @urb: Holds the information about the device/endpoint needed + * to initialize the QH + * @atomic_alloc: Flag to do atomic allocation if needed + * + * Return: Pointer to the newly allocated QH, or NULL on error + */ +struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, + struct dwc2_hcd_urb *urb, + gfp_t mem_flags) +{ + struct dwc2_qh *qh; + + if (!urb->priv) + return NULL; + + /* Allocate memory */ + qh = (struct dwc2_qh *)kzalloc(sizeof(*qh), mem_flags); + if (!qh) + return NULL; + + dwc2_qh_init(hsotg, qh, urb, mem_flags); + + /* if (hsotg->params.dma_desc_enable && + dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { + dwc2_hcd_qh_free(hsotg, qh); + return NULL; + } */ + + return qh; +} + +/** + * dwc2_hcd_qh_free() - Frees the QH + * + * @hsotg: HCD instance + * @qh: The QH to free + * + * QH should already be removed from the list. QTD list should already be empty + * if called from URB Dequeue. + * + * Must NOT be called with interrupt disabled or spinlock held + */ +void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) +{ + /* Make sure any unreserve work is finished. */ + if (0) { + unsigned long flags; + + spin_lock_irqsave(&hsotg->lock, flags); + dwc2_do_unreserve(hsotg, qh); + spin_unlock_irqrestore(&hsotg->lock, flags); + } + dwc2_host_put_tt_info(hsotg, qh->dwc_tt); + + kfree(qh); +} + +/** + * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic + * schedule if it is not already in the schedule. If the QH is already in + * the schedule, no action is taken. + * + * @hsotg: The HCD state structure for the DWC OTG controller + * @qh: The QH to add + * + * Return: 0 if successful, negative error code otherwise + */ +int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) +{ + u32 intr_mask; + + if (dbg_qh(qh)) + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + if (!list_item_empty(&qh->qh_list_entry)) + /* QH already in a schedule */ + return 0; + + /* Add the new QH to the appropriate schedule */ + if (dwc2_qh_is_non_per(qh)) { + /* Schedule right away */ + qh->start_active_frame = hsotg->frame_number; + qh->next_active_frame = qh->start_active_frame; + + /* Always start in inactive schedule */ + list_add_tail(&qh->qh_list_entry, + &hsotg->non_periodic_sched_inactive); + return 0; + } + + intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask |= GINTSTS_SOF; + dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + + return 0; +} + +/** + * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic + * schedule. Memory is not freed. + * + * @hsotg: The HCD state structure + * @qh: QH to remove from schedule + */ +void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) +{ + u32 intr_mask; + + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + if (list_item_empty(&qh->qh_list_entry)) + /* QH is not in a schedule */ + return; + + if (dwc2_qh_is_non_per(qh)) { + if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) { + hsotg->non_periodic_qh_ptr = listGET_NEXT(hsotg->non_periodic_qh_ptr); + } + list_del_init(&qh->qh_list_entry); + return; + } + + intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask &= ~GINTSTS_SOF; + dwc2_writel(intr_mask, hsotg->regs + GINTMSK); +} + +/* + * Deactivates a QH. For non-periodic QHs, removes the QH from the active + * non-periodic schedule. The QH is added to the inactive non-periodic + * schedule if any QTDs are still attached to the QH. + * + * For periodic QHs, the QH is removed from the periodic queued schedule. If + * there are any QTDs still attached to the QH, the QH is added to either the + * periodic inactive schedule or the periodic ready schedule and its next + * scheduled frame is calculated. The QH is placed in the ready schedule if + * the scheduled frame has been reached already. Otherwise it's placed in the + * inactive schedule. If there are no QTDs attached to the QH, the QH is + * completely removed from the periodic schedule. + */ +void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, + int sched_next_periodic_split) +{ + u16 old_frame = qh->next_active_frame; + + dev_vdbg(hsotg->dev, "%s() ep_type:%d\n", __func__, qh->ep_type); + + USB_UNUSED(old_frame); + + if (dbg_qh(qh)) + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + if (dwc2_qh_is_non_per(qh)) { + dwc2_hcd_qh_unlink(hsotg, qh); + if (!list_empty(&qh->qtd_list)) + /* Add back to inactive non-periodic schedule */ + dwc2_hcd_qh_add(hsotg, qh); + return; + } +} + +/** + * dwc2_hcd_qtd_init() - Initializes a QTD structure + * + * @qtd: The QTD to initialize + * @urb: The associated URB + */ +void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) +{ + qtd->urb = urb; + if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == + USB_ENDPOINT_XFER_CONTROL) { + /* + * The only time the QTD data toggle is used is on the data + * phase of control transfers. This phase always starts with + * DATA1. + */ + qtd->data_toggle = DWC2_HC_PID_DATA1; + qtd->control_phase = DWC2_CONTROL_SETUP; + } + + /* Start split */ + qtd->complete_split = 0; + qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; + qtd->in_process = 0; + + /* Store the qtd ptr in the urb to reference the QTD */ + urb->qtd = qtd; +} + +/** + * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH + * Caller must hold driver lock. + * + * @hsotg: The DWC HCD structure + * @qtd: The QTD to add + * @qh: Queue head to add qtd to + * + * Return: 0 if successful, negative error code otherwise + * + * If the QH to which the QTD is added is not currently scheduled, it is placed + * into the proper schedule based on its EP type. + */ +int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, + struct dwc2_qh *qh) +{ + int retval; + + if (unlikely(!qh)) { + dev_err(hsotg->dev, "%s: Invalid QH\n", __func__); + retval = -EINVAL; + goto fail; + } + + retval = dwc2_hcd_qh_add(hsotg, qh); + if (retval) + goto fail; + + qtd->qh = qh; + list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); + + return 0; +fail: + return retval; +} diff --git a/A58-STEPLDR/Src/usb/hw.h b/A58-STEPLDR/Src/usb/hw.h new file mode 100644 index 00000000..b96aa379 --- /dev/null +++ b/A58-STEPLDR/Src/usb/hw.h @@ -0,0 +1,867 @@ +/* + * hw.h - DesignWare HS OTG Controller hardware definitions + * + * Copyright 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DWC2_HW_H__ +#define __DWC2_HW_H__ + +#define HSOTG_REG(x) (x) + +#define GOTGCTL HSOTG_REG(0x000) +#define GOTGCTL_CHIRPEN BIT(27) +#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) +#define GOTGCTL_MULT_VALID_BC_SHIFT 22 +#define GOTGCTL_OTGVER BIT(20) +#define GOTGCTL_BSESVLD BIT(19) +#define GOTGCTL_ASESVLD BIT(18) +#define GOTGCTL_DBNC_SHORT BIT(17) +#define GOTGCTL_CONID_B BIT(16) +#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15) +#define GOTGCTL_DEVHNPEN BIT(11) +#define GOTGCTL_HSTSETHNPEN BIT(10) +#define GOTGCTL_HNPREQ BIT(9) +#define GOTGCTL_HSTNEGSCS BIT(8) +#define GOTGCTL_SESREQ BIT(1) +#define GOTGCTL_SESREQSCS BIT(0) + +#define GOTGINT HSOTG_REG(0x004) +#define GOTGINT_DBNCE_DONE BIT(19) +#define GOTGINT_A_DEV_TOUT_CHG BIT(18) +#define GOTGINT_HST_NEG_DET BIT(17) +#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9) +#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8) +#define GOTGINT_SES_END_DET BIT(2) + +#define GAHBCFG HSOTG_REG(0x008) +#define GAHBCFG_AHB_SINGLE BIT(23) +#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22) +#define GAHBCFG_REM_MEM_SUPP BIT(21) +#define GAHBCFG_P_TXF_EMP_LVL BIT(8) +#define GAHBCFG_NP_TXF_EMP_LVL BIT(7) +#define GAHBCFG_DMA_EN BIT(5) +#define GAHBCFG_HBSTLEN_MASK (0xf << 1) +#define GAHBCFG_HBSTLEN_SHIFT 1 +#define GAHBCFG_HBSTLEN_SINGLE 0 +#define GAHBCFG_HBSTLEN_INCR 1 +#define GAHBCFG_HBSTLEN_INCR4 3 +#define GAHBCFG_HBSTLEN_INCR8 5 +#define GAHBCFG_HBSTLEN_INCR16 7 +#define GAHBCFG_GLBL_INTR_EN BIT(0) +#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ + GAHBCFG_NP_TXF_EMP_LVL | \ + GAHBCFG_DMA_EN | \ + GAHBCFG_GLBL_INTR_EN) + +#define GUSBCFG HSOTG_REG(0x00C) +#define GUSBCFG_FORCEDEVMODE BIT(30) +#define GUSBCFG_FORCEHOSTMODE BIT(29) +#define GUSBCFG_TXENDDELAY BIT(28) +#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27) +#define GUSBCFG_ICUSBCAP BIT(26) +#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25) +#define GUSBCFG_INDICATORPASSTHROUGH BIT(24) +#define GUSBCFG_INDICATORCOMPLEMENT BIT(23) +#define GUSBCFG_TERMSELDLPULSE BIT(22) +#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21) +#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) +#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19) +#define GUSBCFG_ULPI_AUTO_RES BIT(18) +#define GUSBCFG_ULPI_FS_LS BIT(17) +#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16) +#define GUSBCFG_PHY_LP_CLK_SEL BIT(15) +#define GUSBCFG_USBTRDTIM_MASK (0xf << 10) +#define GUSBCFG_USBTRDTIM_SHIFT 10 +#define GUSBCFG_HNPCAP BIT(9) +#define GUSBCFG_SRPCAP BIT(8) +#define GUSBCFG_DDRSEL BIT(7) +#define GUSBCFG_PHYSEL BIT(6) +#define GUSBCFG_FSINTF BIT(5) +#define GUSBCFG_ULPI_UTMI_SEL BIT(4) +#define GUSBCFG_PHYIF16 BIT(3) +#define GUSBCFG_PHYIF8 (0 << 3) +#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) +#define GUSBCFG_TOUTCAL_SHIFT 0 +#define GUSBCFG_TOUTCAL_LIMIT 0x7 +#define GUSBCFG_TOUTCAL(_x) ((_x) << 0) + +#define GRSTCTL HSOTG_REG(0x010) +#define GRSTCTL_AHBIDLE BIT(31) +#define GRSTCTL_DMAREQ BIT(30) +#define GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define GRSTCTL_TXFNUM_SHIFT 6 +#define GRSTCTL_TXFNUM_LIMIT 0x1f +#define GRSTCTL_TXFNUM(_x) ((_x) << 6) +#define GRSTCTL_TXFFLSH BIT(5) +#define GRSTCTL_RXFFLSH BIT(4) +#define GRSTCTL_IN_TKNQ_FLSH BIT(3) +#define GRSTCTL_FRMCNTRRST BIT(2) +#define GRSTCTL_HSFTRST BIT(1) +#define GRSTCTL_CSFTRST BIT(0) + +#define GINTSTS HSOTG_REG(0x014) +#define GINTMSK HSOTG_REG(0x018) +#define GINTSTS_WKUPINT BIT(31) +#define GINTSTS_SESSREQINT BIT(30) +#define GINTSTS_DISCONNINT BIT(29) +#define GINTSTS_CONIDSTSCHNG BIT(28) +#define GINTSTS_LPMTRANRCVD BIT(27) +#define GINTSTS_PTXFEMP BIT(26) +#define GINTSTS_HCHINT BIT(25) +#define GINTSTS_PRTINT BIT(24) +#define GINTSTS_RESETDET BIT(23) +#define GINTSTS_FET_SUSP BIT(22) +#define GINTSTS_INCOMPL_IP BIT(21) +#define GINTSTS_INCOMPL_SOOUT BIT(21) +#define GINTSTS_INCOMPL_SOIN BIT(20) +#define GINTSTS_OEPINT BIT(19) +#define GINTSTS_IEPINT BIT(18) +#define GINTSTS_EPMIS BIT(17) +#define GINTSTS_RESTOREDONE BIT(16) +#define GINTSTS_EOPF BIT(15) +#define GINTSTS_ISOUTDROP BIT(14) +#define GINTSTS_ENUMDONE BIT(13) +#define GINTSTS_USBRST BIT(12) +#define GINTSTS_USBSUSP BIT(11) +#define GINTSTS_ERLYSUSP BIT(10) +#define GINTSTS_I2CINT BIT(9) +#define GINTSTS_ULPI_CK_INT BIT(8) +#define GINTSTS_GOUTNAKEFF BIT(7) +#define GINTSTS_GINNAKEFF BIT(6) +#define GINTSTS_NPTXFEMP BIT(5) +#define GINTSTS_RXFLVL BIT(4) +#define GINTSTS_SOF BIT(3) +#define GINTSTS_OTGINT BIT(2) +#define GINTSTS_MODEMIS BIT(1) +#define GINTSTS_CURMODE_HOST BIT(0) + +#define GRXSTSR HSOTG_REG(0x01C) +#define GRXSTSP HSOTG_REG(0x020) +#define GRXSTS_FN_MASK (0x7f << 25) +#define GRXSTS_FN_SHIFT 25 +#define GRXSTS_PKTSTS_MASK (0xf << 17) +#define GRXSTS_PKTSTS_SHIFT 17 +#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 +#define GRXSTS_PKTSTS_OUTRX 2 +#define GRXSTS_PKTSTS_HCHIN 2 +#define GRXSTS_PKTSTS_OUTDONE 3 +#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 +#define GRXSTS_PKTSTS_SETUPDONE 4 +#define GRXSTS_PKTSTS_DATATOGGLEERR 5 +#define GRXSTS_PKTSTS_SETUPRX 6 +#define GRXSTS_PKTSTS_HCHHALTED 7 +#define GRXSTS_HCHNUM_MASK (0xf << 0) +#define GRXSTS_HCHNUM_SHIFT 0 +#define GRXSTS_DPID_MASK (0x3 << 15) +#define GRXSTS_DPID_SHIFT 15 +#define GRXSTS_BYTECNT_MASK (0x7ff << 4) +#define GRXSTS_BYTECNT_SHIFT 4 +#define GRXSTS_EPNUM_MASK (0xf << 0) +#define GRXSTS_EPNUM_SHIFT 0 + +#define GRXFSIZ HSOTG_REG(0x024) +#define GRXFSIZ_DEPTH_MASK (0xffff << 0) +#define GRXFSIZ_DEPTH_SHIFT 0 + +#define GNPTXFSIZ HSOTG_REG(0x028) +/* Use FIFOSIZE_* constants to access this register */ + +#define GNPTXSTS HSOTG_REG(0x02C) +#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) +#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24 +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16) +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16 +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff) +#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0) +#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0 +#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) + +#define GI2CCTL HSOTG_REG(0x0030) +#define GI2CCTL_BSYDNE BIT(31) +#define GI2CCTL_RW BIT(30) +#define GI2CCTL_I2CDATSE0 BIT(28) +#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) +#define GI2CCTL_I2CDEVADDR_SHIFT 26 +#define GI2CCTL_I2CSUSPCTL BIT(25) +#define GI2CCTL_ACK BIT(24) +#define GI2CCTL_I2CEN BIT(23) +#define GI2CCTL_ADDR_MASK (0x7f << 16) +#define GI2CCTL_ADDR_SHIFT 16 +#define GI2CCTL_REGADDR_MASK (0xff << 8) +#define GI2CCTL_REGADDR_SHIFT 8 +#define GI2CCTL_RWDATA_MASK (0xff << 0) +#define GI2CCTL_RWDATA_SHIFT 0 + +#define GPVNDCTL HSOTG_REG(0x0034) +#define GGPIO HSOTG_REG(0x0038) +#define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16) + +#define GUID HSOTG_REG(0x003c) +#define GSNPSID HSOTG_REG(0x0040) +#define GHWCFG1 HSOTG_REG(0x0044) + +#define GHWCFG2 HSOTG_REG(0x0048) +#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31) +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 +#define GHWCFG2_MULTI_PROC_INT BIT(20) +#define GHWCFG2_DYNAMIC_FIFO BIT(19) +#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18) +#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) +#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 +#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) +#define GHWCFG2_NUM_DEV_EP_SHIFT 10 +#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) +#define GHWCFG2_FS_PHY_TYPE_SHIFT 8 +#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 +#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 +#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 +#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 +#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) +#define GHWCFG2_HS_PHY_TYPE_SHIFT 6 +#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 +#define GHWCFG2_HS_PHY_TYPE_UTMI 1 +#define GHWCFG2_HS_PHY_TYPE_ULPI 2 +#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 +#define GHWCFG2_POINT2POINT BIT(5) +#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) +#define GHWCFG2_ARCHITECTURE_SHIFT 3 +#define GHWCFG2_SLAVE_ONLY_ARCH 0 +#define GHWCFG2_EXT_DMA_ARCH 1 +#define GHWCFG2_INT_DMA_ARCH 2 +#define GHWCFG2_OP_MODE_MASK (0x7 << 0) +#define GHWCFG2_OP_MODE_SHIFT 0 +#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 +#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 +#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 +#define GHWCFG2_OP_MODE_UNDEFINED 7 + +#define GHWCFG3 HSOTG_REG(0x004c) +#define GHWCFG3_DFIFO_DEPTH_MASK (0xffffUL << 16) +#define GHWCFG3_DFIFO_DEPTH_SHIFT 16 +#define GHWCFG3_OTG_LPM_EN BIT(15) +#define GHWCFG3_BC_SUPPORT BIT(14) +#define GHWCFG3_OTG_ENABLE_HSIC BIT(13) +#define GHWCFG3_ADP_SUPP BIT(12) +#define GHWCFG3_SYNCH_RESET_TYPE BIT(11) +#define GHWCFG3_OPTIONAL_FEATURES BIT(10) +#define GHWCFG3_VENDOR_CTRL_IF BIT(9) +#define GHWCFG3_I2C BIT(8) +#define GHWCFG3_OTG_FUNC BIT(7) +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 + +#define GHWCFG4 HSOTG_REG(0x0050) +#define GHWCFG4_DESC_DMA_DYN BIT(31) +#define GHWCFG4_DESC_DMA BIT(30) +#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) +#define GHWCFG4_NUM_IN_EPS_SHIFT 26 +#define GHWCFG4_DED_FIFO_EN BIT(25) +#define GHWCFG4_DED_FIFO_SHIFT 25 +#define GHWCFG4_SESSION_END_FILT_EN BIT(24) +#define GHWCFG4_B_VALID_FILT_EN BIT(23) +#define GHWCFG4_A_VALID_FILT_EN BIT(22) +#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) +#define GHWCFG4_IDDIG_FILT_EN BIT(20) +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 +#define GHWCFG4_XHIBER BIT(7) +#define GHWCFG4_HIBER BIT(6) +#define GHWCFG4_MIN_AHB_FREQ BIT(5) +#define GHWCFG4_POWER_OPTIMIZ BIT(4) +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 + +#define GLPMCFG HSOTG_REG(0x0054) +#define GLPMCFG_INV_SEL_HSIC BIT(31) +#define GLPMCFG_HSIC_CONNECT BIT(30) +#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25) +#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25 +#define GLPMCFG_SEND_LPM BIT(24) +#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21) +#define GLPMCFG_RETRY_COUNT_SHIFT 21 +#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17) +#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17 +#define GLPMCFG_SLEEP_STATE_RESUMEOK BIT(16) +#define GLPMCFG_PRT_SLEEP_STS BIT(15) +#define GLPMCFG_LPM_RESP_MASK (0x3 << 13) +#define GLPMCFG_LPM_RESP_SHIFT 13 +#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) +#define GLPMCFG_HIRD_THRES_SHIFT 8 +#define GLPMCFG_HIRD_THRES_EN (0x10 << 8) +#define GLPMCFG_EN_UTMI_SLEEP BIT(7) +#define GLPMCFG_REM_WKUP_EN BIT(6) +#define GLPMCFG_HIRD_MASK (0xf << 2) +#define GLPMCFG_HIRD_SHIFT 2 +#define GLPMCFG_APPL_RESP BIT(1) +#define GLPMCFG_LPM_CAP_EN BIT(0) + +#define GPWRDN HSOTG_REG(0x0058) +#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) +#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 +#define GPWRDN_ADP_INT BIT(23) +#define GPWRDN_BSESSVLD BIT(22) +#define GPWRDN_IDSTS BIT(21) +#define GPWRDN_LINESTATE_MASK (0x3 << 19) +#define GPWRDN_LINESTATE_SHIFT 19 +#define GPWRDN_STS_CHGINT_MSK BIT(18) +#define GPWRDN_STS_CHGINT BIT(17) +#define GPWRDN_SRP_DET_MSK BIT(16) +#define GPWRDN_SRP_DET BIT(15) +#define GPWRDN_CONNECT_DET_MSK BIT(14) +#define GPWRDN_CONNECT_DET BIT(13) +#define GPWRDN_DISCONN_DET_MSK BIT(12) +#define GPWRDN_DISCONN_DET BIT(11) +#define GPWRDN_RST_DET_MSK BIT(10) +#define GPWRDN_RST_DET BIT(9) +#define GPWRDN_LNSTSCHG_MSK BIT(8) +#define GPWRDN_LNSTSCHG BIT(7) +#define GPWRDN_DIS_VBUS BIT(6) +#define GPWRDN_PWRDNSWTCH BIT(5) +#define GPWRDN_PWRDNRSTN BIT(4) +#define GPWRDN_PWRDNCLMP BIT(3) +#define GPWRDN_RESTORE BIT(2) +#define GPWRDN_PMUACTV BIT(1) +#define GPWRDN_PMUINTSEL BIT(0) + +#define GDFIFOCFG HSOTG_REG(0x005c) +#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) +#define GDFIFOCFG_EPINFOBASE_SHIFT 16 +#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) +#define GDFIFOCFG_GDFIFOCFG_SHIFT 0 + +#define ADPCTL HSOTG_REG(0x0060) +#define ADPCTL_AR_MASK (0x3 << 27) +#define ADPCTL_AR_SHIFT 27 +#define ADPCTL_ADP_TMOUT_INT_MSK BIT(26) +#define ADPCTL_ADP_SNS_INT_MSK BIT(25) +#define ADPCTL_ADP_PRB_INT_MSK BIT(24) +#define ADPCTL_ADP_TMOUT_INT BIT(23) +#define ADPCTL_ADP_SNS_INT BIT(22) +#define ADPCTL_ADP_PRB_INT BIT(21) +#define ADPCTL_ADPENA BIT(20) +#define ADPCTL_ADPRES BIT(19) +#define ADPCTL_ENASNS BIT(18) +#define ADPCTL_ENAPRB BIT(17) +#define ADPCTL_RTIM_MASK (0x7ff << 6) +#define ADPCTL_RTIM_SHIFT 6 +#define ADPCTL_PRB_PER_MASK (0x3 << 4) +#define ADPCTL_PRB_PER_SHIFT 4 +#define ADPCTL_PRB_DELTA_MASK (0x3 << 2) +#define ADPCTL_PRB_DELTA_SHIFT 2 +#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) +#define ADPCTL_PRB_DSCHRG_SHIFT 0 + +#define HPTXFSIZ HSOTG_REG(0x100) +/* Use FIFOSIZE_* constants to access this register */ + +#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) +/* Use FIFOSIZE_* constants to access this register */ + +/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */ +#define FIFOSIZE_DEPTH_MASK (0xffffUL << 16) +#define FIFOSIZE_DEPTH_SHIFT 16 +#define FIFOSIZE_STARTADDR_MASK (0xffff << 0) +#define FIFOSIZE_STARTADDR_SHIFT 0 +#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) + +/* Device mode registers */ + +#define DCFG HSOTG_REG(0x800) +#define DCFG_DESCDMA_EN BIT(23) +#define DCFG_EPMISCNT_MASK (0x1f << 18) +#define DCFG_EPMISCNT_SHIFT 18 +#define DCFG_EPMISCNT_LIMIT 0x1f +#define DCFG_EPMISCNT(_x) ((_x) << 18) +#define DCFG_PERFRINT_MASK (0x3 << 11) +#define DCFG_PERFRINT_SHIFT 11 +#define DCFG_PERFRINT_LIMIT 0x3 +#define DCFG_PERFRINT(_x) ((_x) << 11) +#define DCFG_DEVADDR_MASK (0x7f << 4) +#define DCFG_DEVADDR_SHIFT 4 +#define DCFG_DEVADDR_LIMIT 0x7f +#define DCFG_DEVADDR(_x) ((_x) << 4) +#define DCFG_NZ_STS_OUT_HSHK BIT(2) +#define DCFG_DEVSPD_MASK (0x3 << 0) +#define DCFG_DEVSPD_SHIFT 0 +#define DCFG_DEVSPD_HS 0 +#define DCFG_DEVSPD_FS 1 +#define DCFG_DEVSPD_LS 2 +#define DCFG_DEVSPD_FS48 3 + +#define DCTL HSOTG_REG(0x804) +#define DCTL_PWRONPRGDONE BIT(11) +#define DCTL_CGOUTNAK BIT(10) +#define DCTL_SGOUTNAK BIT(9) +#define DCTL_CGNPINNAK BIT(8) +#define DCTL_SGNPINNAK BIT(7) +#define DCTL_TSTCTL_MASK (0x7 << 4) +#define DCTL_TSTCTL_SHIFT 4 +#define DCTL_GOUTNAKSTS BIT(3) +#define DCTL_GNPINNAKSTS BIT(2) +#define DCTL_SFTDISCON BIT(1) +#define DCTL_RMTWKUPSIG BIT(0) + +#define DSTS HSOTG_REG(0x808) +#define DSTS_SOFFN_MASK (0x3fff << 8) +#define DSTS_SOFFN_SHIFT 8 +#define DSTS_SOFFN_LIMIT 0x3fff +#define DSTS_SOFFN(_x) ((_x) << 8) +#define DSTS_ERRATICERR BIT(3) +#define DSTS_ENUMSPD_MASK (0x3 << 1) +#define DSTS_ENUMSPD_SHIFT 1 +#define DSTS_ENUMSPD_HS 0 +#define DSTS_ENUMSPD_FS 1 +#define DSTS_ENUMSPD_LS 2 +#define DSTS_ENUMSPD_FS48 3 +#define DSTS_SUSPSTS BIT(0) + +#define DIEPMSK HSOTG_REG(0x810) +#define DIEPMSK_NAKMSK BIT(13) +#define DIEPMSK_BNAININTRMSK BIT(9) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(8) +#define DIEPMSK_TXFIFOEMPTY BIT(7) +#define DIEPMSK_INEPNAKEFFMSK BIT(6) +#define DIEPMSK_INTKNEPMISMSK BIT(5) +#define DIEPMSK_INTKNTXFEMPMSK BIT(4) +#define DIEPMSK_TIMEOUTMSK BIT(3) +#define DIEPMSK_AHBERRMSK BIT(2) +#define DIEPMSK_EPDISBLDMSK BIT(1) +#define DIEPMSK_XFERCOMPLMSK BIT(0) + +#define DOEPMSK HSOTG_REG(0x814) +#define DOEPMSK_BNAMSK BIT(9) +#define DOEPMSK_BACK2BACKSETUP BIT(6) +#define DOEPMSK_STSPHSERCVDMSK BIT(5) +#define DOEPMSK_OUTTKNEPDISMSK BIT(4) +#define DOEPMSK_SETUPMSK BIT(3) +#define DOEPMSK_AHBERRMSK BIT(2) +#define DOEPMSK_EPDISBLDMSK BIT(1) +#define DOEPMSK_XFERCOMPLMSK BIT(0) + +#define DAINT HSOTG_REG(0x818) +#define DAINTMSK HSOTG_REG(0x81C) +#define DAINT_OUTEP_SHIFT 16 +#define DAINT_OUTEP(_x) (1 << ((_x) + 16)) +#define DAINT_INEP(_x) (1 << (_x)) + +#define DTKNQR1 HSOTG_REG(0x820) +#define DTKNQR2 HSOTG_REG(0x824) +#define DTKNQR3 HSOTG_REG(0x830) +#define DTKNQR4 HSOTG_REG(0x834) +#define DIEPEMPMSK HSOTG_REG(0x834) + +#define DVBUSDIS HSOTG_REG(0x828) +#define DVBUSPULSE HSOTG_REG(0x82C) + +#define DIEPCTL0 HSOTG_REG(0x900) +#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) + +#define DOEPCTL0 HSOTG_REG(0xB00) +#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) + +/* EP0 specialness: + * bits[29..28] - reserved (no SetD0PID, SetD1PID) + * bits[25..22] - should always be zero, this isn't a periodic endpoint + * bits[10..0] - MPS setting different for EP0 + */ +#define D0EPCTL_MPS_MASK (0x3 << 0) +#define D0EPCTL_MPS_SHIFT 0 +#define D0EPCTL_MPS_64 0 +#define D0EPCTL_MPS_32 1 +#define D0EPCTL_MPS_16 2 +#define D0EPCTL_MPS_8 3 + +#define DXEPCTL_EPENA BIT(31) +#define DXEPCTL_EPDIS BIT(30) +#define DXEPCTL_SETD1PID BIT(29) +#define DXEPCTL_SETODDFR BIT(29) +#define DXEPCTL_SETD0PID BIT(28) +#define DXEPCTL_SETEVENFR BIT(28) +#define DXEPCTL_SNAK BIT(27) +#define DXEPCTL_CNAK BIT(26) +#define DXEPCTL_TXFNUM_MASK (0xf << 22) +#define DXEPCTL_TXFNUM_SHIFT 22 +#define DXEPCTL_TXFNUM_LIMIT 0xf +#define DXEPCTL_TXFNUM(_x) ((_x) << 22) +#define DXEPCTL_STALL BIT(21) +#define DXEPCTL_SNP BIT(20) +#define DXEPCTL_EPTYPE_MASK (0x3 << 18) +#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) +#define DXEPCTL_EPTYPE_ISO (0x1 << 18) +#define DXEPCTL_EPTYPE_BULK (0x2 << 18) +#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) + +#define DXEPCTL_NAKSTS BIT(17) +#define DXEPCTL_DPID BIT(16) +#define DXEPCTL_EOFRNUM BIT(16) +#define DXEPCTL_USBACTEP BIT(15) +#define DXEPCTL_NEXTEP_MASK (0xf << 11) +#define DXEPCTL_NEXTEP_SHIFT 11 +#define DXEPCTL_NEXTEP_LIMIT 0xf +#define DXEPCTL_NEXTEP(_x) ((_x) << 11) +#define DXEPCTL_MPS_MASK (0x7ff << 0) +#define DXEPCTL_MPS_SHIFT 0 +#define DXEPCTL_MPS_LIMIT 0x7ff +#define DXEPCTL_MPS(_x) ((_x) << 0) + +#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) +#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) +#define DXEPINT_SETUP_RCVD BIT(15) +#define DXEPINT_NYETINTRPT BIT(14) +#define DXEPINT_NAKINTRPT BIT(13) +#define DXEPINT_BBLEERRINTRPT BIT(12) +#define DXEPINT_PKTDRPSTS BIT(11) +#define DXEPINT_BNAINTR BIT(9) +#define DXEPINT_TXFIFOUNDRN BIT(8) +#define DXEPINT_OUTPKTERR BIT(8) +#define DXEPINT_TXFEMP BIT(7) +#define DXEPINT_INEPNAKEFF BIT(6) +#define DXEPINT_BACK2BACKSETUP BIT(6) +#define DXEPINT_INTKNEPMIS BIT(5) +#define DXEPINT_STSPHSERCVD BIT(5) +#define DXEPINT_INTKNTXFEMP BIT(4) +#define DXEPINT_OUTTKNEPDIS BIT(4) +#define DXEPINT_TIMEOUT BIT(3) +#define DXEPINT_SETUP BIT(3) +#define DXEPINT_AHBERR BIT(2) +#define DXEPINT_EPDISBLD BIT(1) +#define DXEPINT_XFERCOMPL BIT(0) + +#define DIEPTSIZ0 HSOTG_REG(0x910) +#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) +#define DIEPTSIZ0_PKTCNT_SHIFT 19 +#define DIEPTSIZ0_PKTCNT_LIMIT 0x3 +#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19) +#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0) +#define DIEPTSIZ0_XFERSIZE_SHIFT 0 +#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f +#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0) + +#define DOEPTSIZ0 HSOTG_REG(0xB10) +#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) +#define DOEPTSIZ0_SUPCNT_SHIFT 29 +#define DOEPTSIZ0_SUPCNT_LIMIT 0x3 +#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) +#define DOEPTSIZ0_PKTCNT BIT(19) +#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) +#define DOEPTSIZ0_XFERSIZE_SHIFT 0 + +#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) +#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) +#define DXEPTSIZ_MC_MASK (0x3 << 29) +#define DXEPTSIZ_MC_SHIFT 29 +#define DXEPTSIZ_MC_LIMIT 0x3 +#define DXEPTSIZ_MC(_x) ((_x) << 29) +#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) +#define DXEPTSIZ_PKTCNT_SHIFT 19 +#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff +#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) +#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) +#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) +#define DXEPTSIZ_XFERSIZE_SHIFT 0 +#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff +#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) +#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) + +#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) +#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) + +#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) + +#define PCGCTL HSOTG_REG(0x0e00) +#define PCGCTL_IF_DEV_MODE BIT(31) +#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) +#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 +#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) +#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 +#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) +#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 +#define PCGCTL_MAX_TERMSEL BIT(19) +#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) +#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 +#define PCGCTL_PORT_POWER BIT(16) +#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) +#define PCGCTL_PRT_CLK_SEL_SHIFT 14 +#define PCGCTL_ESS_REG_RESTORED BIT(13) +#define PCGCTL_EXTND_HIBER_SWITCH BIT(12) +#define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11) +#define PCGCTL_ENBL_EXTND_HIBER BIT(10) +#define PCGCTL_RESTOREMODE BIT(9) +#define PCGCTL_RESETAFTSUSP BIT(8) +#define PCGCTL_DEEP_SLEEP BIT(7) +#define PCGCTL_PHY_IN_SLEEP BIT(6) +#define PCGCTL_ENBL_SLEEP_GATING BIT(5) +#define PCGCTL_RSTPDWNMODULE BIT(3) +#define PCGCTL_PWRCLMP BIT(2) +#define PCGCTL_GATEHCLK BIT(1) +#define PCGCTL_STOPPCLK BIT(0) + +#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) + +/* Host Mode Registers */ + +#define HCFG HSOTG_REG(0x0400) +#define HCFG_MODECHTIMEN BIT(31) +#define HCFG_PERSCHEDENA BIT(26) +#define HCFG_FRLISTEN_MASK (0x3 << 24) +#define HCFG_FRLISTEN_SHIFT 24 +#define HCFG_FRLISTEN_8 (0 << 24) +#define FRLISTEN_8_SIZE 8 +#define HCFG_FRLISTEN_16 BIT(24) +#define FRLISTEN_16_SIZE 16 +#define HCFG_FRLISTEN_32 (2 << 24) +#define FRLISTEN_32_SIZE 32 +#define HCFG_FRLISTEN_64 (3 << 24) +#define FRLISTEN_64_SIZE 64 +#define HCFG_DESCDMA BIT(23) +#define HCFG_RESVALID_MASK (0xff << 8) +#define HCFG_RESVALID_SHIFT 8 +#define HCFG_ENA32KHZ BIT(7) +#define HCFG_FSLSSUPP BIT(2) +#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) +#define HCFG_FSLSPCLKSEL_SHIFT 0 +#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 +#define HCFG_FSLSPCLKSEL_48_MHZ 1 +#define HCFG_FSLSPCLKSEL_6_MHZ 2 + +#define HFIR HSOTG_REG(0x0404) +#define HFIR_FRINT_MASK (0xffff << 0) +#define HFIR_FRINT_SHIFT 0 +#define HFIR_RLDCTRL BIT(16) + +#define HFNUM HSOTG_REG(0x0408) +#define HFNUM_FRREM_MASK (0xffffUL << 16) +#define HFNUM_FRREM_SHIFT 16 +#define HFNUM_FRNUM_MASK (0xffff << 0) +#define HFNUM_FRNUM_SHIFT 0 +#define HFNUM_MAX_FRNUM 0x3fff + +#define HPTXSTS HSOTG_REG(0x0410) +#define TXSTS_QTOP_ODD BIT(31) +#define TXSTS_QTOP_CHNEP_MASK (0xf << 27) +#define TXSTS_QTOP_CHNEP_SHIFT 27 +#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) +#define TXSTS_QTOP_TOKEN_SHIFT 25 +#define TXSTS_QTOP_TERMINATE BIT(24) +#define TXSTS_QSPCAVAIL_MASK (0xff << 16) +#define TXSTS_QSPCAVAIL_SHIFT 16 +#define TXSTS_FSPCAVAIL_MASK (0xffff << 0) +#define TXSTS_FSPCAVAIL_SHIFT 0 + +#define HAINT HSOTG_REG(0x0414) +#define HAINTMSK HSOTG_REG(0x0418) +#define HFLBADDR HSOTG_REG(0x041c) + +#define HPRT0 HSOTG_REG(0x0440) +#define HPRT0_SPD_MASK (0x3 << 17) +#define HPRT0_SPD_SHIFT 17 +#define HPRT0_SPD_HIGH_SPEED 0 +#define HPRT0_SPD_FULL_SPEED 1 +#define HPRT0_SPD_LOW_SPEED 2 +#define HPRT0_TSTCTL_MASK (0xf << 13) +#define HPRT0_TSTCTL_SHIFT 13 +#define HPRT0_PWR BIT(12) +#define HPRT0_LNSTS_MASK (0x3 << 10) +#define HPRT0_LNSTS_SHIFT 10 +#define HPRT0_RST BIT(8) +#define HPRT0_SUSP BIT(7) +#define HPRT0_RES BIT(6) +#define HPRT0_OVRCURRCHG BIT(5) +#define HPRT0_OVRCURRACT BIT(4) +#define HPRT0_ENACHG BIT(3) +#define HPRT0_ENA BIT(2) +#define HPRT0_CONNDET BIT(1) +#define HPRT0_CONNSTS BIT(0) + +#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) +#define HCCHAR_CHENA BIT(31) +#define HCCHAR_CHDIS BIT(30) +#define HCCHAR_ODDFRM BIT(29) +#define HCCHAR_DEVADDR_MASK (0x7f << 22) +#define HCCHAR_DEVADDR_SHIFT 22 +#define HCCHAR_MULTICNT_MASK (0x3 << 20) +#define HCCHAR_MULTICNT_SHIFT 20 +#define HCCHAR_EPTYPE_MASK (0x3 << 18) +#define HCCHAR_EPTYPE_SHIFT 18 +#define HCCHAR_LSPDDEV BIT(17) +#define HCCHAR_EPDIR BIT(15) +#define HCCHAR_EPNUM_MASK (0xf << 11) +#define HCCHAR_EPNUM_SHIFT 11 +#define HCCHAR_MPS_MASK (0x7ff << 0) +#define HCCHAR_MPS_SHIFT 0 + +#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) +#define HCSPLT_SPLTENA BIT(31) +#define HCSPLT_COMPSPLT BIT(16) +#define HCSPLT_XACTPOS_MASK (0x3 << 14) +#define HCSPLT_XACTPOS_SHIFT 14 +#define HCSPLT_XACTPOS_MID 0 +#define HCSPLT_XACTPOS_END 1 +#define HCSPLT_XACTPOS_BEGIN 2 +#define HCSPLT_XACTPOS_ALL 3 +#define HCSPLT_HUBADDR_MASK (0x7f << 7) +#define HCSPLT_HUBADDR_SHIFT 7 +#define HCSPLT_PRTADDR_MASK (0x7f << 0) +#define HCSPLT_PRTADDR_SHIFT 0 + +#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) +#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) +#define HCINTMSK_RESERVED14_31 (0x3ffff << 14) +#define HCINTMSK_FRM_LIST_ROLL BIT(13) +#define HCINTMSK_XCS_XACT BIT(12) +#define HCINTMSK_BNA BIT(11) +#define HCINTMSK_DATATGLERR BIT(10) +#define HCINTMSK_FRMOVRUN BIT(9) +#define HCINTMSK_BBLERR BIT(8) +#define HCINTMSK_XACTERR BIT(7) +#define HCINTMSK_NYET BIT(6) +#define HCINTMSK_ACK BIT(5) +#define HCINTMSK_NAK BIT(4) +#define HCINTMSK_STALL BIT(3) +#define HCINTMSK_AHBERR BIT(2) +#define HCINTMSK_CHHLTD BIT(1) +#define HCINTMSK_XFERCOMPL BIT(0) + +#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) +#define TSIZ_DOPNG BIT(31) +#define TSIZ_SC_MC_PID_MASK (0x3 << 29) +#define TSIZ_SC_MC_PID_SHIFT 29 +#define TSIZ_SC_MC_PID_DATA0 0 +#define TSIZ_SC_MC_PID_DATA2 1 +#define TSIZ_SC_MC_PID_DATA1 2 +#define TSIZ_SC_MC_PID_MDATA 3 +#define TSIZ_SC_MC_PID_SETUP 3 +#define TSIZ_PKTCNT_MASK (0x3ff << 19) +#define TSIZ_PKTCNT_SHIFT 19 +#define TSIZ_NTD_MASK (0xff << 8) +#define TSIZ_NTD_SHIFT 8 +#define TSIZ_SCHINFO_MASK (0xff << 0) +#define TSIZ_SCHINFO_SHIFT 0 +#define TSIZ_XFERSIZE_MASK (0x7ffff << 0) +#define TSIZ_XFERSIZE_SHIFT 0 + +#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch)) + +#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch)) + +#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch)) + +/** + * struct dwc2_dma_desc - DMA descriptor structure, + * used for both host and gadget modes + * + * @status: DMA descriptor status quadlet + * @buf: DMA descriptor data buffer pointer + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +struct dwc2_dma_desc { + u32 status; + u32 buf; +};//__packed + +/* Host Mode DMA descriptor status quadlet */ + +#define HOST_DMA_A BIT(31) +#define HOST_DMA_STS_MASK (0x3 << 28) +#define HOST_DMA_STS_SHIFT 28 +#define HOST_DMA_STS_PKTERR BIT(28) +#define HOST_DMA_EOL BIT(26) +#define HOST_DMA_IOC BIT(25) +#define HOST_DMA_SUP BIT(24) +#define HOST_DMA_ALT_QTD BIT(23) +#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) +#define HOST_DMA_QTD_OFFSET_SHIFT 17 +#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) +#define HOST_DMA_ISOC_NBYTES_SHIFT 0 +#define HOST_DMA_NBYTES_MASK (0x1ffff << 0) +#define HOST_DMA_NBYTES_SHIFT 0 +#define HOST_DMA_NBYTES_LIMIT 131071 + +/* Device Mode DMA descriptor status quadlet */ + +#define DEV_DMA_BUFF_STS_MASK (0x3 << 30) +#define DEV_DMA_BUFF_STS_SHIFT 30 +#define DEV_DMA_BUFF_STS_HREADY 0 +#define DEV_DMA_BUFF_STS_DMABUSY 1 +#define DEV_DMA_BUFF_STS_DMADONE 2 +#define DEV_DMA_BUFF_STS_HBUSY 3UL +#define DEV_DMA_STS_MASK (0x3 << 28) +#define DEV_DMA_STS_SHIFT 28 +#define DEV_DMA_STS_SUCC 0 +#define DEV_DMA_STS_BUFF_FLUSH 1 +#define DEV_DMA_STS_BUFF_ERR 3 +#define DEV_DMA_L BIT(27) +#define DEV_DMA_SHORT BIT(26) +#define DEV_DMA_IOC BIT(25) +#define DEV_DMA_SR BIT(24) +#define DEV_DMA_MTRF BIT(23) +#define DEV_DMA_ISOC_PID_MASK (0x3 << 23) +#define DEV_DMA_ISOC_PID_SHIFT 23 +#define DEV_DMA_ISOC_PID_DATA0 0 +#define DEV_DMA_ISOC_PID_DATA2 1 +#define DEV_DMA_ISOC_PID_DATA1 2 +#define DEV_DMA_ISOC_PID_MDATA 3 +#define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12) +#define DEV_DMA_ISOC_FRNUM_SHIFT 12 +#define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0) +#define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff +#define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0) +#define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff +#define DEV_DMA_ISOC_NBYTES_SHIFT 0 +#define DEV_DMA_NBYTES_MASK (0xffff << 0) +#define DEV_DMA_NBYTES_SHIFT 0 +#define DEV_DMA_NBYTES_LIMIT 0xffff + +#define MAX_DMA_DESC_NUM_GENERIC 64 +#define MAX_DMA_DESC_NUM_HS_ISOC 256 + +#endif /* __DWC2_HW_H__ */ diff --git a/A58-STEPLDR/Src/usb/include/asm/dma-mapping.h b/A58-STEPLDR/Src/usb/include/asm/dma-mapping.h new file mode 100644 index 00000000..dbd03cde --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/asm/dma-mapping.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007 + * Stelian Pop + * Lead Tech Design + */ +#ifndef __ASM_ARM_DMA_MAPPING_H +#define __ASM_ARM_DMA_MAPPING_H + +#include + +#define dma_mapping_error(x, y) 0 +struct device; + +static inline void *dma_alloc_coherent(struct device *dev, size_t len, dma_addr_t *handle, gfp_t flag) +{ + (void)flag; + //*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + *handle = (unsigned long)malloc(len + ARCH_DMA_MINALIGN); + return (void *)*handle; +} + +static inline void dma_free_coherent(struct device *dev, size_t size, void *addr, dma_addr_t handle) +{ + free(addr); +} + +static inline void *dmam_alloc_coherent(struct device *dev, size_t len, dma_addr_t *handle, gfp_t flag) +{ + (void)flag; + (void)dev; + *handle = (dma_addr_t)malloc(len + ARCH_DMA_MINALIGN); + return (void *)*handle; +} + +static inline void dmam_free_coherent(struct device *dev, size_t len, void *vaddr, dma_addr_t handle) +{ + free(vaddr); +} + + + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + return (unsigned long)vaddr; +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ +} + +static inline void dma_sync_single_for_device(struct device *dev, + dma_addr_t addr, size_t size, enum dma_data_direction dir) +{ +} + +static inline void dma_sync_single_for_cpu(struct device *dev, + dma_addr_t addr, size_t size, enum dma_data_direction dir) +{ +} + + +#endif /* __ASM_ARM_DMA_MAPPING_H */ diff --git a/A58-STEPLDR/Src/usb/include/linux/dma-direction.h b/A58-STEPLDR/Src/usb/include/linux/dma-direction.h new file mode 100644 index 00000000..95b6a82f --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/linux/dma-direction.h @@ -0,0 +1,13 @@ +#ifndef _LINUX_DMA_DIRECTION_H +#define _LINUX_DMA_DIRECTION_H +/* + * These definitions mirror those in pci.h, so they can be used + * interchangeably with their PCI_ counterparts. + */ +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, + DMA_NONE = 3, +}; +#endif diff --git a/A58-STEPLDR/Src/usb/include/linux/errno.h b/A58-STEPLDR/Src/usb/include/linux/errno.h new file mode 100644 index 00000000..3d94207d --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/linux/errno.h @@ -0,0 +1,168 @@ +#ifndef _LINUX_ERRNO_H +#define _LINUX_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ + +#define ENOSYS 38 /* Invalid system call number */ + +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ +#define ECANCELED 125 /* Operation Canceled */ +#define ENOKEY 126 /* Required key not available */ +#define EKEYEXPIRED 127 /* Key has expired */ +#define EKEYREVOKED 128 /* Key has been revoked */ +#define EKEYREJECTED 129 /* Key was rejected by service */ + +/* for robust mutexes */ +#define EOWNERDEAD 130 /* Owner died */ +#define ENOTRECOVERABLE 131 /* State not recoverable */ + +#define ERFKILL 132 /* Operation not possible due to RF-kill */ + +#define EHWPOISON 133 /* Memory page has hardware error */ + +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ +#define ERESTART_RESTARTBLOCK 516 /* restart by calling sys_restart_syscall */ +#define EPROBE_DEFER 517 /* Driver requests probe retry */ +#define EOPENSTALE 518 /* open found a stale dentry */ + +/* Defined for the NFSv3 protocol */ +#define EBADHANDLE 521 /* Illegal NFS file handle */ +#define ENOTSYNC 522 /* Update synchronization mismatch */ +#define EBADCOOKIE 523 /* Cookie is stale */ +#define ENOTSUPP 524 /* Operation is not supported */ +#define ETOOSMALL 525 /* Buffer or request is too small */ +#define ESERVERFAULT 526 /* An untranslatable error occurred */ +#define EBADTYPE 527 /* Type not supported by server */ +#define EJUKEBOX 528 /* Request initiated, but will not complete before timeout */ +#define EIOCBQUEUED 529 /* iocb queued, will get completion event */ +#define ERECALLCONFLICT 530 /* conflict with recalled state */ + +#endif diff --git a/A58-STEPLDR/Src/usb/include/linux/usb/ch9.h b/A58-STEPLDR/Src/usb/include/linux/usb/ch9.h new file mode 100644 index 00000000..c2d18a28 --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/linux/usb/ch9.h @@ -0,0 +1,981 @@ +/* + * This file holds USB constants and structures that are needed for + * USB device APIs. These are used by the USB device model, which is + * defined in chapter 9 of the USB 2.0 specification and in the + * Wireless USB 1.0 (spread around). Linux has several APIs in C that + * need these: + * + * - the master/host side Linux-USB kernel driver API; + * - the "usbfs" user space API; and + * - the Linux "gadget" slave/device/peripheral side driver API. + * + * USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems + * act either as a USB master/host or as a USB slave/device. That means + * the master and slave side APIs benefit from working well together. + * + * There's also "Wireless USB", using low power short range radios for + * peripheral interconnection but otherwise building on the USB framework. + * + * Note all descriptors are declared '__attribute__((packed))' so that: + * + * [a] they never get padded, either internally (USB spec writers + * probably handled that) or externally; + * + * [b] so that accessing bigger-than-a-bytes fields will never + * generate bus errors on any platform, even when the location of + * its descriptor inside a bundle isn't "naturally aligned", and + * + * [c] for consistency, removing all doubt even when it appears to + * someone that the two other points are non-issues for that + * particular descriptor type. + */ + +#ifndef __LINUX_USB_CH9_H +#define __LINUX_USB_CH9_H + +//#include /* __u8 etc */ + +/*-------------------------------------------------------------------------*/ + +/* CONTROL REQUEST SUPPORT */ + +/* + * USB directions + * + * This bit flag is used in endpoint descriptors' bEndpointAddress field. + * It's also one of three fields in control requests bRequestType. + */ +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ + +/* + * USB types, the second of three bRequestType fields + */ +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* + * USB recipients, the third of three bRequestType fields + */ +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 +/* From Wireless USB 1.0 */ +#define USB_RECIP_PORT 0x04 +#define USB_RECIP_RPIPE 0x05 + +/* + * Standard requests, for the bRequest field of a SETUP packet. + * + * These are qualified by the bRequestType field, so that for example + * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved + * by a GET_STATUS request. + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_SET_SEL 0x30 +#define USB_REQ_SET_ISOCH_DELAY 0x31 + +#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */ +#define USB_REQ_GET_ENCRYPTION 0x0E +#define USB_REQ_RPIPE_ABORT 0x0E +#define USB_REQ_SET_HANDSHAKE 0x0F +#define USB_REQ_RPIPE_RESET 0x0F +#define USB_REQ_GET_HANDSHAKE 0x10 +#define USB_REQ_SET_CONNECTION 0x11 +#define USB_REQ_SET_SECURITY_DATA 0x12 +#define USB_REQ_GET_SECURITY_DATA 0x13 +#define USB_REQ_SET_WUSB_DATA 0x14 +#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQ_LOOPBACK_DATA_READ 0x16 +#define USB_REQ_SET_INTERFACE_DS 0x17 + +/* The Link Power Management (LPM) ECN defines USB_REQ_TEST_AND_SET command, + * used by hubs to put ports into a new L1 suspend state, except that it + * forgot to define its number ... + */ + +/* + * USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and + * are read as a bit array returned by USB_REQ_GET_STATUS. (So there + * are at most sixteen features of each type.) Hubs may also support a + * new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend. + */ +#define USB_DEVICE_SELF_POWERED 0 /* (read only) */ +#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */ +#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */ +#define USB_DEVICE_BATTERY 2 /* (wireless) */ +#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */ +#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/ +#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */ +#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */ +#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */ + +/* + * Test Mode Selectors + * See USB 2.0 spec Table 9-7 + */ +#define TEST_J 1 +#define TEST_K 2 +#define TEST_SE0_NAK 3 +#define TEST_PACKET 4 +#define TEST_FORCE_EN 5 + +/* + * New Feature Selectors as added by USB 3.0 + * See USB 3.0 spec Table 9-6 + */ +#define USB_DEVICE_U1_ENABLE 48 /* dev may initiate U1 transition */ +#define USB_DEVICE_U2_ENABLE 49 /* dev may initiate U2 transition */ +#define USB_DEVICE_LTM_ENABLE 50 /* dev may send LTM */ +#define USB_INTRF_FUNC_SUSPEND 0 /* function suspend */ + +#define USB_INTR_FUNC_SUSPEND_OPT_MASK 0xFF00 +/* + * Suspend Options, Table 9-7 USB 3.0 spec + */ +#define USB_INTRF_FUNC_SUSPEND_LP (1 << (8 + 0)) +#define USB_INTRF_FUNC_SUSPEND_RW (1 << (8 + 1)) + +#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */ + +/* Bit array elements as returned by the USB_REQ_GET_STATUS request. */ +#define USB_DEV_STAT_U1_ENABLED 2 /* transition into U1 state */ +#define USB_DEV_STAT_U2_ENABLED 3 /* transition into U2 state */ +#define USB_DEV_STAT_LTM_ENABLED 4 /* Latency tolerance messages */ + +/** + * struct usb_ctrlrequest - SETUP data for a USB device control request + * @bRequestType: matches the USB bmRequestType field + * @bRequest: matches the USB bRequest field + * @wValue: matches the USB wValue field (le16 byte order) + * @wIndex: matches the USB wIndex field (le16 byte order) + * @wLength: matches the USB wLength field (le16 byte order) + * + * This structure is used to send control requests to a USB device. It matches + * the different fields of the USB 2.0 Spec section 9.3, table 9-2. See the + * USB spec for a fuller description of the different fields, and what they are + * used for. + * + * Note that the driver for any interface can issue control requests. + * For most devices, interfaces don't coordinate with each other, so + * such requests may be made at any time. + */ +struct usb_ctrlrequest { + __u8 bRequestType; + __u8 bRequest; + __le16 wValue; + __le16 wIndex; + __le16 wLength; +} ; + +/*-------------------------------------------------------------------------*/ + +/* + * STANDARD DESCRIPTORS ... as returned by GET_DESCRIPTOR, or + * (rarely) accepted by SET_DESCRIPTOR. + * + * Note that all multi-byte values here are encoded in little endian + * byte order "on the wire". Within the kernel and when exposed + * through the Linux-USB APIs, they are not converted to cpu byte + * order; it is the responsibility of the client code to do this. + * The single exception is when device and configuration descriptors (but + * not other descriptors) are read from usbfs (i.e. /proc/bus/usb/BBB/DDD); + * in this case the fields are converted to host endianness by the kernel. + */ + +/* + * Descriptor types ... USB 2.0 spec table 9.5 + */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONFIG 0x07 +#define USB_DT_INTERFACE_POWER 0x08 +/* these are from a minor usb 2.0 revision (ECN) */ +#define USB_DT_OTG 0x09 +#define USB_DT_DEBUG 0x0a +#define USB_DT_INTERFACE_ASSOCIATION 0x0b +/* these are from the Wireless USB spec */ +#define USB_DT_SECURITY 0x0c +#define USB_DT_KEY 0x0d +#define USB_DT_ENCRYPTION_TYPE 0x0e +#define USB_DT_BOS 0x0f +#define USB_DT_DEVICE_CAPABILITY 0x10 +#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11 +#define USB_DT_WIRE_ADAPTER 0x21 +#define USB_DT_RPIPE 0x22 +#define USB_DT_CS_RADIO_CONTROL 0x23 +/* From the T10 UAS specification */ +#define USB_DT_PIPE_USAGE 0x24 +/* From the USB 3.0 spec */ +#define USB_DT_SS_ENDPOINT_COMP 0x30 +/* From HID 1.11 spec */ +#define USB_DT_HID_REPORT 0x22 + +/* Conventional codes for class-specific descriptors. The convention is + * defined in the USB "Common Class" Spec (3.11). Individual class specs + * are authoritative for their usage, not the "common class" writeup. + */ +#define USB_DT_CS_DEVICE (USB_TYPE_CLASS | USB_DT_DEVICE) +#define USB_DT_CS_CONFIG (USB_TYPE_CLASS | USB_DT_CONFIG) +#define USB_DT_CS_STRING (USB_TYPE_CLASS | USB_DT_STRING) +#define USB_DT_CS_INTERFACE (USB_TYPE_CLASS | USB_DT_INTERFACE) +#define USB_DT_CS_ENDPOINT (USB_TYPE_CLASS | USB_DT_ENDPOINT) + +/* All standard descriptors have these 2 fields at the beginning */ +struct usb_descriptor_header { + __u8 bLength; + __u8 bDescriptorType; +} ; + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE: Device descriptor */ +struct usb_device_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 bcdUSB; + __u8 bDeviceClass; + __u8 bDeviceSubClass; + __u8 bDeviceProtocol; + __u8 bMaxPacketSize0; + __le16 idVendor; + __le16 idProduct; + __le16 bcdDevice; + __u8 iManufacturer; + __u8 iProduct; + __u8 iSerialNumber; + __u8 bNumConfigurations; +} ; + +#define USB_DT_DEVICE_SIZE 18 + + +/* + * Device and/or Interface Class codes + * as found in bDeviceClass or bInterfaceClass + * and defined by www.usb.org documents + */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PHYSICAL 5 +#define USB_CLASS_STILL_IMAGE 6 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_CDC_DATA 0x0a +#define USB_CLASS_CSCID 0x0b /* chip+ smart card */ +#define USB_CLASS_CONTENT_SEC 0x0d /* content security */ +#define USB_CLASS_VIDEO 0x0e +#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 +#define USB_CLASS_MISC 0xef +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff + +#define USB_SUBCLASS_VENDOR_SPEC 0xff + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_CONFIG: Configuration descriptor information. + * + * USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the + * descriptor type is different. Highspeed-capable devices can look + * different depending on what speed they're currently running. Only + * devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG + * descriptors. + */ +struct usb_config_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wTotalLength; + __u8 bNumInterfaces; + __u8 bConfigurationValue; + __u8 iConfiguration; + __u8 bmAttributes; + __u8 bMaxPower; +} ; + +#define USB_DT_CONFIG_SIZE 9 + +/* from config descriptor bmAttributes */ +#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */ +#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */ +#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */ +#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_STRING: String descriptor */ +struct usb_string_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wData[1]; /* UTF-16LE encoded */ +} ; + +/* note that "string" zero is special, it holds language codes that + * the device supports, not Unicode characters. + */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE: Interface descriptor */ +struct usb_interface_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bInterfaceNumber; + __u8 bAlternateSetting; + __u8 bNumEndpoints; + __u8 bInterfaceClass; + __u8 bInterfaceSubClass; + __u8 bInterfaceProtocol; + __u8 iInterface; +} ; + +#define USB_DT_INTERFACE_SIZE 9 + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENDPOINT: Endpoint descriptor */ +struct usb_endpoint_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bEndpointAddress; + __u8 bmAttributes; + __le16 wMaxPacketSize; + __u8 bInterval; + + /* NOTE: these two are _only_ in audio endpoints. */ + /* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */ + __u8 bRefresh; + __u8 bSynchAddress; +} ; + +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ + +/* Used to access common fields */ +struct usb_generic_descriptor { + __u8 bLength; + __u8 bDescriptorType; +}; + +struct usb_class_hid_descriptor { + u8 bLength; + u8 bDescriptorType; + u16 bcdCDC; + u8 bCountryCode; + u8 bNumDescriptors; /* 0x01 */ + u8 bDescriptorType0; + u16 wDescriptorLength0; + /* optional descriptors are not supported. */ +}; + +struct usb_class_report_descriptor { + u8 bLength; /* dummy */ + u8 bDescriptorType; + u16 wLength; + u8 bData[0]; +}; + +/* + * Endpoints + */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 +#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80 + +#define USB_ENDPOINT_MAXP_MASK 0x07ff +#define USB_EP_MAXP_MULT_SHIFT 11 +#define USB_EP_MAXP_MULT_MASK (3 << USB_EP_MAXP_MULT_SHIFT) +#define USB_EP_MAXP_MULT(m) \ + (((m) & USB_EP_MAXP_MULT_MASK) >> USB_EP_MAXP_MULT_SHIFT) + +/* The USB 3.0 spec redefines bits 5:4 of bmAttributes as interrupt ep type. */ +#define USB_ENDPOINT_INTRTYPE 0x30 +#define USB_ENDPOINT_INTR_PERIODIC (0 << 4) +#define USB_ENDPOINT_INTR_NOTIFICATION (1 << 4) + +#define USB_ENDPOINT_SYNCTYPE 0x0c +#define USB_ENDPOINT_SYNC_NONE (0 << 2) +#define USB_ENDPOINT_SYNC_ASYNC (1 << 2) +#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << 2) +#define USB_ENDPOINT_SYNC_SYNC (3 << 2) + +#define USB_ENDPOINT_USAGE_MASK 0x30 +#define USB_ENDPOINT_USAGE_DATA 0x00 +#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 +#define USB_ENDPOINT_USAGE_IMPLICIT_FB 0x20 /* Implicit feedback Data endpoint */ + +/*-------------------------------------------------------------------------*/ + +/** + * usb_endpoint_num - get the endpoint's number + * @epd: endpoint to be checked + * + * Returns @epd's number: 0 to 15. + */ +static inline int usb_endpoint_num(const struct usb_endpoint_descriptor *epd) +{ + return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; +} + +/** + * usb_endpoint_type - get the endpoint's transfer type + * @epd: endpoint to be checked + * + * Returns one of USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT} according + * to @epd's transfer type. + */ +static inline int usb_endpoint_type(const struct usb_endpoint_descriptor *epd) +{ + return epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; +} + +/** + * usb_endpoint_dir_in - check if the endpoint has IN direction + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type IN, otherwise it returns false. + */ +static inline int usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN); +} + +/** + * usb_endpoint_dir_out - check if the endpoint has OUT direction + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type OUT, otherwise it returns false. + */ +static inline int usb_endpoint_dir_out( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT); +} + +/** + * usb_endpoint_xfer_bulk - check if the endpoint has bulk transfer type + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type bulk, otherwise it returns false. + */ +static inline int usb_endpoint_xfer_bulk( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_BULK); +} + +/** + * usb_endpoint_xfer_control - check if the endpoint has control transfer type + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type control, otherwise it returns false. + */ +static inline int usb_endpoint_xfer_control( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_CONTROL); +} + +/** + * usb_endpoint_is_bulk_in - check if the endpoint is bulk IN + * @epd: endpoint to be checked + * + * Returns true if the endpoint has bulk transfer type and IN direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_bulk_in( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_in(epd); +} + +/** + * usb_endpoint_is_bulk_out - check if the endpoint is bulk OUT + * @epd: endpoint to be checked + * + * Returns true if the endpoint has bulk transfer type and OUT direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_bulk_out( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_out(epd); +} + +/** + * usb_endpoint_maxp - get endpoint's max packet size + * @epd: endpoint to be checked + * + * Returns @epd's max packet + */ +static inline int usb_endpoint_maxp(const struct usb_endpoint_descriptor *epd) +{ + return __le16_to_cpu(get_unaligned(&epd->wMaxPacketSize)); +} + +/** + * usb_endpoint_maxp_mult - get endpoint's transactional opportunities + * @epd: endpoint to be checked + * + * Return @epd's wMaxPacketSize[12:11] + 1 + */ +static inline int +usb_endpoint_maxp_mult(const struct usb_endpoint_descriptor *epd) +{ + int maxp = __le16_to_cpu(epd->wMaxPacketSize); + + return USB_EP_MAXP_MULT(maxp) + 1; +} + +static inline int usb_endpoint_interrupt_type( + const struct usb_endpoint_descriptor *epd) +{ + return epd->bmAttributes & USB_ENDPOINT_INTRTYPE; +} + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_SS_ENDPOINT_COMP: SuperSpeed Endpoint Companion descriptor */ +struct usb_ss_ep_comp_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bMaxBurst; + __u8 bmAttributes; + __le16 wBytesPerInterval; +} ; + +#define USB_DT_SS_EP_COMP_SIZE 6 + +/* Bits 4:0 of bmAttributes if this is a bulk endpoint */ +static inline int +usb_ss_max_streams(const struct usb_ss_ep_comp_descriptor *comp) +{ + int max_streams; + + if (!comp) + return 0; + + max_streams = comp->bmAttributes & 0x1f; + + if (!max_streams) + return 0; + + max_streams = 1 << max_streams; + + return max_streams; +} + +/* Bits 1:0 of bmAttributes if this is an isoc endpoint */ +#define USB_SS_MULT(p) (1 + ((p) & 0x3)) + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */ +struct usb_qualifier_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 bcdUSB; + __u8 bDeviceClass; + __u8 bDeviceSubClass; + __u8 bDeviceProtocol; + __u8 bMaxPacketSize0; + __u8 bNumConfigurations; + __u8 bRESERVED; +} ; + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_OTG (from OTG 1.0a supplement) */ +struct usb_otg_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bmAttributes; /* support for HNP, SRP, etc */ +} ; + +/* from usb_otg_descriptor.bmAttributes */ +#define USB_OTG_SRP (1 << 0) +#define USB_OTG_HNP (1 << 1) /* swap host/device roles */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEBUG: for special highspeed devices, replacing serial console */ +struct usb_debug_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + /* bulk endpoints with 8 byte maxpacket */ + __u8 bDebugInEndpoint; + __u8 bDebugOutEndpoint; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE_ASSOCIATION: groups interfaces */ +struct usb_interface_assoc_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bFirstInterface; + __u8 bInterfaceCount; + __u8 bFunctionClass; + __u8 bFunctionSubClass; + __u8 bFunctionProtocol; + __u8 iFunction; +} ; + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_SECURITY: group of wireless security descriptors, including + * encryption types available for setting up a CC/association. + */ +struct usb_security_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wTotalLength; + __u8 bNumEncryptionTypes; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_KEY: used with {GET,SET}_SECURITY_DATA; only public keys + * may be retrieved. + */ +struct usb_key_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 tTKID[3]; + __u8 bReserved; + __u8 bKeyData[0]; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENCRYPTION_TYPE: bundled in DT_SECURITY groups */ +struct usb_encryption_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bEncryptionType; +#define USB_ENC_TYPE_UNSECURE 0 +#define USB_ENC_TYPE_WIRED 1 /* non-wireless mode */ +#define USB_ENC_TYPE_CCM_1 2 /* aes128/cbc session */ +#define USB_ENC_TYPE_RSA_1 3 /* rsa3072/sha1 auth */ + __u8 bEncryptionValue; /* use in SET_ENCRYPTION */ + __u8 bAuthKeyIndex; +}; + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_BOS: group of device-level capabilities */ +struct usb_bos_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wTotalLength; + __u8 bNumDeviceCaps; +}; + +#define USB_DT_BOS_SIZE 5 +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE_CAPABILITY: grouped with BOS */ +struct usb_dev_cap_header { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; +}; + +#define USB_CAP_TYPE_WIRELESS_USB 1 + +struct usb_wireless_cap_descriptor { /* Ultra Wide Band */ + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; + + __u8 bmAttributes; +#define USB_WIRELESS_P2P_DRD (1 << 1) +#define USB_WIRELESS_BEACON_MASK (3 << 2) +#define USB_WIRELESS_BEACON_SELF (1 << 2) +#define USB_WIRELESS_BEACON_DIRECTED (2 << 2) +#define USB_WIRELESS_BEACON_NONE (3 << 2) + __le16 wPHYRates; /* bit rates, Mbps */ +#define USB_WIRELESS_PHY_53 (1 << 0) /* always set */ +#define USB_WIRELESS_PHY_80 (1 << 1) +#define USB_WIRELESS_PHY_107 (1 << 2) /* always set */ +#define USB_WIRELESS_PHY_160 (1 << 3) +#define USB_WIRELESS_PHY_200 (1 << 4) /* always set */ +#define USB_WIRELESS_PHY_320 (1 << 5) +#define USB_WIRELESS_PHY_400 (1 << 6) +#define USB_WIRELESS_PHY_480 (1 << 7) + __u8 bmTFITXPowerInfo; /* TFI power levels */ + __u8 bmFFITXPowerInfo; /* FFI power levels */ + __le16 bmBandGroup; + __u8 bReserved; +}; + +/* USB 2.0 Extension descriptor */ +#define USB_CAP_TYPE_EXT 2 + +struct usb_ext_cap_descriptor { /* Link Power Management */ + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; + __le32 bmAttributes; +#define USB_LPM_SUPPORT (1 << 1) /* supports LPM */ +#define USB_BESL_SUPPORT (1 << 2) /* supports BESL */ +#define USB_BESL_BASELINE_VALID (1 << 3) /* Baseline BESL valid*/ +#define USB_BESL_DEEP_VALID (1 << 4) /* Deep BESL valid */ +#define USB_GET_BESL_BASELINE(p) (((p) & (0xf << 8)) >> 8) +#define USB_GET_BESL_DEEP(p) (((p) & (0xf << 12)) >> 12) +}; + +#define USB_DT_USB_EXT_CAP_SIZE 7 + +/* + * SuperSpeed USB Capability descriptor: Defines the set of SuperSpeed USB + * specific device level capabilities + */ +#define USB_SS_CAP_TYPE 3 +struct usb_ss_cap_descriptor { /* Link Power Management */ + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; + __u8 bmAttributes; +#define USB_LTM_SUPPORT (1 << 1) /* supports LTM */ + __le16 wSpeedSupported; +#define USB_LOW_SPEED_OPERATION (1) /* Low speed operation */ +#define USB_FULL_SPEED_OPERATION (1 << 1) /* Full speed operation */ +#define USB_HIGH_SPEED_OPERATION (1 << 2) /* High speed operation */ +#define USB_5GBPS_OPERATION (1 << 3) /* Operation at 5Gbps */ + __u8 bFunctionalitySupport; + __u8 bU1devExitLat; + __le16 bU2DevExitLat; +}; + +#define USB_DT_USB_SS_CAP_SIZE 10 + +/* + * Container ID Capability descriptor: Defines the instance unique ID used to + * identify the instance across all operating modes + */ +#define CONTAINER_ID_TYPE 4 +struct usb_ss_container_id_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; + __u8 bReserved; + __u8 ContainerID[16]; /* 128-bit number */ +}; + +#define USB_DT_USB_SS_CONTN_ID_SIZE 20 +/*-------------------------------------------------------------------------*/ + +/* USB_DT_WIRELESS_ENDPOINT_COMP: companion descriptor associated with + * each endpoint descriptor for a wireless device + */ +struct usb_wireless_ep_comp_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bMaxBurst; + __u8 bMaxSequence; + __le16 wMaxStreamDelay; + __le16 wOverTheAirPacketSize; + __u8 bOverTheAirInterval; + __u8 bmCompAttributes; +#define USB_ENDPOINT_SWITCH_MASK 0x03 /* in bmCompAttributes */ +#define USB_ENDPOINT_SWITCH_NO 0 +#define USB_ENDPOINT_SWITCH_SWITCH 1 +#define USB_ENDPOINT_SWITCH_SCALE 2 +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_REQ_SET_HANDSHAKE is a four-way handshake used between a wireless + * host and a device for connection set up, mutual authentication, and + * exchanging short lived session keys. The handshake depends on a CC. + */ +struct usb_handshake { + __u8 bMessageNumber; + __u8 bStatus; + __u8 tTKID[3]; + __u8 bReserved; + __u8 CDID[16]; + __u8 nonce[16]; + __u8 MIC[8]; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_REQ_SET_CONNECTION modifies or revokes a connection context (CC). + * A CC may also be set up using non-wireless secure channels (including + * wired USB!), and some devices may support CCs with multiple hosts. + */ +struct usb_connection_context { + __u8 CHID[16]; /* persistent host id */ + __u8 CDID[16]; /* device id (unique w/in host context) */ + __u8 CK[16]; /* connection key */ +}; + +/*-------------------------------------------------------------------------*/ + +/* USB 2.0 defines three speeds, here's how Linux identifies them */ + +enum usb_device_speed { + USB_SPEED_UNKNOWN = 0, /* enumerating */ + USB_SPEED_LOW, USB_SPEED_FULL, /* usb 1.1 */ + USB_SPEED_HIGH, /* usb 2.0 */ + USB_SPEED_WIRELESS, /* wireless (usb 2.5) */ + USB_SPEED_SUPER, /* usb 3.0 */ +}; + +#ifdef __KERNEL__ + +/** + * usb_speed_string() - Returns human readable-name of the speed. + * @speed: The speed to return human-readable name for. If it's not + * any of the speeds defined in usb_device_speed enum, string for + * USB_SPEED_UNKNOWN will be returned. + */ +extern const char *usb_speed_string(enum usb_device_speed speed); + +#endif + +enum usb_device_state { + /* NOTATTACHED isn't in the USB spec, and this state acts + * the same as ATTACHED ... but it's clearer this way. + */ + USB_STATE_NOTATTACHED = 0, + + /* chapter 9 and authentication (wireless) device states */ + USB_STATE_ATTACHED, + USB_STATE_POWERED, /* wired */ + USB_STATE_RECONNECTING, /* auth */ + USB_STATE_UNAUTHENTICATED, /* auth */ + USB_STATE_DEFAULT, /* limited function */ + USB_STATE_ADDRESS, + USB_STATE_CONFIGURED, /* most functions */ + + USB_STATE_SUSPENDED + + /* NOTE: there are actually four different SUSPENDED + * states, returning to POWERED, DEFAULT, ADDRESS, or + * CONFIGURED respectively when SOF tokens flow again. + * At this level there's no difference between L1 and L2 + * suspend states. (L2 being original USB 1.1 suspend.) + */ +}; + +enum usb3_link_state { + USB3_LPM_U0 = 0, + USB3_LPM_U1, + USB3_LPM_U2, + USB3_LPM_U3 +}; + +/* + * A U1 timeout of 0x0 means the parent hub will reject any transitions to U1. + * 0xff means the parent hub will accept transitions to U1, but will not + * initiate a transition. + * + * A U1 timeout of 0x1 to 0x7F also causes the hub to initiate a transition to + * U1 after that many microseconds. Timeouts of 0x80 to 0xFE are reserved + * values. + * + * A U2 timeout of 0x0 means the parent hub will reject any transitions to U2. + * 0xff means the parent hub will accept transitions to U2, but will not + * initiate a transition. + * + * A U2 timeout of 0x1 to 0xFE also causes the hub to initiate a transition to + * U2 after N*256 microseconds. Therefore a U2 timeout value of 0x1 means a U2 + * idle timer of 256 microseconds, 0x2 means 512 microseconds, 0xFE means + * 65.024ms. + */ +#define USB3_LPM_DISABLED 0x0 +#define USB3_LPM_U1_MAX_TIMEOUT 0x7F +#define USB3_LPM_U2_MAX_TIMEOUT 0xFE +#define USB3_LPM_DEVICE_INITIATED 0xFF + +struct usb_set_sel_req { + __u8 u1_sel; + __u8 u1_pel; + __le16 u2_sel; + __le16 u2_pel; +} ; + +/* + * The Set System Exit Latency control transfer provides one byte each for + * U1 SEL and U1 PEL, so the max exit latency is 0xFF. U2 SEL and U2 PEL each + * are two bytes long. + */ +#define USB3_LPM_MAX_U1_SEL_PEL 0xFF +#define USB3_LPM_MAX_U2_SEL_PEL 0xFFFF + +/*-------------------------------------------------------------------------*/ + +/* + * As per USB compliance update, a device that is actively drawing + * more than 100mA from USB must report itself as bus-powered in + * the GetStatus(DEVICE) call. + * http://compliance.usb.org/index.asp?UpdateFile=Electrical&Format=Standard#34 + */ +#define USB_SELF_POWER_VBUS_MAX_DRAW 100 + +/** + * struct usb_string - wraps a C string and its USB id + * @id:the (nonzero) ID for this string + * @s:the string, in UTF-8 encoding + * + * If you're using usb_gadget_get_string(), use this to wrap a string + * together with its ID. + */ +struct usb_string { + u8 id; + const char *s; +}; + +#endif /* __LINUX_USB_CH9_H */ diff --git a/A58-STEPLDR/Src/usb/include/linux/usb/composite.h b/A58-STEPLDR/Src/usb/include/linux/usb/composite.h new file mode 100644 index 00000000..22d8899e --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/linux/usb/composite.h @@ -0,0 +1,327 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * composite.h -- framework for usb gadgets which are composite devices + * + * Copyright (C) 2006-2008 David Brownell + */ + +#ifndef __LINUX_USB_COMPOSITE_H +#define __LINUX_USB_COMPOSITE_H + +/* + * This framework is an optional layer on top of the USB Gadget interface, + * making it easier to build (a) Composite devices, supporting multiple + * functions within any single configuration, and (b) Multi-configuration + * devices, also supporting multiple functions but without necessarily + * having more than one function per configuration. + * + * Example: a device with a single configuration supporting both network + * link and mass storage functions is a composite device. Those functions + * might alternatively be packaged in individual configurations, but in + * the composite model the host can use both functions at the same time. + */ + +#include +#include +#include +#include + +/* + * USB function drivers should return USB_GADGET_DELAYED_STATUS if they + * wish to delay the data/status stages of the control transfer till they + * are ready. The control transfer will then be kept from completing till + * all the function drivers that requested for USB_GADGET_DELAYED_STAUS + * invoke usb_composite_setup_continue(). + */ +#define USB_GADGET_DELAYED_STATUS 0x7fff /* Impossibly large value */ + +struct usb_configuration; + +/** + * struct usb_function - describes one function of a configuration + * @name: For diagnostics, identifies the function. + * @strings: tables of strings, keyed by identifiers assigned during bind() + * and by language IDs provided in control requests + * @descriptors: Table of full (or low) speed descriptors, using interface and + * string identifiers assigned during @bind(). If this pointer is null, + * the function will not be available at full speed (or at low speed). + * @hs_descriptors: Table of high speed descriptors, using interface and + * string identifiers assigned during @bind(). If this pointer is null, + * the function will not be available at high speed. + * @config: assigned when @usb_add_function() is called; this is the + * configuration with which this function is associated. + * @bind: Before the gadget can register, all of its functions bind() to the + * available resources including string and interface identifiers used + * in interface or class descriptors; endpoints; I/O buffers; and so on. + * @unbind: Reverses @bind; called as a side effect of unregistering the + * driver which added this function. + * @set_alt: (REQUIRED) Reconfigures altsettings; function drivers may + * initialize usb_ep.driver data at this time (when it is used). + * Note that setting an interface to its current altsetting resets + * interface state, and that all interfaces have a disabled state. + * @get_alt: Returns the active altsetting. If this is not provided, + * then only altsetting zero is supported. + * @disable: (REQUIRED) Indicates the function should be disabled. Reasons + * include host resetting or reconfiguring the gadget, and disconnection. + * @setup: Used for interface-specific control requests. + * @suspend: Notifies functions when the host stops sending USB traffic. + * @resume: Notifies functions when the host restarts USB traffic. + * + * A single USB function uses one or more interfaces, and should in most + * cases support operation at both full and high speeds. Each function is + * associated by @usb_add_function() with a one configuration; that function + * causes @bind() to be called so resources can be allocated as part of + * setting up a gadget driver. Those resources include endpoints, which + * should be allocated using @usb_ep_autoconfig(). + * + * To support dual speed operation, a function driver provides descriptors + * for both high and full speed operation. Except in rare cases that don't + * involve bulk endpoints, each speed needs different endpoint descriptors. + * + * Function drivers choose their own strategies for managing instance data. + * The simplest strategy just declares it "static', which means the function + * can only be activated once. If the function needs to be exposed in more + * than one configuration at a given speed, it needs to support multiple + * usb_function structures (one for each configuration). + * + * A more complex strategy might encapsulate a @usb_function structure inside + * a driver-specific instance structure to allows multiple activations. An + * example of multiple activations might be a CDC ACM function that supports + * two or more distinct instances within the same configuration, providing + * several independent logical data links to a USB host. + */ +struct usb_function { + const char *name; + struct usb_descriptor_header **descriptors; + struct usb_descriptor_header **hs_descriptors; + + struct usb_configuration *config; + + /* REVISIT: bind() functions can be marked __init, which + * makes trouble for section mismatch analysis. See if + * we can't restructure things to avoid mismatching. + * Related: unbind() may kfree() but bind() won't... + */ + + /* configuration management: bind/unbind */ + int (*bind)(struct usb_configuration *, + struct usb_function *); + void (*unbind)(struct usb_configuration *, + struct usb_function *); + + /* runtime state management */ + int (*set_alt)(struct usb_function *, + unsigned interface, unsigned alt); + int (*get_alt)(struct usb_function *, + unsigned interface); + void (*disable)(struct usb_function *); + int (*setup)(struct usb_function *, + const struct usb_ctrlrequest *); + void (*suspend)(struct usb_function *); + void (*resume)(struct usb_function *); + + /* private: */ + /* internals */ + struct list_head list; + DECLARE_BITMAP(endpoints, 32); +}; + +int usb_add_function(struct usb_configuration *, struct usb_function *); + +int usb_function_deactivate(struct usb_function *); +int usb_function_activate(struct usb_function *); + +int usb_interface_id(struct usb_configuration *, struct usb_function *); + +#define MAX_CONFIG_INTERFACES 16 /* arbitrary; max 255 */ + +/** + * struct usb_configuration - represents one gadget configuration + * @label: For diagnostics, describes the configuration. + * @strings: Tables of strings, keyed by identifiers assigned during @bind() + * and by language IDs provided in control requests. + * @descriptors: Table of descriptors preceding all function descriptors. + * Examples include OTG and vendor-specific descriptors. + * @bind: Called from @usb_add_config() to allocate resources unique to this + * configuration and to call @usb_add_function() for each function used. + * @unbind: Reverses @bind; called as a side effect of unregistering the + * driver which added this configuration. + * @setup: Used to delegate control requests that aren't handled by standard + * device infrastructure or directed at a specific interface. + * @bConfigurationValue: Copied into configuration descriptor. + * @iConfiguration: Copied into configuration descriptor. + * @bmAttributes: Copied into configuration descriptor. + * @bMaxPower: Copied into configuration descriptor. + * @cdev: assigned by @usb_add_config() before calling @bind(); this is + * the device associated with this configuration. + * + * Configurations are building blocks for gadget drivers structured around + * function drivers. Simple USB gadgets require only one function and one + * configuration, and handle dual-speed hardware by always providing the same + * functionality. Slightly more complex gadgets may have more than one + * single-function configuration at a given speed; or have configurations + * that only work at one speed. + * + * Composite devices are, by definition, ones with configurations which + * include more than one function. + * + * The lifecycle of a usb_configuration includes allocation, initialization + * of the fields described above, and calling @usb_add_config() to set up + * internal data and bind it to a specific device. The configuration's + * @bind() method is then used to initialize all the functions and then + * call @usb_add_function() for them. + * + * Those functions would normally be independant of each other, but that's + * not mandatory. CDC WMC devices are an example where functions often + * depend on other functions, with some functions subsidiary to others. + * Such interdependency may be managed in any way, so long as all of the + * descriptors complete by the time the composite driver returns from + * its bind() routine. + */ +struct usb_configuration { + const char *label; + const struct usb_descriptor_header **descriptors; + + /* REVISIT: bind() functions can be marked __init, which + * makes trouble for section mismatch analysis. See if + * we can't restructure things to avoid mismatching... + */ + + /* configuration management: bind/unbind */ + int (*bind)(struct usb_configuration *); + void (*unbind)(struct usb_configuration *); + int (*setup)(struct usb_configuration *, + const struct usb_ctrlrequest *); + + /* fields in the config descriptor */ + u8 bConfigurationValue; + u8 iConfiguration; + u8 bmAttributes; + u8 bMaxPower; + + struct usb_composite_dev *cdev; + + /* private: */ + /* internals */ + struct list_head list; + struct list_head functions; + u8 next_interface_id; + unsigned highspeed:1; + unsigned fullspeed:1; + struct usb_function *interface[MAX_CONFIG_INTERFACES]; +}; + +int usb_add_config(struct usb_composite_dev *, + struct usb_configuration *); + +/** + * struct usb_composite_driver - groups configurations into a gadget + * @name: For diagnostics, identifies the driver. + * @dev: Template descriptor for the device, including default device + * identifiers. + * @strings: tables of strings, keyed by identifiers assigned during bind() + * and language IDs provided in control requests + * @bind: (REQUIRED) Used to allocate resources that are shared across the + * whole device, such as string IDs, and add its configurations using + * @usb_add_config(). This may fail by returning a negative errno + * value; it should return zero on successful initialization. + * @unbind: Reverses @bind(); called as a side effect of unregistering + * this driver. + * @disconnect: optional driver disconnect method + * @suspend: Notifies when the host stops sending USB traffic, + * after function notifications + * @resume: Notifies configuration when the host restarts USB traffic, + * before function notifications + * + * Devices default to reporting self powered operation. Devices which rely + * on bus powered operation should report this in their @bind() method. + * + * Before returning from @bind, various fields in the template descriptor + * may be overridden. These include the idVendor/idProduct/bcdDevice values + * normally to bind the appropriate host side driver, and the three strings + * (iManufacturer, iProduct, iSerialNumber) normally used to provide user + * meaningful device identifiers. (The strings will not be defined unless + * they are defined in @dev and @strings.) The correct ep0 maxpacket size + * is also reported, as defined by the underlying controller driver. + */ +struct usb_composite_driver { + const char *name; + const struct usb_device_descriptor *dev; + + /* REVISIT: bind() functions can be marked __init, which + * makes trouble for section mismatch analysis. See if + * we can't restructure things to avoid mismatching... + */ + + int (*bind)(struct usb_composite_dev *); + int (*unbind)(struct usb_composite_dev *); + + void (*disconnect)(struct usb_composite_dev *); + + /* global suspend hooks */ + void (*suspend)(struct usb_composite_dev *); + void (*resume)(struct usb_composite_dev *); +}; + +extern int usb_composite_register(struct usb_composite_driver *); +extern void usb_composite_unregister(struct usb_composite_driver *); + + +/** + * struct usb_composite_device - represents one composite usb gadget + * @gadget: read-only, abstracts the gadget's usb peripheral controller + * @req: used for control responses; buffer is pre-allocated + * @bufsiz: size of buffer pre-allocated in @req + * @config: the currently active configuration + * + * One of these devices is allocated and initialized before the + * associated device driver's bind() is called. + * + * OPEN ISSUE: it appears that some WUSB devices will need to be + * built by combining a normal (wired) gadget with a wireless one. + * This revision of the gadget framework should probably try to make + * sure doing that won't hurt too much. + * + * One notion for how to handle Wireless USB devices involves: + * (a) a second gadget here, discovery mechanism TBD, but likely + * needing separate "register/unregister WUSB gadget" calls; + * (b) updates to usb_gadget to include flags "is it wireless", + * "is it wired", plus (presumably in a wrapper structure) + * bandgroup and PHY info; + * (c) presumably a wireless_ep wrapping a usb_ep, and reporting + * wireless-specific parameters like maxburst and maxsequence; + * (d) configurations that are specific to wireless links; + * (e) function drivers that understand wireless configs and will + * support wireless for (additional) function instances; + * (f) a function to support association setup (like CBAF), not + * necessarily requiring a wireless adapter; + * (g) composite device setup that can create one or more wireless + * configs, including appropriate association setup support; + * (h) more, TBD. + */ +struct usb_composite_dev { + struct usb_request *req; + unsigned bufsiz; + + struct usb_configuration *config; + + /* private: */ + /* internals */ + unsigned int suspended:1; + struct usb_device_descriptor __aligned(CONFIG_SYS_CACHELINE_SIZE) desc; + struct list_head configs; + struct usb_composite_driver *driver; + u8 next_string_id; + + /* the gadget driver won't enable the data pullup + * while the deactivation count is nonzero. + */ + unsigned deactivations; +}; + +extern int usb_string_id(struct usb_composite_dev *c); +extern int usb_string_ids_tab(struct usb_composite_dev *c, + struct usb_string *str); +extern int usb_string_ids_n(struct usb_composite_dev *c, unsigned n); + +#endif /* __LINUX_USB_COMPOSITE_H */ diff --git a/A58-STEPLDR/Src/usb/include/linux/usb/gadget.h b/A58-STEPLDR/Src/usb/include/linux/usb/gadget.h new file mode 100644 index 00000000..ee082c16 --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/linux/usb/gadget.h @@ -0,0 +1,441 @@ +/* + * + * + * We call the USB code inside a Linux-based peripheral device a "gadget" + * driver, except for the hardware-specific bus glue. One USB host can + * master many USB gadgets, but the gadgets are only slaved to one host. + * + * + * (C) Copyright 2002-2004 by David Brownell + * All Rights Reserved. + * + * This software is licensed under the GNU GPL version 2. + * + * Ported to U-Boot by: Thomas Smits and + * Remy Bohmer + */ + +#ifndef __LINUX_USB_GADGET_H +#define __LINUX_USB_GADGET_H +/* +#include +#include +#include */ +#include "usb_os_adapter.h" +#include +#include + +struct usb_ep; + +/** + * struct usb_request - describes one i/o request + * @buf: Buffer used for data. Always provide this; some controllers + * only use PIO, or don't use DMA for some endpoints. + * @dma: DMA address corresponding to 'buf'. If you don't set this + * field, and the usb controller needs one, it is responsible + * for mapping and unmapping the buffer. + * @stream_id: The stream id, when USB3.0 bulk streams are being used + * @length: Length of that data + * @no_interrupt: If true, hints that no completion irq is needed. + * Helpful sometimes with deep request queues that are handled + * directly by DMA controllers. + * @zero: If true, when writing data, makes the last packet be "short" + * by adding a zero length packet as needed; + * @short_not_ok: When reading data, makes short packets be + * treated as errors (queue stops advancing till cleanup). + * @complete: Function called when request completes, so this request and + * its buffer may be re-used. + * Reads terminate with a short packet, or when the buffer fills, + * whichever comes first. When writes terminate, some data bytes + * will usually still be in flight (often in a hardware fifo). + * Errors (for reads or writes) stop the queue from advancing + * until the completion function returns, so that any transfers + * invalidated by the error may first be dequeued. + * @context: For use by the completion callback + * @list: For use by the gadget driver. + * @status: Reports completion code, zero or a negative errno. + * Normally, faults block the transfer queue from advancing until + * the completion callback returns. + * Code "-ESHUTDOWN" indicates completion caused by device disconnect, + * or when the driver disabled the endpoint. + * @actual: Reports bytes transferred to/from the buffer. For reads (OUT + * transfers) this may be less than the requested length. If the + * short_not_ok flag is set, short reads are treated as errors + * even when status otherwise indicates successful completion. + * Note that for writes (IN transfers) some data bytes may still + * reside in a device-side FIFO when the request is reported as + * complete. + * + * These are allocated/freed through the endpoint they're used with. The + * hardware's driver can add extra per-request data to the memory it returns, + * which often avoids separate memory allocations (potential failures), + * later when the request is queued. + * + * Request flags affect request handling, such as whether a zero length + * packet is written (the "zero" flag), whether a short read should be + * treated as an error (blocking request queue advance, the "short_not_ok" + * flag), or hinting that an interrupt is not required (the "no_interrupt" + * flag, for use with deep request queues). + * + * Bulk endpoints can use any size buffers, and can also be used for interrupt + * transfers. interrupt-only endpoints can be much less functional. + * + * NOTE: this is analagous to 'struct urb' on the host side, except that + * it's thinner and promotes more pre-allocation. + */ + +struct usb_request { + void *buf; + unsigned length; + dma_addr_t dma; + + unsigned stream_id:16; + unsigned no_interrupt:1; + unsigned zero:1; + unsigned short_not_ok:1; + + void (*complete)(struct usb_ep *ep, + struct usb_request *req); + void *context; + + ListItem_t list; + void* powner; + + int status; + unsigned actual; +}; + +/*-------------------------------------------------------------------------*/ + +/* endpoint-specific parts of the api to the usb controller hardware. + * unlike the urb model, (de)multiplexing layers are not required. + * (so this api could slash overhead if used on the host side...) + * + * note that device side usb controllers commonly differ in how many + * endpoints they support, as well as their capabilities. + */ +struct usb_ep_ops { + int (*enable) (struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc); + int (*disable) (struct usb_ep *ep); + + struct usb_request *(*alloc_request) (struct usb_ep *ep, + gfp_t gfp_flags); + void (*free_request) (struct usb_ep *ep, struct usb_request *req); + + int (*queue) (struct usb_ep *ep, struct usb_request *req, + gfp_t gfp_flags); + int (*dequeue) (struct usb_ep *ep, struct usb_request *req); + + int (*set_halt) (struct usb_ep *ep, int value); + int (*set_wedge)(struct usb_ep *ep); + int (*fifo_status) (struct usb_ep *ep); + void (*fifo_flush) (struct usb_ep *ep); +}; + +/** + * struct usb_ep - device side representation of USB endpoint + * @name:identifier for the endpoint, such as "ep-a" or "ep9in-bulk" + * @ops: Function pointers used to access hardware-specific operations. + * @ep_list:the gadget's ep_list holds all of its endpoints + * @maxpacket:The maximum packet size used on this endpoint. The initial + * value can sometimes be reduced (hardware allowing), according to + * the endpoint descriptor used to configure the endpoint. + * @maxpacket_limit:The maximum packet size value which can be handled by this + * endpoint. It's set once by UDC driver when endpoint is initialized, and + * should not be changed. Should not be confused with maxpacket. + * @max_streams: The maximum number of streams supported + * by this EP (0 - 16, actual number is 2^n) + * @maxburst: the maximum number of bursts supported by this EP (for usb3) + * @driver_data:for use by the gadget driver. all other fields are + * read-only to gadget drivers. + * @desc: endpoint descriptor. This pointer is set before the endpoint is + * enabled and remains valid until the endpoint is disabled. + * @comp_desc: In case of SuperSpeed support, this is the endpoint companion + * descriptor that is used to configure the endpoint + * + * the bus controller driver lists all the general purpose endpoints in + * gadget->ep_list. the control endpoint (gadget->ep0) is not in that list, + * and is accessed only in response to a driver setup() callback. + */ +struct usb_ep { + void *driver_data; + const char *name; + const struct usb_ep_ops *ops; + ListItem_t ep_list; + void* powner; + unsigned maxpacket:16; + unsigned maxpacket_limit:16; + unsigned max_streams:16; + unsigned maxburst:5; + const struct usb_endpoint_descriptor *desc; + const struct usb_ss_ep_comp_descriptor *comp_desc; +}; + +/*-------------------------------------------------------------------------*/ + +/** + * usb_ep_set_maxpacket_limit - set maximum packet size limit for endpoint + * @ep:the endpoint being configured + * @maxpacket_limit:value of maximum packet size limit + * + * This function shoud be used only in UDC drivers to initialize endpoint + * (usually in probe function). + */ +static inline void usb_ep_set_maxpacket_limit(struct usb_ep *ep, + unsigned maxpacket_limit) +{ + ep->maxpacket_limit = maxpacket_limit; + ep->maxpacket = maxpacket_limit; +} + +/** + * usb_ep_enable - configure endpoint, making it usable + * @ep:the endpoint being configured. may not be the endpoint named "ep0". + * drivers discover endpoints through the ep_list of a usb_gadget. + * @desc:descriptor for desired behavior. caller guarantees this pointer + * remains valid until the endpoint is disabled; the data byte order + * is little-endian (usb-standard). + * + * when configurations are set, or when interface settings change, the driver + * will enable or disable the relevant endpoints. while it is enabled, an + * endpoint may be used for i/o until the driver receives a disconnect() from + * the host or until the endpoint is disabled. + * + * the ep0 implementation (which calls this routine) must ensure that the + * hardware capabilities of each endpoint match the descriptor provided + * for it. for example, an endpoint named "ep2in-bulk" would be usable + * for interrupt transfers as well as bulk, but it likely couldn't be used + * for iso transfers or for endpoint 14. some endpoints are fully + * configurable, with more generic names like "ep-a". (remember that for + * USB, "in" means "towards the USB master".) + * + * returns zero, or a negative error code. + */ +static inline int usb_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) +{ + return ep->ops->enable(ep, desc); +} + +/** + * usb_ep_disable - endpoint is no longer usable + * @ep:the endpoint being unconfigured. may not be the endpoint named "ep0". + * + * no other task may be using this endpoint when this is called. + * any pending and uncompleted requests will complete with status + * indicating disconnect (-ESHUTDOWN) before this call returns. + * gadget drivers must call usb_ep_enable() again before queueing + * requests to the endpoint. + * + * returns zero, or a negative error code. + */ +static inline int usb_ep_disable(struct usb_ep *ep) +{ + return ep->ops->disable(ep); +} + +/** + * usb_ep_alloc_request - allocate a request object to use with this endpoint + * @ep:the endpoint to be used with with the request + * @gfp_flags:GFP_* flags to use + * + * Request objects must be allocated with this call, since they normally + * need controller-specific setup and may even need endpoint-specific + * resources such as allocation of DMA descriptors. + * Requests may be submitted with usb_ep_queue(), and receive a single + * completion callback. Free requests with usb_ep_free_request(), when + * they are no longer needed. + * + * Returns the request, or null if one could not be allocated. + */ +static inline struct usb_request *usb_ep_alloc_request(struct usb_ep *ep, + gfp_t gfp_flags) +{ + return ep->ops->alloc_request(ep, gfp_flags); +} + +/** + * usb_ep_free_request - frees a request object + * @ep:the endpoint associated with the request + * @req:the request being freed + * + * Reverses the effect of usb_ep_alloc_request(). + * Caller guarantees the request is not queued, and that it will + * no longer be requeued (or otherwise used). + */ +static inline void usb_ep_free_request(struct usb_ep *ep, + struct usb_request *req) +{ + ep->ops->free_request(ep, req); +} + +/** + * usb_ep_queue - queues (submits) an I/O request to an endpoint. + * @ep:the endpoint associated with the request + * @req:the request being submitted + * @gfp_flags: GFP_* flags to use in case the lower level driver couldn't + * pre-allocate all necessary memory with the request. + * + * This tells the device controller to perform the specified request through + * that endpoint (reading or writing a buffer). When the request completes, + * including being canceled by usb_ep_dequeue(), the request's completion + * routine is called to return the request to the driver. Any endpoint + * (except control endpoints like ep0) may have more than one transfer + * request queued; they complete in FIFO order. Once a gadget driver + * submits a request, that request may not be examined or modified until it + * is given back to that driver through the completion callback. + * + * Each request is turned into one or more packets. The controller driver + * never merges adjacent requests into the same packet. OUT transfers + * will sometimes use data that's already buffered in the hardware. + * Drivers can rely on the fact that the first byte of the request's buffer + * always corresponds to the first byte of some USB packet, for both + * IN and OUT transfers. + * + * Bulk endpoints can queue any amount of data; the transfer is packetized + * automatically. The last packet will be short if the request doesn't fill it + * out completely. Zero length packets (ZLPs) should be avoided in portable + * protocols since not all usb hardware can successfully handle zero length + * packets. (ZLPs may be explicitly written, and may be implicitly written if + * the request 'zero' flag is set.) Bulk endpoints may also be used + * for interrupt transfers; but the reverse is not true, and some endpoints + * won't support every interrupt transfer. (Such as 768 byte packets.) + * + * Interrupt-only endpoints are less functional than bulk endpoints, for + * example by not supporting queueing or not handling buffers that are + * larger than the endpoint's maxpacket size. They may also treat data + * toggle differently. + * + * Control endpoints ... after getting a setup() callback, the driver queues + * one response (even if it would be zero length). That enables the + * status ack, after transfering data as specified in the response. Setup + * functions may return negative error codes to generate protocol stalls. + * (Note that some USB device controllers disallow protocol stall responses + * in some cases.) When control responses are deferred (the response is + * written after the setup callback returns), then usb_ep_set_halt() may be + * used on ep0 to trigger protocol stalls. + * + * For periodic endpoints, like interrupt or isochronous ones, the usb host + * arranges to poll once per interval, and the gadget driver usually will + * have queued some data to transfer at that time. + * + * Returns zero, or a negative error code. Endpoints that are not enabled + * report errors; errors will also be + * reported when the usb peripheral is disconnected. + */ +static inline int usb_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags) +{ + return ep->ops->queue(ep, req, gfp_flags); +} + +/** + * usb_ep_dequeue - dequeues (cancels, unlinks) an I/O request from an endpoint + * @ep:the endpoint associated with the request + * @req:the request being canceled + * + * if the request is still active on the endpoint, it is dequeued and its + * completion routine is called (with status -ECONNRESET); else a negative + * error code is returned. + * + * note that some hardware can't clear out write fifos (to unlink the request + * at the head of the queue) except as part of disconnecting from usb. such + * restrictions prevent drivers from supporting configuration changes, + * even to configuration zero (a "chapter 9" requirement). + */ +static inline int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req) +{ + return ep->ops->dequeue(ep, req); +} + +/** + * usb_ep_set_halt - sets the endpoint halt feature. + * @ep: the non-isochronous endpoint being stalled + * + * Use this to stall an endpoint, perhaps as an error report. + * Except for control endpoints, + * the endpoint stays halted (will not stream any data) until the host + * clears this feature; drivers may need to empty the endpoint's request + * queue first, to make sure no inappropriate transfers happen. + * + * Note that while an endpoint CLEAR_FEATURE will be invisible to the + * gadget driver, a SET_INTERFACE will not be. To reset endpoints for the + * current altsetting, see usb_ep_clear_halt(). When switching altsettings, + * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints. + * + * Returns zero, or a negative error code. On success, this call sets + * underlying hardware state that blocks data transfers. + * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any + * transfer requests are still queued, or if the controller hardware + * (usually a FIFO) still holds bytes that the host hasn't collected. + */ +static inline int usb_ep_set_halt(struct usb_ep *ep) +{ + return ep->ops->set_halt(ep, 1); +} + +/** + * usb_ep_clear_halt - clears endpoint halt, and resets toggle + * @ep:the bulk or interrupt endpoint being reset + * + * Use this when responding to the standard usb "set interface" request, + * for endpoints that aren't reconfigured, after clearing any other state + * in the endpoint's i/o queue. + * + * Returns zero, or a negative error code. On success, this call clears + * the underlying hardware state reflecting endpoint halt and data toggle. + * Note that some hardware can't support this request (like pxa2xx_udc), + * and accordingly can't correctly implement interface altsettings. + */ +static inline int usb_ep_clear_halt(struct usb_ep *ep) +{ + return ep->ops->set_halt(ep, 0); +} + +/** + * usb_ep_fifo_status - returns number of bytes in fifo, or error + * @ep: the endpoint whose fifo status is being checked. + * + * FIFO endpoints may have "unclaimed data" in them in certain cases, + * such as after aborted transfers. Hosts may not have collected all + * the IN data written by the gadget driver (and reported by a request + * completion). The gadget driver may not have collected all the data + * written OUT to it by the host. Drivers that need precise handling for + * fault reporting or recovery may need to use this call. + * + * This returns the number of such bytes in the fifo, or a negative + * errno if the endpoint doesn't use a FIFO or doesn't support such + * precise handling. + */ +static inline int usb_ep_fifo_status(struct usb_ep *ep) +{ + if (ep->ops->fifo_status) + return ep->ops->fifo_status(ep); + else + return -EOPNOTSUPP; +} + +/** + * usb_ep_fifo_flush - flushes contents of a fifo + * @ep: the endpoint whose fifo is being flushed. + * + * This call may be used to flush the "unclaimed data" that may exist in + * an endpoint fifo after abnormal transaction terminations. The call + * must never be used except when endpoint is not being used for any + * protocol translation. + */ +static inline void usb_ep_fifo_flush(struct usb_ep *ep) +{ + if (ep->ops->fifo_flush) + ep->ops->fifo_flush(ep); +} + +/*-------------------------------------------------------------------------*/ + +/* utility to simplify managing config descriptors */ + +/* write vector of descriptors into buffer */ +int usb_descriptor_fillbuf(void *, unsigned, + const struct usb_descriptor_header **); +#endif /* __LINUX_USB_GADGET_H */ diff --git a/A58-STEPLDR/Src/usb/include/linux/usb/otg.h b/A58-STEPLDR/Src/usb/include/linux/usb/otg.h new file mode 100644 index 00000000..d2604c5c --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/linux/usb/otg.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* include/linux/usb/otg.h + * + * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * + * USB OTG (On The Go) defines + */ + +#ifndef __LINUX_USB_OTG_H +#define __LINUX_USB_OTG_H + +enum usb_dr_mode { + USB_DR_MODE_UNKNOWN, + USB_DR_MODE_HOST, + USB_DR_MODE_PERIPHERAL, + USB_DR_MODE_OTG, +}; + +/** + * usb_get_dr_mode() - Get dual role mode for given device + * @node: Node offset to the given device + * + * The function gets phy interface string from property 'dr_mode', + * and returns the correspondig enum usb_dr_mode + */ +enum usb_dr_mode usb_get_dr_mode(int node); + +/** + * usb_get_maximum_speed() - Get maximum speed for given device + * @node: Node offset to the given device + * + * The function gets phy interface string from property 'maximum-speed', + * and returns the correspondig enum usb_device_speed + */ +enum usb_device_speed usb_get_maximum_speed(int node); + +#endif /* __LINUX_USB_OTG_H */ diff --git a/A58-STEPLDR/Src/usb/include/scsi.h b/A58-STEPLDR/Src/usb/include/scsi.h new file mode 100644 index 00000000..a4f6f259 --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/scsi.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + */ + #ifndef _SCSI_H + #define _SCSI_H + +struct scsi_cmd { + unsigned char cmd[16]; /* command */ + /* for request sense */ + #pragma pack(ARCH_DMA_MINALIGN) + unsigned char sense_buf[64]; + unsigned char status; /* SCSI Status */ + unsigned char target; /* Target ID */ + unsigned char lun; /* Target LUN */ + unsigned char cmdlen; /* command len */ + unsigned long datalen; /* Total data length */ + unsigned char * pdata; /* pointer to data */ + unsigned char msgout[12]; /* Messge out buffer (NOT USED) */ + unsigned char msgin[12]; /* Message in buffer */ + unsigned char sensecmdlen; /* Sense command len */ + unsigned long sensedatalen; /* Sense data len */ + unsigned char sensecmd[6]; /* Sense command */ + unsigned long contr_stat; /* Controller Status */ + unsigned long trans_bytes; /* tranfered bytes */ + + unsigned int priv; +}; + +/*----------------------------------------------------------- +** +** SCSI constants. +** +**----------------------------------------------------------- +*/ + +/* +** Messages +*/ + +#define M_COMPLETE (0x00) +#define M_EXTENDED (0x01) +#define M_SAVE_DP (0x02) +#define M_RESTORE_DP (0x03) +#define M_DISCONNECT (0x04) +#define M_ID_ERROR (0x05) +#define M_ABORT (0x06) +#define M_REJECT (0x07) +#define M_NOOP (0x08) +#define M_PARITY (0x09) +#define M_LCOMPLETE (0x0a) +#define M_FCOMPLETE (0x0b) +#define M_RESET (0x0c) +#define M_ABORT_TAG (0x0d) +#define M_CLEAR_QUEUE (0x0e) +#define M_INIT_REC (0x0f) +#define M_REL_REC (0x10) +#define M_TERMINATE (0x11) +#define M_SIMPLE_TAG (0x20) +#define M_HEAD_TAG (0x21) +#define M_ORDERED_TAG (0x22) +#define M_IGN_RESIDUE (0x23) +#define M_IDENTIFY (0x80) + +#define M_X_MODIFY_DP (0x00) +#define M_X_SYNC_REQ (0x01) +#define M_X_WIDE_REQ (0x03) +#define M_X_PPR_REQ (0x04) + + +/* +** Status +*/ + +#define S_GOOD (0x00) +#define S_CHECK_COND (0x02) +#define S_COND_MET (0x04) +#define S_BUSY (0x08) +#define S_INT (0x10) +#define S_INT_COND_MET (0x14) +#define S_CONFLICT (0x18) +#define S_TERMINATED (0x20) +#define S_QUEUE_FULL (0x28) +#define S_ILLEGAL (0xff) +#define S_SENSE (0x80) + +/* + * Sense_keys + */ + +#define SENSE_NO_SENSE 0x0 +#define SENSE_RECOVERED_ERROR 0x1 +#define SENSE_NOT_READY 0x2 +#define SENSE_MEDIUM_ERROR 0x3 +#define SENSE_HARDWARE_ERROR 0x4 +#define SENSE_ILLEGAL_REQUEST 0x5 +#define SENSE_UNIT_ATTENTION 0x6 +#define SENSE_DATA_PROTECT 0x7 +#define SENSE_BLANK_CHECK 0x8 +#define SENSE_VENDOR_SPECIFIC 0x9 +#define SENSE_COPY_ABORTED 0xA +#define SENSE_ABORTED_COMMAND 0xB +#define SENSE_VOLUME_OVERFLOW 0xD +#define SENSE_MISCOMPARE 0xE + + +#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_COPY 0x18 /* Copy (O) */ +#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */ +#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */ +#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */ +#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */ +#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */ +#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */ +#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */ +#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */ +#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */ +#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */ +#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */ +#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */ +/*************************************************************************** + * %%% Commands Unique to Direct Access Devices %%% + ***************************************************************************/ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */ +#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */ +#define SCSI_PREFETCH 0x34 /* Prefetch (O) */ +#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */ +#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */ +#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */ +#define SCSI_READ16 0x48 +#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */ +#define SCSI_RD_CAPAC10 SCSI_RD_CAPAC /* Read Capacity (10) */ +#define SCSI_RD_CAPAC16 0x9e /* Read Capacity (16) */ +#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */ +#define SCSI_READ_LONG 0x3E /* Read Long (O) */ +#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */ +#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */ +#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */ +#define SCSI_REZERO 0x01 /* Rezero Unit (O) */ +#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */ +#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */ +#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */ +#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */ +#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */ +#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */ +#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */ +#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */ +#define SCSI_VERIFY 0x2F /* Verify (O) */ +#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */ +#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */ +#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */ +#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */ +#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */ + +/** + * struct scsi_platdata - stores information about SCSI controller + * + * @base: Controller base address + * @max_lun: Maximum number of logical units + * @max_id: Maximum number of target ids + */ +struct scsi_platdata { + unsigned long base; + unsigned long max_lun; + unsigned long max_id; +}; + +#if 0 +/* Operations for SCSI */ +struct scsi_ops { + /** + * exec() - execute a command + * + * @dev: SCSI bus + * @cmd: Command to execute + * @return 0 if OK, -ve on error + */ + int (*exec)(struct udevice *dev, struct scsi_cmd *cmd); + + /** + * bus_reset() - reset the bus + * + * @dev: SCSI bus to reset + * @return 0 if OK, -ve on error + */ + int (*bus_reset)(struct udevice *dev); +}; + +#define scsi_get_ops(dev) ((struct scsi_ops *)(dev)->driver->ops) + +extern struct scsi_ops scsi_ops; + +/** + * scsi_exec() - execute a command + * + * @dev: SCSI bus + * @cmd: Command to execute + * @return 0 if OK, -ve on error + */ +int scsi_exec(struct udevice *dev, struct scsi_cmd *cmd); + +/** + * scsi_bus_reset() - reset the bus + * + * @dev: SCSI bus to reset + * @return 0 if OK, -ve on error + */ +int scsi_bus_reset(struct udevice *dev); + +/** + * scsi_scan() - Scan all SCSI controllers for available devices + * + * @vebose: true to show information about each device found + */ +int scsi_scan(bool verbose); + +/** + * scsi_scan_dev() - scan a SCSI bus and create devices + * + * @dev: SCSI bus + * @verbose: true to show information about each device found + */ +int scsi_scan_dev(struct udevice *dev, bool verbose); +#endif + +void scsi_low_level_init(int busdevfunc); +void scsi_init(void); + +#define SCSI_IDENTIFY 0xC0 /* not used */ + +/* Hardware errors */ +#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */ +#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */ +#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */ +#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */ + +#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */ + +#endif /* _SCSI_H */ diff --git a/A58-STEPLDR/Src/usb/include/usb.h b/A58-STEPLDR/Src/usb/include/usb.h new file mode 100644 index 00000000..7413ceaf --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/usb.h @@ -0,0 +1,900 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * Adapted for U-Boot driver model + * (C) Copyright 2015 Google, Inc + * Note: Part of this code has been derived from linux + * + */ +#ifndef _USB_H_ +#define _USB_H_ + +//#include +#include +#include +//#include +//#include + +/* + * The EHCI spec says that we must align to at least 32 bytes. However, + * some platforms require larger alignment. + */ +#if ARCH_DMA_MINALIGN > 32 +#define USB_DMA_MINALIGN ARCH_DMA_MINALIGN +#else +#define USB_DMA_MINALIGN 32 +#endif + +/* Everything is aribtrary */ +#define USB_ALTSETTINGALLOC 4 +#define USB_MAXALTSETTING 128 /* Hard limit */ + +#define USB_MAX_DEVICE 32 +#define USB_MAXCONFIG 8 +#define USB_MAXINTERFACES 8 +#define USB_MAXENDPOINTS 16 +#define USB_MAXCHILDREN 8 /* This is arbitrary */ +#define USB_MAX_HUB 16 + +#define USB_CNTL_TIMEOUT 10000 /* 100ms timeout */ + +/* + * This is the timeout to allow for submitting an urb in ms. We allow more + * time for a BULK device to react - some are slow. + */ +#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 1000) + +/* device request (setup) */ +struct devrequest { + __u8 requesttype; + __u8 request; + __le16 value; + __le16 index; + __le16 length; +}; + +/* Interface */ +struct usb_interface { + struct usb_interface_descriptor desc; + + __u8 no_of_ep; + __u8 num_altsetting; + __u8 act_altsetting; + + struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS]; + /* + * Super Speed Device will have Super Speed Endpoint + * Companion Descriptor (section 9.6.7 of usb 3.0 spec) + * Revision 1.0 June 6th 2011 + */ + struct usb_ss_ep_comp_descriptor ss_ep_comp_desc[USB_MAXENDPOINTS]; +}; + +/* Configuration information.. */ +struct usb_config { + struct usb_config_descriptor desc; + + __u8 no_of_if; /* number of interfaces */ + struct usb_interface if_desc[USB_MAXINTERFACES]; +}; + +enum { + /* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */ + PACKET_SIZE_8 = 0, + PACKET_SIZE_16 = 1, + PACKET_SIZE_32 = 2, + PACKET_SIZE_64 = 3, +}; + +/** + * struct usb_device - information about a USB device + * + * With driver model both UCLASS_USB (the USB controllers) and UCLASS_USB_HUB + * (the hubs) have this as parent data. Hubs are children of controllers or + * other hubs and there is always a single root hub for each controller. + * Therefore struct usb_device can always be accessed with + * dev_get_parent_priv(dev), where dev is a USB device. + * + * Pointers exist for obtaining both the device (could be any uclass) and + * controller (UCLASS_USB) from this structure. The controller does not have + * a struct usb_device since it is not a device. + */ +struct usb_device { + int devnum; /* Device number on USB bus */ + int speed; /* full/low/high */ + char mf[32]; /* manufacturer */ + char prod[32]; /* product */ + char serial[32]; /* serial number */ + + struct usb_tt *tt; + int ttport; + + /* Maximum packet size; one of: PACKET_SIZE_* */ + int maxpacketsize; + /* one bit for each endpoint ([0] = IN, [1] = OUT) */ + unsigned int toggle[2]; + /* endpoint halts; one bit per endpoint # & direction; + * [0] = IN, [1] = OUT + */ + unsigned int halted[2]; + int epmaxpacketin[16]; /* INput endpoint specific maximums */ + int epmaxpacketout[16]; /* OUTput endpoint specific maximums */ + + int configno; /* selected config number */ + /* Device Descriptor */ + struct usb_device_descriptor descriptor; + struct usb_config config; /* config descriptor */ + + int have_langid; /* whether string_langid is valid yet */ + int string_langid; /* language ID for strings */ + int (*irq_handle)(struct usb_device *dev); + unsigned long irq_status; + int irq_act_len; /* transferred bytes */ + void *privptr; + /* + * Child devices - if this is a hub device + * Each instance needs its own set of data structures. + */ + unsigned long status; + unsigned long int_pending; /* 1 bit per ep, used by int_queue */ + int act_len; /* transferred bytes */ + int maxchild; /* Number of ports if hub */ + int portnr; /* Port number, 1=first */ +#ifndef CONFIG_DM_USB + /* parent hub, or NULL if this is the root hub */ + struct usb_device *parent; + struct usb_device *children[USB_MAXCHILDREN]; + void *controller; /* hardware controller private data */ +#endif + /* slot_id - for xHCI enabled devices */ + unsigned int slot_id; +#ifdef CONFIG_DM_USB + struct udevice *dev; /* Pointer to associated device */ + struct udevice *controller_dev; /* Pointer to associated controller */ +#endif +}; + +struct int_queue; + +/* + * You can initialize platform's USB host or device + * ports by passing this enum as an argument to + * board_usb_init(). + */ +enum usb_init_type { + USB_INIT_HOST, + USB_INIT_DEVICE +}; + +/********************************************************************** + * this is how the lowlevel part communicate with the outer world + */ + +int usb_lowlevel_init(int index, enum usb_init_type init, void **controller); +int usb_lowlevel_stop(int index); + +#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_DM_USB) +int usb_reset_root_port(struct usb_device *dev); +#else +#define usb_reset_root_port(dev) +#endif + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, int *actual_length, int timeout); +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int timeout); + +/* Defines */ +#define USB_UHCI_VEND_ID 0x8086 +#define USB_UHCI_DEV_ID 0x7112 + +/* + * PXA25x can only act as USB device. There are drivers + * which works with USB CDC gadgets implementations. + * Some of them have common routines which can be used + * in boards init functions e.g. udc_disconnect() used for + * forced device disconnection from host. + */ +extern void udc_disconnect(void); + +/* + * board-specific hardware initialization, called by + * usb drivers and u-boot commands + * + * @param index USB controller number + * @param init initializes controller as USB host or device + */ +int board_usb_init(int index, enum usb_init_type init); + +/* + * can be used to clean up after failed USB initialization attempt + * vide: board_usb_init() + * + * @param index USB controller number for selective cleanup + * @param init usb_init_type passed to board_usb_init() + */ +int board_usb_cleanup(int index, enum usb_init_type init); + +#ifdef CONFIG_USB_STORAGE + +#define USB_MAX_STOR_DEV 7 +int usb_stor_scan(int mode); +int usb_stor_info(void); + +#endif + +#ifdef CONFIG_USB_HOST_ETHER + +#define USB_MAX_ETH_DEV 5 +int usb_host_eth_scan(int mode); + +#endif + +#ifdef CONFIG_USB_KEYBOARD + +int drv_usb_kbd_init(void); +int usb_kbd_deregister(int force); + +#endif +/* routines */ +int usb_init(void); /* initialize the USB Controller */ +int usb_stop(void); /* stop the USB Controller */ +int usb_detect_change(void); /* detect if a USB device has been (un)plugged */ + + +int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol); +int usb_set_idle(struct usb_device *dev, int ifnum, int duration, + int report_id); +int usb_control_msg(struct usb_device *dev, unsigned int pipe, + unsigned char request, unsigned char requesttype, + unsigned short value, unsigned short index, + void *data, unsigned short size, int timeout); +int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, + void *data, int len, int *actual_length, int timeout); +int usb_disable_asynch(int disable); +int usb_maxpacket(struct usb_device *dev, unsigned long pipe); +int usb_get_configuration_no(struct usb_device *dev, int cfgno, + unsigned char *buffer, int length); +int usb_get_configuration_len(struct usb_device *dev, int cfgno); +int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, + unsigned char id, void *buf, int size); +int usb_get_class_descriptor(struct usb_device *dev, int ifnum, + unsigned char type, unsigned char id, void *buf, + int size); +int usb_clear_halt(struct usb_device *dev, int pipe); +int usb_string(struct usb_device *dev, int index, char *buf, size_t size); +int usb_set_interface(struct usb_device *dev, int interface, int alternate); +int usb_get_port_status(struct usb_device *dev, int port, void *data); + +/* big endian -> little endian conversion */ +/* some CPUs are already little endian e.g. the ARM920T */ +#define __swap_16(x) \ + ({ unsigned short x_ = (unsigned short)x; \ + (unsigned short)( \ + ((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \ + }) +#define __swap_32(x) \ + ({ unsigned long x_ = (unsigned long)x; \ + (unsigned long)( \ + ((x_ & 0x000000FFUL) << 24) | \ + ((x_ & 0x0000FF00UL) << 8) | \ + ((x_ & 0x00FF0000UL) >> 8) | \ + ((x_ & 0xFF000000UL) >> 24)); \ + }) + +#ifdef __LITTLE_ENDIAN +# define swap_16(x) (x) +# define swap_32(x) (x) +#else +# define swap_16(x) __swap_16(x) +# define swap_32(x) __swap_32(x) +#endif + +/* + * Calling this entity a "pipe" is glorifying it. A USB pipe + * is something embarrassingly simple: it basically consists + * of the following information: + * - device number (7 bits) + * - endpoint number (4 bits) + * - current Data0/1 state (1 bit) + * - direction (1 bit) + * - speed (2 bits) + * - max packet size (2 bits: 8, 16, 32 or 64) + * - pipe type (2 bits: control, interrupt, bulk, isochronous) + * + * That's 18 bits. Really. Nothing more. And the USB people have + * documented these eighteen bits as some kind of glorious + * virtual data structure. + * + * Let's not fall in that trap. We'll just encode it as a simple + * unsigned int. The encoding is: + * + * - max size: bits 0-1 (00 = 8, 01 = 16, 10 = 32, 11 = 64) + * - direction: bit 7 (0 = Host-to-Device [Out], + * (1 = Device-to-Host [In]) + * - device: bits 8-14 + * - endpoint: bits 15-18 + * - Data0/1: bit 19 + * - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt, + * 10 = control, 11 = bulk) + * + * Why? Because it's arbitrary, and whatever encoding we select is really + * up to us. This one happens to share a lot of bit positions with the UHCI + * specification, so that much of the uhci driver can just mask the bits + * appropriately. + */ +/* Create various pipes... */ +#define create_pipe(dev,endpoint) \ + (((dev)->devnum << 8) | ((endpoint) << 15) | \ + (dev)->maxpacketsize) +#define default_pipe(dev) ((dev)->speed << 26) + +#define usb_sndctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_sndisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_sndbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_sndintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \ + create_pipe(dev, endpoint)) +#define usb_rcvintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \ + create_pipe(dev, endpoint) | \ + USB_DIR_IN) +#define usb_snddefctrl(dev) ((PIPE_CONTROL << 30) | \ + default_pipe(dev)) +#define usb_rcvdefctrl(dev) ((PIPE_CONTROL << 30) | \ + default_pipe(dev) | \ + USB_DIR_IN) + +/* The D0/D1 toggle bits */ +#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1) +#define usb_dotoggle(dev, ep, out) ((dev)->toggle[out] ^= (1 << ep)) +#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \ + ((dev)->toggle[out] & \ + ~(1 << ep)) | ((bit) << ep)) + +/* Endpoint halt control/status */ +#define usb_endpoint_out(ep_dir) (((ep_dir >> 7) & 1) ^ 1) +#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep))) +#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep))) +#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep))) + +#define usb_packetid(pipe) (((pipe) & USB_DIR_IN) ? USB_PID_IN : \ + USB_PID_OUT) + +//#define usb_pipeout(pipe) ((((pipe) >> 7) & 1) ^ 1) +//#define usb_pipein(pipe) (((pipe) >> 7) & 1) + +#define usb_pipein(pipe) ((pipe) & USB_DIR_IN) +#define usb_pipeout(pipe) (!usb_pipein(pipe)) + +#define usb_pipedevice(pipe) (((pipe) >> 8) & 0x7f) +#define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff) +#define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf) +#define usb_pipedata(pipe) (((pipe) >> 19) & 1) +#define usb_pipetype(pipe) (((pipe) >> 30) & 3) +#define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS) +#define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT) +#define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL) +#define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK) + +#define usb_pipe_ep_index(pipe) \ + usb_pipecontrol(pipe) ? (usb_pipeendpoint(pipe) * 2) : \ + ((usb_pipeendpoint(pipe) * 2) - \ + (usb_pipein(pipe) ? 0 : 1)) + +/** + * struct usb_device_id - identifies USB devices for probing and hotplugging + * @match_flags: Bit mask controlling which of the other fields are used to + * match against new devices. Any field except for driver_info may be + * used, although some only make sense in conjunction with other fields. + * This is usually set by a USB_DEVICE_*() macro, which sets all + * other fields in this structure except for driver_info. + * @idVendor: USB vendor ID for a device; numbers are assigned + * by the USB forum to its members. + * @idProduct: Vendor-assigned product ID. + * @bcdDevice_lo: Low end of range of vendor-assigned product version numbers. + * This is also used to identify individual product versions, for + * a range consisting of a single device. + * @bcdDevice_hi: High end of version number range. The range of product + * versions is inclusive. + * @bDeviceClass: Class of device; numbers are assigned + * by the USB forum. Products may choose to implement classes, + * or be vendor-specific. Device classes specify behavior of all + * the interfaces on a device. + * @bDeviceSubClass: Subclass of device; associated with bDeviceClass. + * @bDeviceProtocol: Protocol of device; associated with bDeviceClass. + * @bInterfaceClass: Class of interface; numbers are assigned + * by the USB forum. Products may choose to implement classes, + * or be vendor-specific. Interface classes specify behavior only + * of a given interface; other interfaces may support other classes. + * @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass. + * @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass. + * @bInterfaceNumber: Number of interface; composite devices may use + * fixed interface numbers to differentiate between vendor-specific + * interfaces. + * @driver_info: Holds information used by the driver. Usually it holds + * a pointer to a descriptor understood by the driver, or perhaps + * device flags. + * + * In most cases, drivers will create a table of device IDs by using + * USB_DEVICE(), or similar macros designed for that purpose. + * They will then export it to userspace using MODULE_DEVICE_TABLE(), + * and provide it to the USB core through their usb_driver structure. + * + * See the usb_match_id() function for information about how matches are + * performed. Briefly, you will normally use one of several macros to help + * construct these entries. Each entry you provide will either identify + * one or more specific products, or will identify a class of products + * which have agreed to behave the same. You should put the more specific + * matches towards the beginning of your table, so that driver_info can + * record quirks of specific products. + */ +struct usb_device_id { + /* which fields to match against? */ + u16 match_flags; + + /* Used for product specific matches; range is inclusive */ + u16 idVendor; + u16 idProduct; + u16 bcdDevice_lo; + u16 bcdDevice_hi; + + /* Used for device class matches */ + u8 bDeviceClass; + u8 bDeviceSubClass; + u8 bDeviceProtocol; + + /* Used for interface class matches */ + u8 bInterfaceClass; + u8 bInterfaceSubClass; + u8 bInterfaceProtocol; + + /* Used for vendor-specific interface matches */ + u8 bInterfaceNumber; + + /* not matched against */ + ulong driver_info; +}; + +/* Some useful macros to use to create struct usb_device_id */ +#define USB_DEVICE_ID_MATCH_VENDOR 0x0001 +#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002 +#define USB_DEVICE_ID_MATCH_DEV_LO 0x0004 +#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008 +#define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010 +#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020 +#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040 +#define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080 +#define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100 +#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200 +#define USB_DEVICE_ID_MATCH_INT_NUMBER 0x0400 + +/* Match anything, indicates this is a valid entry even if everything is 0 */ +#define USB_DEVICE_ID_MATCH_NONE 0x0800 +#define USB_DEVICE_ID_MATCH_ALL 0x07ff + +/** + * struct usb_driver_entry - Matches a driver to its usb_device_ids + * @driver: Driver to use + * @match: List of match records for this driver, terminated by {} + */ +struct usb_driver_entry { + struct driver *driver; + const struct usb_device_id *match; +}; + +#define USB_DEVICE_ID_MATCH_DEVICE \ + (USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT) + +/** + * USB_DEVICE - macro used to describe a specific usb device + * @vend: the 16 bit USB Vendor ID + * @prod: the 16 bit USB Product ID + * + * This macro is used to create a struct usb_device_id that matches a + * specific device. + */ +#define USB_DEVICE(vend, prod) \ + .match_flags = USB_DEVICE_ID_MATCH_DEVICE, \ + .idVendor = (vend), \ + .idProduct = (prod) + +#define U_BOOT_USB_DEVICE(__name, __match) \ + ll_entry_declare(struct usb_driver_entry, __name, usb_driver_entry) = {\ + .driver = llsym(struct driver, __name, driver), \ + .match = __match, \ + } + +/************************************************************************* + * Hub Stuff + */ +struct usb_port_status { + unsigned short wPortStatus; + unsigned short wPortChange; +}; + +struct usb_hub_status { + unsigned short wHubStatus; + unsigned short wHubChange; +}; + +/* + * Hub Device descriptor + * USB Hub class device protocols + */ +#define USB_HUB_PR_FS 0 /* Full speed hub */ +#define USB_HUB_PR_HS_NO_TT 0 /* Hi-speed hub without TT */ +#define USB_HUB_PR_HS_SINGLE_TT 1 /* Hi-speed hub with single TT */ +#define USB_HUB_PR_HS_MULTI_TT 2 /* Hi-speed hub with multiple TT */ +#define USB_HUB_PR_SS 3 /* Super speed hub */ + +/* Transaction Translator Think Times, in bits */ +#define HUB_TTTT_8_BITS 0x00 +#define HUB_TTTT_16_BITS 0x20 +#define HUB_TTTT_24_BITS 0x40 +#define HUB_TTTT_32_BITS 0x60 + +/* Hub descriptor */ +struct usb_hub_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bNbrPorts; + unsigned short wHubCharacteristics; + unsigned char bPwrOn2PwrGood; + unsigned char bHubContrCurrent; + /* 2.0 and 3.0 hubs differ here */ + union { + struct { + /* add 1 bit for hub status change; round to bytes */ + __u8 DeviceRemovable[(USB_MAXCHILDREN + 1 + 7) / 8]; + __u8 PortPowerCtrlMask[(USB_MAXCHILDREN + 1 + 7) / 8]; + }hs; + + struct { + __u8 bHubHdrDecLat; + __le16 wHubDelay; + __le16 DeviceRemovable; + }ss; + } u; +}; + + +struct usb_hub_device { + struct usb_device *pusb_dev; + struct usb_hub_descriptor desc; + + ulong connect_timeout; /* Device connection timeout in ms */ + ulong query_delay; /* Device query delay in ms */ + int overcurrent_count[USB_MAXCHILDREN]; /* Over-current counter */ + int hub_depth; /* USB 3.0 hub depth */ + struct usb_tt tt; /* Transaction Translator */ +}; + +#ifdef CONFIG_DM_USB +/** + * struct usb_platdata - Platform data about a USB controller + * + * Given a USB controller (UCLASS_USB) dev this is dev_get_platdata(dev) + */ +struct usb_platdata { + enum usb_init_type init_type; +}; + +/** + * struct usb_dev_platdata - Platform data about a USB device + * + * Given a USB device dev this structure is dev_get_parent_platdata(dev). + * This is used by sandbox to provide emulation data also. + * + * @id: ID used to match this device + * @devnum: Device address on the USB bus + * @udev: usb-uclass internal use only do NOT use + * @strings: List of descriptor strings (for sandbox emulation purposes) + * @desc_list: List of descriptors (for sandbox emulation purposes) + */ +struct usb_dev_platdata { + struct usb_device_id id; + int devnum; + /* + * This pointer is used to pass the usb_device used in usb_scan_device, + * to get the usb descriptors before the driver is known, to the + * actual udevice once the driver is known and the udevice is created. + * This will be NULL except during probe, do NOT use. + * + * This should eventually go away. + */ + struct usb_device *udev; + + int configno; +}; + +/** + * struct usb_bus_priv - information about the USB controller + * + * Given a USB controller (UCLASS_USB) 'dev', this is + * dev_get_uclass_priv(dev). + * + * @next_addr: Next device address to allocate minus 1. Incremented by 1 + * each time a new device address is set, so this holds the + * number of devices on the bus + * @desc_before_addr: true if we can read a device descriptor before it + * has been assigned an address. For XHCI this is not possible + * so this will be false. + * @companion: True if this is a companion controller to another USB + * controller + */ +struct usb_bus_priv { + int next_addr; + bool desc_before_addr; + bool companion; +}; + +/** + * struct usb_emul_platdata - platform data about the USB emulator + * + * Given a USB emulator (UCLASS_USB_EMUL) 'dev', this is + * dev_get_uclass_platdata(dev). + * + * @port1: USB emulator device port number on the parent hub + */ +struct usb_emul_platdata { + int port1; /* Port number (numbered from 1) */ +}; + +/** + * struct dm_usb_ops - USB controller operations + * + * This defines the operations supoorted on a USB controller. Common + * arguments are: + * + * @bus: USB bus (i.e. controller), which is in UCLASS_USB. + * @udev: USB device parent data. Controllers are not expected to need + * this, since the device address on the bus is encoded in @pipe. + * It is used for sandbox, and can be handy for debugging and + * logging. + * @pipe: An assortment of bitfields which provide address and packet + * type information. See create_pipe() above for encoding + * details + * @buffer: A buffer to use for sending/receiving. This should be + * DMA-aligned. + * @length: Buffer length in bytes + */ +struct dm_usb_ops { + /** + * control() - Send a control message + * + * Most parameters are as above. + * + * @setup: Additional setup information required by the message + */ + int (*control)(struct udevice *bus, struct usb_device *udev, + unsigned long pipe, void *buffer, int length, + struct devrequest *setup); + /** + * bulk() - Send a bulk message + * + * Parameters are as above. + */ + int (*bulk)(struct udevice *bus, struct usb_device *udev, + unsigned long pipe, void *buffer, int length); + /** + * interrupt() - Send an interrupt message + * + * Most parameters are as above. + * + * @interval: Interrupt interval + */ + int (*interrupt)(struct udevice *bus, struct usb_device *udev, + unsigned long pipe, void *buffer, int length, + int interval); + + /** + * alloc_device() - Allocate a new device context (XHCI) + * + * Before sending packets to a new device on an XHCI bus, a device + * context must be created. If this method is not NULL it will be + * called before the device is enumerated (even before its descriptor + * is read). This should be NULL for EHCI, which does not need this. + */ + int (*alloc_device)(struct udevice *bus, struct usb_device *udev); + + /** + * reset_root_port() - Reset usb root port + */ + int (*reset_root_port)(struct udevice *bus, struct usb_device *udev); + + /** + * get_max_xfer_size() - Get HCD's maximum transfer bytes + * + * The HCD may have limitation on the maximum bytes to be transferred + * in a USB transfer. USB class driver needs to be aware of this. + */ + int (*get_max_xfer_size)(struct udevice *bus, size_t *size); +}; + +#define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) +#define usb_get_emul_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) + +/** + * usb_get_dev_index() - look up a device index number + * + * Look up devices using their index number (starting at 0). This works since + * in U-Boot device addresses are allocated starting at 1 with no gaps. + * + * TODO(sjg@chromium.org): Remove this function when usb_ether.c is modified + * to work better with driver model. + * + * @bus: USB bus to check + * @index: Index number of device to find (0=first). This is just the + * device address less 1. + */ +struct usb_device *usb_get_dev_index(struct udevice *bus, int index); + +/** + * usb_setup_device() - set up a device ready for use + * + * @dev: USB device pointer. This need not be a real device - it is + * common for it to just be a local variable with its ->dev + * member (i.e. @dev->dev) set to the parent device and + * dev->portnr set to the port number on the hub (1=first) + * @do_read: true to read the device descriptor before an address is set + * (should be false for XHCI buses, true otherwise) + * @parent: Parent device (either UCLASS_USB or UCLASS_USB_HUB) + * @return 0 if OK, -ve on error */ +int usb_setup_device(struct usb_device *dev, bool do_read, + struct usb_device *parent); + +/** + * usb_hub_is_root_hub() - Test whether a hub device is root hub or not + * + * @hub: USB hub device to test + * @return: true if the hub device is root hub, false otherwise. + */ +bool usb_hub_is_root_hub(struct udevice *hub); + +/** + * usb_hub_scan() - Scan a hub and find its devices + * + * @hub: Hub device to scan + */ +int usb_hub_scan(struct udevice *hub); + +/** + * usb_scan_device() - Scan a device on a bus + * + * Scan a device on a bus. It has already been detected and is ready to + * be enumerated. This may be either the root hub (@parent is a bus) or a + * normal device (@parent is a hub) + * + * @parent: Parent device + * @port: Hub port number (numbered from 1) + * @speed: USB speed to use for this device + * @devp: Returns pointer to device if all is well + * @return 0 if OK, -ve on error + */ +int usb_scan_device(struct udevice *parent, int port, + enum usb_device_speed speed, struct udevice **devp); + +/** + * usb_get_bus() - Find the bus for a device + * + * Search up through parents to find the bus this device is connected to. This + * will be a device with uclass UCLASS_USB. + * + * @dev: Device to check + * @return The bus, or NULL if not found (this indicates a critical error in + * the USB stack + */ +struct udevice *usb_get_bus(struct udevice *dev); + +/** + * usb_select_config() - Set up a device ready for use + * + * This function assumes that the device already has an address and a driver + * bound, and is ready to be set up. + * + * This re-reads the device and configuration descriptors and sets the + * configuration + * + * @dev: Device to set up + */ +int usb_select_config(struct usb_device *dev); + +/** + * usb_child_pre_probe() - Pre-probe function for USB devices + * + * This is called on all children of hubs and USB controllers (i.e. UCLASS_USB + * and UCLASS_USB_HUB) when a new device is about to be probed. It sets up the + * device from the saved platform data and calls usb_select_config() to + * finish set up. + * + * Once this is done, the device's normal driver can take over, knowing the + * device is accessible on the USB bus. + * + * This function is for use only by the internal USB stack. + * + * @dev: Device to set up + */ +int usb_child_pre_probe(struct udevice *dev); + +struct ehci_ctrl; + +/** + * usb_stor_reset() - Prepare to scan USB storage devices + * + * Empty the list of USB storage devices in preparation for scanning them. + * This must be called before a USB scan. + */ +void usb_stor_reset(void); + +#else /* !CONFIG_DM_USB */ + +struct usb_device *usb_get_dev_index(int index); + +#endif + +bool usb_device_has_child_on_port(struct usb_device *parent, int port); + +int usb_hub_probe(struct usb_device *dev, int ifnum); +void usb_hub_reset(void); + + +/** + * usb_alloc_new_device() - Allocate a new device + * + * @devp: returns a pointer of a new device structure. With driver model this + * is a device pointer, but with legacy USB this pointer is + * driver-specific. + * @return 0 if OK, -ENOSPC if we have found out of room for new devices + */ +int usb_alloc_new_device(void *controller, struct usb_device **devp); + +/** + * usb_free_device() - Free a partially-inited device + * + * This is an internal function. It is used to reverse the action of + * usb_alloc_new_device() when we hit a problem during init. + */ +void usb_free_device(void *controller); + +int usb_new_device(struct usb_device *dev); + +int usb_alloc_device(struct usb_device *dev); + +/** + * usb_get_max_xfer_size() - Get HCD's maximum transfer bytes + * + * The HCD may have limitation on the maximum bytes to be transferred + * in a USB transfer. USB class driver needs to be aware of this. + * + * @dev: USB device + * @size: maximum transfer bytes + * @return 0 if OK, -ve on error + */ +int usb_get_max_xfer_size(struct usb_device *dev, size_t *size); + +/** + * usb_show_tree() - show the USB device tree + * + * This shows a list of active USB devices along with basic information about + * each. + */ +void usb_show_tree(void); + +#define USB_DEV_PLUGED 0 +#define USB_DEV_UNPLUGED 1 +int usb_wait_dev_pluged(uint32_t timeout); + +#endif /*_USB_H_ */ diff --git a/A58-STEPLDR/Src/usb/include/usb_defs.h b/A58-STEPLDR/Src/usb/include/usb_defs.h new file mode 100644 index 00000000..7e029979 --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/usb_defs.h @@ -0,0 +1,380 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * Note: Part of this code has been derived from linux + */ +#ifndef _USB_DEFS_H_ +#define _USB_DEFS_H_ + +/* USB constants */ + +/* Device and/or Interface Class codes */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_DATA 10 +#define USB_CLASS_VENDOR_SPEC 0xff + +/* some HID sub classes */ +#define USB_SUB_HID_NONE 0 +#define USB_SUB_HID_BOOT 1 + +/* some UID Protocols */ +#define USB_PROT_HID_NONE 0 +#define USB_PROT_HID_KEYBOARD 1 +#define USB_PROT_HID_MOUSE 2 + + +/* Sub STORAGE Classes */ +#define US_SC_RBC 1 /* Typically, flash devices */ +#define US_SC_8020 2 /* CD-ROM */ +#define US_SC_QIC 3 /* QIC-157 Tapes */ +#define US_SC_UFI 4 /* Floppy */ +#define US_SC_8070 5 /* Removable media */ +#define US_SC_SCSI 6 /* Transparent */ +#define US_SC_MIN US_SC_RBC +#define US_SC_MAX US_SC_SCSI + +/* STORAGE Protocols */ +#define US_PR_CB 1 /* Control/Bulk w/o interrupt */ +#define US_PR_CBI 0 /* Control/Bulk/Interrupt */ +#define US_PR_BULK 0x50 /* bulk only */ + +/* USB types */ +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* USB recipients */ +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + +/* USB directions */ +#define USB_DIR_OUT 0 +#define USB_DIR_IN 0x80 + +/* + * bmRequestType: USB Device Requests, table 9.2 USB 2.0 spec. + * (shifted) direction/type/recipient. + */ +#define DeviceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define DeviceOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define InterfaceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +/* Descriptor types */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +#define USB_DT_HID (USB_TYPE_CLASS | 0x01) +#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) +#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) +#define USB_DT_HUB (USB_TYPE_CLASS | 0x09) +#define USB_DT_SS_HUB (USB_TYPE_CLASS | 0x0a) + +/* Descriptor sizes per descriptor type */ +#define USB_DT_DEVICE_SIZE 18 +#define USB_DT_CONFIG_SIZE 9 +#define USB_DT_INTERFACE_SIZE 9 +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ +#define USB_DT_HUB_NONVAR_SIZE 7 +#define USB_DT_HID_SIZE 9 + +/* Endpoints */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 + +/* USB Packet IDs (PIDs) */ +#define USB_PID_UNDEF_0 0xf0 +#define USB_PID_OUT 0xe1 +#define USB_PID_ACK 0xd2 +#define USB_PID_DATA0 0xc3 +#define USB_PID_UNDEF_4 0xb4 +#define USB_PID_SOF 0xa5 +#define USB_PID_UNDEF_6 0x96 +#define USB_PID_UNDEF_7 0x87 +#define USB_PID_UNDEF_8 0x78 +#define USB_PID_IN 0x69 +#define USB_PID_NAK 0x5a +#define USB_PID_DATA1 0x4b +#define USB_PID_PREAMBLE 0x3c +#define USB_PID_SETUP 0x2d +#define USB_PID_STALL 0x1e +#define USB_PID_UNDEF_F 0x0f + +/* Standard requests */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +/* HID requests */ +#define USB_REQ_GET_REPORT 0x01 +#define USB_REQ_GET_IDLE 0x02 +#define USB_REQ_GET_PROTOCOL 0x03 +#define USB_REQ_SET_REPORT 0x09 +#define USB_REQ_SET_IDLE 0x0A +#define USB_REQ_SET_PROTOCOL 0x0B + +/* Device features */ +#define USB_FEAT_HALT 0x00 +#define USB_FEAT_WAKEUP 0x01 +#define USB_FEAT_TEST 0x02 + +/* Test modes */ +#define USB_TEST_MODE_J 0x01 +#define USB_TEST_MODE_K 0x02 +#define USB_TEST_MODE_SE0_NAK 0x03 +#define USB_TEST_MODE_PACKET 0x04 +#define USB_TEST_MODE_FORCE_ENABLE 0x05 + + +/* + * "pipe" definitions, use unsigned so we can compare reliably, since this + * value is shifted up to bits 30/31. + */ +#define PIPE_ISOCHRONOUS 0U +#define PIPE_INTERRUPT 1U +#define PIPE_CONTROL 2U +#define PIPE_BULK 3U +#define PIPE_DEVEP_MASK 0x0007ff00 + +#define USB_ISOCHRONOUS 0 +#define USB_INTERRUPT 1 +#define USB_CONTROL 2 +#define USB_BULK 3 + +#define USB_PIPE_TYPE_SHIFT 30 +#define USB_PIPE_TYPE_MASK (3 << USB_PIPE_TYPE_SHIFT) + +#define USB_PIPE_DEV_SHIFT 8 +#define USB_PIPE_DEV_MASK (0x7f << USB_PIPE_DEV_SHIFT) + +#define USB_PIPE_EP_SHIFT 15 +#define USB_PIPE_EP_MASK (0xf << USB_PIPE_EP_SHIFT) + +/* USB-status codes: */ +#define USB_ST_ACTIVE 0x1 /* TD is active */ +#define USB_ST_STALLED 0x2 /* TD is stalled */ +#define USB_ST_BUF_ERR 0x4 /* buffer error */ +#define USB_ST_BABBLE_DET 0x8 /* Babble detected */ +#define USB_ST_NAK_REC 0x10 /* NAK Received*/ +#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */ +#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */ +#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */ + + +/************************************************************************* + * Hub defines + */ + +/* + * Hub request types + */ + +#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE) +#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER) + +/* + * Hub Class feature numbers + */ +#define C_HUB_LOCAL_POWER 0 +#define C_HUB_OVER_CURRENT 1 + +/* + * Port feature numbers + */ +#define USB_PORT_FEAT_CONNECTION 0 +#define USB_PORT_FEAT_ENABLE 1 +#define USB_PORT_FEAT_SUSPEND 2 +#define USB_PORT_FEAT_OVER_CURRENT 3 +#define USB_PORT_FEAT_RESET 4 +#define USB_PORT_FEAT_POWER 8 +#define USB_PORT_FEAT_LOWSPEED 9 +#define USB_PORT_FEAT_HIGHSPEED 10 +#define USB_PORT_FEAT_C_CONNECTION 16 +#define USB_PORT_FEAT_C_ENABLE 17 +#define USB_PORT_FEAT_C_SUSPEND 18 +#define USB_PORT_FEAT_C_OVER_CURRENT 19 +#define USB_PORT_FEAT_C_RESET 20 +#define USB_PORT_FEAT_TEST 21 + +/* + * Changes to Port feature numbers for Super speed, + * from USB 3.0 spec Table 10-8 + */ +#define USB_SS_PORT_FEAT_U1_TIMEOUT 23 +#define USB_SS_PORT_FEAT_U2_TIMEOUT 24 +#define USB_SS_PORT_FEAT_C_LINK_STATE 25 +#define USB_SS_PORT_FEAT_C_CONFIG_ERROR 26 +#define USB_SS_PORT_FEAT_BH_RESET 28 +#define USB_SS_PORT_FEAT_C_BH_RESET 29 + +/* wPortStatus bits */ +#define USB_PORT_STAT_CONNECTION 0x0001 +#define USB_PORT_STAT_ENABLE 0x0002 +#define USB_PORT_STAT_SUSPEND 0x0004 +#define USB_PORT_STAT_OVERCURRENT 0x0008 +#define USB_PORT_STAT_RESET 0x0010 +#define USB_PORT_STAT_POWER 0x0100 +#define USB_PORT_STAT_LOW_SPEED 0x0200 +#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */ +#define USB_PORT_STAT_SUPER_SPEED 0x0600 /* faking support to XHCI */ +#define USB_PORT_STAT_SPEED_MASK \ + (USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED) + +/* + * Changes to wPortStatus bit field in USB 3.0 + * See USB 3.0 spec Table 10-10 + */ +#define USB_SS_PORT_STAT_LINK_STATE 0x01e0 +#define USB_SS_PORT_STAT_POWER 0x0200 +#define USB_SS_PORT_STAT_SPEED 0x1c00 +#define USB_SS_PORT_STAT_SPEED_5GBPS 0x0000 +/* Bits that are the same from USB 2.0 */ +#define USB_SS_PORT_STAT_MASK (USB_PORT_STAT_CONNECTION | \ + USB_PORT_STAT_ENABLE | \ + USB_PORT_STAT_OVERCURRENT | \ + USB_PORT_STAT_RESET) + +/* wPortChange bits */ +#define USB_PORT_STAT_C_CONNECTION 0x0001 +#define USB_PORT_STAT_C_ENABLE 0x0002 +#define USB_PORT_STAT_C_SUSPEND 0x0004 +#define USB_PORT_STAT_C_OVERCURRENT 0x0008 +#define USB_PORT_STAT_C_RESET 0x0010 + +/* + * Changes to wPortChange bit fields in USB 3.0 + * See USB 3.0 spec Table 10-12 + */ +#define USB_SS_PORT_STAT_C_BH_RESET 0x0020 +#define USB_SS_PORT_STAT_C_LINK_STATE 0x0040 +#define USB_SS_PORT_STAT_C_CONFIG_ERROR 0x0080 + +/* wHubCharacteristics (masks) */ +#define HUB_CHAR_LPSM 0x0003 +#define HUB_CHAR_COMPOUND 0x0004 +#define HUB_CHAR_OCPM 0x0018 +#define HUB_CHAR_TTTT 0x0060 /* TT Think Time mask */ + +/* + * Hub Status & Hub Change bit masks + */ +#define HUB_STATUS_LOCAL_POWER 0x0001 +#define HUB_STATUS_OVERCURRENT 0x0002 + +#define HUB_CHANGE_LOCAL_POWER 0x0001 +#define HUB_CHANGE_OVERCURRENT 0x0002 + +/* Mask for wIndex in get/set port feature */ +#define USB_HUB_PORT_MASK 0xf + +/* Hub class request codes */ +#define USB_REQ_SET_HUB_DEPTH 0x0c + +/* + * As of USB 2.0, full/low speed devices are segregated into trees. + * One type grows from USB 1.1 host controllers (OHCI, UHCI etc). + * The other type grows from high speed hubs when they connect to + * full/low speed devices using "Transaction Translators" (TTs). + */ +#if 0 +struct usb_tt { + bool multi; /* true means one TT per port */ + unsigned think_time; /* think time in ns */ +}; +#else +struct usb_device; +struct usb_tt { + struct usb_device *hub; /* upstream highspeed hub */ + int multi; /* true means one TT per port */ + unsigned think_time; /* think time in ns */ + void *hcpriv; /* HCD private data */ + + /* for control/bulk error recovery (CLEAR_TT_BUFFER) */ + spinlock_t lock; + //struct list_head clear_list; /* of usb_tt_clear */ +}; +#endif + + +/* + * CBI style + */ + +#define US_CBI_ADSC 0 + +/* Command Block Wrapper */ +struct umass_bbb_cbw { + __u32 dCBWSignature; +# define CBWSIGNATURE 0x43425355 + __u32 dCBWTag; + __u32 dCBWDataTransferLength; + __u8 bCBWFlags; +# define CBWFLAGS_OUT 0x00 +# define CBWFLAGS_IN 0x80 +# define CBWFLAGS_SBZ 0x7f + __u8 bCBWLUN; + __u8 bCDBLength; +# define CBWCDBLENGTH 16 + __u8 CBWCDB[CBWCDBLENGTH]; +}; +#define UMASS_BBB_CBW_SIZE 31 + +/* Command Status Wrapper */ +struct umass_bbb_csw { + __u32 dCSWSignature; +# define CSWSIGNATURE 0x53425355 + __u32 dCSWTag; + __u32 dCSWDataResidue; + __u8 bCSWStatus; +# define CSWSTATUS_GOOD 0x0 +# define CSWSTATUS_FAILED 0x1 +# define CSWSTATUS_PHASE 0x2 +}; +#define UMASS_BBB_CSW_SIZE 13 + +/* + * BULK only + */ +#define US_BBB_RESET 0xff +#define US_BBB_GET_MAX_LUN 0xfe + +#endif /*_USB_DEFS_H_ */ diff --git a/A58-STEPLDR/Src/usb/include/usbdescriptors.h b/A58-STEPLDR/Src/usb/include/usbdescriptors.h new file mode 100644 index 00000000..9a503874 --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/usbdescriptors.h @@ -0,0 +1,534 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/usb-function.h - USB Function + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + */ + +/* USB Descriptors - Create a complete description of all of the + * function driver capabilities. These map directly to the USB descriptors. + * + * This heirarchy is created by the functions drivers and is passed to the + * usb-device driver when the function driver is registered. + * + * device + * configuration + * interface + * alternate + * class + * class + * alternate + * endpoint + * endpoint + * interface + * alternate + * endpoint + * endpoint + * configuration + * interface + * alternate + * endpoint + * endpoint + * + * + * The configuration structures refer to the USB Configurations that will be + * made available to a USB HOST during the enumeration process. + * + * The USB HOST will select a configuration and optionally an interface with + * the usb set configuration and set interface commands. + * + * The selected interface (or the default interface if not specifically + * selected) will define the list of endpoints that will be used. + * + * The configuration and interfaces are stored in an array that is indexed + * by the specified configuratin or interface number minus one. + * + * A configuration number of zero is used to specify a return to the unconfigured + * state. + * + */ + + +#ifndef __USBDESCRIPTORS_H__ +#define __USBDESCRIPTORS_H__ + +#include + +/* + * communications class types + * + * c.f. CDC USB Class Definitions for Communications Devices + * c.f. WMCD USB CDC Subclass Specification for Wireless Mobile Communications Devices + * + */ + +#define CLASS_BCD_VERSION 0x0110 + +/* c.f. CDC 4.1 Table 14 */ +#define COMMUNICATIONS_DEVICE_CLASS 0x02 + +/* c.f. CDC 4.2 Table 15 */ +#define COMMUNICATIONS_INTERFACE_CLASS_CONTROL 0x02 +#define COMMUNICATIONS_INTERFACE_CLASS_DATA 0x0A +#define COMMUNICATIONS_INTERFACE_CLASS_VENDOR 0x0FF + +/* c.f. CDC 4.3 Table 16 */ +#define COMMUNICATIONS_NO_SUBCLASS 0x00 +#define COMMUNICATIONS_DLCM_SUBCLASS 0x01 +#define COMMUNICATIONS_ACM_SUBCLASS 0x02 +#define COMMUNICATIONS_TCM_SUBCLASS 0x03 +#define COMMUNICATIONS_MCCM_SUBCLASS 0x04 +#define COMMUNICATIONS_CCM_SUBCLASS 0x05 +#define COMMUNICATIONS_ENCM_SUBCLASS 0x06 +#define COMMUNICATIONS_ANCM_SUBCLASS 0x07 + +/* c.f. WMCD 5.1 */ +#define COMMUNICATIONS_WHCM_SUBCLASS 0x08 +#define COMMUNICATIONS_DMM_SUBCLASS 0x09 +#define COMMUNICATIONS_MDLM_SUBCLASS 0x0a +#define COMMUNICATIONS_OBEX_SUBCLASS 0x0b + +/* c.f. CDC 4.4 Table 17 */ +#define COMMUNICATIONS_NO_PROTOCOL 0x00 +#define COMMUNICATIONS_V25TER_PROTOCOL 0x01 /*Common AT Hayes compatible*/ + +/* c.f. CDC 4.5 Table 18 */ +#define DATA_INTERFACE_CLASS 0x0a + +/* c.f. CDC 4.6 No Table */ +#define DATA_INTERFACE_SUBCLASS_NONE 0x00 /* No subclass pertinent */ + +/* c.f. CDC 4.7 Table 19 */ +#define DATA_INTERFACE_PROTOCOL_NONE 0x00 /* No class protcol required */ + + +/* c.f. CDC 5.2.3 Table 24 */ +#define CS_INTERFACE 0x24 +#define CS_ENDPOINT 0x25 + +/* + * bDescriptorSubtypes + * + * c.f. CDC 5.2.3 Table 25 + * c.f. WMCD 5.3 Table 5.3 + */ + +#define USB_ST_HEADER 0x00 +#define USB_ST_CMF 0x01 +#define USB_ST_ACMF 0x02 +#define USB_ST_DLMF 0x03 +#define USB_ST_TRF 0x04 +#define USB_ST_TCLF 0x05 +#define USB_ST_UF 0x06 +#define USB_ST_CSF 0x07 +#define USB_ST_TOMF 0x08 +#define USB_ST_USBTF 0x09 +#define USB_ST_NCT 0x0a +#define USB_ST_PUF 0x0b +#define USB_ST_EUF 0x0c +#define USB_ST_MCMF 0x0d +#define USB_ST_CCMF 0x0e +#define USB_ST_ENF 0x0f +#define USB_ST_ATMNF 0x10 + +#define USB_ST_WHCM 0x11 +#define USB_ST_MDLM 0x12 +#define USB_ST_MDLMD 0x13 +#define USB_ST_DMM 0x14 +#define USB_ST_OBEX 0x15 +#define USB_ST_CS 0x16 +#define USB_ST_CSD 0x17 +#define USB_ST_TCM 0x18 + +/* endpoint modifiers + * static struct usb_endpoint_description function_default_A_1[] = { + * + * {this_endpoint: 0, attributes: CONTROL, max_size: 8, polling_interval: 0 }, + * {this_endpoint: 1, attributes: BULK, max_size: 64, polling_interval: 0, direction: IN}, + * {this_endpoint: 2, attributes: BULK, max_size: 64, polling_interval: 0, direction: OUT}, + * {this_endpoint: 3, attributes: INTERRUPT, max_size: 8, polling_interval: 0}, + * + * + */ +#define OUT 0x00 +#define IN 0x80 + +#define CONTROL 0x00 +#define ISOCHRONOUS 0x01 +#define BULK 0x02 +#define INTERRUPT 0x03 + + +/* configuration modifiers + */ +#define BMATTRIBUTE_RESERVED 0x80 +#define BMATTRIBUTE_SELF_POWERED 0x40 + +/* + * standard usb descriptor structures + */ + +struct usb_endpoint_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x5 */ + u8 bEndpointAddress; + u8 bmAttributes; + u16 wMaxPacketSize; + u8 bInterval; +} __attribute__ ((packed)); + +struct usb_interface_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x04 */ + u8 bInterfaceNumber; + u8 bAlternateSetting; + u8 bNumEndpoints; + u8 bInterfaceClass; + u8 bInterfaceSubClass; + u8 bInterfaceProtocol; + u8 iInterface; +} __attribute__ ((packed)); + +struct usb_configuration_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x2 */ + u16 wTotalLength; + u8 bNumInterfaces; + u8 bConfigurationValue; + u8 iConfiguration; + u8 bmAttributes; + u8 bMaxPower; +} __attribute__ ((packed)); + +struct usb_device_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x01 */ + u16 bcdUSB; + u8 bDeviceClass; + u8 bDeviceSubClass; + u8 bDeviceProtocol; + u8 bMaxPacketSize0; + u16 idVendor; + u16 idProduct; + u16 bcdDevice; + u8 iManufacturer; + u8 iProduct; + u8 iSerialNumber; + u8 bNumConfigurations; +} __attribute__ ((packed)); + +#if defined(CONFIG_USBD_HS) +struct usb_qualifier_descriptor { + u8 bLength; + u8 bDescriptorType; + + u16 bcdUSB; + u8 bDeviceClass; + u8 bDeviceSubClass; + u8 bDeviceProtocol; + u8 bMaxPacketSize0; + u8 bNumConfigurations; + u8 breserved; +} __attribute__ ((packed)); +#endif + +struct usb_string_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x03 */ + u16 wData[0]; +} __attribute__ ((packed)); + +struct usb_generic_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; +} __attribute__ ((packed)); + + +/* + * communications class descriptor structures + * + * c.f. CDC 5.2 Table 25c + */ + +struct usb_class_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; +} __attribute__ ((packed)); + +struct usb_class_function_descriptor_generic { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_header_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x00 */ + u16 bcdCDC; +} __attribute__ ((packed)); + +struct usb_class_call_management_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x01 */ + u8 bmCapabilities; + u8 bDataInterface; +} __attribute__ ((packed)); + +struct usb_class_abstract_control_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x02 */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_direct_line_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x03 */ +} __attribute__ ((packed)); + +struct usb_class_telephone_ringer_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x04 */ + u8 bRingerVolSeps; + u8 bNumRingerPatterns; +} __attribute__ ((packed)); + +struct usb_class_telephone_call_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x05 */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_union_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x06 */ + u8 bMasterInterface; + /* u8 bSlaveInterface0[0]; */ + u8 bSlaveInterface0; +} __attribute__ ((packed)); + +struct usb_class_country_selection_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x07 */ + u8 iCountryCodeRelDate; + u16 wCountryCode0[0]; +} __attribute__ ((packed)); + + +struct usb_class_telephone_operational_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x08 */ + u8 bmCapabilities; +} __attribute__ ((packed)); + + +struct usb_class_usb_terminal_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x09 */ + u8 bEntityId; + u8 bInterfaceNo; + u8 bOutInterfaceNo; + u8 bmOptions; + u8 bChild0[0]; +} __attribute__ ((packed)); + +struct usb_class_network_channel_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0a */ + u8 bEntityId; + u8 iName; + u8 bChannelIndex; + u8 bPhysicalInterface; +} __attribute__ ((packed)); + +struct usb_class_protocol_unit_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0b */ + u8 bEntityId; + u8 bProtocol; + u8 bChild0[0]; +} __attribute__ ((packed)); + +struct usb_class_extension_unit_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0c */ + u8 bEntityId; + u8 bExtensionCode; + u8 iName; + u8 bChild0[0]; +} __attribute__ ((packed)); + +struct usb_class_multi_channel_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0d */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_capi_control_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0e */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_ethernet_networking_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0f */ + u8 iMACAddress; + u32 bmEthernetStatistics; + u16 wMaxSegmentSize; + u16 wNumberMCFilters; + u8 bNumberPowerFilters; +} __attribute__ ((packed)); + +struct usb_class_atm_networking_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x10 */ + u8 iEndSystermIdentifier; + u8 bmDataCapabilities; + u8 bmATMDeviceStatistics; + u16 wType2MaxSegmentSize; + u16 wType3MaxSegmentSize; + u16 wMaxVC; +} __attribute__ ((packed)); + + +struct usb_class_mdlm_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x12 */ + u16 bcdVersion; + u8 bGUID[16]; +} __attribute__ ((packed)); + +struct usb_class_mdlmd_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x13 */ + u8 bGuidDescriptorType; + u8 bDetailData[0]; + +} __attribute__ ((packed)); + +/* + * HID class descriptor structures + * + * c.f. HID 6.2.1 + */ + +struct usb_class_hid_descriptor { + u8 bLength; + u8 bDescriptorType; + u16 bcdCDC; + u8 bCountryCode; + u8 bNumDescriptors; /* 0x01 */ + u8 bDescriptorType0; + u16 wDescriptorLength0; + /* optional descriptors are not supported. */ +} __attribute__((packed)); + +struct usb_class_report_descriptor { + u8 bLength; /* dummy */ + u8 bDescriptorType; + u16 wLength; + u8 bData[0]; +} __attribute__((packed)); + +/* + * descriptor union structures + */ + +struct usb_descriptor { + union { + struct usb_generic_descriptor generic; + struct usb_endpoint_descriptor endpoint; + struct usb_interface_descriptor interface; + struct usb_configuration_descriptor configuration; + struct usb_device_descriptor device; + struct usb_string_descriptor string; + } descriptor; + +} __attribute__ ((packed)); + +struct usb_class_descriptor { + union { + struct usb_class_function_descriptor function; + struct usb_class_function_descriptor_generic generic; + struct usb_class_header_function_descriptor header_function; + struct usb_class_call_management_descriptor call_management; + struct usb_class_abstract_control_descriptor abstract_control; + struct usb_class_direct_line_descriptor direct_line; + struct usb_class_telephone_ringer_descriptor telephone_ringer; + struct usb_class_telephone_operational_descriptor telephone_operational; + struct usb_class_telephone_call_descriptor telephone_call; + struct usb_class_union_function_descriptor union_function; + struct usb_class_country_selection_descriptor country_selection; + struct usb_class_usb_terminal_descriptor usb_terminal; + struct usb_class_network_channel_descriptor network_channel; + struct usb_class_extension_unit_descriptor extension_unit; + struct usb_class_multi_channel_descriptor multi_channel; + struct usb_class_capi_control_descriptor capi_control; + struct usb_class_ethernet_networking_descriptor ethernet_networking; + struct usb_class_atm_networking_descriptor atm_networking; + struct usb_class_mdlm_descriptor mobile_direct; + struct usb_class_mdlmd_descriptor mobile_direct_detail; + struct usb_class_hid_descriptor hid; + } descriptor; + +} __attribute__ ((packed)); + +#ifdef DEBUG +static inline void print_device_descriptor(struct usb_device_descriptor *d) +{ + serial_printf("usb device descriptor \n"); + serial_printf("\tbLength %2.2x\n", d->bLength); + serial_printf("\tbDescriptorType %2.2x\n", d->bDescriptorType); + serial_printf("\tbcdUSB %4.4x\n", d->bcdUSB); + serial_printf("\tbDeviceClass %2.2x\n", d->bDeviceClass); + serial_printf("\tbDeviceSubClass %2.2x\n", d->bDeviceSubClass); + serial_printf("\tbDeviceProtocol %2.2x\n", d->bDeviceProtocol); + serial_printf("\tbMaxPacketSize0 %2.2x\n", d->bMaxPacketSize0); + serial_printf("\tidVendor %4.4x\n", d->idVendor); + serial_printf("\tidProduct %4.4x\n", d->idProduct); + serial_printf("\tbcdDevice %4.4x\n", d->bcdDevice); + serial_printf("\tiManufacturer %2.2x\n", d->iManufacturer); + serial_printf("\tiProduct %2.2x\n", d->iProduct); + serial_printf("\tiSerialNumber %2.2x\n", d->iSerialNumber); + serial_printf("\tbNumConfigurations %2.2x\n", d->bNumConfigurations); +} + +#else + +/* stubs */ +#define print_device_descriptor(d) + +#endif /* DEBUG */ +#endif diff --git a/A58-STEPLDR/Src/usb/include/usbdevice.h b/A58-STEPLDR/Src/usb/include/usbdevice.h new file mode 100644 index 00000000..f479724e --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/usbdevice.h @@ -0,0 +1,777 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on linux/drivers/usbd/usbd.h + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + */ + +#ifndef __USBDCORE_H__ +#define __USBDCORE_H__ + +#include +#include "usbdescriptors.h" + + +#define MAX_URBS_QUEUED 5 + + +#if 1 +#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#else +#define usberr(fmt,args...) do{}while(0) +#endif + +#if 0 +#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#else +#define usbdbg(fmt,args...) do{}while(0) +#endif + +#if 0 +#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#else +#define usbinfo(fmt,args...) do{}while(0) +#endif + +#ifndef le16_to_cpu +#define le16_to_cpu(x) (x) +#endif + +#ifndef inb +#define inb(p) (*(volatile u8*)(p)) +#endif + +#ifndef outb +#define outb(val,p) (*(volatile u8*)(p) = (val)) +#endif + +#ifndef inw +#define inw(p) (*(volatile u16*)(p)) +#endif + +#ifndef outw +#define outw(val,p) (*(volatile u16*)(p) = (val)) +#endif + +#ifndef inl +#define inl(p) (*(volatile u32*)(p)) +#endif + +#ifndef outl +#define outl(val,p) (*(volatile u32*)(p) = (val)) +#endif + +#ifndef insw +#define insw(p,to,len) mmio_insw(p,to,len) +#endif + +#ifndef outsw +#define outsw(p,from,len) mmio_outsw(p,from,len) +#endif + +#ifndef insb +#define insb(p,to,len) mmio_insb(p,to,len) +#endif + +#ifndef mmio_insw +#define mmio_insw(r,b,l) ({ int __i ; \ + u16 *__b2; \ + __b2 = (u16 *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = inw(r); \ + }; \ + }) +#endif + +#ifndef mmio_outsw +#define mmio_outsw(r,b,l) ({ int __i; \ + u16 *__b2; \ + __b2 = (u16 *) b; \ + for (__i = 0; __i < l; __i++) { \ + outw( *(__b2 + __i), r); \ + } \ + }) +#endif + +#ifndef mmio_insb +#define mmio_insb(r,b,l) ({ int __i ; \ + u8 *__b2; \ + __b2 = (u8 *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = inb(r); \ + }; \ + }) +#endif + +/* + * Structure member address manipulation macros. + * These are used by client code (code using the urb_link routines), since + * the urb_link structure is embedded in the client data structures. + * + * Note: a macro offsetof equivalent to member_offset is defined in stddef.h + * but this is kept here for the sake of portability. + * + * p2surround returns a pointer to the surrounding structure given + * type of the surrounding structure, the name memb of the structure + * member pointed at by ptr. For example, if you have: + * + * struct foo { + * int x; + * float y; + * char z; + * } thingy; + * + * char *cp = &thingy.z; + * + * then + * + * &thingy == p2surround(struct foo, z, cp) + * + * Clear? + */ +#define _cv_(ptr) ((char*)(void*)(ptr)) +#define member_offset(type,memb) (_cv_(&(((type*)0)->memb))-(char*)0) +#define p2surround(type,memb,ptr) ((type*)(void*)(_cv_(ptr)-member_offset(type,memb))) + +struct urb; + +struct usb_endpoint_instance; +struct usb_interface_instance; +struct usb_configuration_instance; +struct usb_device_instance; +struct usb_bus_instance; + +/* + * Device and/or Interface Class codes + */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PHYSICAL 5 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_DATA 10 +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff + +/* + * USB types + */ +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* + * USB recipients + */ +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + +/* + * USB directions + */ +#define USB_DIR_OUT 0 +#define USB_DIR_IN 0x80 + +/* + * Descriptor types + */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +#if defined(CONFIG_USBD_HS) +#define USB_DT_QUAL 0x06 +#endif + +#define USB_DT_HID (USB_TYPE_CLASS | 0x01) +#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) +#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) +#define USB_DT_HUB (USB_TYPE_CLASS | 0x09) + +/* + * Descriptor sizes per descriptor type + */ +#define USB_DT_DEVICE_SIZE 18 +#define USB_DT_CONFIG_SIZE 9 +#define USB_DT_INTERFACE_SIZE 9 +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ +#define USB_DT_HUB_NONVAR_SIZE 7 +#define USB_DT_HID_SIZE 9 + +/* + * Endpoints + */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 + +/* + * USB Packet IDs (PIDs) + */ +#define USB_PID_UNDEF_0 0xf0 +#define USB_PID_OUT 0xe1 +#define USB_PID_ACK 0xd2 +#define USB_PID_DATA0 0xc3 +#define USB_PID_PING 0xb4 /* USB 2.0 */ +#define USB_PID_SOF 0xa5 +#define USB_PID_NYET 0x96 /* USB 2.0 */ +#define USB_PID_DATA2 0x87 /* USB 2.0 */ +#define USB_PID_SPLIT 0x78 /* USB 2.0 */ +#define USB_PID_IN 0x69 +#define USB_PID_NAK 0x5a +#define USB_PID_DATA1 0x4b +#define USB_PID_PREAMBLE 0x3c /* Token mode */ +#define USB_PID_ERR 0x3c /* USB 2.0: handshake mode */ +#define USB_PID_SETUP 0x2d +#define USB_PID_STALL 0x1e +#define USB_PID_MDATA 0x0f /* USB 2.0 */ + +/* + * Standard requests + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USBD_DEVICE_REQUESTS(x) (((unsigned int)x <= USB_REQ_SYNCH_FRAME) ? usbd_device_requests[x] : "UNKNOWN") + +/* + * HID requests + */ +#define USB_REQ_GET_REPORT 0x01 +#define USB_REQ_GET_IDLE 0x02 +#define USB_REQ_GET_PROTOCOL 0x03 +#define USB_REQ_SET_REPORT 0x09 +#define USB_REQ_SET_IDLE 0x0A +#define USB_REQ_SET_PROTOCOL 0x0B + + +/* + * USB Spec Release number + */ + +#if defined(CONFIG_USBD_HS) +#define USB_BCD_VERSION 0x0200 +#else +#define USB_BCD_VERSION 0x0110 +#endif + + +/* + * Device Requests (c.f Table 9-2) + */ + +#define USB_REQ_DIRECTION_MASK 0x80 +#define USB_REQ_TYPE_MASK 0x60 +#define USB_REQ_RECIPIENT_MASK 0x1f + +#define USB_REQ_DEVICE2HOST 0x80 +#define USB_REQ_HOST2DEVICE 0x00 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_OTHER 0x03 + +/* + * get status bits + */ + +#define USB_STATUS_SELFPOWERED 0x01 +#define USB_STATUS_REMOTEWAKEUP 0x02 + +#define USB_STATUS_HALT 0x01 + +/* + * descriptor types + */ + +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01 +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define USB_DESCRIPTOR_TYPE_STRING 0x03 +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04 +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05 +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06 +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07 +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08 +#define USB_DESCRIPTOR_TYPE_HID 0x21 +#define USB_DESCRIPTOR_TYPE_REPORT 0x22 + +#define USBD_DEVICE_DESCRIPTORS(x) (((unsigned int)x <= USB_DESCRIPTOR_TYPE_INTERFACE_POWER) ? \ + usbd_device_descriptors[x] : "UNKNOWN") + +/* + * standard feature selectors + */ +#define USB_ENDPOINT_HALT 0x00 +#define USB_DEVICE_REMOTE_WAKEUP 0x01 +#define USB_TEST_MODE 0x02 + + +/* USB Requests + * + */ + +struct usb_device_request { + u8 bmRequestType; + u8 bRequest; + u16 wValue; + u16 wIndex; + u16 wLength; +} __attribute__ ((packed)); + + +/* USB Status + * + */ +typedef enum urb_send_status { + SEND_IN_PROGRESS, + SEND_FINISHED_OK, + SEND_FINISHED_ERROR, + RECV_READY, + RECV_OK, + RECV_ERROR +} urb_send_status_t; + +/* + * Device State (c.f USB Spec 2.0 Figure 9-1) + * + * What state the usb device is in. + * + * Note the state does not change if the device is suspended, we simply set a + * flag to show that it is suspended. + * + */ +typedef enum usb_device_state { + STATE_INIT, /* just initialized */ + STATE_CREATED, /* just created */ + STATE_ATTACHED, /* we are attached */ + STATE_POWERED, /* we have seen power indication (electrical bus signal) */ + STATE_DEFAULT, /* we been reset */ + STATE_ADDRESSED, /* we have been addressed (in default configuration) */ + STATE_CONFIGURED, /* we have seen a set configuration device command */ + STATE_UNKNOWN, /* destroyed */ +} usb_device_state_t; + +#define USBD_DEVICE_STATE(x) (((unsigned int)x <= STATE_UNKNOWN) ? usbd_device_states[x] : "UNKNOWN") + +/* + * Device status + * + * Overall state + */ +typedef enum usb_device_status { + USBD_OPENING, /* we are currently opening */ + USBD_OK, /* ok to use */ + USBD_SUSPENDED, /* we are currently suspended */ + USBD_CLOSING, /* we are currently closing */ +} usb_device_status_t; + +#define USBD_DEVICE_STATUS(x) (((unsigned int)x <= USBD_CLOSING) ? usbd_device_status[x] : "UNKNOWN") + +/* + * Device Events + * + * These are defined in the USB Spec (c.f USB Spec 2.0 Figure 9-1). + * + * There are additional events defined to handle some extra actions we need + * to have handled. + * + */ +typedef enum usb_device_event { + + DEVICE_UNKNOWN, /* bi - unknown event */ + DEVICE_INIT, /* bi - initialize */ + DEVICE_CREATE, /* bi - */ + DEVICE_HUB_CONFIGURED, /* bi - bus has been plugged int */ + DEVICE_RESET, /* bi - hub has powered our port */ + + DEVICE_ADDRESS_ASSIGNED, /* ep0 - set address setup received */ + DEVICE_CONFIGURED, /* ep0 - set configure setup received */ + DEVICE_SET_INTERFACE, /* ep0 - set interface setup received */ + + DEVICE_SET_FEATURE, /* ep0 - set feature setup received */ + DEVICE_CLEAR_FEATURE, /* ep0 - clear feature setup received */ + + DEVICE_DE_CONFIGURED, /* ep0 - set configure setup received for ?? */ + + DEVICE_BUS_INACTIVE, /* bi - bus in inactive (no SOF packets) */ + DEVICE_BUS_ACTIVITY, /* bi - bus is active again */ + + DEVICE_POWER_INTERRUPTION, /* bi - hub has depowered our port */ + DEVICE_HUB_RESET, /* bi - bus has been unplugged */ + DEVICE_DESTROY, /* bi - device instance should be destroyed */ + + DEVICE_HOTPLUG, /* bi - a hotplug event has occurred */ + + DEVICE_FUNCTION_PRIVATE, /* function - private */ + +} usb_device_event_t; + + +typedef struct urb_link { + struct urb_link *next; + struct urb_link *prev; +} urb_link; + +/* USB Data structure - for passing data around. + * + * This is used for both sending and receiving data. + * + * The callback function is used to let the function driver know when + * transmitted data has been sent. + * + * The callback function is set by the alloc_recv function when an urb is + * allocated for receiving data for an endpoint and used to call the + * function driver to inform it that data has arrived. + */ + +/* in linux we'd malloc this, but in u-boot we prefer static data */ +#define URB_BUF_SIZE 512 + +struct urb { + + struct usb_endpoint_instance *endpoint; + struct usb_device_instance *device; + + struct usb_device_request device_request; /* contents of received SETUP packet */ + + struct urb_link link; /* embedded struct for circular doubly linked list of urbs */ + + u8* buffer; + unsigned int buffer_length; + unsigned int actual_length; + + urb_send_status_t status; + int data; + + u16 buffer_data[URB_BUF_SIZE]; /* data received (OUT) or being sent (IN) */ +}; + +/* Endpoint configuration + * + * Per endpoint configuration data. Used to track which function driver owns + * an endpoint. + * + */ +struct usb_endpoint_instance { + int endpoint_address; /* logical endpoint address */ + + /* control */ + int status; /* halted */ + int state; /* available for use by bus interface driver */ + + /* receive side */ + struct urb_link rcv; /* received urbs */ + struct urb_link rdy; /* empty urbs ready to receive */ + struct urb *rcv_urb; /* active urb */ + int rcv_attributes; /* copy of bmAttributes from endpoint descriptor */ + int rcv_packetSize; /* maximum packet size from endpoint descriptor */ + int rcv_transferSize; /* maximum transfer size from function driver */ + int rcv_queue; + + /* transmit side */ + struct urb_link tx; /* urbs ready to transmit */ + struct urb_link done; /* transmitted urbs */ + struct urb *tx_urb; /* active urb */ + int tx_attributes; /* copy of bmAttributes from endpoint descriptor */ + int tx_packetSize; /* maximum packet size from endpoint descriptor */ + int tx_transferSize; /* maximum transfer size from function driver */ + int tx_queue; + + int sent; /* data already sent */ + int last; /* data sent in last packet XXX do we need this */ +}; + +struct usb_alternate_instance { + struct usb_interface_descriptor *interface_descriptor; + + int endpoints; + int *endpoint_transfersize_array; + struct usb_endpoint_descriptor **endpoints_descriptor_array; +}; + +struct usb_interface_instance { + int alternates; + struct usb_alternate_instance *alternates_instance_array; +}; + +struct usb_configuration_instance { + int interfaces; + struct usb_configuration_descriptor *configuration_descriptor; + struct usb_interface_instance *interface_instance_array; +}; + + +/* USB Device Instance + * + * For each physical bus interface we create a logical device structure. This + * tracks all of the required state to track the USB HOST's view of the device. + * + * Keep track of the device configuration for a real physical bus interface, + * this includes the bus interface, multiple function drivers, the current + * configuration and the current state. + * + * This will show: + * the specific bus interface driver + * the default endpoint 0 driver + * the configured function driver + * device state + * device status + * endpoint list + */ + +struct usb_device_instance { + + /* generic */ + char *name; + struct usb_device_descriptor *device_descriptor; /* per device descriptor */ +#if defined(CONFIG_USBD_HS) + struct usb_qualifier_descriptor *qualifier_descriptor; +#endif + + void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data); + + /* Do cdc device specific control requests */ + int (*cdc_recv_setup)(struct usb_device_request *request, struct urb *urb); + + /* bus interface */ + struct usb_bus_instance *bus; /* which bus interface driver */ + + /* configuration descriptors */ + int configurations; + struct usb_configuration_instance *configuration_instance_array; + + /* device state */ + usb_device_state_t device_state; /* current USB Device state */ + usb_device_state_t device_previous_state; /* current USB Device state */ + + u8 address; /* current address (zero is default) */ + u8 configuration; /* current show configuration (zero is default) */ + u8 interface; /* current interface (zero is default) */ + u8 alternate; /* alternate flag */ + + usb_device_status_t status; /* device status */ + + int urbs_queued; /* number of submitted urbs */ + + /* Shouldn't need to make this atomic, all we need is a change indicator */ + unsigned long usbd_rxtx_timestamp; + unsigned long usbd_last_rxtx_timestamp; + +}; + +/* Bus Interface configuration structure + * + * This is allocated for each configured instance of a bus interface driver. + * + * The privdata pointer may be used by the bus interface driver to store private + * per instance state information. + */ +struct usb_bus_instance { + + struct usb_device_instance *device; + struct usb_endpoint_instance *endpoint_array; /* array of available configured endpoints */ + + int max_endpoints; /* maximimum number of rx enpoints */ + unsigned char maxpacketsize; + + unsigned int serial_number; + char *serial_number_str; + void *privdata; /* private data for the bus interface */ + +}; + +extern char *usbd_device_events[]; +extern char *usbd_device_states[]; +extern char *usbd_device_status[]; +extern char *usbd_device_requests[]; +extern char *usbd_device_descriptors[]; + +void urb_link_init (urb_link * ul); +void urb_detach (struct urb *urb); +urb_link *first_urb_link (urb_link * hd); +struct urb *first_urb (urb_link * hd); +struct urb *first_urb_detached (urb_link * hd); +void urb_append (urb_link * hd, struct urb *urb); + +struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint); +void usbd_dealloc_urb (struct urb *urb); + +/* + * usbd_device_event is used by bus interface drivers to tell the higher layers that + * certain events have taken place. + */ +void usbd_device_event_irq (struct usb_device_instance *conf, usb_device_event_t, int); +void usbd_device_event (struct usb_device_instance *conf, usb_device_event_t, int); + +/* descriptors + * + * Various ways of finding descriptors based on the current device and any + * possible configuration / interface / endpoint for it. + */ +struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct usb_device_instance *, int, int); +struct usb_function_instance *usbd_device_function_instance (struct usb_device_instance *, unsigned int); +struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *, int, int, int); +struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *, int, int, int, int); +struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance *, int, int, int, int); +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance *, int, int, int, int, int); +struct usb_class_descriptor *usbd_device_class_descriptor_index (struct usb_device_instance *, int, int, int, int, int); +struct usb_class_report_descriptor *usbd_device_class_report_descriptor_index( struct usb_device_instance *, int , int , int , int , int ); +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *, int, int, int, int, int); +int usbd_device_endpoint_transfersize (struct usb_device_instance *, int, int, int, int, int); +struct usb_string_descriptor *usbd_get_string (u8); +struct usb_device_descriptor *usbd_device_device_descriptor(struct + usb_device_instance *, int); + +#if defined(CONFIG_USBD_HS) +/* + * is_usbd_high_speed routine needs to be defined by specific gadget driver + * It returns true if device enumerates at High speed + * Retuns false otherwise + */ +int is_usbd_high_speed(void); +#endif +int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint); +void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad); +void usbd_tx_complete (struct usb_endpoint_instance *endpoint); + +/* These are macros used in debugging */ +#ifdef DEBUG +static inline void print_urb(struct urb *u) +{ + serial_printf("urb %p\n", (u)); + serial_printf("\tendpoint %p\n", u->endpoint); + serial_printf("\tdevice %p\n", u->device); + serial_printf("\tbuffer %p\n", u->buffer); + serial_printf("\tbuffer_length %d\n", u->buffer_length); + serial_printf("\tactual_length %d\n", u->actual_length); + serial_printf("\tstatus %d\n", u->status); + serial_printf("\tdata %d\n", u->data); +} + +static inline void print_usb_device_request(struct usb_device_request *r) +{ + serial_printf("usb request\n"); + serial_printf("\tbmRequestType 0x%2.2x\n", r->bmRequestType); + if ((r->bmRequestType & USB_REQ_DIRECTION_MASK) == 0) + serial_printf("\t\tDirection : To device\n"); + else + serial_printf("\t\tDirection : To host\n"); + if ((r->bmRequestType & USB_TYPE_STANDARD) == USB_TYPE_STANDARD) + serial_printf("\t\tType : Standard\n"); + if ((r->bmRequestType & USB_TYPE_CLASS) == USB_TYPE_CLASS) + serial_printf("\t\tType : Standard\n"); + if ((r->bmRequestType & USB_TYPE_VENDOR) == USB_TYPE_VENDOR) + serial_printf("\t\tType : Standard\n"); + if ((r->bmRequestType & USB_TYPE_RESERVED) == USB_TYPE_RESERVED) + serial_printf("\t\tType : Standard\n"); + if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) + serial_printf("\t\tRecipient : Device\n"); + if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_INTERFACE) + serial_printf("\t\tRecipient : Interface\n"); + if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_ENDPOINT) + serial_printf("\t\tRecipient : Endpoint\n"); + if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_OTHER) + serial_printf("\t\tRecipient : Other\n"); + serial_printf("\tbRequest 0x%2.2x\n", r->bRequest); + if (r->bRequest == USB_REQ_GET_STATUS) + serial_printf("\t\tGET_STATUS\n"); + else if (r->bRequest == USB_REQ_SET_ADDRESS) + serial_printf("\t\tSET_ADDRESS\n"); + else if (r->bRequest == USB_REQ_SET_FEATURE) + serial_printf("\t\tSET_FEATURE\n"); + else if (r->bRequest == USB_REQ_GET_DESCRIPTOR) + serial_printf("\t\tGET_DESCRIPTOR\n"); + else if (r->bRequest == USB_REQ_SET_CONFIGURATION) + serial_printf("\t\tSET_CONFIGURATION\n"); + else if (r->bRequest == USB_REQ_SET_INTERFACE) + serial_printf("\t\tUSB_REQ_SET_INTERFACE\n"); + else + serial_printf("\tUNKNOWN %d\n", r->bRequest); + serial_printf("\twValue 0x%4.4x\n", r->wValue); + if (r->bRequest == USB_REQ_GET_DESCRIPTOR) { + switch (r->wValue >> 8) { + case USB_DESCRIPTOR_TYPE_DEVICE: + serial_printf("\tDEVICE\n"); + break; + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + serial_printf("\tCONFIGURATION\n"); + break; + case USB_DESCRIPTOR_TYPE_STRING: + serial_printf("\tSTRING\n"); + break; + case USB_DESCRIPTOR_TYPE_INTERFACE: + serial_printf("\tINTERFACE\n"); + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + serial_printf("\tENDPOINT\n"); + break; + case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: + serial_printf("\tDEVICE_QUALIFIER\n"); + break; + case USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION: + serial_printf("\tOTHER_SPEED_CONFIGURATION\n"); + break; + case USB_DESCRIPTOR_TYPE_INTERFACE_POWER: + serial_printf("\tINTERFACE_POWER\n"); + break; + case USB_DESCRIPTOR_TYPE_HID: + serial_printf("\tHID\n"); + break; + case USB_DESCRIPTOR_TYPE_REPORT: + serial_printf("\tREPORT\n"); + break; + default: + serial_printf("\tUNKNOWN TYPE\n"); + break; + } + } + serial_printf("\twIndex 0x%4.4x\n", r->wIndex); + serial_printf("\twLength 0x%4.4x\n", r->wLength); +} +#else +/* stubs */ +#define print_urb(u) +#define print_usb_device_request(r) +#endif /* DEBUG */ +#endif diff --git a/A58-STEPLDR/Src/usb/include/usbroothubdes.h b/A58-STEPLDR/Src/usb/include/usbroothubdes.h new file mode 100644 index 00000000..e743555d --- /dev/null +++ b/A58-STEPLDR/Src/usb/include/usbroothubdes.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * USB virtual root hub descriptors + * + * (C) Copyright 2014 + * Stephen Warren swarren@wwwdotorg.org + * + * Based on ohci-hcd.c + */ + +#ifndef __USBROOTHUBDES_H__ +#define __USBROOTHUBDES_H__ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01, /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + * Bit 7: Bus-powered + * 6: Self-powered, + * 5 Remote-wakwup, + * 4..0: resvd + */ + 0x00, /* __u8 MaxPower; */ + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff, /* __u8 ep_bInterval; 255 ms */ +}; + +#ifdef WANT_USB_ROOT_HUB_HUB_DES +static unsigned char root_hub_hub_des[] = { + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x02, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff, /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; +#endif + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 32, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'U', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + '-', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'B', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +#endif diff --git a/A58-STEPLDR/Src/usb/params.c b/A58-STEPLDR/Src/usb/params.c new file mode 100644 index 00000000..a7b06511 --- /dev/null +++ b/A58-STEPLDR/Src/usb/params.c @@ -0,0 +1,382 @@ +/* + * Copyright (C) 2004-2016 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include + +#include "core.h" +#include "board.h" + +/* static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->host_rx_fifo_size = 774; + p->max_transfer_size = 65535; + p->max_packet_count = 511; + p->ahbcfg = 0x10; + p->uframe_sched = false; +} + +static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; + p->speed = DWC2_SPEED_PARAM_HIGH; + p->host_rx_fifo_size = 512; + p->host_nperio_tx_fifo_size = 512; + p->host_perio_tx_fifo_size = 512; + p->max_transfer_size = 65535; + p->max_packet_count = 511; + p->host_channels = 16; + p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; + p->phy_utmi_width = 8; + p->i2c_enable = false; + p->reload_ctl = false; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; + p->uframe_sched = false; + p->change_speed_quirk = true; +} + +static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; + p->host_rx_fifo_size = 525; + p->host_nperio_tx_fifo_size = 128; + p->host_perio_tx_fifo_size = 256; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; +} + +static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->otg_cap = 2; + p->host_rx_fifo_size = 288; + p->host_nperio_tx_fifo_size = 128; + p->host_perio_tx_fifo_size = 96; + p->max_transfer_size = 65535; + p->max_packet_count = 511; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << + GAHBCFG_HBSTLEN_SHIFT; +} + +static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; + p->speed = DWC2_SPEED_PARAM_HIGH; + p->host_rx_fifo_size = 512; + p->host_nperio_tx_fifo_size = 500; + p->host_perio_tx_fifo_size = 500; + p->host_channels = 16; + p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << + GAHBCFG_HBSTLEN_SHIFT; + p->uframe_sched = false; +} + +static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; +} + +static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; + p->speed = DWC2_SPEED_PARAM_FULL; + p->host_rx_fifo_size = 128; + p->host_nperio_tx_fifo_size = 96; + p->host_perio_tx_fifo_size = 96; + p->max_packet_count = 256; + p->phy_type = DWC2_PHY_TYPE_PARAM_FS; + p->i2c_enable = false; + p->uframe_sched = false; + p->activate_stm_fs_transceiver = true; +} */ + +static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) +{ + u8 val; + + switch (hsotg->hw_params.op_mode) { + case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: + val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; + break; + case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: + case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: + case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: + val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; + break; + default: + val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; + break; + } + + hsotg->params.otg_cap = val; +} + +static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) +{ + int val; + u32 hs_phy_type = hsotg->hw_params.hs_phy_type; + + val = DWC2_PHY_TYPE_PARAM_FS; + if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { + if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || + hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) + val = DWC2_PHY_TYPE_PARAM_UTMI; + else + val = DWC2_PHY_TYPE_PARAM_ULPI; + } + + if (dwc2_is_fs_iot(hsotg)) + hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; + + hsotg->params.phy_type = val; +} + +static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) +{ + int val; + + val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? + DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; + + if (dwc2_is_fs_iot(hsotg)) + val = DWC2_SPEED_PARAM_FULL; + + if (dwc2_is_hs_iot(hsotg)) + val = DWC2_SPEED_PARAM_HIGH; + + hsotg->params.speed = val; +} + +static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) +{ + int val; + + val = (hsotg->hw_params.utmi_phy_data_width == + GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; + + hsotg->params.phy_utmi_width = val; +} + +/** + * dwc2_set_default_params() - Set all core parameters to their + * auto-detected default values. + */ +static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_hw_params *hw = &hsotg->hw_params; + struct dwc2_core_params *p = &hsotg->params; +#ifdef USB_DMA + bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); +#endif + + dwc2_set_param_otg_cap(hsotg); + dwc2_set_param_phy_type(hsotg); + dwc2_set_param_speed(hsotg); + dwc2_set_param_phy_utmi_width(hsotg); + + p->enable_dynamic_fifo = hw->enable_dynamic_fifo; + p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; + p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); + p->max_packet_count = hw->max_packet_count; + p->max_transfer_size = hw->max_transfer_size; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; + + if ((hsotg->dr_mode == USB_DR_MODE_HOST) || + (hsotg->dr_mode == USB_DR_MODE_OTG)) { + p->host_channels = hw->host_channels; + p->host_rx_fifo_size = hw->rx_fifo_size; + p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; + p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; + } +} + +/* + * Gets host hardware parameters. Forces host mode if not currently in + * host mode. Should be called immediately after a core soft reset in + * order to get the reset values. + */ +static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) +{ + struct dwc2_hw_params *hw = &hsotg->hw_params; + u32 gnptxfsiz; + u32 hptxfsiz; + + gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); + hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); + + hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> + FIFOSIZE_DEPTH_SHIFT; + hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> + FIFOSIZE_DEPTH_SHIFT; +} + +/* + * Gets device hardware parameters. Forces device mode if not + * currently in device mode. Should be called immediately after a core + * soft reset in order to get the reset values. + */ +static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) +{ + struct dwc2_hw_params *hw = &hsotg->hw_params; + u32 gnptxfsiz; + + if (hsotg->dr_mode == USB_DR_MODE_HOST) + return; + + gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); + + hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> + FIFOSIZE_DEPTH_SHIFT; +} + +/** + * During device initialization, read various hardware configuration + * registers and interpret the contents. + */ +int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) +{ + struct dwc2_hw_params *hw = &hsotg->hw_params; + unsigned int width; + u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; + u32 grxfsiz; + + /* + * Attempt to ensure this device is really a DWC_otg Controller. + * Read and verify the GSNPSID register contents. The value should be + * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", + * as in "OTG version 2.xx" or "OTG version 3.xx". + */ + hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); + if ((hw->snpsid & 0xfffff000) != 0x4f542000 && + (hw->snpsid & 0xfffff000) != 0x4f543000 && + (hw->snpsid & 0xffff0000) != 0x55310000 && + (hw->snpsid & 0xffff0000) != 0x55320000) { + dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", + hw->snpsid); + return -ENODEV; + } + + dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", + hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, + hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); + + hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); + hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); + hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); + hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); + grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + + /* + * Host specific hardware parameters. Reading these parameters + * requires the controller to be in host mode. The mode will + * be forced, if necessary, to read these values. + */ + dwc2_get_host_hwparams(hsotg); + dwc2_get_dev_hwparams(hsotg); + + /* hwcfg1 */ + hw->dev_ep_dirs = hwcfg1; + + /* hwcfg2 */ + hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> + GHWCFG2_OP_MODE_SHIFT; + hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> + GHWCFG2_ARCHITECTURE_SHIFT; + hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); + hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> + GHWCFG2_NUM_HOST_CHAN_SHIFT); + hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> + GHWCFG2_HS_PHY_TYPE_SHIFT; + hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> + GHWCFG2_FS_PHY_TYPE_SHIFT; + hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> + GHWCFG2_NUM_DEV_EP_SHIFT; + hw->nperio_tx_q_depth = + (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> + GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; + hw->host_perio_tx_q_depth = + (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> + GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; + hw->dev_token_q_depth = + (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> + GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; + + /* hwcfg3 */ + width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> + GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; + hw->max_transfer_size = (1 << (width + 11)) - 1; + width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> + GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; + hw->max_packet_count = (1 << (width + 4)) - 1; + hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> + GHWCFG3_DFIFO_DEPTH_SHIFT; + + /* hwcfg4 */ + hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); + hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> + GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; + hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); + hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> + GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; + + /* fifo sizes */ + hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> + GRXFSIZ_DEPTH_SHIFT; + + return 0; +} + +int dwc2_init_params(struct dwc2_hsotg *hsotg) +{ + dwc2_set_default_params(hsotg); + + return 0; +} diff --git a/A58-STEPLDR/Src/usb/platform.c b/A58-STEPLDR/Src/usb/platform.c new file mode 100644 index 00000000..8376d964 --- /dev/null +++ b/A58-STEPLDR/Src/usb/platform.c @@ -0,0 +1,176 @@ +/* + * platform.c - DesignWare HS OTG Controller platform driver + * + * Copyright (C) Matthijs Kooijman + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include +#include +#include "core.h" +#include "hcd.h" +#include "amt630h.h" +#include "aic.h" + +static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) +{ + hsotg->dr_mode = USB_DR_MODE_HOST; + + return 0; +} + +//static QueueHandle_t usb_irq_queue; +//static TaskHandle_t usb_irq_task; +//static char first_irq = 1; + +static void ark_usb_interrupt(void *param) +{ + struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)param; + //printf("ark_usb_interrupt\r\n"); + dwc2_handle_common_intr(hsotg->irq, param); + dwc2_hcd_irq(hsotg); + /*if (first_irq) { + dwc2_hcd_irq(hsotg); + first_irq = 0; + } else { + portDISABLE_INTERRUPTS(); + xQueueSendFromISR(usb_irq_queue, NULL, 0); + }*/ +} + +#if 0 +static void usb_irq_task_proc(void *pvParameters) +{ + struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)pvParameters; + int ret = -1; + + while(1) { + ret = xQueueReceive(usb_irq_queue, NULL, portMAX_DELAY); + + if (pdFALSE == ret) { + continue; + } + //portENTER_CRITICAL(); + + dwc2_hcd_irq(hsotg); + portENABLE_INTERRUPTS(); + //portEXIT_CRITICAL(); + } +} +#endif + +int dwc2_driver_init(struct dwc2_hsotg **dev, struct usb_hcd *hcd) +{ + struct dwc2_hsotg *hsotg; + int retval = -1; + u32 size = sizeof(struct device); + + hsotg = devm_kzalloc(NULL, sizeof(*hsotg), GFP_KERNEL); + if (!hsotg) + return -ENOMEM; + + hsotg->dev = (struct device *)kzalloc(size, (__GFP_ZERO | GFP_KERNEL)); + if (NULL == hsotg->dev) + goto error; + + hsotg->phyif = GUSBCFG_PHYIF16; + hsotg->regs = REGS_USB_BASE; + + spin_lock_init(&(hsotg->lock)); + + hsotg->irq = USB_IRQn; + retval = request_irq(hsotg->irq, 0, ark_usb_interrupt, (void*)hsotg); + if (retval) + goto error; + + retval = dwc2_get_dr_mode(hsotg); + if (retval) + goto error; + + /* + * Reset before dwc2_get_hwparams() then it could get power-on real + * reset value form registers. + */ + dwc2_core_reset_and_force_dr_mode(hsotg); + + /* Detect config values from hardware */ + retval = dwc2_get_hwparams(hsotg); + if (retval) + goto error; + + dwc2_force_dr_mode(hsotg); + + retval = dwc2_init_params(hsotg); + if (retval) + goto error; + + if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { + //usb_irq_queue = xQueueCreate(1, 0); + //xTaskCreate(usb_irq_task_proc, "usb_irq_proc", configMINIMAL_STACK_SIZE * 5, (void*)dev, configMAX_PRIORITIES, &usb_irq_task); + retval = dwc2_hcd_init(hsotg, hcd); + if (retval) { + goto error; + } + hsotg->hcd_enabled = 1; + } + + if (dev) { + *dev = hsotg; + } + + return 0; + +error: + if (hsotg && hsotg->dev) { + kfree(hsotg->dev); + } + if (hsotg) { + kfree(hsotg); + } + return retval; +} + +int dwc2_driver_uninit(struct dwc2_hsotg *hsotg) +{ + if (NULL == hsotg) + return 0; + if (hsotg->hcd_enabled) + dwc2_hcd_remove(hsotg); + + if (hsotg->dev) + kfree(hsotg->dev); + + kfree(hsotg); + return 0; +} diff --git a/A58-STEPLDR/Src/usb/usb-compat.h b/A58-STEPLDR/Src/usb/usb-compat.h new file mode 100644 index 00000000..674f897d --- /dev/null +++ b/A58-STEPLDR/Src/usb/usb-compat.h @@ -0,0 +1,253 @@ +#ifndef __USB_COMPAT_H__ +#define __USB_COMPAT_H__ + +//#include +#include "usb.h" +#include "timer.h" + + +struct usb_bus { + int busnum; /* Bus number (in order of reg) */ + const char *bus_name; /* stable id (PCI slot_name etc) */ + u8 uses_dma; /* Does the host controller use DMA? */ + u8 uses_pio_for_control; /* + * Does the host controller use PIO + * for control transfers? + */ + u8 otg_port; /* 0, or number of OTG/HNP port */ + unsigned is_b_host:1; /* true during some HNP roleswitches */ + unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */ + unsigned no_stop_on_short:1; /* + * Quirk: some controllers don't stop + * the ep queue on a short transfer + * with the URB_SHORT_NOT_OK flag set. + */ + unsigned no_sg_constraint:1; /* no sg constraint */ + unsigned sg_tablesize; /* 0 or largest number of sg list entries */ + + int devnum_next; /* Next open device number in + * round-robin allocation */ + + int bandwidth_allocated; /* on this bus: how much of the time + * reserved for periodic (intr/iso) + * requests is used, on average? + * Units: microseconds/frame. + * Limits: Full/low speed reserve 90%, + * while high speed reserves 80%. + */ + int bandwidth_int_reqs; /* number of Interrupt requests */ + int bandwidth_isoc_reqs; /* number of Isoc. requests */ + + unsigned resuming_ports; /* bit array: resuming root-hub ports */ +}; + + +struct usb_hcd { + struct usb_bus self; + int has_tt; + void *hcd_priv; +}; + +struct usb_host_endpoint { + struct usb_endpoint_descriptor desc; + List_t urb_list; + void *hcpriv; +}; + +/* + * urb->transfer_flags: + * + * Note: URB_DIR_IN/OUT is automatically set in usb_submit_urb(). + */ +#define URB_SHORT_NOT_OK 0x0001 /* report short reads as errors */ +#define URB_ZERO_PACKET 0x0040 /* Finish bulk OUT with short packet */ +#define URB_NO_INTERRUPT 0x0080 /* HINT: no non-error interrupt*/ + +struct urb; + +typedef void (*usb_complete_t)(struct urb *); + +struct urb { + void *hcpriv; /* private data for host controller */ + ListItem_t urb_list; + int urb_complete; + struct usb_device *dev; /* (in) pointer to associated device */ + struct usb_host_endpoint *ep; /* (internal) pointer to endpoint */ + unsigned int pipe; /* (in) pipe information */ + int status; /* (return) non-ISO status */ + unsigned int transfer_flags; /* (in) URB_SHORT_NOT_OK | ...*/ + void *transfer_buffer; /* (in) associated data buffer */ + dma_addr_t transfer_dma; /* (in) dma addr for transfer_buffer */ + u32 transfer_buffer_length; /* (in) data buffer length */ + u32 actual_length; /* (return) actual transfer length */ + unsigned char *setup_packet; /* (in) setup packet (control only) */ + dma_addr_t setup_dma; + int start_frame; /* (modify) start frame (ISO) */ + void *context; + usb_complete_t complete; /* (in) completion routine */ + int interval; + + int error_count; /* (return) number of ISO errors */ + int number_of_packets; /* (in) number of ISO packets */ +}; + +struct hc_driver { + const char *description; /* "ehci-hcd" etc */ + const char *product_desc; /* product/vendor string */ + size_t hcd_priv_size; /* size of private data */ + + /* irq handler */ + irqreturn_t (*irq) (struct usb_hcd *hcd); + + int flags; +#define HCD_MEMORY 0x0001 /* HC regs use memory (else I/O) */ +#define HCD_LOCAL_MEM 0x0002 /* HC needs local memory */ +#define HCD_SHARED 0x0004 /* Two (or more) usb_hcds share HW */ +#define HCD_USB11 0x0010 /* USB 1.1 */ +#define HCD_USB2 0x0020 /* USB 2.0 */ +#define HCD_USB25 0x0030 /* Wireless USB 1.0 (USB 2.5)*/ +#define HCD_USB3 0x0040 /* USB 3.0 */ +#define HCD_USB31 0x0050 /* USB 3.1 */ +#define HCD_MASK 0x0070 +#define HCD_BH 0x0100 /* URB complete in BH context */ + + /* called to init HCD and root hub */ + int (*start) (struct usb_hcd *hcd); + + /* cleanly make HCD stop writing memory and doing I/O */ + void (*stop) (struct usb_hcd *hcd); + + /* return current frame number */ + int (*get_frame_number) (struct usb_hcd *hcd); + + /* manage i/o requests, device state */ + int (*urb_enqueue)(struct usb_hcd *hcd, + struct urb *urb, gfp_t mem_flags); + int (*urb_dequeue)(struct usb_hcd *hcd, + struct urb *urb, int status); + + /* hw synch, freeing endpoint resources that urb_dequeue can't */ + void (*endpoint_disable)(struct usb_hcd *hcd, + struct usb_host_endpoint *ep); + + /* (optional) reset any endpoint state such as sequence number + and current window */ + void (*endpoint_reset)(struct usb_hcd *hcd, + struct usb_host_endpoint *ep); + + /* root hub support */ + int (*hub_status_data) (struct usb_hcd *hcd, char *buf); + int (*hub_control) (struct usb_hcd *hcd, + u16 typeReq, u16 wValue, u16 wIndex, + char *buf, u16 wLength); +}; + +#define usb_hcd_link_urb_to_ep(hcd, urb) do { \ + list_add_tail(&urb->urb_list, &urb->ep->urb_list); \ +} while(0) + +#define usb_hcd_unlink_urb_from_ep(hcd, urb) list_del_init(&urb->urb_list) +#define usb_hcd_check_unlink_urb(hdc, urb, status) 0 + +static inline void usb_hcd_giveback_urb(struct usb_hcd *hcd, + struct urb *urb, + int status) +{ + urb->status = status; + if (urb->complete) + urb->complete(urb); +} + +static inline int usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, + struct urb *urb) +{ + /* TODO: add cache invalidation here */ + return 0; +} + +static inline struct usb_bus *hcd_to_bus(struct usb_hcd *hcd) +{ + return &hcd->self; +} + +static inline void usb_hcd_resume_root_hub(struct usb_hcd *hcd) +{ + (void)hcd; + return; +} + +/* + * Generic bandwidth allocation constants/support + */ +#define FRAME_TIME_USECS 1000L +#define BitTime(bytecount) (7 * 8 * bytecount / 6) /* with integer truncation */ + /* Trying not to use worst-case bit-stuffing + * of (7/6 * 8 * bytecount) = 9.33 * bytecount */ + /* bytecount = data payload byte count */ + +#define NS_TO_US(ns) DIV_ROUND_UP(ns, 1000L) + /* convert nanoseconds to microseconds, rounding up */ + +/* + * Full/low speed bandwidth allocation constants/support. + */ +#define BW_HOST_DELAY 1000L /* nanoseconds */ +#define BW_HUB_LS_SETUP 333L /* nanoseconds */ + /* 4 full-speed bit times (est.) */ + +#define FRAME_TIME_BITS 12000L /* frame = 1 millisecond */ +#define FRAME_TIME_MAX_BITS_ALLOC (90L * FRAME_TIME_BITS / 100L) +#define FRAME_TIME_MAX_USECS_ALLOC (90L * FRAME_TIME_USECS / 100L) + +/* + * Ceiling [nano/micro]seconds (typical) for that many bytes at high speed + * ISO is a bit less, no ACK ... from USB 2.0 spec, 5.11.3 (and needed + * to preallocate bandwidth) + */ +#define USB2_HOST_DELAY 5 /* nsec, guess */ +#define HS_NSECS(bytes) (((55 * 8 * 2083) \ + + (2083UL * (3 + BitTime(bytes))))/1000 \ + + USB2_HOST_DELAY) +#define HS_NSECS_ISO(bytes) (((38 * 8 * 2083) \ + + (2083UL * (3 + BitTime(bytes))))/1000 \ + + USB2_HOST_DELAY) +#define HS_USECS(bytes) NS_TO_US(HS_NSECS(bytes)) +#define HS_USECS_ISO(bytes) NS_TO_US(HS_NSECS_ISO(bytes)) + +#ifdef CONFIG_DM_USB +static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) +{ + struct udevice *parent = udev->dev->parent; + + /* + * When called from usb-uclass.c: usb_scan_device() udev->dev points + * to the parent udevice, not the actual udevice belonging to the + * udev as the device is not instantiated yet. + * + * If dev is an usb-bus, then we are called from usb_scan_device() for + * an usb-device plugged directly into the root port, return NULL. + */ + if (device_get_uclass_id(udev->dev) == UCLASS_USB) + return NULL; + + /* + * If these 2 are not the same we are being called from + * usb_scan_device() and udev itself is the parent. + */ + if (dev_get_parent_priv(udev->dev) != udev) + return udev; + + /* We are being called normally, use the parent pointer */ + if (device_get_uclass_id(parent) == UCLASS_USB_HUB) + return dev_get_parent_priv(parent); + + return NULL; +} +#else +static inline struct usb_device *usb_dev_get_parent(struct usb_device *dev) +{ + return dev->parent; +} +#endif + +#endif /* __USB_COMPAT_H__ */ diff --git a/A58-STEPLDR/Src/usb/usb.c b/A58-STEPLDR/Src/usb/usb.c new file mode 100644 index 00000000..6b1e0ad2 --- /dev/null +++ b/A58-STEPLDR/Src/usb/usb.c @@ -0,0 +1,1705 @@ +#include +#include +#include +#include + +#define CONFIG_USB_STORAGE + +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include "usb.h" +#include "dwc2_compat.h" +#include +#include "ark_dwc2.h" +#include "timer.h" + +extern int hub_status_data(char buf[8]); +void usb_stor_disconnect(); +static char connect_status = 0; + +#define USB_BUFSIZ 512 +#define HUB_SHORT_RESET_TIME 20 +#define HUB_LONG_RESET_TIME 200 +#define PORT_OVERCURRENT_MAX_SCAN_COUNT 3 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + + +static int asynch_allowed; +static struct usb_device usb_dev[USB_MAX_DEVICE]; +static int dev_index; + +struct usb_device_scan { + ListItem_t list; + struct usb_device *dev; /* USB hub device to scan */ + struct usb_hub_device *hub; /* USB hub struct */ + int port; /* USB port to scan */ +}; + +static List_t usb_scan_list; +static struct usb_hub_device hub_dev[USB_MAX_HUB]; +static int usb_hub_index; + +void usb_hub_reset(void) +{ + usb_hub_index = 0; + + /* Zero out global hub_dev in case its re-used again */ + memset(hub_dev, 0, sizeof(hub_dev)); +} + +static struct usb_hub_device *usb_hub_allocate(void) +{ + if (usb_hub_index < USB_MAX_HUB) + return &hub_dev[usb_hub_index++]; + + return NULL; +} + +/*------------------------------------------------------------------- + * Max Packet stuff + */ + +/* + * returns the max packet size, depending on the pipe direction and + * the configurations values + */ +int usb_maxpacket(struct usb_device *dev, unsigned long pipe) +{ + /* direction is out -> use emaxpacket out */ + if ((pipe & USB_DIR_IN) == 0) + return dev->epmaxpacketout[((pipe>>15) & 0xf)]; + else + return dev->epmaxpacketin[((pipe>>15) & 0xf)]; +} + +/* + * The routine usb_set_maxpacket_ep() is extracted from the loop of routine + * usb_set_maxpacket(), because the optimizer of GCC 4.x chokes on this routine + * when it is inlined in 1 single routine. What happens is that the register r3 + * is used as loop-count 'i', but gets overwritten later on. + * This is clearly a compiler bug, but it is easier to workaround it here than + * to update the compiler (Occurs with at least several GCC 4.{1,2},x + * CodeSourcery compilers like e.g. 2007q3, 2008q1, 2008q3 lite editions on ARM) + * + * NOTE: Similar behaviour was observed with GCC4.6 on ARMv5. + */ +static void usb_set_maxpacket_ep(struct usb_device *dev, int if_idx, int ep_idx) +{ + int b; + struct usb_endpoint_descriptor *ep; + u16 ep_wMaxPacketSize; + unsigned char *tmp; + + ep = &dev->config.if_desc[if_idx].ep_desc[ep_idx]; + + b = ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + tmp = (unsigned char*)&ep->wMaxPacketSize; + ep_wMaxPacketSize = (tmp[1] << 8) | tmp[0];//get_unaligned(&ep->wMaxPacketSize); + USB_UNUSED(ep_wMaxPacketSize); + + if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_CONTROL) { + /* Control => bidirectional */ + dev->epmaxpacketout[b] = ep_wMaxPacketSize; + dev->epmaxpacketin[b] = ep_wMaxPacketSize; + /* debug("##Control EP epmaxpacketout/in[%d] = %d\n", + b, dev->epmaxpacketin[b]); */ + } else { + if ((ep->bEndpointAddress & 0x80) == 0) { + /* OUT Endpoint */ + if (ep_wMaxPacketSize > dev->epmaxpacketout[b]) { + dev->epmaxpacketout[b] = ep_wMaxPacketSize; + /* debug("##EP epmaxpacketout[%d] = %d\n", + b, dev->epmaxpacketout[b]); */ + } + } else { + /* IN Endpoint */ + if (ep_wMaxPacketSize > dev->epmaxpacketin[b]) { + dev->epmaxpacketin[b] = ep_wMaxPacketSize; + /* debug("##EP epmaxpacketin[%d] = %d\n", + b, dev->epmaxpacketin[b]); */ + } + } /* if out */ + } /* if control */ +} + +/* + * set the max packed value of all endpoints in the given configuration + */ +static int usb_set_maxpacket(struct usb_device *dev) +{ + int i, ii; + + for (i = 0; i < dev->config.desc.bNumInterfaces; i++) + for (ii = 0; ii < dev->config.if_desc[i].desc.bNumEndpoints; ii++) + usb_set_maxpacket_ep(dev, i, ii); + + return 0; +} + +/* + * submits a control message and waits for comletion (at least timeout * 1ms) + * If timeout is 0, we don't wait for completion (used as example to set and + * clear keyboards LEDs). For data transfers, (storage transfers) we don't + * allow control messages with 0 timeout, by previousely resetting the flag + * asynch_allowed (usb_disable_asynch(1)). + * returns the transferred length if OK or -1 if error. The transferred length + * and the current status are stored in the dev->act_len and dev->status. + */ +int usb_control_msg(struct usb_device *dev, unsigned int pipe, + unsigned char request, unsigned char requesttype, + unsigned short value, unsigned short index, + void *data, unsigned short size, int timeout) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct devrequest, setup_packet, 1); + int err; + + if ((timeout == 0) && (!asynch_allowed)) { + /* request for a asynch control pipe is not allowed */ + return -EINVAL; + } + + /* set setup command */ + setup_packet->requesttype = requesttype; + setup_packet->request = request; + setup_packet->value = value; + setup_packet->index = index; + setup_packet->length = size; + + if (0 == connect_status && dev->parent != NULL) { + return -1; + } + dev->status = USB_ST_NOT_PROC; /*not yet processed */ + + err = submit_control_msg(dev, pipe, data, size, setup_packet, timeout); + if (err < 0) { + err = -1; + } + if (dev->status) { + err = -1; + } + + return err; + +} + +/*------------------------------------------------------------------- + * submits bulk message, and waits for completion. returns 0 if Ok or + * negative if Error. + * synchronous behavior + */ +#define BULK_BUF_LEN 2048 +int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, + void *data, int len, int *actual_length, int timeout) +{ +#if 1 + int err; + ALLOC_CACHE_ALIGN_BUFFER(char, dma_buf, BULK_BUF_LEN); + int transfer_len = 0, total_len = 0, act_len = 0; + unsigned int addr = 0; + int is_in = usb_pipein(pipe); + + if (len < 0) + return -EINVAL; + while(len > 0) { + dev->status = USB_ST_NOT_PROC; /*not yet processed */ + if (len < BULK_BUF_LEN) + transfer_len = len; + else + transfer_len = BULK_BUF_LEN; + if (is_in == 0) { + memcpy(dma_buf, data, transfer_len); + } + if (0 == connect_status && dev->parent != NULL) { + dev->status = -1; + break; + } + err = submit_bulk_msg(dev, pipe, dma_buf, transfer_len, &act_len, timeout); + if (err < 0) + break; + if (is_in) { + memcpy(data, dma_buf, transfer_len); + } + total_len += act_len; + addr = (unsigned int)data + transfer_len; + data = (void *)addr; + len -= transfer_len; + } + if (len == 0) + *actual_length = total_len; + else + *actual_length = 0; + if (dev->status) + return -1; + return 0; +#else + int err; + + if (len < 0) + return -EINVAL; + dev->status = USB_ST_NOT_PROC; /*not yet processed */ + err = submit_bulk_msg(dev, pipe, data, len, timeout); + if (err < 0) + return err; + + *actual_length = dev->act_len; + if (dev->status) + return -1; + return 0; +#endif +} + +/******************************************************************************* + * Parse the config, located in buffer, and fills the dev->config structure. + * Note that all little/big endian swapping are done automatically. + * (wTotalLength has already been swapped and sanitized when it was read.) + */ +static int usb_parse_config(struct usb_device *dev, + unsigned char *buffer, int cfgno) +{ + struct usb_descriptor_header *head; + int index, ifno, epno, curr_if_num; + u16 ep_wMaxPacketSize; + unsigned char *tmp; + struct usb_interface *if_desc = NULL; + + ifno = -1; + epno = -1; + curr_if_num = -1; + + dev->configno = cfgno; + head = (struct usb_descriptor_header *) &buffer[0]; + if (head->bDescriptorType != USB_DT_CONFIG) { + /* printf(" ERROR: NOT USB_CONFIG_DESC %x\n", + head->bDescriptorType); */ + return -EINVAL; + } + if (head->bLength != USB_DT_CONFIG_SIZE) { + //printf("ERROR: Invalid USB CFG length (%d)\n", head->bLength); + return -EINVAL; + } + memcpy(&dev->config, head, USB_DT_CONFIG_SIZE); + dev->config.no_of_if = 0; + + index = dev->config.desc.bLength; + /* Ok the first entry must be a configuration entry, + * now process the others */ + head = (struct usb_descriptor_header *) &buffer[index]; + while (index + 1 < dev->config.desc.wTotalLength && head->bLength) { + switch (head->bDescriptorType) { + case USB_DT_INTERFACE: + if (head->bLength != USB_DT_INTERFACE_SIZE) { + /* printf("ERROR: Invalid USB IF length (%d)\n", + head->bLength); */ + break; + } + if (index + USB_DT_INTERFACE_SIZE > + dev->config.desc.wTotalLength) { + //puts("USB IF descriptor overflowed buffer!\n"); + break; + } + if (((struct usb_interface_descriptor *) \ + head)->bInterfaceNumber != curr_if_num) { + /* this is a new interface, copy new desc */ + ifno = dev->config.no_of_if; + if (ifno >= USB_MAXINTERFACES) { + //puts("Too many USB interfaces!\n"); + /* try to go on with what we have */ + return -EINVAL; + } + if_desc = &dev->config.if_desc[ifno]; + dev->config.no_of_if++; + memcpy(if_desc, head, + USB_DT_INTERFACE_SIZE); + if_desc->no_of_ep = 0; + if_desc->num_altsetting = 1; + curr_if_num = + if_desc->desc.bInterfaceNumber; + } else { + /* found alternate setting for the interface */ + if (ifno >= 0) { + if_desc = &dev->config.if_desc[ifno]; + if_desc->num_altsetting++; + } + } + break; + case USB_DT_ENDPOINT: + if (head->bLength != USB_DT_ENDPOINT_SIZE && + head->bLength != USB_DT_ENDPOINT_AUDIO_SIZE) { + /* printf("ERROR: Invalid USB EP length (%d)\n", + head->bLength); */ + break; + } + if (index + head->bLength > + dev->config.desc.wTotalLength) { + //puts("USB EP descriptor overflowed buffer!\n"); + break; + } + if (ifno < 0) { + //puts("Endpoint descriptor out of order!\n"); + break; + } + epno = dev->config.if_desc[ifno].no_of_ep; + if_desc = &dev->config.if_desc[ifno]; + if (epno >= USB_MAXENDPOINTS) { + /* printf("Interface %d has too many endpoints!\n", + if_desc->desc.bInterfaceNumber); */ + return -EINVAL; + } + /* found an endpoint */ + if_desc->no_of_ep++; + memcpy(&if_desc->ep_desc[epno], head, + USB_DT_ENDPOINT_SIZE); + /* ep_wMaxPacketSize = get_unaligned(&dev->config.\ + if_desc[ifno].\ + ep_desc[epno].\ + wMaxPacketSize); */ + tmp = (unsigned char*)&dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize; + ep_wMaxPacketSize = (tmp[1] << 8) | tmp[0]; + USB_UNUSED(ep_wMaxPacketSize); + /* put_unaligned(le16_to_cpu(ep_wMaxPacketSize), + &dev->config.\ + if_desc[ifno].\ + ep_desc[epno].\ + wMaxPacketSize); */ + //debug("if %d, ep %d\n", ifno, epno); + break; + case USB_DT_SS_ENDPOINT_COMP: + if (head->bLength != USB_DT_SS_EP_COMP_SIZE) { + /* printf("ERROR: Invalid USB EPC length (%d)\n", + head->bLength); */ + break; + } + if (index + USB_DT_SS_EP_COMP_SIZE > + dev->config.desc.wTotalLength) { + //puts("USB EPC descriptor overflowed buffer!\n"); + break; + } + if (ifno < 0 || epno < 0) { + //puts("EPC descriptor out of order!\n"); + break; + } + if_desc = &dev->config.if_desc[ifno]; + memcpy(&if_desc->ss_ep_comp_desc[epno], head, + USB_DT_SS_EP_COMP_SIZE); + break; + default: + if (head->bLength == 0) + return -EINVAL; + + /* debug("unknown Description Type : %x\n", + head->bDescriptorType); */ + +#ifdef DEBUG + { + unsigned char *ch = (unsigned char *)head; + int i; + + for (i = 0; i < head->bLength; i++) + debug("%02X ", *ch++); + debug("\n\n\n"); + } +#endif + break; + } + index += head->bLength; + head = (struct usb_descriptor_header *)&buffer[index]; + } + return 0; +} + +struct usb_device *usb_get_dev_index(int index) +{ + if (usb_dev[index].devnum == -1) + return NULL; + else + return &usb_dev[index]; +} + +void usb_free_device(void *controller) +{ + dev_index--; + //debug("Freeing device node: %d\n", dev_index); + memset(&usb_dev[dev_index], 0, sizeof(struct usb_device)); + usb_dev[dev_index].devnum = -1; +} + +int usb_alloc_device(struct usb_device *udev) +{ + return 0; +} + +/*********************************************************************** + * Clears an endpoint + * endp: endpoint number in bits 0-3; + * direction flag in bit 7 (1 = IN, 0 = OUT) + */ +int usb_clear_halt(struct usb_device *dev, int pipe) +{ + int result; + int endp = usb_pipeendpoint(pipe)|(usb_pipein(pipe)<<7); + + result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, + endp, NULL, 0, USB_CNTL_TIMEOUT * 3); + + /* don't clear if failed */ + if (result < 0) + return result; + + /* + * NOTE: we do not get status and verify reset was successful + * as some devices are reported to lock up upon this check.. + */ + + usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + /* toggle is reset on clear */ + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0); + return 0; +} + +/********************************************************************** + * get_descriptor type + */ +static int usb_get_descriptor(struct usb_device *dev, unsigned char type, + unsigned char index, void *buf, int size) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, + (type << 8) + index, 0, buf, size, + USB_CNTL_TIMEOUT); +} + +/********************************************************************** + * gets len of configuration cfgno + */ +int usb_get_configuration_len(struct usb_device *dev, int cfgno) +{ + int result; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, 9); + struct usb_config_descriptor *config; + + config = (struct usb_config_descriptor *)&buffer[0]; + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 9); + if (result < 9) { + if (result < 0) + ;/* printf("unable to get descriptor, error %lX\n", + dev->status); */ + else + ;/* printf("config descriptor too short " \ + "(expected %i, got %i)\n", 9, result); */ + return -EIO; + } + return config->wTotalLength; +} + +/********************************************************************** + * gets configuration cfgno and store it in the buffer + */ +int usb_get_configuration_no(struct usb_device *dev, int cfgno, + unsigned char *buffer, int length) +{ + int result; + struct usb_config_descriptor *config; + + config = (struct usb_config_descriptor *)&buffer[0]; + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length); + /* debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, + le16_to_cpu(config->wTotalLength)); */ + config->wTotalLength = result; /* validated, with CPU byte order */ + + return result; +} + +static int get_descriptor_len(struct usb_device *dev, int len, int expect_len) +{ + struct usb_device_descriptor *desc; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ); + int err; + + desc = (struct usb_device_descriptor *)tmpbuf; + + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, len); + if (err < expect_len) { + if (err < 0) { + /* printf("unable to get device descriptor (error=%d)\n", + err); */ + return err; + } else { + /* printf("USB device descriptor short read (expected %i, got %i)\n", + expect_len, err); */ + return -EIO; + } + } + memcpy(&dev->descriptor, tmpbuf, sizeof(dev->descriptor)); + + return 0; +} + +/******************************************************************** + * set address of a device to the value in dev->devnum. + * This can only be done by addressing the device via the default address (0) + */ +static int usb_set_address(struct usb_device *dev) +{ + //debug("set address %d\n", dev->devnum); + + return usb_control_msg(dev, usb_snddefctrl(dev), USB_REQ_SET_ADDRESS, + 0, (dev->devnum), 0, NULL, 0, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * set interface number to interface + */ +int usb_set_interface(struct usb_device *dev, int interface, int alternate) +{ + struct usb_interface *if_face = NULL; + int ret, i; + + for (i = 0; i < dev->config.desc.bNumInterfaces; i++) { + if (dev->config.if_desc[i].desc.bInterfaceNumber == interface) { + if_face = &dev->config.if_desc[i]; + break; + } + } + if (!if_face) { + //printf("selecting invalid interface %d", interface); + return -EINVAL; + } + /* + * We should return now for devices with only one alternate setting. + * According to 9.4.10 of the Universal Serial Bus Specification + * Revision 2.0 such devices can return with a STALL. This results in + * some USB sticks timeouting during initialization and then being + * unusable in U-Boot. + */ + if (if_face->num_altsetting == 1) + return 0; + + ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE, + alternate, interface, NULL, 0, + USB_CNTL_TIMEOUT * 5); + if (ret < 0) + return ret; + + return 0; +} + +/******************************************************************** + * set configuration number to configuration + */ +static int usb_set_configuration(struct usb_device *dev, int configuration) +{ + int res; + //debug("set configuration %d\n", configuration); + /* set setup command */ + res = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_CONFIGURATION, 0, + configuration, 0, + NULL, 0, USB_CNTL_TIMEOUT); + if (res == 0) { + dev->toggle[0] = 0; + dev->toggle[1] = 0; + return 0; + } else + return -EIO; +} + +static int usb_setup_descriptor(struct usb_device *dev, bool do_read) +{ + /* + * This is a Windows scheme of initialization sequence, with double + * reset of the device (Linux uses the same sequence) + * Some equipment is said to work only with such init sequence; this + * patch is based on the work by Alan Stern: + * http://sourceforge.net/mailarchive/forum.php? + * thread_id=5729457&forum_id=5398 + */ + + /* + * send 64-byte GET-DEVICE-DESCRIPTOR request. Since the descriptor is + * only 18 bytes long, this will terminate with a short packet. But if + * the maxpacket size is 8 or 16 the device may be waiting to transmit + * some more, or keeps on retransmitting the 8 byte header. + */ + + if (dev->speed == USB_SPEED_LOW) { + dev->descriptor.bMaxPacketSize0 = 8; + dev->maxpacketsize = PACKET_SIZE_8; + } else { + dev->descriptor.bMaxPacketSize0 = 64; + dev->maxpacketsize = PACKET_SIZE_64; + } + dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0; + dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; + + if (do_read && dev->speed == USB_SPEED_FULL) { + int err; + + /* + * Validate we've received only at least 8 bytes, not that + * we've received the entire descriptor. The reasoning is: + * - The code only uses fields in the first 8 bytes, so + * that's all we need to have fetched at this stage. + * - The smallest maxpacket size is 8 bytes. Before we know + * the actual maxpacket the device uses, the USB controller + * may only accept a single packet. Consequently we are only + * guaranteed to receive 1 packet (at least 8 bytes) even in + * a non-error case. + * + * At least the DWC2 controller needs to be programmed with + * the number of packets in addition to the number of bytes. + * A request for 64 bytes of data with the maxpacket guessed + * as 64 (above) yields a request for 1 packet. + */ + err = get_descriptor_len(dev, 64, 8); + if (err) + return err; + } + + dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0; + dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; + switch (dev->descriptor.bMaxPacketSize0) { + case 8: + dev->maxpacketsize = PACKET_SIZE_8; + break; + case 16: + dev->maxpacketsize = PACKET_SIZE_16; + break; + case 32: + dev->maxpacketsize = PACKET_SIZE_32; + break; + case 64: + dev->maxpacketsize = PACKET_SIZE_64; + break; + default: + //printf("%s: invalid max packet size\n", __func__); + return -EIO; + } + + return 0; +} + +int usb_alloc_new_device(void *controller, struct usb_device **devp) +{ + int i; + + if (dev_index == USB_MAX_DEVICE) { + SendUartString("ERROR, too many USB Devices\n"); + return -ENOSPC; + } + /* default Address is 0, real addresses start with 1 */ + usb_dev[dev_index].devnum = dev_index + 1; + usb_dev[dev_index].maxchild = 0; + for (i = 0; i < USB_MAXCHILDREN; i++) + usb_dev[dev_index].children[i] = NULL; + usb_dev[dev_index].parent = NULL; + usb_dev[dev_index].controller = controller; + dev_index++; + *devp = &usb_dev[dev_index - 1]; + + return 0; +} + +static int usb_prepare_device(struct usb_device *dev, int addr, bool do_read, + struct usb_device *parent) +{ + int err; + + /* + * Allocate usb 3.0 device context. + * USB 3.0 (xHCI) protocol tries to allocate device slot + * and related data structures first. This call does that. + * Refer to sec 4.3.2 in xHCI spec rev1.0 + */ + err = usb_alloc_device(dev); + if (err) { + //printf("Cannot allocate device context to get SLOT_ID\n"); + return err; + } + err = usb_setup_descriptor(dev, do_read); + if (err) + return err; + /* err = usb_hub_port_reset(dev, parent); + if (err) + return err; */ + + dev->devnum = addr; + + err = usb_set_address(dev); /* set address */ + + if (err < 0) { + /* printf("\n USB device not accepting new address " \ + "(error=%lX)\n", dev->status); */ + return err; + } + + mdelay(10); /* Let the SET_ADDRESS settle */ + + /* + * If we haven't read device descriptor before, read it here + * after device is assigned an address. This is only applicable + * to xHCI so far. + */ + if (!do_read) { + err = usb_setup_descriptor(dev, true); + if (err) + return err; + } + + return 0; +} + +int usb_select_config(struct usb_device *dev) +{ + unsigned char *rawtmpbuf = NULL, *tmpbuf = NULL; + int err; + + err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE); + if (err) + return err; + + /* + * Kingston DT Ultimate 32GB USB 3.0 seems to be extremely sensitive + * about this first Get Descriptor request. If there are any other + * requests in the first microframe, the stick crashes. Wait about + * one microframe duration here (1mS for USB 1.x , 125uS for USB 2.0). + */ + mdelay(1); + + /* only support for one config for now */ + err = usb_get_configuration_len(dev, 0); + if (err >= 0) { + rawtmpbuf = (unsigned char *)malloc(err + ARCH_DMA_MINALIGN - 1); + if (!rawtmpbuf) + err = -ENOMEM; + else { + tmpbuf = (unsigned char*)ALIGN((uintptr_t)rawtmpbuf, ARCH_DMA_MINALIGN); + err = usb_get_configuration_no(dev, 0, tmpbuf, err); + } + } + if (err < 0) { + /* printf("usb_new_device: Cannot read configuration, " \ + "skipping device %04x:%04x\n", + dev->descriptor.idVendor, dev->descriptor.idProduct); */ + if (rawtmpbuf) + free(rawtmpbuf); + return err; + } + usb_parse_config(dev, tmpbuf, 0); + free(rawtmpbuf); + usb_set_maxpacket(dev); + /* + * we set the default configuration here + * This seems premature. If the driver wants a different configuration + * it will need to select itself. + */ + err = usb_set_configuration(dev, dev->config.desc.bConfigurationValue); + if (err < 0) { + /* printf("failed to set default configuration " \ + "len %d, status %lX\n", dev->act_len, dev->status); */ + return err; + } + + /* + * Wait until the Set Configuration request gets processed by the + * device. This is required by at least SanDisk Cruzer Pop USB 2.0 + * and Kingston DT Ultimate 32GB USB 3.0 on DWC2 OTG controller. + */ + mdelay(10); + + return 0; +} + +int usb_setup_device(struct usb_device *dev, bool do_read, + struct usb_device *parent) +{ + int addr; + int ret; + + /* We still haven't set the Address yet */ + addr = dev->devnum; + dev->devnum = 0; + + ret = usb_prepare_device(dev, addr, do_read, parent); + if (ret) + return ret; + ret = usb_select_config(dev); + + return ret; +} + +bool usb_device_has_child_on_port(struct usb_device *parent, int port) +{ + return parent->children[port] != NULL; +} + + +static inline bool usb_hub_is_superspeed(struct usb_device *hdev) +{ + return hdev->descriptor.bDeviceProtocol == 3; +} + +static int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size) +{ + unsigned short dtype = USB_DT_HUB; + + if (usb_hub_is_superspeed(dev)) + dtype = USB_DT_SS_HUB; + + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB, + dtype << 8, 0, data, size, USB_CNTL_TIMEOUT); +} + +static struct usb_hub_device *usb_get_hub_device(struct usb_device *dev) +{ + struct usb_hub_device *hub; + + /* "allocate" Hub device */ + hub = usb_hub_allocate(); + + return hub; +} + +static int usb_get_hub_status(struct usb_device *dev, void *data) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_HUB, 0, 0, + data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT); +} + +static int usb_clear_port_feature(struct usb_device *dev, int port, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RT_PORT, feature, + port, NULL, 0, USB_CNTL_TIMEOUT); +} + +static int usb_set_port_feature(struct usb_device *dev, int port, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_FEATURE, USB_RT_PORT, feature, + port, NULL, 0, USB_CNTL_TIMEOUT); +} + +int usb_get_port_status(struct usb_device *dev, int port, void *data) +{ + int ret; + + ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port, + data, sizeof(struct usb_port_status), USB_CNTL_TIMEOUT); + + return ret; +} + +static void usb_hub_power_on(struct usb_hub_device *hub) +{ + int i; + struct usb_device *dev; + unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2; + //const char *env; + + dev = hub->pusb_dev; + + //debug("enabling power on all ports\n"); + for (i = 0; i < dev->maxchild; i++) { + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); + //debug("port %d returns %lX\n", i + 1, dev->status); + } + + /* + * Wait for power to become stable, + * plus spec-defined max time for device to connect + * but allow this time to be increased via env variable as some + * devices break the spec and require longer warm-up times + */ + /* env = env_get("usb_pgood_delay"); + if (env) + pgood_delay = max(pgood_delay, + (unsigned)simple_strtol(env, NULL, 0)); + debug("pgood_delay=%dms\n", pgood_delay); */ + + /* + * Do a minimum delay of the larger value of 100ms or pgood_delay + * so that the power can stablize before the devices are queried + */ + hub->query_delay = get_timer(0) + max(100, (int)pgood_delay); + + /* + * Record the power-on timeout here. The max. delay (timeout) + * will be done based on this value in the USB port loop in + * usb_hub_configure() later. + */ + hub->connect_timeout = hub->query_delay + 1000; + /* debug("devnum=%d poweron: query_delay=%d connect_timeout=%d\n", + dev->devnum, max(100, (int)pgood_delay), + max(100, (int)pgood_delay) + 1000); */ +} + +#define MAX_TRIES 5 + +/** + * usb_hub_port_reset() - reset a port given its usb_device pointer + * + * Reset a hub port and see if a device is present on that port, providing + * sufficient time for it to show itself. The port status is returned. + * + * @dev: USB device to reset + * @port: Port number to reset (note ports are numbered from 0 here) + * @portstat: Returns port status + */ +static int usb_hub_port_reset(struct usb_device *dev, int port, + unsigned short *portstat) +{ + int err, tries; + ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); + unsigned short portstatus, portchange; + int delay = HUB_SHORT_RESET_TIME; /* start with short reset delay */ + + //debug("%s: resetting port %d...\n", __func__, port + 1); + + for (tries = 0; tries < MAX_TRIES; tries++) { + err = usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); + if (err < 0) + return err; + + mdelay(delay); + + if (usb_get_port_status(dev, port + 1, portsts) < 0) { + /* debug("get_port_status failed status %lX\n", + dev->status); */ + return -1; + } + portstatus = le16_to_cpu(portsts->wPortStatus); + portchange = le16_to_cpu(portsts->wPortChange); + USB_UNUSED(portchange); + /* debug("portstatus %x, change %x, %s\n", portstatus, portchange, + portspeed(portstatus)); + + debug("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \ + " USB_PORT_STAT_ENABLE %d\n", + (portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0, + (portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0, + (portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0); */ + + /* + * Perhaps we should check for the following here: + * - C_CONNECTION hasn't been set. + * - CONNECTION is still set. + * + * Doing so would ensure that the device is still connected + * to the bus, and hasn't been unplugged or replaced while the + * USB bus reset was going on. + * + * However, if we do that, then (at least) a San Disk Ultra + * USB 3.0 16GB device fails to reset on (at least) an NVIDIA + * Tegra Jetson TK1 board. For some reason, the device appears + * to briefly drop off the bus when this second bus reset is + * executed, yet if we retry this loop, it'll eventually come + * back after another reset or two. + */ + + if (portstatus & USB_PORT_STAT_ENABLE) + break; + + /* Switch to long reset delay for the next round */ + delay = HUB_LONG_RESET_TIME; + } + + if (tries == MAX_TRIES) { + /* debug("Cannot enable port %i after %i retries, " \ + "disabling port.\n", port + 1, MAX_TRIES); + debug("Maybe the USB cable is bad?\n"); */ + return -1; + } + + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_RESET); + if (portstat) + *portstat = portstatus; + return 0; +} + +int usb_new_device(struct usb_device *dev); + +int usb_hub_port_connect_change(struct usb_device *dev, int port) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); + unsigned short portstatus; + int ret, speed; + + /* Check status */ + ret = usb_get_port_status(dev, port + 1, portsts); + if (ret < 0) { + //debug("get_port_status failed\n"); + return ret; + } + + portstatus = portsts->wPortStatus; + /* debug("portstatus %x, change %x, %s\n", + portstatus, + le16_to_cpu(portsts->wPortChange), + portspeed(portstatus)); */ + + /* Clear the connection change status */ + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION); + + /* Disconnect any existing devices under this port */ + if (((!(portstatus & USB_PORT_STAT_CONNECTION)) && + (!(portstatus & USB_PORT_STAT_ENABLE))) || + usb_device_has_child_on_port(dev, port)) { + //debug("usb_disconnect(&hub->children[port]);\n"); + /* Return now if nothing is connected */ + if (!(portstatus & USB_PORT_STAT_CONNECTION)) + return -ENOTCONN; + } + + /* Reset the port */ + ret = usb_hub_port_reset(dev, port, &portstatus); + if (ret < 0) { + if (ret != -ENXIO) + ;//printf("cannot reset port %i!?\n", port + 1); + return ret; + } + + switch (portstatus & USB_PORT_STAT_SPEED_MASK) { + case USB_PORT_STAT_SUPER_SPEED: + speed = USB_SPEED_SUPER; + break; + case USB_PORT_STAT_HIGH_SPEED: + speed = USB_SPEED_HIGH; + break; + case USB_PORT_STAT_LOW_SPEED: + speed = USB_SPEED_LOW; + break; + default: + speed = USB_SPEED_FULL; + break; + } + + struct usb_device *usb; + + ret = usb_alloc_new_device(dev->controller, &usb); + if (ret) { + //printf("cannot create new device: ret=%d", ret); + return ret; + } + + dev->children[port] = usb; + usb->speed = speed; + usb->parent = dev; + usb->portnr = port + 1; + /* Run it through the hoops (find a driver, etc) */ + ret = usb_new_device(usb); + if (ret < 0) { + /* Woops, disable the port */ + usb_free_device(dev->controller); + dev->children[port] = NULL; + } + + if (ret < 0) { + //debug("hub: disabling port %d\n", port + 1); + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE); + } + + return ret; +} + + +static int usb_scan_port(struct usb_device_scan *usb_scan) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); + unsigned short portstatus; + unsigned short portchange; + struct usb_device *dev; + struct usb_hub_device *hub; + int ret = 0; + int i; + + dev = usb_scan->dev; + hub = usb_scan->hub; + i = usb_scan->port; + + /* + * Don't talk to the device before the query delay is expired. + * This is needed for voltages to stabalize. + */ + if (get_timer(0) < hub->query_delay) + return 0; + + ret = usb_get_port_status(dev, i + 1, portsts); + if (ret < 0) { + //debug("get_port_status failed\n"); + if (get_timer(0) >= hub->connect_timeout) { + /* debug("devnum=%d port=%d: timeout\n", + dev->devnum, i + 1); */ + /* Remove this device from scanning list */ + list_del(&usb_scan->list); + free(usb_scan); + return -1; + } + return 0; + } + + portstatus = portsts->wPortStatus; + portchange = portsts->wPortChange; + USB_UNUSED(portchange); + //debug("Port %d Status %X Change %X\n", i + 1, portstatus, portchange); + + /* + * No connection change happened, wait a bit more. + * + * For some situation, the hub reports no connection change but a + * device is connected to the port (eg: CCS bit is set but CSC is not + * in the PORTSC register of a root hub), ignore such case. + */ + if (!(portchange & USB_PORT_STAT_C_CONNECTION) && + !(portstatus & USB_PORT_STAT_CONNECTION)) { + if (get_timer(0) >= hub->connect_timeout) { + /* debug("devnum=%d port=%d: timeout\n", + dev->devnum, i + 1); */ + /* Remove this device from scanning list */ + list_del(&usb_scan->list); + free(usb_scan); + return -1; + } + return 0; + } + + if (portchange & USB_PORT_STAT_C_RESET) { + //debug("port %d reset change\n", i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_RESET); + } + + if ((portchange & USB_SS_PORT_STAT_C_BH_RESET) && + usb_hub_is_superspeed(dev)) { + //debug("port %d BH reset change\n", i + 1); + usb_clear_port_feature(dev, i + 1, USB_SS_PORT_FEAT_C_BH_RESET); + } + + /* A new USB device is ready at this point */ + //debug("devnum=%d port=%d: USB dev found\n", dev->devnum, i + 1); + + ret = usb_hub_port_connect_change(dev, i); + if (ret < 0) { + PrintVariableValueHex("usb port change err at line", __LINE__); + goto exit; + } + + if (portchange & USB_PORT_STAT_C_ENABLE) { + //debug("port %d enable change, status %x\n", i + 1, portstatus); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_ENABLE); + /* + * The following hack causes a ghost device problem + * to Faraday EHCI + */ + + /* + * EM interference sometimes causes bad shielded USB + * devices to be shutdown by the hub, this hack enables + * them again. Works at least with mouse driver + */ + if (!(portstatus & USB_PORT_STAT_ENABLE) && + (portstatus & USB_PORT_STAT_CONNECTION) && + usb_device_has_child_on_port(dev, i)) { + /* debug("already running port %i disabled by hub (EMI?), re-enabling...\n", + i + 1); */ + ret = usb_hub_port_connect_change(dev, i); + if (ret < 0) { + PrintVariableValueHex("usb port change err at line", __LINE__); + goto exit; + } + } + } + + if (portstatus & USB_PORT_STAT_SUSPEND) { + //debug("port %d suspend change\n", i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_SUSPEND); + } + + if (portchange & USB_PORT_STAT_C_OVERCURRENT) { + //debug("port %d over-current change\n", i + 1); + usb_clear_port_feature(dev, i + 1, + USB_PORT_FEAT_C_OVER_CURRENT); + /* Only power-on this one port */ + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); + hub->overcurrent_count[i]++; + + /* + * If the max-scan-count is not reached, return without removing + * the device from scan-list. This will re-issue a new scan. + */ + if (hub->overcurrent_count[i] <= + PORT_OVERCURRENT_MAX_SCAN_COUNT) + return 0; + + /* Otherwise the device will get removed */ + /* printf("Port %d over-current occurred %d times\n", i + 1, + hub->overcurrent_count[i]); */ + } + + /* + * We're done with this device, so let's remove this device from + * scanning list + */ + ret = 0; +exit: + list_del(&usb_scan->list); + free(usb_scan); + PrintVariableValueHex("usb_scan_port ret", ret); + + return ret; +} + +static int usb_device_list_scan(void) +{ + struct usb_device_scan *usb_scan; + //struct usb_device_scan *tmp; + static int running; + int ret = 0; + ListItem_t *pxListItem, *nListItem; + + /* Only run this loop once for each controller */ + if (running) + return 0; + + running = 1; + + while (1) { + /* We're done, once the list is empty again */ + if (list_empty(&usb_scan_list)) + goto out; + list_for_each_entry_safe(pxListItem, nListItem, usb_scan, &usb_scan_list) { + int ret; + + /* Scan this port */ + ret = usb_scan_port(usb_scan); + if (ret) + goto out; + ret = usb_stor_scan(0); + } + } + +out: + /* + * This USB controller has finished scanning all its connected + * USB devices. Set "running" back to 0, so that other USB controllers + * will scan their devices too. + */ + running = 0; + + return ret; +} + +static int usb_hub_configure(struct usb_device *dev) +{ + int i, length; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, USB_BUFSIZ); + unsigned char *bitmap; + short hubCharacteristics; + struct usb_hub_descriptor *descriptor; + struct usb_hub_device *hub; + struct usb_hub_status *hubsts; + unsigned char *tmp; + unsigned short tmpval; + int ret; + + hub = usb_get_hub_device(dev); + if (hub == NULL) + return -ENOMEM; + hub->pusb_dev = dev; + + /* Get the the hub descriptor */ + ret = usb_get_hub_descriptor(dev, buffer, 4); + if (ret < 0) { + /* debug("usb_hub_configure: failed to get hub " \ + "descriptor, giving up %lX\n", dev->status); */ + return ret; + } + descriptor = (struct usb_hub_descriptor *)buffer; + + length = min(descriptor->bLength, + sizeof(struct usb_hub_descriptor)); + + ret = usb_get_hub_descriptor(dev, buffer, length); + if (ret < 0) { + /* debug("usb_hub_configure: failed to get hub " \ + "descriptor 2nd giving up %lX\n", dev->status); */ + return ret; + } + memcpy((unsigned char *)&hub->desc, buffer, length); + /* adjust 16bit values */ + /* put_unaligned(le16_to_cpu(get_unaligned( + &descriptor->wHubCharacteristics)), + &hub->desc.wHubCharacteristics); */ + tmp = (unsigned char*)&descriptor->wHubCharacteristics; + tmpval = (tmp[1] << 8) | tmp[0]; + tmp = (unsigned char*)&hub->desc.wHubCharacteristics; + tmp[0] = tmpval & 0xff; + tmp[1] = (tmpval >> 8) & 0xff; + + /* set the bitmap */ + bitmap = (unsigned char *)&hub->desc.u.hs.DeviceRemovable[0]; + /* devices not removable by default */ + memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); + bitmap = (unsigned char *)&hub->desc.u.hs.PortPowerCtrlMask[0]; + memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); /* PowerMask = 1B */ + + for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++) + hub->desc.u.hs.DeviceRemovable[i] = + descriptor->u.hs.DeviceRemovable[i]; + + for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++) + hub->desc.u.hs.PortPowerCtrlMask[i] = + descriptor->u.hs.PortPowerCtrlMask[i]; + + dev->maxchild = descriptor->bNbrPorts; + //debug("%d ports detected\n", dev->maxchild); + + tmp = (unsigned char*)&hub->desc.wHubCharacteristics; + hubCharacteristics = (tmp[1] << 8) | tmp[0];//get_unaligned(&hub->desc.wHubCharacteristics); + switch (hubCharacteristics & HUB_CHAR_LPSM) { + case 0x00: + //debug("ganged power switching\n"); + break; + case 0x01: + //debug("individual port power switching\n"); + break; + case 0x02: + case 0x03: + //debug("unknown reserved power switching mode\n"); + break; + } + + if (hubCharacteristics & HUB_CHAR_COMPOUND) + ;//debug("part of a compound device\n"); + else + ;//debug("standalone hub\n"); + + switch (hubCharacteristics & HUB_CHAR_OCPM) { + case 0x00: + //debug("global over-current protection\n"); + break; + case 0x08: + //debug("individual port over-current protection\n"); + break; + case 0x10: + case 0x18: + //debug("no over-current protection\n"); + break; + } + + switch (dev->descriptor.bDeviceProtocol) { + case USB_HUB_PR_FS: + break; + case USB_HUB_PR_HS_SINGLE_TT: + //debug("Single TT\n"); + break; + case USB_HUB_PR_HS_MULTI_TT: + ret = usb_set_interface(dev, 0, 1); + if (ret == 0) { + //debug("TT per port\n"); + hub->tt.multi = true; + } else { + ;//debug("Using single TT (err %d)\n", ret); + } + break; + case USB_HUB_PR_SS: + /* USB 3.0 hubs don't have a TT */ + break; + default: + /* debug("Unrecognized hub protocol %d\n", + dev->descriptor.bDeviceProtocol); */ + break; + } + + /* Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns */ + switch (hubCharacteristics & HUB_CHAR_TTTT) { + case HUB_TTTT_8_BITS: + if (dev->descriptor.bDeviceProtocol != 0) { + hub->tt.think_time = 666; + /* debug("TT requires at most %d FS bit times (%d ns)\n", + 8, hub->tt.think_time); */ + } + break; + case HUB_TTTT_16_BITS: + hub->tt.think_time = 666 * 2; + /* debug("TT requires at most %d FS bit times (%d ns)\n", + 16, hub->tt.think_time); */ + break; + case HUB_TTTT_24_BITS: + hub->tt.think_time = 666 * 3; + /* debug("TT requires at most %d FS bit times (%d ns)\n", + 24, hub->tt.think_time); */ + break; + case HUB_TTTT_32_BITS: + hub->tt.think_time = 666 * 4; + /* debug("TT requires at most %d FS bit times (%d ns)\n", + 32, hub->tt.think_time); */ + break; + } + + /* debug("power on to power good time: %dms\n", + descriptor->bPwrOn2PwrGood * 2); + debug("hub controller current requirement: %dmA\n", + descriptor->bHubContrCurrent); + + for (i = 0; i < dev->maxchild; i++) + debug("port %d is%s removable\n", i + 1, + hub->desc.u.hs.DeviceRemovable[(i + 1) / 8] & \ + (1 << ((i + 1) % 8)) ? " not" : ""); */ + + if (sizeof(struct usb_hub_status) > USB_BUFSIZ) { + /* debug("usb_hub_configure: failed to get Status - " \ + "too long: %d\n", descriptor->bLength); */ + return -EFBIG; + } + + ret = usb_get_hub_status(dev, buffer); + if (ret < 0) { + /* debug("usb_hub_configure: failed to get Status %lX\n", + dev->status); */ + return ret; + } + + hubsts = (struct usb_hub_status *)buffer; + USB_UNUSED(hubsts); + /* debug("get_hub_status returned status %X, change %X\n", + le16_to_cpu(hubsts->wHubStatus), + le16_to_cpu(hubsts->wHubChange)); + debug("local power source is %s\n", + (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? \ + "lost (inactive)" : "good"); + debug("%sover-current condition exists\n", + (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \ + "" : "no "); */ + + usb_hub_power_on(hub); + + return ret; +} + +static int usb_hub_check(struct usb_device *dev, int ifnum) +{ + struct usb_interface *iface; + struct usb_endpoint_descriptor *ep = NULL; + + iface = &dev->config.if_desc[ifnum]; + /* Is it a hub? */ + if (iface->desc.bInterfaceClass != USB_CLASS_HUB) + goto err; + /* Some hubs have a subclass of 1, which AFAICT according to the */ + /* specs is not defined, but it works */ + if ((iface->desc.bInterfaceSubClass != 0) && + (iface->desc.bInterfaceSubClass != 1)) + goto err; + /* Multiple endpoints? What kind of mutant ninja-hub is this? */ + if (iface->desc.bNumEndpoints != 1) + goto err; + ep = &iface->ep_desc[0]; + /* Output endpoint? Curiousier and curiousier.. */ + if (!(ep->bEndpointAddress & USB_DIR_IN)) + goto err; + /* If it's not an interrupt endpoint, we'd better punt! */ + if ((ep->bmAttributes & 3) != 3) + goto err; + /* We found a hub */ + //debug("USB hub found\n"); + return 0; + +err: + /* debug("USB hub not found: bInterfaceClass=%d, bInterfaceSubClass=%d, bNumEndpoints=%d\n", + iface->desc.bInterfaceClass, iface->desc.bInterfaceSubClass, + iface->desc.bNumEndpoints); + if (ep) { + debug(" bEndpointAddress=%#x, bmAttributes=%d", + ep->bEndpointAddress, ep->bmAttributes); + } */ + + return -ENOENT; +} + +int usb_hub_probe(struct usb_device *dev, int ifnum) +{ + int ret; + + ret = usb_hub_check(dev, ifnum); + if (ret) + return 0; + ret = usb_hub_configure(dev); + return ret; +} + +int usb_new_device(struct usb_device *dev) +{ + bool do_read = true; + int err; + + err = usb_setup_device(dev, do_read, dev->parent); + if (err) + return err; + + /* Now probe if the device is a hub */ + err = usb_hub_probe(dev, 0); + if (err < 0) + return err; + + return 0; +} + +void usb_connect_state_notify_cb(void* ctx, int state) +{ + +} + +/* + * disables the asynch behaviour of the control message. This is used for data + * transfers that uses the exclusiv access to the control and bulk messages. + * Returns the old value so it can be restored later. + */ +int usb_disable_asynch(int disable) +{ + int old_value = asynch_allowed; + + asynch_allowed = !disable; + return old_value; +} + +static void notify_new_dev_attach() +{ + int i; + struct usb_hub_device *hub = NULL; + struct usb_device *dev = NULL; + //int ret; + + hub = &hub_dev[0]; + if (NULL == hub) + return; + dev = hub->pusb_dev; + + for (i = 0; i < dev->maxchild; i++) { + struct usb_device_scan *usb_scan; + + usb_scan = malloc(sizeof(*usb_scan)); + if (!usb_scan) { + //printf("Can't allocate memory for USB device!\n"); + return; + } + memset(usb_scan, 0, sizeof(struct usb_device_scan)); + usb_scan->dev = dev; + usb_scan->hub = hub; + usb_scan->port = i; + INIT_LIST_ITEM(&usb_scan->list); + //listSET_LIST_ITEM_OWNER(usb_scan->list.pvOwner, usb_scan); + usb_scan->list.pvOwner = (void*)usb_scan; + list_add_tail(&usb_scan->list, &usb_scan_list); + } +} + +static void hub_usb_dev_reset() +{ + int i; + struct usb_device *dev; + + //usb_disable_endpoint(); + reset_usb_phy(); + usb_clear_port_feature(&usb_dev[0], 1, USB_PORT_FEAT_C_ENABLE); + for (i = 1; i < USB_MAX_DEVICE; i++) { + dev = &usb_dev[i]; + if (dev->devnum != -1) { + memset(dev, 0, sizeof(struct usb_device)); + dev->devnum = -1; + if (dev_index > 0) + dev_index--; + } + } +} + +int ark_usb_init(void) +{ + void *ctrl = NULL; + struct usb_device *dev; + int i, start_index = 0; + int controllers_initialized = 0; + int ret; + unsigned int start_time; + + usb_sysctrl_init(); + dev_index = 0; + asynch_allowed = 1; + usb_hub_reset(); + + USB_UNUSED(start_index); + + vListInitialise(&usb_scan_list); + + /* first make all devices unknown */ + for (i = 0; i < USB_MAX_DEVICE; i++) { + memset(&usb_dev[i], 0, sizeof(struct usb_device)); + usb_dev[i].devnum = -1; + } + + + /* init low_level USB */ + ret = usb_dwc2_lowlevel_init(); + if (ret) { + SendUartString("lowlevel init failed\n"); + return -ENODEV; + } + /* + * lowlevel init is OK, now scan the bus for devices + * i.e. search HUBs and configure them + */ + controllers_initialized++; + start_index = dev_index; + ret = usb_alloc_new_device(ctrl, &dev);//usb 0 for root hub + if (ret) + return -ENODEV; + + /* + * device 0 is always present + * (root hub, so let it analyze) + */ + ret = usb_new_device(dev); + if (ret) + usb_free_device(dev->controller); + + start_time = get_timer(0); + while(1) { + char buf[8] = {0}; + int ret = 1; + char status = 0; + + if (get_timer(start_time) > 10000) //10s timeout + break; + + hub_status_data(buf); + status = (buf[0] >> 1) & 0x1; + if (connect_status != status) { + PrintVariableValueHex("usb state changed now!state", buf[0]); + connect_status = status; + if (status) { + notify_new_dev_attach(); + usb_disable_endpoint(); + ret = usb_device_list_scan(); + if (!ret) { + return 0; + } + } else { + usb_stor_disconnect(); + hub_usb_dev_reset(); + return -1; + } + } + + mdelay(100); + } + + return -1; +} diff --git a/A58-STEPLDR/Src/usb/usb_massstorage.c b/A58-STEPLDR/Src/usb/usb_massstorage.c new file mode 100644 index 00000000..8a8dc2aa --- /dev/null +++ b/A58-STEPLDR/Src/usb/usb_massstorage.c @@ -0,0 +1,847 @@ +#include +#include +#include +#include + +#define CONFIG_USB_STORAGE + +#include "usb_os_adapter.h" +#include "trace.h" +#include +#include "scsi.h" +#include "usb.h" +#include "dwc2_compat.h" +#include +#include "ark_dwc2.h" +#include "usb_massstorage.h" +#include "timer.h" +#include "fs/ff.h" +#include "fs/diskio.h" + +/* direction table -- this indicates the direction of the data + * transfer for each command code -- a 1 indicates input + */ +static const unsigned char us_direction[256/8] = { + 0x28, 0x81, 0x14, 0x14, 0x20, 0x01, 0x90, 0x77, + 0x0C, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +#define US_DIRECTION(x) ((us_direction[x>>3] >> (x & 7)) & 1) + +#pragma pack(ARCH_DMA_MINALIGN) +static struct scsi_cmd usb_ccb; +static u32 CBWTag; + +static int usb_max_devs; /* number of highest available usb device */ + +struct blk_desc usb_dev_desc[6]; + +struct us_data; +typedef int (*trans_cmnd)(struct scsi_cmd *cb, struct us_data *data); +typedef int (*trans_reset)(struct us_data *data); + +#define USB_READY (1 << 0) +struct us_data { + struct usb_device *pusb_dev; /* this usb_device */ + unsigned int flags; /* from filter initially */ + unsigned char ifnum; /* interface number */ + unsigned char ep_in; /* in endpoint */ + unsigned char ep_out; /* out ....... */ + unsigned char ep_int; /* interrupt . */ + unsigned char subclass; /* as in overview */ + unsigned char protocol; /* .............. */ + unsigned char attention_done; /* force attn on first cmd */ + unsigned short ip_data; /* interrupt data */ + int action; /* what to do */ + int ip_wanted; /* needed */ + int *irq_handle; /* for USB int requests */ + unsigned int irqpipe; /* pipe for release_irq */ + unsigned char irqmaxp; /* max packed for irq Pipe */ + unsigned char irqinterval; /* Intervall for IRQ Pipe */ + struct scsi_cmd *srb; /* current srb */ + trans_reset transport_reset; /* reset routine */ + trans_cmnd transport; /* transport routine */ + unsigned short max_xfer_blk; /* maximum transfer blocks */ +}; + +static struct us_data usb_stor[USB_MAX_STOR_DEV]; + +#define USB_STOR_TRANSPORT_GOOD 0 +#define USB_STOR_TRANSPORT_FAILED -1 +#define USB_STOR_TRANSPORT_ERROR -2 + +static int usb_media_ready = 0; + +/*********************************************************************** + * Data transfer routines + ***********************************************************************/ + +static unsigned int usb_get_max_lun(struct us_data *us) +{ + int len; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, result, 1); + len = usb_control_msg(us->pusb_dev, + usb_rcvctrlpipe(us->pusb_dev, 0), + US_BBB_GET_MAX_LUN, + USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN, + 0, us->ifnum, + result, sizeof(char), + USB_CNTL_TIMEOUT * 5); + //debug("Get Max LUN -> len = %i, result = %i\n", len, (int) *result); + return (len > 0) ? *result : 0; +} + +static int usb_stor_BBB_reset(struct us_data *us) +{ + int result; + unsigned int pipe; + + /* + * Reset recovery (5.3.4 in Universal Serial Bus Mass Storage Class) + * + * For Reset Recovery the host shall issue in the following order: + * a) a Bulk-Only Mass Storage Reset + * b) a Clear Feature HALT to the Bulk-In endpoint + * c) a Clear Feature HALT to the Bulk-Out endpoint + * + * This is done in 3 steps. + * + * If the reset doesn't succeed, the device should be port reset. + * + * This comment stolen from FreeBSD's /sys/dev/usb/umass.c. + */ + //debug("BBB_reset\n"); + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), + US_BBB_RESET, + USB_TYPE_CLASS | USB_RECIP_INTERFACE, + 0, us->ifnum, NULL, 0, USB_CNTL_TIMEOUT * 5); + + if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { + //debug("RESET:stall\n"); + return -1; + } + if (usb_media_ready == 0) + return -1; + + /* long wait for reset */ + mdelay(150); + /* debug("BBB_reset result %d: status %lX reset\n", + result, us->pusb_dev->status); */ + pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + result = usb_clear_halt(us->pusb_dev, pipe); + /* long wait for reset */ + mdelay(150); + /* debug("BBB_reset result %d: status %lX clearing IN endpoint\n", + result, us->pusb_dev->status); */ + /* long wait for reset */ + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + result = usb_clear_halt(us->pusb_dev, pipe); + mdelay(150); + /* debug("BBB_reset result %d: status %lX clearing OUT endpoint\n", + result, us->pusb_dev->status); + debug("BBB_reset done\n"); */ + return 0; +} + +/* + * Set up the command for a BBB device. Note that the actual SCSI + * command is copied into cbw.CBWCDB. + */ +static int usb_stor_BBB_comdat(struct scsi_cmd *srb, struct us_data *us) +{ + int result; + int actlen; + int dir_in; + unsigned int pipe; + ALLOC_CACHE_ALIGN_BUFFER(struct umass_bbb_cbw, cbw, 1); + + dir_in = US_DIRECTION(srb->cmd[0]); + + /* sanity checks */ + if (!(srb->cmdlen <= CBWCDBLENGTH)) { + //debug("usb_stor_BBB_comdat:cmdlen too large\n"); + return -1; + } + + /* always OUT to the ep */ + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + + cbw->dCBWSignature = cpu_to_le32(CBWSIGNATURE); + cbw->dCBWTag = cpu_to_le32(CBWTag++); + cbw->dCBWDataTransferLength = cpu_to_le32(srb->datalen); + cbw->bCBWFlags = (dir_in ? CBWFLAGS_IN : CBWFLAGS_OUT); + cbw->bCBWLUN = srb->lun; + cbw->bCDBLength = srb->cmdlen; + /* copy the command data into the CBW command data buffer */ + /* DST SRC LEN!!! */ + + memcpy(cbw->CBWCDB, srb->cmd, srb->cmdlen); + result = usb_bulk_msg(us->pusb_dev, pipe, cbw, UMASS_BBB_CBW_SIZE, + &actlen, USB_CNTL_TIMEOUT * 5); + if (result < 0) + ;//debug("usb_stor_BBB_comdat:usb_bulk_msg error\n"); + return result; +} + +#define USB_TRANSPORT_UNKNOWN_RETRY 5 +#define USB_TRANSPORT_NOT_READY_RETRY 10 + +/* clear a stall on an endpoint - special for BBB devices */ +static int usb_stor_BBB_clear_endpt_stall(struct us_data *us, u8 endpt) +{ + /* ENDPOINT_HALT = 0, so set value to 0 */ + return usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, + endpt, NULL, 0, USB_CNTL_TIMEOUT * 5); +} + +static int usb_stor_BBB_transport(struct scsi_cmd *srb, struct us_data *us) +{ + int result, retry; + int dir_in; + int actlen, data_actlen; + unsigned int pipe, pipein, pipeout; + ALLOC_CACHE_ALIGN_BUFFER(struct umass_bbb_csw, csw, 1); + + dir_in = US_DIRECTION(srb->cmd[0]); + + /* COMMAND phase */ + //debug("COMMAND phase\n"); + result = usb_stor_BBB_comdat(srb, us); + if (result < 0) { + /* debug("failed to send CBW status %ld\n", + us->pusb_dev->status); */ + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } + if (!(us->flags & USB_READY)) + mdelay(5); + pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + /* DATA phase + error handling */ + data_actlen = 0; + /* no data, go immediately to the STATUS phase */ + if (srb->datalen == 0) + goto st; + //debug("DATA phase\n"); + if (dir_in) + pipe = pipein; + else + pipe = pipeout; + + result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, + &data_actlen, USB_CNTL_TIMEOUT * 5); + + /* special handling of STALL in DATA phase */ + if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { + //debug("DATA:stall\n"); + /* clear the STALL on the endpoint */ + result = usb_stor_BBB_clear_endpt_stall(us, + dir_in ? us->ep_in : us->ep_out); + if (result >= 0) + /* continue on to STATUS phase */ + goto st; + } + if (result < 0) { + /* debug("usb_bulk_msg error status %ld\n", + us->pusb_dev->status); */ + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } + + /* STATUS phase + error handling */ + char *tmpcsw; +st: + retry = 0; +again: + //debug("STATUS phase\n"); + tmpcsw = (char *)csw; + tmpcsw[0] = 0x55; + tmpcsw[1] = 0x53; + tmpcsw[2] = 0x42; + tmpcsw[3] = 0x43; + tmpcsw[4] = 0x01; + tmpcsw[5] = 0x00; + tmpcsw[6] = 0x00; + tmpcsw[7] = 0x00; + tmpcsw[8] = 0x24; + tmpcsw[9] = 0x00; + tmpcsw[10] = 0x00; + tmpcsw[11] = 0x00; + tmpcsw[12] = 0x80; + + + result = usb_bulk_msg(us->pusb_dev, pipein, csw, UMASS_BBB_CSW_SIZE, + &actlen, USB_CNTL_TIMEOUT); + + /* special handling of STALL in STATUS phase */ + if ((result < 0) && (retry < 1) && + (us->pusb_dev->status & USB_ST_STALLED)) { + //debug("STATUS:stall\n"); + /* clear the STALL on the endpoint */ + result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in); + if (result >= 0 && (retry++ < 1)) + /* do a retry */ + goto again; + } + if (result < 0) { + /* debug("usb_bulk_msg error status %ld\n", + us->pusb_dev->status); */ + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } + + /* misuse pipe to get the residue */ + pipe = le32_to_cpu(csw->dCSWDataResidue); + if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0) + pipe = srb->datalen - data_actlen; + if (CSWSIGNATURE != le32_to_cpu(csw->dCSWSignature)) { + //debug("!CSWSIGNATURE\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if ((CBWTag - 1) != le32_to_cpu(csw->dCSWTag)) { + //debug("!Tag\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if (csw->bCSWStatus > CSWSTATUS_PHASE) { + //debug(">PHASE\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if (csw->bCSWStatus == CSWSTATUS_PHASE) { + //debug("=PHASE\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if (data_actlen > srb->datalen) { + /* debug("transferred %dB instead of %ldB\n", + data_actlen, srb->datalen); */ + return USB_STOR_TRANSPORT_FAILED; + } else if (csw->bCSWStatus == CSWSTATUS_FAILED) { + //debug("FAILED\n"); + return USB_STOR_TRANSPORT_FAILED; + } + + return result; +} + +static int usb_stor_irq(struct usb_device *dev) +{ + struct us_data *us; + us = (struct us_data *)dev->privptr; + + if (us->ip_wanted) + us->ip_wanted = 0; + return 0; +} + +static void usb_stor_set_max_xfer_blk(struct usb_device *udev, + struct us_data *us) +{ + unsigned short blk = 20; + + us->max_xfer_blk = blk; +} + +static int usb_inquiry(struct scsi_cmd *srb, struct us_data *ss) +{ + int retry, i; + retry = 5; + do { + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_INQUIRY; + srb->cmd[1] = srb->lun << 5; + srb->cmd[4] = 36; + srb->datalen = 36; + srb->cmdlen = 12; + i = ss->transport(srb, ss); + //debug("inquiry returns %d\n", i); + if (i == 0) + break; + } while (--retry); + + if (!retry) { + //printf("error in inquiry\n"); + return -1; + } + return 0; +} + +static int usb_request_sense(struct scsi_cmd *srb, struct us_data *ss) +{ + char *ptr; + int ret = -1; + + ptr = (char *)srb->pdata; + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_REQ_SENSE; + srb->cmd[1] = srb->lun << 5; + srb->cmd[4] = 18; + srb->datalen = 18; + srb->pdata = &srb->sense_buf[0]; + srb->cmdlen = 12; + ret = ss->transport(srb, ss); + /* debug("Request Sense returned %02X %02X %02X\n", + srb->sense_buf[2], srb->sense_buf[12], + srb->sense_buf[13]); */ + srb->pdata = (unsigned char *)ptr; + return ret; +} + +static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) +{ + int retries = 10; + int ret = -1; + + do { + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_TST_U_RDY; + srb->cmd[1] = srb->lun << 5; + srb->datalen = 0; + srb->cmdlen = 12; + if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) { + ss->flags |= USB_READY; + return 0; + } + ret = usb_request_sense(srb, ss); + if (ret != USB_STOR_TRANSPORT_GOOD) + break; + /* + * Check the Key Code Qualifier, if it matches + * "Not Ready - medium not present" + * (the sense Key equals 0x2 and the ASC is 0x3a) + * return immediately as the medium being absent won't change + * unless there is a user action. + */ + if ((srb->sense_buf[2] == 0x02) && + (srb->sense_buf[12] == 0x3a)) + return -1; + if (usb_media_ready == 0) + break; + mdelay(100); + } while (retries--); + + return -1; +} + +static int usb_read_capacity(struct scsi_cmd *srb, struct us_data *ss) +{ + int retry; + /* XXX retries */ + retry = 3; + do { + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_RD_CAPAC; + srb->cmd[1] = srb->lun << 5; + srb->datalen = 8; + srb->cmdlen = 12; + if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) + return 0; + } while (retry--); + + return -1; +} + +static int usb_read_10(struct scsi_cmd *srb, struct us_data *ss, + unsigned long start, unsigned short blocks) +{ + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_READ10; + srb->cmd[1] = srb->lun << 5; + srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff; + srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff; + srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff; + srb->cmd[5] = ((unsigned char) (start)) & 0xff; + srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff; + srb->cmd[8] = (unsigned char) blocks & 0xff; + srb->cmdlen = 12; + //debug("read10: start %lx blocks %x\n", start, blocks); + return ss->transport(srb, ss); +} + +/* Probe to see if a new device is actually a Storage device */ +int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, + struct us_data *ss) +{ + struct usb_interface *iface; + int i; + struct usb_endpoint_descriptor *ep_desc; + unsigned int flags = 0; + + /* let's examine the device now */ + iface = &dev->config.if_desc[ifnum]; + if (dev->descriptor.bDeviceClass != 0 || + iface->desc.bInterfaceClass != USB_CLASS_MASS_STORAGE || + iface->desc.bInterfaceSubClass < US_SC_MIN || + iface->desc.bInterfaceSubClass > US_SC_MAX) { + //SendUartString("Not mass storage\r\n"); + /* if it's not a mass storage, we go no further */ + return 0; + } + memset(ss, 0, sizeof(struct us_data)); + usb_media_ready = 1; + + /* At this point, we know we've got a live one */ + //debug("\n\nUSB Mass Storage device detected\n"); + + /* Initialize the us_data structure with some useful info */ + ss->flags = flags; + ss->ifnum = ifnum; + ss->pusb_dev = dev; + ss->attention_done = 0; + ss->subclass = iface->desc.bInterfaceSubClass; + ss->protocol = iface->desc.bInterfaceProtocol; + + /* set the handler pointers based on the protocol */ + //debug("Transport: "); + switch (ss->protocol) { + case US_PR_BULK: + //debug("Bulk/Bulk/Bulk\n"); + ss->transport = usb_stor_BBB_transport; + ss->transport_reset = usb_stor_BBB_reset; + break; + default: + //printf("USB Storage Transport unknown / not yet implemented\n"); + return 0; + break; + } + + /* + * We are expecting a minimum of 2 endpoints - in and out (bulk). + * An optional interrupt is OK (necessary for CBI protocol). + * We will ignore any others. + */ + for (i = 0; i < iface->desc.bNumEndpoints; i++) { + ep_desc = &iface->ep_desc[i]; + /* is it an BULK endpoint? */ + if ((ep_desc->bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { + if (ep_desc->bEndpointAddress & USB_DIR_IN) + ss->ep_in = ep_desc->bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + else + ss->ep_out = + ep_desc->bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + } + + /* is it an interrupt endpoint? */ + if ((ep_desc->bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { + ss->ep_int = ep_desc->bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + ss->irqinterval = ep_desc->bInterval; + } + } + /* debug("Endpoints In %d Out %d Int %d\n", + ss->ep_in, ss->ep_out, ss->ep_int); */ + + /* Do some basic sanity checks, and bail if we find a problem */ + if (usb_set_interface(dev, iface->desc.bInterfaceNumber, 0) || + !ss->ep_in || !ss->ep_out || + (ss->protocol == US_PR_CBI && ss->ep_int == 0)) { + //debug("Problems with device\n"); + return 0; + } + /* set class specific stuff */ + /* We only handle certain protocols. Currently, these are + * the only ones. + * The SFF8070 accepts the requests used in u-boot + */ + if (ss->subclass != US_SC_UFI && ss->subclass != US_SC_SCSI && + ss->subclass != US_SC_8070) { + //printf("Sorry, protocol %d not yet supported.\n", ss->subclass); + return 0; + } + if (ss->ep_int) { + /* we had found an interrupt endpoint, prepare irq pipe + * set up the IRQ pipe and handler + */ + ss->irqinterval = (ss->irqinterval > 0) ? ss->irqinterval : 255; + ss->irqpipe = usb_rcvintpipe(ss->pusb_dev, ss->ep_int); + ss->irqmaxp = usb_maxpacket(dev, ss->irqpipe); + dev->irq_handle = usb_stor_irq; + } + + /* Set the maximum transfer size per host controller setting */ + usb_stor_set_max_xfer_blk(dev, ss); + + dev->privptr = (void *)ss; + return 1; +} + +int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, + struct blk_desc *dev_desc) +{ + unsigned char perq, modi; + ALLOC_CACHE_ALIGN_BUFFER(u32, cap, 2); + ALLOC_CACHE_ALIGN_BUFFER(u8, usb_stor_buf, 36); + u32 capacity, blksz; + struct scsi_cmd *pccb = &usb_ccb; + memset(usb_stor_buf, 0, 36); + pccb->pdata = usb_stor_buf; + + dev_desc->target = dev->devnum; + pccb->lun = dev_desc->lun; + //debug(" address %d\n", dev_desc->target); + + if (usb_inquiry(pccb, ss)) { + //debug("%s: usb_inquiry() failed\n", __func__); + return -1; + } + + perq = usb_stor_buf[0]; + modi = usb_stor_buf[1]; + + /* + * Skip unknown devices (0x1f) and enclosure service devices (0x0d), + * they would not respond to test_unit_ready . + */ + if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) { + //debug("%s: unknown/unsupported device\n", __func__); + return 0; + } + if ((modi&0x80) == 0x80) { + /* drive is removable */ + dev_desc->removable = 1; + } + memcpy(dev_desc->vendor, (const void *)&usb_stor_buf[8], 8); + memcpy(dev_desc->product, (const void *)&usb_stor_buf[16], 16); + memcpy(dev_desc->revision, (const void *)&usb_stor_buf[32], 4); + dev_desc->vendor[8] = 0; + dev_desc->product[16] = 0; + dev_desc->revision[4] = 0; + /* debug("ISO Vers %X, Response Data %X\n", usb_stor_buf[2], + usb_stor_buf[3]); */ + if (usb_test_unit_ready(pccb, ss)) { + /* printf("Device NOT ready\n" + " Request Sense returned %02X %02X %02X\n", + pccb->sense_buf[2], pccb->sense_buf[12], + pccb->sense_buf[13]); */ + if (dev_desc->removable == 1) + dev_desc->type = perq; + return 0; + } + pccb->pdata = (unsigned char *)cap; + memset(pccb->pdata, 0, 8); + if (usb_read_capacity(pccb, ss) != 0) { + //printf("READ_CAP ERROR\n"); + cap[0] = 2880; + cap[1] = 0x200; + } + ss->flags &= ~USB_READY; + //debug("Read Capacity returns: 0x%08x, 0x%08x\n", cap[0], cap[1]); +#if 0 + if (cap[0] > (0x200000 * 10)) /* greater than 10 GByte */ + cap[0] >>= 16; + + cap[0] = cpu_to_be32(cap[0]); + cap[1] = cpu_to_be32(cap[1]); +#endif + + capacity = be32_to_cpu(cap[0]) + 1; + blksz = be32_to_cpu(cap[1]); + + dev_desc->lba = capacity; + dev_desc->blksz = blksz; + dev_desc->log2blksz = LOG2(dev_desc->blksz); + dev_desc->type = perq; + + return 1; +} + +static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer) +{ + lbaint_t start, blks; + uintptr_t buf_addr; + unsigned short smallblks; + struct usb_device *udev; + struct us_data *ss; + int retry; + struct scsi_cmd *srb = &usb_ccb; + + if (blkcnt == 0) + return 0; + /* Setup device */ + udev = usb_dev_desc[block_dev->devnum].priv; + if (!udev) { + return 0; + } + + ss = (struct us_data *)udev->privptr; + usb_disable_asynch(1); /* asynch transfer not allowed */ + srb->lun = block_dev->lun; + buf_addr = (uintptr_t)buffer; + start = blknr; + blks = blkcnt; + + do { + retry = 2; + srb->pdata = (unsigned char *)buf_addr; + if (blks > ss->max_xfer_blk) + smallblks = ss->max_xfer_blk; + else + smallblks = (unsigned short) blks; +retry_it: + if (usb_media_ready == 0) + break; + /* if (smallblks == ss->max_xfer_blk) + usb_show_progress(); */ + srb->datalen = block_dev->blksz * smallblks; + srb->pdata = (unsigned char *)buf_addr; + if (usb_read_10(srb, ss, start, smallblks)) { + usb_request_sense(srb, ss); + if (retry--) + goto retry_it; + blkcnt -= blks; + break; + } + start += smallblks; + blks -= smallblks; + buf_addr += srb->datalen; + } while (blks != 0); + ss->flags &= ~USB_READY; + + usb_disable_asynch(0); + + return blkcnt; +} + +static int usb_stor_probe_device(struct usb_device *udev) +{ + int lun, max_lun; + int start; + + if (udev == NULL) + return -ENOENT; /* no more devices available */ + + //debug("\n\nProbing for storage\n"); + + /* We don't have space to even probe if we hit the maximum */ + if (usb_max_devs == USB_MAX_STOR_DEV) { + /* printf("max USB Storage Device reached: %d stopping\n", + usb_max_devs); */ + return -ENOSPC; + } + + if (!usb_storage_probe(udev, 0, &usb_stor[usb_max_devs])) + return 0; + + /* + * OK, it's a storage device. Iterate over its LUNs and populate + * usb_dev_desc' + */ + start = usb_max_devs; + + max_lun = usb_get_max_lun(&usb_stor[usb_max_devs]); + for (lun = 0; lun <= max_lun && usb_max_devs < USB_MAX_STOR_DEV; + lun++) { + struct blk_desc *blkdev; + + blkdev = &usb_dev_desc[usb_max_devs]; + memset(blkdev, '\0', sizeof(struct blk_desc)); + blkdev->if_type = IF_TYPE_USB; + blkdev->devnum = usb_max_devs; + blkdev->part_type = PART_TYPE_UNKNOWN; + blkdev->target = 0xff; + blkdev->type = DEV_TYPE_UNKNOWN; + blkdev->block_read = usb_stor_read; + //blkdev->block_write = usb_stor_write; + blkdev->lun = lun; + blkdev->priv = udev; + + if (usb_stor_get_info(udev, &usb_stor[start], + &usb_dev_desc[usb_max_devs]) == 1) { + //debug("partype: %d\n", blkdev->part_type); + //part_init(blkdev); + //debug("partype: %d\n", blkdev->part_type); + usb_max_devs++; + //debug("%s: Found device %p\n", __func__, udev); + /* blkdev->disk_priv = (void *)FF_USBDiskInit("/usb"); + if (NULL == blkdev->disk_priv) { + printf("FF_USBDiskInit failed\r\n"); + continue; + } + mdelay(200); + usb_disk_file_test(); */ + } + } + + return 0; +} + +void usb_stor_reset(void) +{ + usb_max_devs = 0; + CBWTag = 0; +} + +/******************************************************************************* + * scan the usb and reports device info + * to the user if mode = 1 + * returns current device or -1 if no + */ +int usb_stor_scan(int mode) +{ + unsigned char i; + + if (mode == 1) + SendUartString("scanning usb for storage devices... "); + + usb_disable_asynch(1); /* asynch transfer not allowed */ + + usb_stor_reset(); + for (i = 0; i < USB_MAX_DEVICE; i++) { + struct usb_device *dev; + + dev = usb_get_dev_index(i); /* get device */ + //debug("i=%d\n", i); + if (usb_stor_probe_device(dev)) + break; + } /* for */ + + usb_disable_asynch(0); /* asynch transfer allowed */ + + if (usb_max_devs > 0) { + SendUartString("Storage Device(s) found\r\n"); + return 0; + } + return -1; +} + +void usb_stor_disconnect() +{ + usb_media_ready = 0; +} + +int USB_disk_initialize(void) +{ + return 0; +} + +int USB_disk_read(void *buff, DWORD sector, BYTE count) +{ + struct blk_desc *dev_desc = &usb_dev_desc[0]; + + return dev_desc->block_read(dev_desc, sector, count, buff); +} + +int USB_disk_ioctl(BYTE ctrl, void *buff) +{ + struct blk_desc *dev_desc = &usb_dev_desc[0]; + + switch(ctrl) + { + case CTRL_SYNC: + break; + case GET_SECTOR_COUNT: + *(DWORD*)buff = dev_desc->lba; + break; + case GET_BLOCK_SIZE: + *(DWORD*)buff = 512; + break; + default: + return -1; + } + return 0; +} diff --git a/A58-STEPLDR/Src/usb/usb_massstorage.h b/A58-STEPLDR/Src/usb/usb_massstorage.h new file mode 100644 index 00000000..740d9e87 --- /dev/null +++ b/A58-STEPLDR/Src/usb/usb_massstorage.h @@ -0,0 +1,110 @@ +#ifndef __USB_MASS_STORAGE_H +#define __USB_MASS_STORAGE_H + + +/* Part types */ +#define PART_TYPE_UNKNOWN 0x00 +#define PART_TYPE_MAC 0x01 +#define PART_TYPE_DOS 0x02 +#define PART_TYPE_ISO 0x03 +#define PART_TYPE_AMIGA 0x04 +#define PART_TYPE_EFI 0x05 + +/* device types */ +#define DEV_TYPE_UNKNOWN 0xff /* not connected */ +#define DEV_TYPE_HARDDISK 0x00 /* harddisk */ +#define DEV_TYPE_TAPE 0x01 /* Tape */ +#define DEV_TYPE_CDROM 0x05 /* CD-ROM */ +#define DEV_TYPE_OPDISK 0x07 /* optical disk */ + +#define PART_NAME_LEN 32 +#define PART_TYPE_LEN 32 +#define MAX_SEARCH_PARTITIONS 64 + +typedef unsigned long lbaint_t; + +typedef struct { + u8 b[16]; +} efi_guid_t; + + +/* Interface types: */ +enum if_type { + IF_TYPE_UNKNOWN = 0, + IF_TYPE_IDE, + IF_TYPE_SCSI, + IF_TYPE_ATAPI, + IF_TYPE_USB, + IF_TYPE_DOC, + IF_TYPE_MMC, + IF_TYPE_SD, + IF_TYPE_SATA, + IF_TYPE_HOST, + IF_TYPE_NVME, + IF_TYPE_EFI, + + IF_TYPE_COUNT, /* Number of interface types */ +}; + +#define BLK_VEN_SIZE 40 +#define BLK_PRD_SIZE 20 +#define BLK_REV_SIZE 8 + +/* + * Identifies the partition table type (ie. MBR vs GPT GUID) signature + */ +enum sig_type { + SIG_TYPE_NONE, + SIG_TYPE_MBR, + SIG_TYPE_GUID, + + SIG_TYPE_COUNT /* Number of signature types */ +}; + +/* + * With driver model (CONFIG_BLK) this is uclass platform data, accessible + * with dev_get_uclass_platdata(dev) + */ +struct blk_desc { + /* + * TODO: With driver model we should be able to use the parent + * device's uclass instead. + */ + enum if_type if_type; /* type of the interface */ + int devnum; /* device number */ + unsigned char part_type; /* partition type */ + unsigned char target; /* target SCSI ID */ + unsigned char lun; /* target LUN */ + unsigned char hwpart; /* HW partition, e.g. for eMMC */ + unsigned char type; /* device type */ + unsigned char removable; /* removable device */ + lbaint_t lba; /* number of blocks */ + unsigned long blksz; /* block size */ + int log2blksz; /* for convenience: log2(blksz) */ + char vendor[BLK_VEN_SIZE + 1]; /* device vendor string */ + char product[BLK_PRD_SIZE + 1]; /* device product number */ + char revision[BLK_REV_SIZE + 1]; /* firmware revision */ + enum sig_type sig_type; /* Partition table signature type */ + union { + u32 mbr_sig; /* MBR integer signature */ + efi_guid_t guid_sig; /* GPT GUID Signature */ + }; + + unsigned long (*block_read)(struct blk_desc *block_dev, + lbaint_t start, + lbaint_t blkcnt, + void *buffer); + unsigned long (*block_write)(struct blk_desc *block_dev, + lbaint_t start, + lbaint_t blkcnt, + const void *buffer); + unsigned long (*block_erase)(struct blk_desc *block_dev, + lbaint_t start, + lbaint_t blkcnt); + void *priv; /* driver private struct pointer */ + void *disk_priv; +}; + +extern struct blk_desc usb_dev_desc[6]; + +#endif diff --git a/A58-STEPLDR/Src/usb/usb_os_adapter.c b/A58-STEPLDR/Src/usb/usb_os_adapter.c new file mode 100644 index 00000000..d9bf9aa1 --- /dev/null +++ b/A58-STEPLDR/Src/usb/usb_os_adapter.c @@ -0,0 +1,228 @@ +#include "usb_os_adapter.h" + +void *kmem_cache_alloc(struct kmem_cache *obj, int flag) +{ + (void)flag; + return pvPortMalloc(obj->sz); +} + +void kmem_cache_free(struct kmem_cache *cachep, void *obj) +{ + (void)cachep; + vPortFree(obj); +} + +void kmem_cache_destroy(struct kmem_cache *cachep) +{ + free(cachep); +} + +static void *kmalloc_array(size_t n, size_t size, gfp_t flags) +{ + void* ptr = NULL; + if (size != 0 && n > SIZE_MAX / size) + return NULL; + ptr = pvPortMalloc(n * size); + + if (flags & __GFP_ZERO) { + memset(ptr, 0, n * size); + } + + return ptr; +} + +void *kcalloc(size_t n, size_t size, gfp_t flags) +{ + return kmalloc_array(n, size, flags | __GFP_ZERO); +} + +void *kmalloc(size_t size, int flags) +{ + void *p; + + p = pvPortMalloc(size); + if (flags & __GFP_ZERO) + memset(p, 0, size); + + return p; +} + +void *kzalloc(size_t size, gfp_t flags) +{ + return kmalloc(size, flags | __GFP_ZERO); +} + +//struct device; +void *devm_kzalloc(struct device *dev, size_t size, gfp_t flags) +{ + return kmalloc(size, flags | __GFP_ZERO); +} + + +void kfree(void* addr) +{ + vPortFree(addr); +} + +struct kmem_cache *get_mem(int element_sz) +{ + struct kmem_cache *ret; + + ret = pvPortMalloc(sizeof(struct kmem_cache)); + ret->sz = element_sz; + + return ret; +} + + +static unsigned long _find_next_bit(const unsigned long *addr1, + const unsigned long *addr2, unsigned long nbits, + unsigned long start, unsigned long invert) +{ + unsigned long tmp; + + if (unlikely(start >= nbits)) + return nbits; + + tmp = addr1[start / BITS_PER_LONG]; + if (addr2) + tmp &= addr2[start / BITS_PER_LONG]; + tmp ^= invert; + + /* Handle 1st word. */ + tmp &= BITMAP_FIRST_WORD_MASK(start); + start = round_down(start, BITS_PER_LONG); + + while (!tmp) { + start += BITS_PER_LONG; + if (start >= nbits) + return nbits; + + tmp = addr1[start / BITS_PER_LONG]; + if (addr2) + tmp &= addr2[start / BITS_PER_LONG]; + tmp ^= invert; + } + + return min(start + __ffs(tmp), nbits); +} +unsigned long find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + return _find_next_bit(addr, NULL, size, offset, 0UL); +} + +unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + return _find_next_bit(addr, NULL, size, offset, ~0UL); +} + +unsigned long bitmap_find_next_zero_area_off(unsigned long *map, + unsigned long size, + unsigned long start, + unsigned int nr, + unsigned long align_mask, + unsigned long align_offset) +{ + unsigned long index, end, i; +again: + index = find_next_zero_bit(map, size, start); + + /* Align allocation */ + index = __ALIGN_MASK(index + align_offset, align_mask) - align_offset; + + end = index + nr; + if (end > size) + return end; + i = find_next_bit(map, end, index); + if (i < end) { + start = i + 1; + goto again; + } + return index; +} + +unsigned long +bitmap_find_next_zero_area(unsigned long *map, + unsigned long size, + unsigned long start, + unsigned int nr, + unsigned long align_mask) +{ + return bitmap_find_next_zero_area_off(map, size, start, nr, align_mask, 0); +} + +void bitmap_set(unsigned long *map, unsigned int start, int len) +{ + unsigned long *p = map + BIT_WORD(start); + const unsigned int size = start + len; + int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); + unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); + + while (len - bits_to_set >= 0) { + *p |= mask_to_set; + len -= bits_to_set; + bits_to_set = BITS_PER_LONG; + mask_to_set = ~0UL; + p++; + } + if (len) { + mask_to_set &= BITMAP_LAST_WORD_MASK(size); + *p |= mask_to_set; + } +} + +void bitmap_clear(unsigned long *map, unsigned int start, int len) +{ + unsigned long *p = map + BIT_WORD(start); + const unsigned int size = start + len; + int bits_to_clear = BITS_PER_LONG - (start % BITS_PER_LONG); + unsigned long mask_to_clear = BITMAP_FIRST_WORD_MASK(start); + + while (len - bits_to_clear >= 0) { + *p &= ~mask_to_clear; + len -= bits_to_clear; + bits_to_clear = BITS_PER_LONG; + mask_to_clear = ~0UL; + p++; + } + if (len) { + mask_to_clear &= BITMAP_LAST_WORD_MASK(size); + *p &= ~mask_to_clear; + } +} + +void writesl(u32 addr, const void *buffer, unsigned int count) +{ + if (count) { + const u32 *buf = (u32 *)buffer; + + do { + writel(*buf++, addr); + } while (--count); + } +} + +void readsl(u32 addr, void *buffer, unsigned int count) +{ + if (count) { + u32 *buf = (u32 *)buffer; + + do { + u32 x = readl(addr); + *buf++ = x; + } while (--count); + } +} + +void iowrite32_rep(u32 addr, const void *buffer, unsigned int count) +{ + writesl(addr, buffer, count); +} + +void ioread32_rep(u32 addr, void *buffer, unsigned int count) +{ + readsl(addr, buffer, count); +} + diff --git a/A58-STEPLDR/Src/usb/usb_os_adapter.h b/A58-STEPLDR/Src/usb/usb_os_adapter.h new file mode 100644 index 00000000..d241b471 --- /dev/null +++ b/A58-STEPLDR/Src/usb/usb_os_adapter.h @@ -0,0 +1,332 @@ +#ifndef _USB_OS_ADAPTER_H +#define _USB_OS_ADAPTER_H + +#include "os_adapt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define pr_err(...) TRACE_ERROR(__VA_ARGS__) +#define WARN_ON_ONCE(condition) WARN_ON(condition) + +#define USB_UNUSED(x) ((void) x) + +typedef INT8 __s8; +typedef UINT8 __u8; +typedef INT16 __s16; +typedef UINT16 __u16; +typedef INT32 __s32; +typedef UINT32 __u32; +typedef long long __s64; +typedef unsigned long long __u64; + +typedef __u16 __le16; +typedef __u16 __be16; +//typedef __u32 __le32; +typedef __u32 __be32; +typedef __u64 __le64; +typedef __u64 __be64; + +typedef unsigned long ulong; +typedef __u32 dev_t; + + +#define __cpu_to_le16(x) (x) +#define cpu_to_le16(x) (x) +#define __le16_to_cpu le16_to_cpu +#define get_unaligned(x) (*x) + + +void iowrite32_rep(u32 addr, const void *buffer, unsigned int count); +void ioread32_rep(u32 addr, void *buffer, unsigned int count); +unsigned long bitmap_find_next_zero_area(unsigned long *map, + unsigned long size, + unsigned long start, + unsigned int nr, + unsigned long align_mask); +void bitmap_set(unsigned long *map, unsigned int start, int len); +void bitmap_clear(unsigned long *map, unsigned int start, int len); + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(ListItem_t *item, List_t *list) +{ + if (!listIS_CONTAINED_WITHIN(NULL, item)) + uxListRemove(item); + vListInsertEnd(list, item); +} + +static inline void list_del_init(ListItem_t *item) +{ + if (!listIS_CONTAINED_WITHIN(NULL, item))//maybe item has removed from list + uxListRemove(item); + //vListInitialiseItem(item); +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(ListItem_t *item, List_t *list) +{ + vListInsertEnd(list, item); +} + +static inline void INIT_LIST_HEAD(List_t *list) +{ + vListInitialise(list); +} + +static inline void INIT_LIST_ITEM(ListItem_t *item) +{ + vListInitialiseItem(item); +} + +#define list_for_each_entry_safe(pxListItem, nListItem, pvOwner, list) \ + for (pxListItem = listGET_HEAD_ENTRY(list), \ + nListItem = listGET_NEXT(pxListItem), \ + pvOwner = listGET_LIST_ITEM_OWNER(pxListItem); \ + pxListItem != listGET_END_MARKER(list); \ + pxListItem = nListItem, \ + nListItem = listGET_NEXT(pxListItem), \ + pvOwner = listGET_LIST_ITEM_OWNER(pxListItem)) + +#define list_for_each_safe(pxListItem, nListItem, list) \ + for (pxListItem = listGET_HEAD_ENTRY(list), \ + nListItem = listGET_NEXT(pxListItem); \ + pxListItem != listGET_END_MARKER(list); \ + pxListItem = nListItem, \ + nListItem = listGET_NEXT(pxListItem)) + +#define list_del(pxListItem) uxListRemove(pxListItem) +#define list_empty(pxList) listLIST_IS_EMPTY(pxList) +#define list_item_empty(pxListItem) ((pxListItem)->pxContainer == NULL) + +#define __ARG_PLACEHOLDER_1 0, +#define config_enabled(cfg) _config_enabled(cfg) +#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value) +#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0) +#define ___config_enabled(__ignored, val, ...) val + +/* + * IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y' or 'm', + * 0 otherwise. + * + */ +#define IS_ENABLED(option) \ + (config_enabled(option) || config_enabled(option##_MODULE)) +struct timer_list +{ + int a; +}; + +struct unused { + int a; +}; +typedef struct unused unused_t; + + +#define task_pid_nr(x) 0 +#define set_freezable(...) do { } while (0) +#define try_to_freeze(...) 0 +#define set_current_state(...) do { } while (0) +#define kthread_should_stop(...) 0 +#define schedule() do { } while (0) + +#define setup_timer(timer, func, data) do {} while (0) +#define del_timer_sync(timer) do {} while (0) +#define schedule_work(work) do {} while (0) +#define INIT_WORK(work, fun) do {} while (0) +#define local_irq_save(flag) do {(void)flag;} while (0) +#define local_irq_restore(flag) do {(void)flag;} while (0) + +//#define local_irq_save(flag) do {portENTER_CRITICAL(); (void)flag;} while(0) +//#define local_irq_restore(flag) do {portEXIT_CRITICAL(); (void)flag;} while(0) + + +struct work_struct { +int a; +}; + +struct kmem_cache { + int sz; +}; + +typedef int wait_queue_head_t; + + +typedef struct { + volatile unsigned int slock; +} spinlock_t; + +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + //TODO + unsigned volatile long y; + switch(size){ + case 1: + y = (*(char *)ptr) & 0x000000ff; + *((char *)ptr) = (char)x; + break; + case 2: + y = (*(short *)ptr) & 0x0000ffff; + *((short *)ptr) = (short)x; + break; + default: // 4 + y = (*(unsigned long *)ptr) & 0xffffffff; + *((unsigned long *)ptr) = x; + break; + } + return y; +} + +#define ARCH_SPIN_LOCK_UNLOCKED 1 +#define arch_spin_is_locked(x) (*(volatile signed char *)(&(x)->slock) <= 0) +#define arch_spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) +#define xchg(ptr,v) ((unsigned int)__xchg((unsigned long)(v),(ptr),sizeof(*(ptr)))) +#define __xg(x) ((volatile long *)(x)) + +static inline void _raw_spin_unlock(spinlock_t *lock) +{ + xchg(&lock->slock, 1); +} + +static inline int _raw_spin_trylock(spinlock_t *lock) +{ + return xchg(&lock->slock, 0) != 0 ? 1 : 0; +} + +static inline void _raw_spin_lock(spinlock_t *lock) +{ + volatile int was_locked; + do { + was_locked = xchg(&lock->slock, 0) == 0 ? 1 : 0; + } while(was_locked); +} + +#define SPINLOCK_MAGIC 0xdead4ead +#define SPIN_LOCK_UNLOCKED ARCH_SPIN_LOCK_UNLOCKED +#define spin_lock_init(x) do { (x)->slock = SPIN_LOCK_UNLOCKED; } while(0) +#define spin_is_locked(x) arch_spin_is_locked(x) +#define spin_unlock_wait(x) arch_spin_unlock_wait(x) +#define _spin_trylock(lock) ({_raw_spin_trylock(lock) ? \ + 1 : ({ 0;});}) +#define _spin_lock(lock) \ +do { \ + _raw_spin_lock(lock); \ +} while(0) + +#define _spin_unlock(lock) \ +do { \ + _raw_spin_unlock(lock); \ +} while (0) + +#define spin_lock(lock) _spin_lock(lock) +#define spin_unlock(lock) _spin_unlock(lock) +#define DEFINE_SPINLOCK(x) spinlock_t x = SPIN_LOCK_UNLOCKED + + +#define spin_lock_irqsave(lock, flags) \ +do { \ + flags = __get_interrupt_state(); __disable_irq(); \ +} while (0) + +#define spin_unlock_irqrestore(lock, flags) \ +do { \ + __set_interrupt_state(flags); \ +} while (0) + +#define assert_spin_locked(lock) do {} while (0) + +#define irqreturn_t int +#define IRQ_NONE 0 +#define IRQ_HANDLED 1 +#define IRQ_WAKE_THREAD 2 +#define GFP_ATOMIC ((gfp_t) 0) +#define GFP_KERNEL ((gfp_t) 0) +#define GFP_NOFS ((gfp_t) 0) +#define GFP_USER ((gfp_t) 0) +#define __GFP_NOWARN ((gfp_t) 0) +#define __GFP_ZERO ((gfp_t)0x8000u) +#define UINT_MAX (~0U) + +void *kmem_cache_alloc(struct kmem_cache *obj, int flag); +void kmem_cache_free(struct kmem_cache *cachep, void *obj); +void kmem_cache_destroy(struct kmem_cache *cachep); + +void *kcalloc(size_t n, size_t size, gfp_t flags); +void *kmalloc(size_t size, int flags); +void *kzalloc(size_t size, gfp_t flags); +void kfree(void* addr); +struct device; +void *devm_kzalloc(struct device *dev, size_t size, gfp_t flags); +struct kmem_cache *get_mem(int element_sz); +#define kmem_cache_create(a, sz, c, d, e) get_mem(sz) + + + +#define min_t(type, x, y) (x < y ? x: y) +#define max_t(type, x, y) (x > y ? x: y) +#define msleep mdelay + +#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) +#define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) +#define __round_mask(x, y) ((unsigned long)((y)-1)) +#define round_down(x, y) ((x) & ~(__round_mask((x), (y)))) +#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) + + +//#define min(x,y) ((x) < (y) ? x : y) +#define max(x,y) ((x) > (y) ? x : y) + + +#define min3(x, y, z) min(min(x, y), z) +#define max3(x, y, z) max(max(x, y), z) + +#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +#define ALIGN(x,a) __ALIGN_MASK((x),(uintptr_t)(a)-1) +//#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) + + +//typedef unsigned long uintptr_t; + +#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) +#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) +#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ + char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ + + (align - 1)]; \ + \ + type *name = (type *)ALIGN((uintptr_t)__##name, align) +#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) +#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) +#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ + ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +#define be32_to_cpu(x) ((uint32_t)( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define LOG2(x) (((x & 0xaaaaaaaa) ? 1 : 0) + ((x & 0xcccccccc) ? 2 : 0) + \ + ((x & 0xf0f0f0f0) ? 4 : 0) + ((x & 0xff00ff00) ? 8 : 0) + \ + ((x & 0xffff0000) ? 16 : 0)) + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/A58-STEPLDR/Src/wdt.c b/A58-STEPLDR/Src/wdt.c new file mode 100644 index 00000000..35083edc --- /dev/null +++ b/A58-STEPLDR/Src/wdt.c @@ -0,0 +1,142 @@ +#include "amt630h.h" +#include "uart.h" + +#define WTCON 0x00 +#define WTPSR 0x04 +#define WTCNT 0x08 +#define WTCLRINT 0x10 +#define WTRCR 0x14 + +#define WTCNT_MAXCNT 0xffff +#define WTCON_MAXDIV 0x80 + +#define WTCON_ENABLE (1 << 0) +#define WTCON_RSTEN (1 << 1) +#define WTCON_INTEN (1 << 2) + +#define WTCON_DIV16 (0 << 4) +#define WTCON_DIV32 (1 << 4) +#define WTCON_DIV64 (2 << 4) +#define WTCON_DIV128 (3 << 4) +#define WTCON_DIVMASK (0x3 << 4) + +#define WTCON_PRESCALE_MAX 0x10000 + +#define WATCHDOG_DEFAULT_TIME (3) + +#define CLK_APB_FREQ 198000000 + +static int wdt_timeout = WATCHDOG_DEFAULT_TIME; +static int soft_noboot = 0; /* 1: not reboot when watchdog timer expired */ +static int wdt_count; + +static inline unsigned int wdt_max_timeout() +{ + unsigned long freq = CLK_APB_FREQ; + + return WTCNT_MAXCNT / (freq / WTCON_PRESCALE_MAX + / WTCON_MAXDIV); +} + +int wdt_set_heartbeat(unsigned int timeout) +{ + unsigned long freq = CLK_APB_FREQ; + unsigned int count; + unsigned int divisor = 1; + + if (timeout < 1 || timeout > wdt_max_timeout()) + return -EINVAL; + + freq = DIV_ROUND_UP(freq, 128); + count = timeout * freq; + + /* TRACE_DEBUG("Heartbeat: count=%d, timeout=%d, freq=%lu\n", + count, timeout, freq); */ + + /* if the count is bigger than the watchdog register, + then work out what we need to do (and if) we can + actually make this value + */ + + if (count >= 0x10000) { + divisor = DIV_ROUND_UP(count, 0xffff); + + if (divisor > WTCON_PRESCALE_MAX) { + SendUartString("timeout too big\n"); + return -EINVAL; + } + } + + /* TRACE_DEBUG("Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", + timeout, divisor, count, DIV_ROUND_UP(count, divisor)); */ + + count = DIV_ROUND_UP(count, divisor); + wdt_count = count; + + /* update the pre-scaler */ + writel(divisor - 1, WDT_BASE + WTPSR); + + writel(count, WDT_BASE + WTCNT); + + wdt_timeout = timeout; + + return 0; +} + +void wdt_stop(void) +{ + unsigned long wtcon; + + wtcon = readl(WDT_BASE + WTCON); + wtcon &= ~(WTCON_ENABLE | WTCON_RSTEN); + writel(wtcon, WDT_BASE + WTCON); +} + +void wdt_start(void) +{ + unsigned long wtcon; + + wdt_stop(); + + wtcon = readl(WDT_BASE + WTCON); + wtcon &= ~WTCON_DIVMASK; + wtcon |= WTCON_ENABLE | WTCON_DIV128; + if (soft_noboot) { + wtcon |= WTCON_INTEN; + wtcon &= ~WTCON_RSTEN; + } else { + wtcon &= ~WTCON_INTEN; + wtcon |= WTCON_RSTEN; + } + + /* TRACE_DEBUG("Starting watchdog: count=0x%08x, wtcon=%08lx\n", + wdt_count, wtcon); */ + + writel(wdt_count, WDT_BASE + WTCNT); + writel(wtcon, WDT_BASE + WTCON); +} + +int wdt_init(void) +{ + int ret; + + wdt_stop(); + + ret = wdt_set_heartbeat(wdt_timeout); + if (ret) { + SendUartString("failed to set timeout value\n"); + } + + wdt_start(); + + return 0; +} + +void wdt_cpu_reboot(void) +{ + SendUartString("cpu reboot...\n"); + soft_noboot = 0; + wdt_count = 300; + wdt_start(); + while(1); +} diff --git a/A58-STEPLDR/gen_checksum.exe b/A58-STEPLDR/gen_checksum.exe new file mode 100644 index 0000000000000000000000000000000000000000..6ba579024911f7f0e5e5df93c2c98d8cddf6543a GIT binary patch literal 887808 zcmeFa33yb+*6-b!pn-%0OcWtvL{OALAgDk90ck}gm;eDp<}n08goHtvViTopnnA%4 zWK>a6abQx=Fi1c_QBhD)gQD(`s8JCD2KxK`tGhD*qQ2+c_q+Fb;2f)~Y7Mn&)vBsh ztM=YW>^;{OVzb#o`OoXM+1B%`f9*_q?xYBC)l1*3YI~#7?#tE(b>4kh_tX*N;>L`< zd-&Laqv8e+96kE(^teGoStS8p^rBmxknY9A{ z-ErytHJehtP*wk21$)mLtMbz5sG|MY)z zfp@Xl3XfH@wKyGCrd+?MTKTa`s&3mBR0iR+Y~%Ey6VnHc8~5q&H0qb@G!)wsn=RMi z0l4xRbP&&xSYjuDe0p*9T&qEiY(xkS%Z4c9MPbNvhvrx8;2`w1O>fWxa~Fyx)%o+wy8prszrywdD=D5Q@du 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+ + + + diff --git a/A58-STEPLDR/settings/stepldr_Debug.jlink b/A58-STEPLDR/settings/stepldr_Debug.jlink new file mode 100644 index 00000000..2d53bb4a --- /dev/null +++ b/A58-STEPLDR/settings/stepldr_Debug.jlink @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="UNSPECIFIED" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/A58-STEPLDR/stepldr.dep b/A58-STEPLDR/stepldr.dep new file mode 100644 index 00000000..4b1cf6ad --- /dev/null +++ b/A58-STEPLDR/stepldr.dep @@ -0,0 +1,1126 @@ + + + 4 + 1334301929 + + Debug + + $PROJ_DIR$\Src\cp15.c + $PROJ_DIR$\Src\os_adapt.c + $PROJ_DIR$\Src\sdmmc.c + $PROJ_DIR$\Src\list.h + $PROJ_DIR$\Src\exception.c + $PROJ_DIR$\Src\sdmmc.h + $PROJ_DIR$\Src\SpiBooter.c + $PROJ_DIR$\Src\lcd.c + $PROJ_DIR$\Src\SpinandBooter.c + $PROJ_DIR$\Src\pxp.h + $PROJ_DIR$\Src\spi.h + $PROJ_DIR$\Src\usb\hcd_intr.c + $PROJ_DIR$\Src\usb\usb_massstorage.c + $PROJ_DIR$\Src\crc32.h + $PROJ_DIR$\Src\usb\platform.c + $PROJ_DIR$\Src\usb\usb.c + $PROJ_DIR$\Src\usb\params.c + $PROJ_DIR$\Src\usb\usb_os_adapter.c + $PROJ_DIR$\Src\board.h + $PROJ_DIR$\Src\cp15_asm_iar.s + $PROJ_DIR$\Src\aic.c + $PROJ_DIR$\Src\gpio.c + $PROJ_DIR$\Src\Entry.c + $PROJ_DIR$\Src\i2c-gpio.c + $PROJ_DIR$\Src\crc32.c + $PROJ_DIR$\Src\Boot.s + $PROJ_DIR$\Src\i2c.c + $PROJ_DIR$\Src\mipi.c + $PROJ_DIR$\Src\mmu.c + $PROJ_DIR$\Src\pinctrl.c + $PROJ_DIR$\Src\pxp.c + $PROJ_DIR$\Src\usb\hcd_queue.c + $PROJ_DIR$\Src\fs\diskio.c + $PROJ_DIR$\Src\usb\ark_dwc2.c + $PROJ_DIR$\Src\usb\core_intr.c + $PROJ_DIR$\Src\usb\hcd.c + $PROJ_DIR$\Src\fs\integer.h + $PROJ_DIR$\Src\fs\ff.h + $PROJ_DIR$\Src\fs\diskio.h + $PROJ_DIR$\Src\fs\ff.c + $PROJ_DIR$\FreeRTOS\Source\portable\MemMang\heap_4.c + $PROJ_DIR$\Src\usb\core.c + $PROJ_DIR$\FreeRTOS\Source\list.c + $PROJ_DIR$\Src\usb\usb_massstorage.h + $PROJ_DIR$\Debug\Obj\wdt.pbi + $PROJ_DIR$\Debug\Exe\stepldr.out + $PROJ_DIR$\Src\usb\ark_dwc2.h + $TOOLKIT_DIR$\inc\c\stdbool.h + $PROJ_DIR$\Debug\Obj\core_intr.pbi + $TOOLKIT_DIR$\inc\c\string.h + $PROJ_DIR$\Debug\Obj\mipi.pbi + $PROJ_DIR$\Src\usb\include\usb_defs.h + $PROJ_DIR$\Debug\Obj\cp15.pbi + $PROJ_DIR$\Debug\Obj\list.o + $PROJ_DIR$\Src\usb\include\asm\dma-mapping.h + $TOOLKIT_DIR$\inc\c\stdint.h + $PROJ_DIR$\Debug\Obj\heap_4.o + $PROJ_DIR$\FreeRTOS\Source\include\FreeRTOSConfig.h + $PROJ_DIR$\Debug\Exe\stepldr.bin + $TOOLKIT_DIR$\inc\c\ysizet.h + $TOOLKIT_DIR$\lib\m7Sx_tl.a + $TOOLKIT_DIR$\inc\c\stddef.h + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\Src\trace.h + $PROJ_DIR$\Src\update.h + $PROJ_DIR$\Debug\Obj\SpiBooter.o + $PROJ_DIR$\Src\pinctrl.h + $PROJ_DIR$\Debug\Obj\sysctl.pbi + $PROJ_DIR$\Debug\Obj\gpio.pbi + $PROJ_DIR$\Debug\Obj\usb_massstorage.o + $PROJ_DIR$\Debug\Obj\ark_dwc2.o + $PROJ_DIR$\Debug\Obj\params.o + $PROJ_DIR$\Debug\Obj\usb_os_adapter.pbi + $PROJ_DIR$\Debug\Obj\update.o + $PROJ_DIR$\Debug\Obj\gpio.o + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\Debug\Obj\exception.pbi + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $TOOLKIT_DIR$\inc\c\ctype.h + $PROJ_DIR$\Src\usb\hw.h + $TOOLKIT_DIR$\lib\dl7Sx_tln.a + $PROJ_DIR$\Src\usb\include\scsi.h + $PROJ_DIR$\Debug\Obj\pinctrl.o + $PROJ_DIR$\Src\usb\include\linux\errno.h + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\Src\usb\dwc2_compat.h + $PROJ_DIR$\Debug\Obj\SpinandBooter.o + $PROJ_DIR$\FreeRTOS\Source\portable\portmacro.h + $PROJ_DIR$\Src\os_adapt.h + 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MemMang + + $PROJ_DIR$\FreeRTOS\Source\portable\MemMang\heap_4.c + + + + + $PROJ_DIR$\FreeRTOS\Source\list.c + + + + Src + + fs + + $PROJ_DIR$\Src\fs\diskio.c + + + $PROJ_DIR$\Src\fs\diskio.h + + + $PROJ_DIR$\Src\fs\ff.c + + + $PROJ_DIR$\Src\fs\ff.h + + + $PROJ_DIR$\Src\fs\integer.h + + + $PROJ_DIR$\Src\fs\sd_if.h + + + + usb + + $PROJ_DIR$\Src\usb\ark_dwc2.c + + + $PROJ_DIR$\Src\usb\core.c + + + $PROJ_DIR$\Src\usb\core_intr.c + + + $PROJ_DIR$\Src\usb\hcd.c + + + $PROJ_DIR$\Src\usb\hcd_intr.c + + + $PROJ_DIR$\Src\usb\hcd_queue.c + + + $PROJ_DIR$\Src\usb\params.c + + + $PROJ_DIR$\Src\usb\platform.c + + + $PROJ_DIR$\Src\usb\usb.c + + + $PROJ_DIR$\Src\usb\usb_massstorage.c + + + $PROJ_DIR$\Src\usb\usb_os_adapter.c + + + + $PROJ_DIR$\Src\aic.c + + + $PROJ_DIR$\Src\board.h + + + $PROJ_DIR$\Src\Boot.s + + + $PROJ_DIR$\Src\cp15.c + + + $PROJ_DIR$\Src\cp15_asm_iar.s + + + $PROJ_DIR$\Src\crc32.c + + + $PROJ_DIR$\Src\crc32.h + + + $PROJ_DIR$\Src\Entry.c + + + $PROJ_DIR$\Src\exception.c + + + $PROJ_DIR$\Src\gpio.c + + + $PROJ_DIR$\Src\i2c-gpio.c + + + $PROJ_DIR$\Src\i2c.c + + + $PROJ_DIR$\Src\lcd.c + + + $PROJ_DIR$\Src\list.h + + + $PROJ_DIR$\Src\mipi.c + + + $PROJ_DIR$\Src\mmu.c + + + $PROJ_DIR$\Src\os_adapt.c + + + $PROJ_DIR$\Src\pinctrl.c + + + $PROJ_DIR$\Src\pxp.c + + + $PROJ_DIR$\Src\pxp.h + + + $PROJ_DIR$\Src\sdmmc.c + + + $PROJ_DIR$\Src\sdmmc.h + + + $PROJ_DIR$\Src\spi.h + + + $PROJ_DIR$\Src\SpiBooter.c + + + $PROJ_DIR$\Src\SpinandBooter.c + + + $PROJ_DIR$\Src\sysctl.c + + + $PROJ_DIR$\Src\sysinfo.c + + + $PROJ_DIR$\Src\timer.c + + + $PROJ_DIR$\Src\timer.h + + + $PROJ_DIR$\Src\typedef.h + + + $PROJ_DIR$\Src\uart.c + + + $PROJ_DIR$\Src\update.c + + + $PROJ_DIR$\Src\wdt.c + + + + $PROJ_DIR$\Src\amt630h.h + + + $PROJ_DIR$\Src\uart.h + + diff --git a/A58-STEPLDR/stepldr.eww b/A58-STEPLDR/stepldr.eww new file mode 100644 index 00000000..a3f1f6ff --- /dev/null +++ b/A58-STEPLDR/stepldr.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\stepldr.ewp + + + + + diff --git a/A58-STEPLDR/stepldr.icf b/A58-STEPLDR/stepldr.icf new file mode 100644 index 00000000..706344d7 --- /dev/null +++ b/A58-STEPLDR/stepldr.icf @@ -0,0 +1,43 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20f00000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20f00080; +define symbol __ICFEDIT_region_ROM_end__ = 0x20f1ffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x20f20000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20feffff; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x40; +define symbol __ICFEDIT_size_irqstack__ = 0x40; +define symbol __ICFEDIT_size_fiqstack__ = 0x40; +define symbol __ICFEDIT_size_undstack__ = 0x40; +define symbol __ICFEDIT_size_abtstack__ = 0x40; +define symbol __ICFEDIT_size_heap__ = 0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; \ No newline at end of file diff --git a/MXC_A27-PCB4.5-270T/ArkmicroFiles/libcpu-amt630hv100/source/uart_and_can.c b/MXC_A27-PCB4.5-270T/ArkmicroFiles/libcpu-amt630hv100/source/uart_and_can.c index e897af36..daa2fd37 100644 --- a/MXC_A27-PCB4.5-270T/ArkmicroFiles/libcpu-amt630hv100/source/uart_and_can.c +++ b/MXC_A27-PCB4.5-270T/ArkmicroFiles/libcpu-amt630hv100/source/uart_and_can.c @@ -44,7 +44,7 @@ unsigned char uart_time_request[13] = {0}; static uint8_t uart_tx_flag = 0; static uint32_t send_idletick = 0;//发送时间检测 extern uint8_t flash_flag;//检测是否收到device信息 -uint8_t uart_state = 0;//串口状态 + uint8_t uart_state_flag = 0;//串口当前状态标识 uint8_t bt_communication_heartbeat = 10;//时间检测 uint8_t uart_flag =0;//串口变化标志 @@ -107,7 +107,7 @@ static void protocol_uart_tx_thread(void *param) if((!flash_flag) && (!data_error_flag)){ //确认蓝牙不处于升级 + 确认630不处于升级 + 确认串口收到通讯信息 - if(Get_sys_bt_upgrade() == 0 && Get_sys_upgrade_Flag() == 0 && uart_state){//蓝牙升级 不发送数据 630升级 不发送数据 + if(Get_sys_bt_upgrade() == 0 && Get_sys_upgrade_Flag() == 0){//蓝牙升级 不发送数据 630升级 不发送数据 #ifndef DATA_CAN SendDataToBT(heartbeat_data); // printf("tx>"); @@ -321,7 +321,6 @@ static void protocol_uart_rx_thread(void *param) printf("\n"); } }else{ - uart_state = 3; bt_communication_heartbeat = 3; if(equipment_data){ device_data_analysis(tlv_data_value); @@ -413,7 +412,7 @@ static void protocol_uart_rx_thread(void *param) #if 1 }else{//升级逻辑 timeout ++; - uart_state = 3; + for (i = 0; i < len; i++) { switch (uup_rx_state) { case 0: diff --git a/MXC_A27-PCB4.5-270T/FreeRTOSConfig.h b/MXC_A27-PCB4.5-270T/FreeRTOSConfig.h index 13f7a62a..1daea5ea 100644 --- a/MXC_A27-PCB4.5-270T/FreeRTOSConfig.h +++ b/MXC_A27-PCB4.5-270T/FreeRTOSConfig.h @@ -67,7 +67,7 @@ // //#define configTOTAL_HEAP_SIZE ( ( size_t ) ( (18.8+32) * 1024 * 1024) ) // google拼音出现异常 //#define configTOTAL_HEAP_SIZE ( ( size_t ) ( (8.5+32) * 1024 * 1024) ) // google拼音正常工作 -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( (3.5+30) * 1024 * 1024) ) // google拼音正常工作 +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( (2.5+28) * 1024 * 1024) ) // google拼音正常工作 #elif defined(REVERSE_TRACK) #define configTOTAL_HEAP_SIZE ( ( size_t ) ( (22+32) * 1024 * 1024) ) diff --git a/MXC_A27-PCB4.5-270T/app/main_awtk.c b/MXC_A27-PCB4.5-270T/app/main_awtk.c index 3d15ab6d..bedf9a76 100644 --- a/MXC_A27-PCB4.5-270T/app/main_awtk.c +++ b/MXC_A27-PCB4.5-270T/app/main_awtk.c @@ -92,7 +92,7 @@ int carlink_cp_init(); **********************/ #ifdef VG_DRIVER #pragma data_alignment=1024 -#define VG_HEAP_SIZE 0xc00000 +#define VG_HEAP_SIZE 0xd00000 __no_init static uint8_t vgHeap[VG_HEAP_SIZE]; #endif diff --git a/MXC_A27-PCB4.5-270T/app/moto/protocol/Bt_Interaction_protocol.c b/MXC_A27-PCB4.5-270T/app/moto/protocol/Bt_Interaction_protocol.c index 0b4bbcd1..12732dc0 100644 --- a/MXC_A27-PCB4.5-270T/app/moto/protocol/Bt_Interaction_protocol.c +++ b/MXC_A27-PCB4.5-270T/app/moto/protocol/Bt_Interaction_protocol.c @@ -18,13 +18,14 @@ // #define MAX_ENTRIES 500 // 假设最大条目数为500 #define MAX_ENTRIES 3000 // 假设最大条目数为500 uint8_t time_flag = 0; +uint8_t wifi_time_flag = 0; -char bt121_name[50]; -char bt121_name1[50]; +char bt121_name[CALL_NAME_MAX]; +char bt121_name1[CALL_NAME_MAX]; // 定义电话本条目结构体 typedef struct { - char name[50]; - char phone[20]; + char name[CALL_NAME_MAX]; + char phone[PHONE_MAX]; } PhoneBookEntry; PhoneBookEntry phoneBook[MAX_ENTRIES]; // 存储电话本信息的数组 @@ -47,6 +48,26 @@ char* findNameByPhoneNumber(const char* phoneNumber) { if (strcmp(phoneBook[i].phone, phoneNumber) == 0) { printf("find> i=%d,name=%s.\r\n",i,phoneBook[i].name); return phoneBook[i].name; + } + + // 检查phoneBook中的号码是否有+86前缀，如果有则去掉后比较 + if (strlen(phoneBook[i].phone) > 3 && + strncmp(phoneBook[i].phone, "+86", 3) == 0) { + const char* phoneWithoutPrefix = phoneBook[i].phone + 3; + if (strcmp(phoneWithoutPrefix, phoneNumber) == 0) { + printf("find> i=%d,name=%s.\r\n",i,phoneBook[i].name); + return phoneBook[i].name; + } + } + + // 检查输入的号码是否有+86前缀，如果有则去掉后比较 + if (strlen(phoneNumber) > 3 && + strncmp(phoneNumber, "+86", 3) == 0) { + const char* inputWithoutPrefix = phoneNumber + 3; + if (strcmp(phoneBook[i].phone, inputWithoutPrefix) == 0) { + printf("find> i=%d,name=%s.\r\n",i,phoneBook[i].name); + return phoneBook[i].name; + } } } printf("unfind .\r\n"); @@ -67,12 +88,10 @@ void BW_121_Switch(uint8_t type){ switch(type){ case 0: - printf("send close bt.\r\n"); console_send_atcmd("AT+BTEN=0\r\n", strlen("AT+BTEN=0\r\n"));//关蓝牙 bt121_state = 1; break; case 1: - printf("send open bt.\r\n"); console_send_atcmd("AT+BTEN=1\r\n", strlen("AT+BTEN=1\r\n"));//开蓝牙 bt121_state = 2; break; @@ -245,12 +264,13 @@ void bw121call_number_data_event_handler(char* cAtCmd){ static uint8_t flag = 0; void parseBtATCommand(char* cAtCmd,int cATLen) { - // printf("###"); + // printf("BW121>"); // for(uint16_t i =0;i= 2 && !memcmp(cAtCmd,"OK",2))//蓝牙连接设备信息 远端设备信息 蓝牙连接 + if(strlen(cAtCmd) > 2 && !memcmp(cAtCmd,"OK",2))//蓝牙连接设备信息 远端设备信息 蓝牙连接 { switch(bt121_state){ case 1: @@ -262,26 +282,42 @@ void parseBtATCommand(char* cAtCmd,int cATLen) { default:break; } - }else if(strlen(cAtCmd) > 8 && !memcmp(cAtCmd,"+A2DPDEV",8))//蓝牙连接设备信息 远端设备信息 蓝牙连接 - { + }else if(strlen(cAtCmd) > 7 && !memcmp(cAtCmd,"+HFPDEV",7)){//设备状态 Set_sys_bt_connect_state(1); - vTaskDelay(500); - //查询电话本信息 - printf("select phonebook.\r\n"); - console_send_atcmd("AT+PBDOWN=1\r\n", strlen("AT+PBDOWN=1\r\n")); + //获取时间 当前只有苹果小米可用 + console_send_atcmd("AT+HFPTIME\r\n", strlen("AT+HFPTIME\r\n")); + // bt_connect_flag = 1; + // vTaskDelay(500); + // if(!broadcastStatus){ + // //查询电话本信息 + // printf("select phonebook.\r\n"); + // console_send_atcmd("AT+PBDOWN=1\r\n", strlen("AT+PBDOWN=1\r\n")); + // } + // }else if(strlen(cAtCmd) > 8 && !memcmp(cAtCmd,"+A2DPDEV",8))//蓝牙连接设备信息 远端设备信息 蓝牙连接 //屏蔽音频后无效 + // { + // Set_sys_bt_connect_state(1); + // vTaskDelay(500); + // //查询电话本信息 + // printf("select phonebook.\r\n"); + // console_send_atcmd("AT+PBDOWN=1\r\n", strlen("AT+PBDOWN=1\r\n")); }else if(strlen(cAtCmd) > 8 && !memcmp(cAtCmd,"+DEVSTAT",8)){//设备状态 uint32_t num = 0; - num = cAtCmd[9] - '0';//状态 0 off 1 on - printf("bt>state = %d",num); - switch(num){ - case 0: - Set_sys_bt_on_off(0); - break; - case 1: - Set_sys_bt_on_off(1); - break; - } - printf(".ok\r\n"); + // 提取数值部分 + char *valueStr = strchr(cAtCmd, '='); // 查找 '=' 字符 + if (valueStr != NULL) { + valueStr++; // 移动到 '=' 后面的字符 + num = (uint32_t)atoi(valueStr); // 将字符串转换为整数 + } + // 判断蓝牙开关状态和广播状态 + uint8_t bluetoothStatus = (num & 0x01); // bit0 + uint8_t broadcastStatus = (num & 0x02) >> 1; // bit1 //1为可发现 0为不可发现 + + Set_sys_bt_on_off(bluetoothStatus); + // printf("broadcastStatus = %d,",broadcastStatus); + if(!broadcastStatus) Set_sys_bt_connect_state(0); + // Set_sys_bt_connect_state(broadcastStatus?0:1); + // printf("bt_state=%d,",Get_sys_bt_connect_state()); + }else if(strlen(cAtCmd) > 8 && !memcmp(cAtCmd,"+HFPSTAT",8)){//来电 或 蓝牙断开 if(strlen(cAtCmd) == 10){ @@ -307,6 +343,15 @@ void parseBtATCommand(char* cAtCmd,int cATLen) { Set_sys_bt_connect_state(0); }else if(strlen(cAtCmd) > 5 && !memcmp(cAtCmd,"+NAME",5)){//远距离断开 设备丢失 sscanf(cAtCmd, "+NAME=%s", bt121_name1); + + // 获取字符串长度 + size_t len = strlen(bt121_name1); + + // 判断字符串长度是否大于等于2，并检查最后两位是否为 "01" + if (len >= 2 && bt121_name1[len - 2] == '0' && bt121_name1[len - 1] == '1') { + // 修改字符串，删除最后两位 + bt121_name1[len - 2] = '\0'; // 将倒数第二个字符设置为字符串结束符 + } }else if(strlen(cAtCmd) > 7 && !memcmp(cAtCmd,"+LEADDR",7)){//远距离断开 设备丢失 char last_four[5]; strncpy(last_four, cAtCmd + strlen(cAtCmd) - 4, 4); @@ -335,6 +380,7 @@ void parseBtATCommand(char* cAtCmd,int cATLen) { check_buffer[4] = minute; check_buffer[5] = second; send_wifi_set_time(check_buffer); + wifi_time_flag = 1; #endif printf(">>bt time %s.\r\n",cAtCmd); }else if(strlen(cAtCmd) > 7 && !memcmp(cAtCmd,"+PBSTAT",7)){//下载状态 @@ -353,8 +399,8 @@ void parseBtATCommand(char* cAtCmd,int cATLen) { return; // 解析字符串并提取姓名和电话号码 uint8_t count = 0; - char call_num[20]; - char call_name[50]; + char call_num[PHONE_MAX]; + char call_name[CALL_NAME_MAX]; memset(call_name, 0, sizeof(call_name)); memset(call_num, 0, sizeof(call_num)); uint16_t y = 0; @@ -373,7 +419,7 @@ void parseBtATCommand(char* cAtCmd,int cATLen) { y++; } - // printf("ID:%d,name:%s,call:%s.\r\n",numEntries,call_name,call_num); + // printf("ID:%d,name:<%s>,call:<%s>\r\n",numEntries,call_name,call_num); if(strlen(call_name) && strlen(call_num)){ strcpy(phoneBook[numEntries].name, call_name); strcpy(phoneBook[numEntries].phone, call_num); @@ -381,5 +427,7 @@ void parseBtATCommand(char* cAtCmd,int cATLen) { } + }else if(strlen(cAtCmd) > 10 && !memcmp(cAtCmd,"+HFPAUDIO=1",10)){//AVRCP状态 1是配对状态 蓝牙断开 + console_send_atcmd("AT+HFPADTS=1\r\n", strlen("AT+HFPADTS=1\r\n"));//查询profile使能 } } diff --git a/MXC_A27-PCB4.5-270T/app/moto/protocol/tire_pressure_protocol.c b/MXC_A27-PCB4.5-270T/app/moto/protocol/tire_pressure_protocol.c index 113796cf..0630a466 100644 --- a/MXC_A27-PCB4.5-270T/app/moto/protocol/tire_pressure_protocol.c +++ b/MXC_A27-PCB4.5-270T/app/moto/protocol/tire_pressure_protocol.c @@ -6,30 +6,19 @@ #include "universal.h" -extern void SaveDataToFlash(SfudData_t user_data); +// extern void SaveDataToFlash(SfudData_t user_data); uint8_t power_on_flag = 0; uint32_t tire_pressure_flag = 0; uint32_t tire_front_time = 0; uint32_t tire_rear_time = 0; +extern uint8_t tire_power; +static date_time_t dt; +extern uint8_t save_flag; -//保存里程信息 -static void Save_tire_data(void){ +void tire_data_synchronous(void){ Pressure_t ago_pressure = Get_sys_front_pressure(); Pressure_t after_pressure = Get_sys_rear_pressure(); - DEBUG_PRINT("****************\r\n"); - DEBUG_PRINT("mac: %02X%02X%02X%02X%02X%02X , %02X%02X%02X%02X%02X%02X \r\n", - ago_pressure.mac_address[0],ago_pressure.mac_address[1],ago_pressure.mac_address[2], - ago_pressure.mac_address[3],ago_pressure.mac_address[4],ago_pressure.mac_address[5], - after_pressure.mac_address[0],after_pressure.mac_address[1],after_pressure.mac_address[2], - after_pressure.mac_address[3],after_pressure.mac_address[4],after_pressure.mac_address[5]); - DEBUG_PRINT("****************\r\n"); - DEBUG_PRINT("mac: %02X%02X%02X%02X%02X%02X , %02X%02X%02X%02X%02X%02X \r\n", - custom_data.user_data.f_mac_address[0],custom_data.user_data.f_mac_address[1],custom_data.user_data.f_mac_address[2], - custom_data.user_data.f_mac_address[3],custom_data.user_data.f_mac_address[4],custom_data.user_data.f_mac_address[5], - custom_data.user_data.r_mac_address[0],custom_data.user_data.r_mac_address[1],custom_data.user_data.r_mac_address[2], - custom_data.user_data.r_mac_address[3],custom_data.user_data.r_mac_address[4],custom_data.user_data.r_mac_address[5]); - DEBUG_PRINT("****************\r\n"); strcpy(custom_data.user_data.f_mac_address,ago_pressure.mac_address); custom_data.user_data.f_mac_address[6]=ago_pressure.temp&0xFF; custom_data.user_data.f_mac_address[7]=ago_pressure.psi>>8&0xFF; @@ -38,13 +27,26 @@ static void Save_tire_data(void){ custom_data.user_data.r_mac_address[6]=after_pressure.temp&0xFF; custom_data.user_data.r_mac_address[7]=after_pressure.psi>>8&0xFF; custom_data.user_data.r_mac_address[8]=after_pressure.psi&0xFF; +} + +//保存里程信息 +void Save_tire_data(void){ + tire_data_synchronous(); Set_sys_pressure_signal(0); - //保存flash - SaveDataToFlash(custom_data.user_data);//保存数据 + save_flag = 1; + // //保存flash + // SaveDataToFlash(custom_data.user_data);//保存数据 } //数据刷新函数 void pressure_buffer_event_handing(Pressure_t pressure,char buffer[],uint8_t type,uint8_t pairing_status){ + + // printf("enter data>"); + // for(uint8_t i=0;i<11;i++){ + // printf("%02x ",buffer[i]); + // } + // printf("\r\n"); + uint8_t len = strlen(buffer); // uint8_t buffer_state=0; // uint8_t buffer_check=0; @@ -68,7 +70,7 @@ void pressure_buffer_event_handing(Pressure_t pressure,char buffer[],uint8_t typ //DEBUG_PRINT("%x, ",data); pressure.blow_by_state = JUDGE_BIN_1(data); pressure.voltage_state = JUDGE_BIN_2(data); - //pressure.temp_state = JUDGE_BIN_3(data); + pressure.temp_state = JUDGE_BIN_3(data); //V data = *(sign++);//电压 0x1e=>30=>3.0V @@ -76,11 +78,15 @@ void pressure_buffer_event_handing(Pressure_t pressure,char buffer[],uint8_t typ //DEBUG_PRINT("%x, ",data); //T data = *(sign++);//温度 0x14=>20=>20°C - pressure.temp = data; - if(data>=70 && data<128){ - pressure.temp_state = 1; - }else - pressure.temp_state = 0; + pressure.temp = data; + // if(pressure.temp<=127){ + // if(pressure.temp>=70) + // pressure.temp_state = 1; + // else + // pressure.temp_state = 0; + // }else + // pressure.temp_state = 0; + //DEBUG_PRINT("%x, ",data); //P sum = 0; @@ -99,7 +105,7 @@ void pressure_buffer_event_handing(Pressure_t pressure,char buffer[],uint8_t typ date_time_t dt; date_time_init(&dt); - uint16_t check_buffer[6]; + uint32_t check_buffer[6]; check_buffer[0] = dt.year; check_buffer[1] = dt.month; check_buffer[2] = dt.day; @@ -115,21 +121,17 @@ void pressure_buffer_event_handing(Pressure_t pressure,char buffer[],uint8_t typ pressure.blow_by_state,pressure.voltage_state,pressure.temp_state,pressure.temp,pressure.psi); switch(type){ case 1: - if((sum - tire_front_time)>3600){ - pressure.lose_flag = 1; - } Set_sys_front_pressure(pressure); break; case 2: - if((sum - tire_rear_time)>3600){ - pressure.lose_flag = 1; - } Set_sys_rear_pressure(pressure); break; default:break; } + if(pairing_status){//若配对模式 + Save_tire_data(); Send_tire_pressure_information(); Set_sys_tire_pressure_mesg(10); } @@ -158,48 +160,51 @@ void tire_pressure_data_analysis(uint8_t *buf){ Pressure_t ago_pressure = Get_sys_front_pressure(); Pressure_t after_pressure = Get_sys_rear_pressure(); - data = *(buf++); - if(data!=0xAA) - return; + (buf++); + (buf++); + (buf++); + (buf++); + (buf++); - data = *(buf++); - if(data!=0x1b) - return; + // data = *(buf++); + // if(data!=0xAA) + // return; - data = *(buf++); - if(data!=0x03) - return; + // data = *(buf++); + // if(data!=0x1b) + // return; - data = *(buf++); - if(data!=0x51) - return; + // data = *(buf++); + // if(data!=0x03) + // return; - data = *(buf++); - if(data!=0x17) - return; + // data = *(buf++); + // if(data!=0x51) + // return; + + // data = *(buf++); + // if(data!=0x17) + // return; data_flag = *(buf++); - if(!data_flag && !power_on_flag){ - return; - }else{ - date_time_t dt; - date_time_init(&dt); - uint16_t check_buffer[6]; - check_buffer[0] = dt.year; - check_buffer[1] = dt.month; - check_buffer[2] = dt.day; - check_buffer[3] = dt.hour; - check_buffer[4] = dt.minute; - check_buffer[5] = dt.second; - uint32_t sum = fml_time_to_stamp(check_buffer); - switch(data_flag){ - case 1:tire_front_time =sum;break; - case 2:tire_rear_time =sum;break; - case 3:tire_front_time =sum;tire_rear_time =sum;break; - default:break; - } + + date_time_init(&dt); + uint32_t check_buffer[6]; + check_buffer[0] = dt.year; + check_buffer[1] = dt.month; + check_buffer[2] = dt.day; + check_buffer[3] = dt.hour; + check_buffer[4] = dt.minute; + check_buffer[5] = dt.second; + uint32_t sum = fml_time_to_stamp(check_buffer); + switch(data_flag){ + case 1:tire_front_time =sum; break; + case 2:tire_rear_time =sum; break; + case 3:tire_front_time =sum;tire_rear_time =sum; break; + default:break; } + for(uint8_t i=0;i<11;i++){ trip_buffer1[i] = *(buf++); if(i<6) @@ -211,6 +216,7 @@ void tire_pressure_data_analysis(uint8_t *buf){ if(i<6) mac2[i]=trip_buffer2[i]; } + //tk_snDEBUG_PRINT(mac1, sizeof(mac1), "%02X%02X%02X%02X%02X%02X",trip_buffer1[0],trip_buffer1[1],trip_buffer1[2],trip_buffer1[3],trip_buffer1[4],trip_buffer1[5]); //tk_snDEBUG_PRINT(mac2, sizeof(mac2), "%02X%02X%02X%02X%02X%02X",trip_buffer2[0],trip_buffer2[1],trip_buffer2[2],trip_buffer2[3],trip_buffer2[4],trip_buffer2[5]); @@ -223,12 +229,28 @@ void tire_pressure_data_analysis(uint8_t *buf){ } DEBUG_PRINT("\r\n"); DEBUG_PRINT("***************************\r\n"); - + if(tire_power){ + tire_power = 0; + if(!Get_sys_pressure_signal()) + data_flag = 3; + // printf("data_flag = %d\r\n",data_flag); + }else if(!data_flag && !Get_sys_pressure_signal()){ + //判断本地是否有mac地址 + if(mac_address_normal(ago_pressure.mac_address, 6) != 0 && (compare_arrays(ago_pressure.mac_address,mac1,6)==0)){ + Send_tire_pressure_information(); + }else if(mac_address_normal(after_pressure.mac_address, 6) != 0 && (compare_arrays(after_pressure.mac_address,mac2,6)==0)){ + Send_tire_pressure_information(); + } + + return; + } + switch(Get_sys_pressure_signal()){ case 0://正常情况下需要刷新数据 - DEBUG_PRINT("0>>>> data_flag = %d \n",data_flag); + uint8_t tire_error = 0; + // DEBUG_PRINT("0>>>> data_flag = %d \n",data_flag); //if(strcmp(ago_pressure.mac_address,mac1)==0){//若和前胎压地址相同，则将数据丢给前胎压 - if(compare_arrays(ago_pressure.mac_address,mac1,6)==1 && (data_flag == 1 || data_flag == 3) || power_on_flag){//若和前胎压地址相同，则将数据丢给前胎压 + if(compare_arrays(ago_pressure.mac_address,mac1,6)==1 && ((data_flag == 1 || data_flag == 3) || power_on_flag)){//若和前胎压地址相同，则将数据丢给前胎压 pressure_buffer_event_handing(ago_pressure,trip_buffer1,1,0); strcpy(custom_data.user_data.f_mac_address,ago_pressure.mac_address); custom_data.user_data.f_mac_address[6]=ago_pressure.temp&0xFF; @@ -243,6 +265,15 @@ void tire_pressure_data_analysis(uint8_t *buf){ custom_data.user_data.r_mac_address[7]=after_pressure.psi>>8&0xFF; custom_data.user_data.r_mac_address[8]=after_pressure.psi&0xFF; } + + // if((compare_arrays(ago_pressure.mac_address,mac1,6)==0) || (compare_arrays(after_pressure.mac_address,mac2,6)==0))//若不同 + // Send_tire_pressure_information(); + if(mac_address_normal(ago_pressure.mac_address, 6) != 0 && (compare_arrays(ago_pressure.mac_address,mac1,6)==0)){ + Send_tire_pressure_information(); + }else if(mac_address_normal(after_pressure.mac_address, 6) != 0 && (compare_arrays(after_pressure.mac_address,mac2,6)==0)){ + Send_tire_pressure_information(); + } + if(power_on_flag){ DEBUG_PRINT("power_on_flag = %d, tire_pressure ,ago_pressure.psi = %d , after_pressure.psi =%d .\r\n",power_on_flag,ago_pressure.psi,after_pressure.psi); power_on_flag--; @@ -250,13 +281,13 @@ void tire_pressure_data_analysis(uint8_t *buf){ break; case 1://学习前胎压 前胎压不能于后胎压相同 前胎压mac清零 - DEBUG_PRINT("1>>>> data_flag = %d \n",data_flag); + // DEBUG_PRINT("1>>>> data_flag = %d \n",data_flag); if(data_flag==1){//只做mac1的判断 DEBUG_PRINT("mac1-------------------.\r\n"); //判断mac是否正常 if(mac_address_normal(mac1,6) == 1){//正常进 - DEBUG_PRINT("mac1 ok-------------------.\r\n"); + // DEBUG_PRINT("mac1 ok-------------------.\r\n"); //判断是否等于后胎压mac地址 if(compare_arrays(after_pressure.mac_address,mac1,6)==1){//若等于，那么刷新后胎压 pressure_buffer_event_handing(after_pressure,trip_buffer1,2,0); @@ -280,7 +311,7 @@ void tire_pressure_data_analysis(uint8_t *buf){ } }else if(data_flag==2){//只做mac2的判断 - DEBUG_PRINT("mac2 -------------------.\r\n"); + // DEBUG_PRINT("mac2 -------------------.\r\n"); //判断mac是否正常 if(mac_address_normal(mac2,6) == 1){//正常进 DEBUG_PRINT("mac2 ok-------------------.\r\n"); @@ -304,20 +335,20 @@ void tire_pressure_data_analysis(uint8_t *buf){ } } - }else{ + }else if(data_flag==3){ //先判断mac1是否正常 再判断mac2 if(mac_address_normal(mac1,6) == 1){//正常进 - DEBUG_PRINT("mac1 -------------------.\r\n"); + // DEBUG_PRINT("mac1 -------------------.\r\n"); //判断是否等于后胎压mac地址 if(compare_arrays(after_pressure.mac_address,mac1,6)==1){//若等于，那么刷新后胎压 - DEBUG_PRINT("mac1 after -------------------.\r\n"); + // DEBUG_PRINT("mac1 after -------------------.\r\n"); pressure_buffer_event_handing(after_pressure,trip_buffer1,2,0); //后胎压刷新完毕 //1.判断mac2 1.是否正常 是转2 否退出 //2.是否等于后胎压 是则刷后胎压 否转3 //3.学习前胎压 if(mac_address_normal(mac2,6) == 1){//判断mac2是否正常 - DEBUG_PRINT("mac2 -------------------.\r\n"); + // DEBUG_PRINT("mac2 -------------------.\r\n"); if(compare_arrays(after_pressure.mac_address,mac2,6)==1){//若等于，那么刷新后胎压 pressure_buffer_event_handing(after_pressure,trip_buffer2,2,0); }else{//反之学习前胎压 @@ -338,11 +369,11 @@ void tire_pressure_data_analysis(uint8_t *buf){ } }else{ - DEBUG_PRINT("mac2 error-------------------.\r\n"); + // DEBUG_PRINT("mac2 error-------------------.\r\n"); } }else{//若不等于 那么就学习前胎压 - DEBUG_PRINT("mac2 ago-------------------.\r\n"); + // DEBUG_PRINT("mac2 ago-------------------.\r\n"); //S data = trip_buffer1[6]; @@ -398,13 +429,13 @@ void tire_pressure_data_analysis(uint8_t *buf){ break; case 2://学习后胎压 - DEBUG_PRINT("2>>>> data_flag =%d\n",data_flag); + // DEBUG_PRINT("2>>>> data_flag =%d\n",data_flag); if(data_flag==1){//只做mac1的判断 DEBUG_PRINT("mac1-------------------.\r\n"); //判断mac是否正常 if(mac_address_normal(mac1,6) == 1){//正常进 - DEBUG_PRINT("mac1 ok-------------------.\r\n"); + // DEBUG_PRINT("mac1 ok-------------------.\r\n"); //判断是否等于前胎压mac地址 if(compare_arrays(ago_pressure.mac_address,mac1,6)==1){//若等于，那么刷新前胎压 pressure_buffer_event_handing(ago_pressure,trip_buffer1,1,0); @@ -430,7 +461,7 @@ void tire_pressure_data_analysis(uint8_t *buf){ DEBUG_PRINT("mac2 -------------------.\r\n"); //判断mac是否正常 if(mac_address_normal(mac2,6) == 1){//正常进 - DEBUG_PRINT("mac2 ok-------------------.\r\n"); + // DEBUG_PRINT("mac2 ok-------------------.\r\n"); //判断是否等于前胎压mac地址 if(compare_arrays(ago_pressure.mac_address,mac2,6)==1){//若等于，那么刷新前胎压 pressure_buffer_event_handing(ago_pressure,trip_buffer2,1,0); @@ -450,7 +481,7 @@ void tire_pressure_data_analysis(uint8_t *buf){ } } - }else{ + }else if(data_flag==3){ //先判断mac1是否正常 再判断mac2 if(mac_address_normal(mac1,6) == 1){//正常进 DEBUG_PRINT("mac1 -------------------.\r\n"); diff --git a/MXC_A27-PCB4.5-270T/app/moto/protocol/user_protocol.c b/MXC_A27-PCB4.5-270T/app/moto/protocol/user_protocol.c index a522eb0b..ddd80667 100644 --- a/MXC_A27-PCB4.5-270T/app/moto/protocol/user_protocol.c +++ b/MXC_A27-PCB4.5-270T/app/moto/protocol/user_protocol.c @@ -14,6 +14,7 @@ extern double total_mile; uint8_t data_error_flag = 0; +extern uint8_t wifi_time_flag; #define KEY_DATA_PRESS 0x01 // 短按 #define KEY_DATA_LONG_PRESS 0x02 // 长按 @@ -25,6 +26,8 @@ enum }; uint8_t save_data = 0; +uint8_t tire_power = 0; +uint8_t bt_reset_flag = 0; #define ADC_VPLTAGE_MIN 1666 #define ADC_VPLTAGE_MAX 2486 @@ -74,7 +77,7 @@ double adc_voltage_calculation(void){ //MOTO通讯 设备信息+时间戳解析协议 void device_data_analysis(uint8_t *buf){ - printf("device information............................................\r\n"); + // printf("device information............................................\r\n"); uint8_t data; uint8_t sum1,sum2,sum3,sum4; uint32_t save_total_mile,save_trip_mile; @@ -168,23 +171,26 @@ void device_data_analysis(uint8_t *buf){ data = *(buf++);//0x04 //DEBUG_PRINT("0x04 -- %02x .\n",data); //DEBUG_PRINT("time stamp >> "); - uint16_t time_transfer[6]; + if(!wifi_time_flag){ + uint16_t time_transfer[6]; - sum1 = *(buf++); - sum2 = *(buf++); - sum3 = *(buf++); - sum4 = *(buf++); + sum1 = *(buf++); + sum2 = *(buf++); + sum3 = *(buf++); + sum4 = *(buf++); - //sum = sum1 | sum2<<8 | sum3<<16 | sum4<<24; - sum = sum1<<24 | sum2<<16 | sum3<<8 | sum4; - DEBUG_PRINT("time > %08x \n",sum); - tire_rear_time = sum; - tire_front_time = sum; - // if(sum<1706198400) - // sum = 1706198400; - fml_stamp_to_time(sum,time_transfer); + //sum = sum1 | sum2<<8 | sum3<<16 | sum4<<24; + sum = sum1<<24 | sum2<<16 | sum3<<8 | sum4; + printf("bt time > %08x \n",sum); + tire_rear_time = sum; + tire_front_time = sum; + // if(sum<1706198400) + // sum = 1706198400; + fml_stamp_to_time(sum,time_transfer); - Uart_set_time(time_transfer);//去设置时间并不再发送询问时间指令 + Uart_set_time(time_transfer);//去设置时间并不再发送询问时间指令 + }else + wifi_time_flag--; //Set_sys_ttrb_time(10); data = *(buf++);//0x05 @@ -491,6 +497,11 @@ void data_analysis(uint8_t *buf){ if(JUDGE_BIN_4(data)){//收到胎压信息，不再发送 DEBUG_PRINT("Received tire pressure command, no longer sending.\n"); Set_sys_tire_pressure_mesg(10); + tire_power = 1; + } + if(JUDGE_BIN_5(data) && JUDGE_BIN_6(data)){ + DEBUG_PRINT("bt reset.\n"); + bt_reset_flag = 2; } #ifdef DATA_CAN switch(result){ diff --git a/MXC_A27-PCB4.5-270T/lib/awtk/awtk-examples/MOTO_A270T/design/default/strings/en_US.bin b/MXC_A27-PCB4.5-270T/lib/awtk/awtk-examples/MOTO_A270T/design/default/strings/en_US.bin index 3ab51e388bcb1b9146182d57ad06002a4dfb6869..48186a4a23dcf040117a3502b376e7d3c2679121 100644 GIT binary patch delta 632 zcmWO1Pe_vi7{~FSTcvJuZli->%3y*fItU_2QBaH$#Xpq9ZoRUxL~?KMJ20`Df;iAi zR1n@gRGvg|lA&EHL9mm0Db0&GmyjL?hEj*VhtH4ad3Y|r<6iTD`fjdRg4%&*PZTv(QCpbl!OS*+l^df=>cmx|`n06_p8HRUQ z#3yVa4~JXwq6}AX6-{WvZFJ!t48$>v3B187zF-~S@f-h8M+o&E`ZqGPqX&I> zfj=lL;SmoV2PE1K-4q6myC!8cHp_bHA9AuXr)WXFM4ojkygAyro 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