A27系列优化I2C/RTC处理，新增版本A270Y
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A27-STEPLDR/Src/usb/core.c
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296
A27-STEPLDR/Src/usb/core.c
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/*
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* core.c - DesignWare HS OTG Controller common routines
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The Core code provides basic services for accessing and managing the
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* DWC_otg hardware. These services are used by both the Host Controller
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* Driver and the Peripheral Controller Driver.
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*/
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#include "usb_os_adapter.h"
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#include "trace.h"
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#include <asm/dma-mapping.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include "core.h"
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#include "hcd.h"
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/**
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* dwc2_wait_for_mode() - Waits for the controller mode.
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* @hsotg: Programming view of the DWC_otg controller.
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* @host_mode: If true, waits for host mode, otherwise device mode.
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*/
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static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
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bool host_mode)
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{
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uint32_t tick = get_timer(0);
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unsigned int timeout = 110;//ms
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dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
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host_mode ? "host" : "device");
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while (1) {
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__s64 ms;
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if (dwc2_is_host_mode(hsotg) == host_mode) {
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dev_vdbg(hsotg->dev, "%s mode set\n",
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host_mode ? "Host" : "Device");
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break;
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}
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ms = get_timer(tick);
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if (ms >= (__s64)timeout) {
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dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
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__func__, host_mode ? "host" : "device");
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break;
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}
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//vTaskDelay(2000 / portTICK_RATE_MS);
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mdelay(10);
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}
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}
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/*
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*/
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int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
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{
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u32 greset;
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int count = 0;
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bool wait_for_host_mode = false;
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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/*
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* If the current mode is host, either due to the force mode
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* bit being set (which persists after core reset) or the
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* connector id pin, a core soft reset will temporarily reset
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* the mode to device. A delay from the IDDIG debounce filter
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* will occur before going back to host mode.
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*
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* Determine whether we will go back into host mode after a
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* reset and account for this delay after the reset.
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*/
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/* Core Soft Reset */
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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greset |= GRSTCTL_CSFTRST;
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dwc2_writel(greset, hsotg->regs + GRSTCTL);
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do {
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udelay(1);
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 50) {
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dev_warn(hsotg->dev,
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"%s() HANG! Soft Reset GRSTCTL=%0x\n",
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__func__, greset);
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return -EBUSY;
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}
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} while (greset & GRSTCTL_CSFTRST);
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/* Wait for AHB master IDLE state */
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count = 0;
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do {
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udelay(1);
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 50) {
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dev_warn(hsotg->dev,
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"%s() HANG! AHB Idle GRSTCTL=%0x\n",
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__func__, greset);
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return -EBUSY;
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}
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} while (!(greset & GRSTCTL_AHBIDLE));
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if (wait_for_host_mode && !skip_wait)
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dwc2_wait_for_mode(hsotg, true);
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return 0;
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}
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/*
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* Sets or clears force mode based on the dr_mode parameter.
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*/
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void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
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{
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switch (hsotg->dr_mode) {
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case USB_DR_MODE_HOST:
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/*
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* NOTE: This is required for some rockchip soc based
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* platforms on their host-only dwc2.
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*/
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msleep(50);
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break;
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default:
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dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
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__func__, hsotg->dr_mode);
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break;
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}
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}
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/*
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*
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* Additionally this will apply force mode as per the hsotg->dr_mode
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* parameter.
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*/
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int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
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{
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int retval;
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retval = dwc2_core_reset(hsotg, false);
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if (retval)
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return retval;
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dwc2_force_dr_mode(hsotg);
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return 0;
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}
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/**
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* dwc2_flush_tx_fifo() - Flushes a Tx FIFO
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*
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* @hsotg: Programming view of DWC_otg controller
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* @num: Tx FIFO to flush
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*/
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void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
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{
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u32 greset;
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int count = 0;
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dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
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greset = GRSTCTL_TXFFLSH;
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greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
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dwc2_writel(greset, hsotg->regs + GRSTCTL);
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do {
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 10000) {
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dev_warn(hsotg->dev,
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"%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
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__func__, greset,
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dwc2_readl(hsotg->regs + GNPTXSTS));
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break;
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}
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udelay(1);
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} while (greset & GRSTCTL_TXFFLSH);
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/* Wait for at least 3 PHY Clocks */
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udelay(1);
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}
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/**
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* dwc2_flush_rx_fifo() - Flushes the Rx FIFO
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*
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* @hsotg: Programming view of DWC_otg controller
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*/
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void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
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{
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u32 greset;
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int count = 0;
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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greset = GRSTCTL_RXFFLSH;
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dwc2_writel(greset, hsotg->regs + GRSTCTL);
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do {
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greset = dwc2_readl(hsotg->regs + GRSTCTL);
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if (++count > 10000) {
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dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
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__func__, greset);
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break;
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}
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udelay(1);
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} while (greset & GRSTCTL_RXFFLSH);
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/* Wait for at least 3 PHY Clocks */
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udelay(1);
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}
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bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
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{
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if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
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return false;
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else
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return true;
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}
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/**
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* dwc2_enable_global_interrupts() - Enables the controller's Global
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* Interrupt in the AHB Config register
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*
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* @hsotg: Programming view of DWC_otg controller
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*/
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void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
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{
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u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
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ahbcfg |= GAHBCFG_GLBL_INTR_EN;
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dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
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}
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/**
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* dwc2_disable_global_interrupts() - Disables the controller's Global
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* Interrupt in the AHB Config register
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*
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* @hsotg: Programming view of DWC_otg controller
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*/
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void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
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{
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u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
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ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
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dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
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}
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/* Returns the controller's GHWCFG2.OTG_MODE. */
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unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
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{
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u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
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return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
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GHWCFG2_OP_MODE_SHIFT;
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}
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/* Returns true if the controller is host-only. */
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bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
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{
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unsigned int op_mode = dwc2_op_mode(hsotg);
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return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
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(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
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}
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