A27系列优化I2C/RTC处理，新增版本A270Y
This commit is contained in:
429
A27-STEPLDR/Src/usb/hcd_queue.c
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429
A27-STEPLDR/Src/usb/hcd_queue.c
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/*
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* hcd_queue.c - DesignWare HS OTG Controller host queuing routines
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file contains the functions to manage Queue Heads and Queue
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* Transfer Descriptors for Host mode
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*/
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#include "usb_os_adapter.h"
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#include "trace.h"
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#include <asm/dma-mapping.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include "core.h"
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#include "hcd.h"
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/* Wait this long before releasing periodic reservation */
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#define DWC2_UNRESERVE_DELAY (5)
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#define swap(a, b) do {unsigned long tmp = (a); (a) = (b); (b) = tmp;} while(0)
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unsigned long gcd(unsigned long a, unsigned long b)
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{
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unsigned long r = a | b;
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if (!a || !b)
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return r;
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/* Isolate lsbit of r */
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r &= -r;
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while (!(b & r))
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b >>= 1;
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if (b == r)
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return r;
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for (;;) {
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while (!(a & r))
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a >>= 1;
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if (a == r)
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return r;
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if (a == b)
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return a;
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if (a < b)
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swap(a, b);
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a -= b;
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a >>= 1;
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if (a & r)
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a += b;
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a >>= 1;
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}
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}
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/**
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* dwc2_do_unreserve() - Actually release the periodic reservation
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*
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* This function actually releases the periodic bandwidth that was reserved
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* by the given qh.
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @qh: QH for the periodic transfer.
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*/
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static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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assert_spin_locked(&hsotg->lock);
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WARN_ON(!qh->unreserve_pending);
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/* No more unreserve pending--we're doing it */
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qh->unreserve_pending = false;
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if (!list_item_empty(&qh->qh_list_entry)) {
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WARN_ON(!list_item_empty(&qh->qh_list_entry));
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list_del_init(&qh->qh_list_entry);
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}
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}
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/**
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* dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
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*
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* According to the kernel doc for usb_submit_urb() (specifically the part about
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* "Reserved Bandwidth Transfers"), we need to keep a reservation active as
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* long as a device driver keeps submitting. Since we're using HCD_BH to give
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* back the URB we need to give the driver a little bit of time before we
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* release the reservation. This worker is called after the appropriate
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* delay.
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*
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* @work: Pointer to a qh unreserve_work.
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*/
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/* static void dwc2_unreserve_timer_fn(unsigned long data)
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{
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} */
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/**
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* dwc2_qh_init() - Initializes a QH structure
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @qh: The QH to init
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* @urb: Holds the information about the device/endpoint needed to initialize
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* the QH
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* @mem_flags: Flags for allocating memory.
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*/
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static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
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struct dwc2_hcd_urb *urb, gfp_t mem_flags)
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{
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int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
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u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
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bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
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u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
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u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
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bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
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dev_speed != USB_SPEED_HIGH);
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int maxp = dwc2_hcd_get_mps(&urb->pipe_info);
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int bytecount = dwc2_hb_mult(maxp) * dwc2_max_packet(maxp);
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char *speed, *type;
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/* Initialize QH */
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qh->hsotg = hsotg;
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qh->ep_type = ep_type;
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qh->ep_is_in = ep_is_in;
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qh->data_toggle = DWC2_HC_PID_DATA0;
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qh->maxp = maxp;
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INIT_LIST_HEAD(&qh->qtd_list);
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INIT_LIST_ITEM(&qh->qh_list_entry);
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qh->qh_list_entry.pvOwner = (void *)qh;
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qh->do_split = do_split;
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qh->dev_speed = dev_speed;
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switch (dev_speed) {
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case USB_SPEED_LOW:
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speed = "low";
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break;
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case USB_SPEED_FULL:
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speed = "full";
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break;
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case USB_SPEED_HIGH:
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speed = "high";
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break;
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default:
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speed = "?";
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break;
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}
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switch (qh->ep_type) {
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case USB_ENDPOINT_XFER_CONTROL:
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type = "control";
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break;
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case USB_ENDPOINT_XFER_BULK:
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type = "bulk";
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break;
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default:
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type = "?";
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break;
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}
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USB_UNUSED(bytecount);
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USB_UNUSED(speed);
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USB_UNUSED(type);
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dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
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speed, bytecount);
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dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
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dwc2_hcd_get_dev_addr(&urb->pipe_info),
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dwc2_hcd_get_ep_num(&urb->pipe_info),
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ep_is_in ? "IN" : "OUT");
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}
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/**
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* dwc2_hcd_qh_create() - Allocates and initializes a QH
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @urb: Holds the information about the device/endpoint needed
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* to initialize the QH
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* @atomic_alloc: Flag to do atomic allocation if needed
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*
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* Return: Pointer to the newly allocated QH, or NULL on error
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*/
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struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
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struct dwc2_hcd_urb *urb,
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gfp_t mem_flags)
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{
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struct dwc2_qh *qh;
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if (!urb->priv)
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return NULL;
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/* Allocate memory */
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qh = (struct dwc2_qh *)kzalloc(sizeof(*qh), mem_flags);
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if (!qh)
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return NULL;
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dwc2_qh_init(hsotg, qh, urb, mem_flags);
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/* if (hsotg->params.dma_desc_enable &&
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dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
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dwc2_hcd_qh_free(hsotg, qh);
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return NULL;
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} */
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return qh;
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}
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/**
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* dwc2_hcd_qh_free() - Frees the QH
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*
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* @hsotg: HCD instance
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* @qh: The QH to free
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*
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* QH should already be removed from the list. QTD list should already be empty
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* if called from URB Dequeue.
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*
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* Must NOT be called with interrupt disabled or spinlock held
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*/
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void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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/* Make sure any unreserve work is finished. */
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if (0) {
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unsigned long flags;
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spin_lock_irqsave(&hsotg->lock, flags);
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dwc2_do_unreserve(hsotg, qh);
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spin_unlock_irqrestore(&hsotg->lock, flags);
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}
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dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
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kfree(qh);
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}
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/**
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* dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
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* schedule if it is not already in the schedule. If the QH is already in
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* the schedule, no action is taken.
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*
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* @hsotg: The HCD state structure for the DWC OTG controller
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* @qh: The QH to add
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*
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* Return: 0 if successful, negative error code otherwise
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*/
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int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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u32 intr_mask;
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if (dbg_qh(qh))
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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if (!list_item_empty(&qh->qh_list_entry))
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/* QH already in a schedule */
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return 0;
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/* Add the new QH to the appropriate schedule */
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if (dwc2_qh_is_non_per(qh)) {
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/* Schedule right away */
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qh->start_active_frame = hsotg->frame_number;
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qh->next_active_frame = qh->start_active_frame;
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/* Always start in inactive schedule */
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list_add_tail(&qh->qh_list_entry,
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&hsotg->non_periodic_sched_inactive);
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return 0;
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}
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intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
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intr_mask |= GINTSTS_SOF;
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dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
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return 0;
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}
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/**
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* dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
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* schedule. Memory is not freed.
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*
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* @hsotg: The HCD state structure
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* @qh: QH to remove from schedule
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*/
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void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
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{
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u32 intr_mask;
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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if (list_item_empty(&qh->qh_list_entry))
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/* QH is not in a schedule */
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return;
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if (dwc2_qh_is_non_per(qh)) {
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if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) {
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hsotg->non_periodic_qh_ptr = listGET_NEXT(hsotg->non_periodic_qh_ptr);
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}
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list_del_init(&qh->qh_list_entry);
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return;
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}
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intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
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intr_mask &= ~GINTSTS_SOF;
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dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
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}
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/*
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* Deactivates a QH. For non-periodic QHs, removes the QH from the active
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* non-periodic schedule. The QH is added to the inactive non-periodic
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* schedule if any QTDs are still attached to the QH.
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*
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* For periodic QHs, the QH is removed from the periodic queued schedule. If
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* there are any QTDs still attached to the QH, the QH is added to either the
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* periodic inactive schedule or the periodic ready schedule and its next
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* scheduled frame is calculated. The QH is placed in the ready schedule if
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* the scheduled frame has been reached already. Otherwise it's placed in the
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* inactive schedule. If there are no QTDs attached to the QH, the QH is
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* completely removed from the periodic schedule.
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*/
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void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
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int sched_next_periodic_split)
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{
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u16 old_frame = qh->next_active_frame;
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dev_vdbg(hsotg->dev, "%s() ep_type:%d\n", __func__, qh->ep_type);
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USB_UNUSED(old_frame);
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if (dbg_qh(qh))
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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if (dwc2_qh_is_non_per(qh)) {
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dwc2_hcd_qh_unlink(hsotg, qh);
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if (!list_empty(&qh->qtd_list))
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/* Add back to inactive non-periodic schedule */
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dwc2_hcd_qh_add(hsotg, qh);
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return;
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}
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}
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/**
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* dwc2_hcd_qtd_init() - Initializes a QTD structure
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*
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* @qtd: The QTD to initialize
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* @urb: The associated URB
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*/
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void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
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{
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qtd->urb = urb;
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if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
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USB_ENDPOINT_XFER_CONTROL) {
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/*
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* The only time the QTD data toggle is used is on the data
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* phase of control transfers. This phase always starts with
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* DATA1.
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*/
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qtd->data_toggle = DWC2_HC_PID_DATA1;
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qtd->control_phase = DWC2_CONTROL_SETUP;
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}
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/* Start split */
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qtd->complete_split = 0;
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qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
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qtd->in_process = 0;
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/* Store the qtd ptr in the urb to reference the QTD */
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urb->qtd = qtd;
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}
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/**
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* dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
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* Caller must hold driver lock.
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*
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* @hsotg: The DWC HCD structure
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* @qtd: The QTD to add
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* @qh: Queue head to add qtd to
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*
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* Return: 0 if successful, negative error code otherwise
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*
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* If the QH to which the QTD is added is not currently scheduled, it is placed
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* into the proper schedule based on its EP type.
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*/
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int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
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struct dwc2_qh *qh)
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{
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int retval;
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if (unlikely(!qh)) {
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dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
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retval = -EINVAL;
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goto fail;
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}
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retval = dwc2_hcd_qh_add(hsotg, qh);
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if (retval)
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goto fail;
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qtd->qh = qh;
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list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
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return 0;
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fail:
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return retval;
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}
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