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CARPLAY版本整理

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LiJie
2025-01-21 16:49:37 +08:00
commit f0fb64e4e6
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60
MXC_A27-PCB4.5-270S/ArkmicroFiles/libcpu-amt630hv100/include/adc.h Normal file
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#ifndef _ADC_H
#define _ADC_H
typedef enum {
ADC_CH_BAT = 1,
ADC_CH_TP = 2,
ADC_CH_AUX0 = 3,
ADC_CH_AUX1 = 4,
ADC_CH_AUX2 = 5,
ADC_CH_AUX3 = 6,
ADC_CH_AUX4 = 7,
ADC_CH_AUX5 = 8,
ADC_CH_AUX6 = 9,
ADC_CH_AUX7 = 10,
} eAdcChannel;
#define AUX0_START_INT (1<<0)
#define AUX0_STOP_INT (1<<1)
#define AUX0_VALUE_INT (1<<2)
#define AUX1_START_INT (1<<3)
#define AUX1_STOP_INT (1<<4)
#define AUX1_VALUE_INT (1<<5)
#define AUX2_START_INT (1<<6)
#define AUX2_STOP_INT (1<<7)
#define AUX2_VALUE_INT (1<<8)
#define AUX3_START_INT (1<<9)
#define AUX3_STOP_INT (1<<10)
#define AUX3_VALUE_INT (1<<11)
#define AUX4_START_INT (1<<16)
#define AUX4_STOP_INT (1<<17)
#define AUX4_VALUE_INT (1<<18)
#define AUX5_START_INT (1<<19)
#define AUX5_STOP_INT (1<<20)
#define AUX5_VALUE_INT (1<<21)
#define AUX6_START_INT (1<<22)
#define AUX6_STOP_INT (1<<23)
#define AUX6_VALUE_INT (1<<24)
#define AUX7_START_INT (1<<25)
#define AUX7_STOP_INT (1<<26)
#define AUX7_VALUE_INT (1<<27)
#define TP_START_INT (1<<12)
#define TP_STOP_INT (1<<13)
#define TP_VALUE_INT (1<<14)
#define BAT_INT (1<<15)
void adc_init(void);
void adc_channel_enable(eAdcChannel ch);
void adc_channel_disable(eAdcChannel ch);
unsigned int adc_get_channel_value(int ch);
#endif

56
MXC_A27-PCB4.5-270S/ArkmicroFiles/libcpu-amt630hv100/include/aic.h Normal file
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/**
* \file
*
* \section Purpose
*
* Methods and definitions for configuring interrupts.
*
* \section Usage
* -# Enable or disable interrupt generation of a particular source with
* IRQ_EnableIT and IRQ_DisableIT.
* -# Start or stop the timer clock using TC_Start() and TC_Stop().
*/
#ifndef AIC_H
#define AIC_H
/*------------------------------------------------------------------------------
* Headers
*------------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
/*------------------------------------------------------------------------------
* Global functions
*------------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*ISRFunction_t)( void *param );
enum {
IRQ_TYPE_EDGE_BOTH,
IRQ_TYPE_EDGE_RISING,
IRQ_TYPE_EDGE_FALLING,
IRQ_TYPE_LEVEL_HIGH,
IRQ_TYPE_LEVEL_LOW,
};
extern void AIC_Initialize(void);
extern void AIC_EnableIT( uint32_t source);
extern void AIC_DisableIT(uint32_t source);
extern int32_t request_irq(uint32_t irq_source, int32_t priority, ISRFunction_t func, void *param);
extern int32_t free_irq(uint32_t irq_source);
extern void AIC_IrqHandler(void);
extern uint8_t interrupt_get_nest(void);
#ifdef __cplusplus
}
#endif
#endif //#ifndef AIC_H

113
MXC_A27-PCB4.5-270S/ArkmicroFiles/libcpu-amt630hv100/include/amt630hv100.h Normal file
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#ifndef __AMT630HV100__H
#define __AMT630HV100__H
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifdef __cplusplus
#define __I volatile /**< Defines 'read-only' permissions */
#else
#define __I volatile const /**< Defines 'read-only' permissions */
#endif
#define __O volatile /**< Defines 'write-only' permissions */
#define __IO volatile /**< Defines 'read/write' permissions */
#endif
#include "os_adapt.h"
typedef enum IRQn
{
LCD_IRQn = 0, /**< 0 AMT630HV100 LCD Interrupt ID */
JPG_IRQn = 1, /**< 1 AMT630HV100 Jpeg Decoder Interrupt (JPG) */
GPU_IRQn = 2, /**< 2 AMT630HV100 GPU Interrupt (GPU) */
USB_IRQn = 3, /**< 3 AMT630HV100 USB Controller Interrupt (USB) */
PXP_IRQn = 4, /**< 4 AMT630HV100 PXP Interrupt (PXP) */
DMA_IRQn = 5, /**< 5 AMT630HV100 DMA Controller Interrupt (DMAC) */
SDMMC0_IRQn = 6, /**< 6 AMT630HV100 SDMMC 0 Controller Interrupt (SDMMC0) */
SPI0_IRQn = 7, /**< 7 AMT630HV100 SPI 0 Controller Interrupt (SPI0) */
SPI1_IRQn = 8, /**< 8 AMT630HV100 SPI 1 Controller Interrupt (SPI1) */
I2C0_IRQn = 9, /**< 9 AMT630HV100 I2C0 Controller Interrupt (I2C0) */
I2C1_IRQn = 10, /**< 10 AMT630HV100 I2C1 Controller Interrupt (I2C1) */
UART0_IRQn = 11, /**< 11 AMT630HV100 UART 0 Controller Interrupt (UART0) */
UART1_IRQn = 12, /**< 12 AMT630HV100 UART 1 Controller Interrupt (UART1) */
UART2_IRQn = 13, /**< 13 AMT630HV100 UART 2 Controller Interrupt (UART2) */
UART3_IRQn = 14, /**< 14 AMT630HV100 UART 3 Controller Interrupt (UART3) */
GPIOA_IRQn = 15, /**< 15 AMT630HV100 GPIO0~31 Controller Interrupt (GPIOA) */
GPIOB_IRQn = 16, /**< 16 AMT630HV100 GPIO32~63 Controller Interrupt (GPIOB) */
GPIOC_IRQn = 17, /**< 17 AMT630HV100 GPIO64~95 Controller Interrupt (GPIOC) */
GPIOD_IRQn = 18, /**< 18 AMT630HV100 GPIO96~127 Controller Interrupt (GPIOD) */
TIMER0_IRQn = 19, /**< 19 AMT630HV100 Timer 0 Interrupt (TIMER0) */
TIMER1_IRQn = 20, /**< 20 AMT630HV100 Timer 1 Interrupt (TIMER1) */
TIMER2_IRQn = 21, /**< 21 AMT630HV100 Timer 2/3 Interrupt (TIMER2/TIMER3) */
I2S1_IRQn = 22, /**< 22 AMT630HV100 I2S1 Interrupt (I2S1) */
ITU_IRQn = 23, /**< 23 AMT630HV100 ITU Controller Interrupt (ITU) */
WDT_IRQn = 24, /**< 24 AMT630HV100 Watchdog timer Interrupt (WDT) */
I2S_IRQn = 25, /**< 25 AMT630HV100 I2S Interrupt (I2S) */
BLEND2D_IRQn = 26, /**< 26 AMT630HV100 BLEND2D Interrupt (BLEND2D) */
RTC_PRD_IRQn = 27, /**< 27 AMT630HV100 RTC Controller Period Interrupt (RTCP) */
ADC_IRQn = 28, /**< 28 AMT630HV100 ADC controller Interrupt (ADC) */
RCRT_IRQn = 29, /**< 29 */
CAN0_IRQn = 30, /**< 30 AMT630HV100 CAN0 Controller Interrupt (CAN0) */
CAN1_IRQn = 31, /**< 31 AMT630HV100 CAN1 Controller Interrupt (CAN1) */
MAX_IRQ_NUM = 32 /**< Number of peripheral IDs */
} IRQn_Type;
/*@}*/
/* ************************************************************************** */
/* BASE ADDRESS DEFINITIONS FOR AMT630HV100 */
/* ************************************************************************** */
/** \addtogroup AMT630HV100_base Peripheral Base Address Definitions */
/*@{*/
#define REGS_SYSCTL_BASE (0x60000000U)
#define REGS_SPI0_BASE (0x60100000U)
#define REGS_SPI1_BASE (0x60200000U)
#define REGS_IIC0_BASE (0x60300000U)
#define REGS_IIC1_BASE (0x60400000U)
#define REGS_UART0_BASE (0x60500000U)
#define REGS_UART1_BASE (0x60600000U)
#define REGS_UART2_BASE (0x60700000U)
#define REGS_UART3_BASE (0x60800000U)
#define REGS_GPIO_BASE (0x60900000U)
#define REGS_TIMER_BASE (0x60a00000U)
#define REGS_PWM_BASE (0x60b00000U)
#define REGS_WDT_BASE (0x60c00000U)
#define REGS_I2S_BASE (0x60d00000U)
#define REGS_I2S1_BASE (0x60f00000U)
#define REGS_MIPI_BASE (0x60e00000U)
#define REGS_RTC_BASE (0x61000000U)
#define REGS_ADC_BASE (0x61100000U)
#define REGS_RCRT_BASE (0x61200000U)
#define REGS_AES_BASE (0x61300000U)
#define REGS_AIC_BASE (0x61400000U)
#define REGS_CAN0_BASE (0x61500000U)
#define REGS_CAN1_BASE (0x61600000U)
#define REGS_DMAC_BASE (0x70100000U)
#define REGS_GPU_BASE (0x70200000U)
#define REGS_USB_BASE (0x70300000U)
#define REGS_SDMMC0_BASE (0X70400000U)
#define REGS_ITU_BASE (0X70600000U)
#define REGS_BLEND2D_BASE (0x70700000U)
#define REGS_LCD_BASE (0X71000000U)
#define REGS_PXP_BASE (0X71100000U)
#define REGS_ROTATE_BASE (0X71207000U)
#define REGS_JPG_BASE (0X71208000U)
#define REGS_DDRC_BASE (0X71300000U)
/* ************************************************************************** */
/* ELECTRICAL DEFINITIONS FOR AMT630HV100 */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* __AMT630HV100__H */

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#ifndef __AUDIO_H__
#define __AUDIO_H__
/* AUDIO command */
#define _AUDIO_CTL(a) (0x10 + a)
#define AUDIO_CTL_GETCAPS _AUDIO_CTL(1)
#define AUDIO_CTL_CONFIGURE _AUDIO_CTL(2)
#define AUDIO_CTL_START _AUDIO_CTL(3)
#define AUDIO_CTL_STOP _AUDIO_CTL(4)
#define AUDIO_CTL_GETBUFFERINFO _AUDIO_CTL(5)
/* Audio Device Types */
#define AUDIO_TYPE_QUERY 0x00
#define AUDIO_TYPE_INPUT 0x01
#define AUDIO_TYPE_OUTPUT 0x02
#define AUDIO_TYPE_MIXER 0x04
/* Supported Sampling Rates */
#define AUDIO_SAMP_RATE_8K 0x0001
#define AUDIO_SAMP_RATE_11K 0x0002
#define AUDIO_SAMP_RATE_16K 0x0004
#define AUDIO_SAMP_RATE_22K 0x0008
#define AUDIO_SAMP_RATE_32K 0x0010
#define AUDIO_SAMP_RATE_44K 0x0020
#define AUDIO_SAMP_RATE_48K 0x0040
#define AUDIO_SAMP_RATE_96K 0x0080
#define AUDIO_SAMP_RATE_128K 0x0100
#define AUDIO_SAMP_RATE_160K 0x0200
#define AUDIO_SAMP_RATE_172K 0x0400
#define AUDIO_SAMP_RATE_192K 0x0800
/* Supported Bit Rates */
#define AUDIO_BIT_RATE_22K 0x01
#define AUDIO_BIT_RATE_44K 0x02
#define AUDIO_BIT_RATE_48K 0x04
#define AUDIO_BIT_RATE_96K 0x08
#define AUDIO_BIT_RATE_128K 0x10
#define AUDIO_BIT_RATE_160K 0x20
#define AUDIO_BIT_RATE_172K 0x40
#define AUDIO_BIT_RATE_192K 0x80
/* Support Dsp(input/output) Units controls */
#define AUDIO_DSP_PARAM 0 /* get/set all params */
#define AUDIO_DSP_SAMPLERATE 1 /* samplerate */
#define AUDIO_DSP_CHANNELS 2 /* channels */
#define AUDIO_DSP_SAMPLEBITS 3 /* sample bits width */
/* Supported Mixer Units controls */
#define AUDIO_MIXER_QUERY 0x0000
#define AUDIO_MIXER_MUTE 0x0001
#define AUDIO_MIXER_VOLUME 0x0002
#define AUDIO_MIXER_BASS 0x0004
#define AUDIO_MIXER_MID 0x0008
#define AUDIO_MIXER_TREBLE 0x0010
#define AUDIO_MIXER_EQUALIZER 0x0020
#define AUDIO_MIXER_LINE 0x0040
#define AUDIO_MIXER_DIGITAL 0x0080
#define AUDIO_MIXER_MIC 0x0100
#define AUDIO_MIXER_VITURAL 0x0200
#define AUDIO_MIXER_EXTEND 0x8000 /* extend mixer command */
#define AUDIO_VOLUME_MAX (100)
#define AUDIO_VOLUME_MIN (0)
#define CFG_AUDIO_REPLAY_QUEUE_COUNT 8
/**
* audio flags defitions
*/
//#define AUDIO_FLAG_REPLAY 0
//#define AUDIO_FLAG_RECORD 1
#define AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define AUDIO_REPLAY_MP_BLOCK_COUNT 4
#define AUDIO_RECORD_PIPE_SIZE 2048
//typedef int (*audio_record_callback)(struct audio_device *audio, void *buffer, int size);
enum
{
AUDIO_STREAM_REPLAY = 0,
AUDIO_STREAM_RECORD = 1,
};
/* the preferred number and size of audio pipeline buffer for the audio device */
struct audio_buf_info
{
uint8_t *buffer;
uint16_t block_size;
uint16_t block_count;
uint32_t total_size;
};
struct audio_device;
struct audio_caps;
struct audio_configure;
struct audio_ops
{
int (*getcaps)(struct audio_device *audio, struct audio_caps *caps);
int (*configure)(struct audio_device *audio, struct audio_caps *caps);
int (*init)(struct audio_device *audio);
int (*start)(struct audio_device *audio, int stream);
int (*stop)(struct audio_device *audio, int stream);
size_t (*transmit)(struct audio_device *audio, const void *writeBuf, void *readBuf, size_t size);
/* get page size of codec or private buffer's info */
void (*buffer_info)(struct audio_device *audio, struct audio_buf_info *info, int flags);
};
struct audio_configure
{
uint32_t samplerate;
uint16_t channels;
uint16_t samplebits;
};
struct audio_caps
{
int main_type;
int sub_type;
union
{
uint32_t mask;
int value;
struct audio_configure config;
} udata;
};
struct audio_replay
{
QueueHandle_t queue;
SemaphoreHandle_t lock;
QueueHandle_t cmp;
struct audio_buf_info buf_info;
uint8_t *mempool;
uint8_t mpstatus[AUDIO_REPLAY_MP_BLOCK_COUNT];
uint8_t *write_data;
uint16_t write_index;
uint16_t read_index;
uint32_t pos;
uint8_t event;
bool activated;
};
struct audio_record
{
QueueHandle_t cmp;
struct audio_buf_info buf_info;
int read_index;
int remain_size;
uint8_t event;
bool activated;
int (*receive_cb)(struct audio_device *audio);
};
struct audio_device
{
struct audio_ops *ops;
struct audio_replay *replay;
struct audio_record *record;
/* device call back */
int (*rx_indicate)(struct audio_device *audio, size_t size);
int (*tx_complete)(struct audio_device *audio, void *buffer);
uint32_t flag;
uint32_t id;
void *user_data; /**< device private data */
};
int audio_register(struct audio_device *audio);
void audio_tx_complete(struct audio_device *audio);
int audio_rx_complete(struct audio_device *audio);
void audio_rx_done(struct audio_device *audio, uint8_t *pbuf, size_t len);
struct audio_device *audio_dev_open(uint32_t oflag);
int audio_dev_close(struct audio_device *audio, uint32_t oflag);
size_t audio_dev_read(struct audio_device *audio, void *buffer, size_t size);
size_t audio_dev_write(struct audio_device *audio, const void *buffer, size_t size);
int audio_dev_configure(struct audio_device *audio, struct audio_caps *caps);
int audio_dev_register_record_callback(struct audio_device *audio, int (*callback)(struct audio_device *audio));
int audio_dev_record_set_param(struct audio_device *audio, uint8_t *buf, int size);
int audio_dev_record_start(struct audio_device *audio);
int audio_dev_record_stop(struct audio_device *audio);
/* Device Control Commands */
#define CODEC_CMD_RESET 0
#define CODEC_CMD_SET_VOLUME 1
#define CODEC_CMD_GET_VOLUME 2
#define CODEC_CMD_SAMPLERATE 3
#define CODEC_CMD_EQ 4
#define CODEC_CMD_3D 5
#define CODEC_VOLUME_MAX (63)
#endif /* __AUDIO_H__ */

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/*
* blend2d.h
*
*/
#ifndef _BLEND2D_H
#define _BLEND2D_H
typedef enum {
BLEND2D_RGBA = 0,
BLEND2D_ARGB,
} BLEND2D_BLEND_ENDIAN;
typedef enum {
BLEND2D_RGB = 0,
BLEND2D_RBG,
BLEND2D_GRB,
BLEND2D_GBR,
BLEND2D_BRG,
BLEND2D_BGR,
} BLEND2D_RGB_ORDER;
typedef enum {
BLEND2D_FORAMT_RGB565 = 5,
BLEND2D_FORAMT_ARGB888 = 6,
BLEND2D_FORAMT_BGR565 = BLEND2D_FORAMT_RGB565 | (5 << 8),
BLEND2D_FORMAT_ABGR888 = BLEND2D_FORAMT_ARGB888 | (5 << 8),
} BLEND2D_FORMAT;
typedef enum {
BLEND2D_ALPHA_DATA = 0,
BLEND2D_ALPHA_REG,
} BLEND2D_LAYER_ALPHA_MODE;
typedef enum {
BLEND2D_ALPHA_LAYER1 = 0,
BLEND2D_ALPHA_LAYER2,
BLEND2D_ALPHA_BLEND_REG,
} BLEND2D_BLEND_ALPHA_MODE;
typedef enum {
BLEND2D_MIX_BLEND = 0,
BLEND2D_MIX_LAYER1 = 1,
BLEND2D_MIX_LAYER2 = 2,
BLEND2D_MIX_LAYER1_COLORKEY_COVER_TRANSP = 3,
BLEND2D_MIX_LAYER2_COLORKEY_COVER_TRANSP = 0xc,
BLEND2D_MIX_LAYER2_COLORKEY_BLEND_COVER = 0xd,
BLEND2D_MIX_LAYER2_COLORKEY_BLEND_TRANSP = 0xe,
} BLEND2D_BLEND_MIX_MODE;
typedef enum {
BLEND2D_LAYER1 = 0,
BLEND2D_LAYER2,
BLEND2D_NUMS,
} BLEND2D_LAYER;
int blend2d_demo(void);
int blend2d_init(void);
void blend2d_fill(uint32_t address, int xpos, int ypos, int width, int height, int source_width, int source_height,
uint8_t cr, uint8_t cg, uint8_t cb, int format, uint8_t opa, int alpha_byte);
void blend2d_blit(uint32_t dst_addr, int dst_w, int dst_h, int dst_x, int dst_y, int dst_format, int width, int height,
uint32_t src_addr, int src_w, int src_h, int src_x, int src_y, int src_format, uint8_t opa, int alpha_byte);
int blend2d_run(void);
#endif

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#ifndef _CAN_H
#define _CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#define CAN0 ( (CAN_TypeDef* )REGS_CAN0_BASE)
#define CAN1 ( (CAN_TypeDef* )REGS_CAN1_BASE)
#define CAN_InitStatus_Failed ((unsigned char)0x00) /*!< CAN initialization failed */
#define CAN_InitStatus_Success ((unsigned char)0x01) /*!< CAN initialization OK */
#define CAN_SJW_1tq ((unsigned char)0x00) /*!< 1 time quantum */
#define CAN_SJW_2tq ((unsigned char)0x01) /*!< 2 time quantum */
#define CAN_SJW_3tq ((unsigned char)0x02) /*!< 3 time quantum */
#define CAN_SJW_4tq ((unsigned char)0x03) /*!< 4 time quantum */
#define CAN_BS1_1tq ((unsigned char)0x00) /*!< 1 time quantum */
#define CAN_BS1_2tq ((unsigned char)0x01) /*!< 2 time quantum */
#define CAN_BS1_3tq ((unsigned char)0x02) /*!< 3 time quantum */
#define CAN_BS1_4tq ((unsigned char)0x03) /*!< 4 time quantum */
#define CAN_BS1_5tq ((unsigned char)0x04) /*!< 5 time quantum */
#define CAN_BS1_6tq ((unsigned char)0x05) /*!< 6 time quantum */
#define CAN_BS1_7tq ((unsigned char)0x06) /*!< 7 time quantum */
#define CAN_BS1_8tq ((unsigned char)0x07) /*!< 8 time quantum */
#define CAN_BS1_9tq ((unsigned char)0x08) /*!< 9 time quantum */
#define CAN_BS1_10tq ((unsigned char)0x09) /*!< 10 time quantum */
#define CAN_BS1_11tq ((unsigned char)0x0A) /*!< 11 time quantum */
#define CAN_BS1_12tq ((unsigned char)0x0B) /*!< 12 time quantum */
#define CAN_BS1_13tq ((unsigned char)0x0C) /*!< 13 time quantum */
#define CAN_BS1_14tq ((unsigned char)0x0D) /*!< 14 time quantum */
#define CAN_BS1_15tq ((unsigned char)0x0E) /*!< 15 time quantum */
#define CAN_BS1_16tq ((unsigned char)0x0F) /*!< 16 time quantum */
#define CAN_BS2_1tq ((unsigned char)0x00) /*!< 1 time quantum */
#define CAN_BS2_2tq ((unsigned char)0x01) /*!< 2 time quantum */
#define CAN_BS2_3tq ((unsigned char)0x02) /*!< 3 time quantum */
#define CAN_BS2_4tq ((unsigned char)0x03) /*!< 4 time quantum */
#define CAN_BS2_5tq ((unsigned char)0x04) /*!< 5 time quantum */
#define CAN_BS2_6tq ((unsigned char)0x05) /*!< 6 time quantum */
#define CAN_BS2_7tq ((unsigned char)0x06) /*!< 7 time quantum */
#define CAN_BS2_8tq ((unsigned char)0x07) /*!< 8 time quantum */
#define CAN_Id_Standard 0
#define CAN_Id_Extended 1
#define CAN_RTR_DATA 0
#define CAN_RTR_Remote 1
/*!< CAN 控制状态寄存器 */
/************************** CAN_MOD 寄存器位定义*******************************/
#define CAN_Mode_RM ((unsigned char)0x01) /*!< 复位模式 */
#define CAN_Mode_LOM ((unsigned char)0x02) /*!< 只听模式 1:只听 0:正常 */
#define CAN_Mode_STM ((unsigned char)0x04) /*!< 正常工作模式1:自检测 0:正常 */
#define CAN_Mode_AFM ((unsigned char)0x08) /*!< 单/双滤波模式 1:单 0: 双*/
#define CAN_Mode_SM ((unsigned char)0x10) /*!< 睡眠模式1: 睡眠 0: 唤醒 */
/************************** CAN_CMR 寄存器位定义*******************************/
#define CAN_CMR_TR ((unsigned char)0x01) /*!< 发送请求 1: 当前信息被发送 0: 空 */
#define CAN_CMR_AT ((unsigned char)0x02) /*!< 中止发送 1: 等待发送的信息取消 0: 空缺 */
#define CAN_CMR_RRB ((unsigned char)0x04) /*!< 释放接收缓冲器 1:释放 0: 无动作 */
#define CAN_CMR_CDO ((unsigned char)0x08) /*!< 清除数据溢出 1:清除 0: 无动作 */
//#define CAN_CMR_GTS ((unsigned char)0x10) /*!< STD模式< 睡眠: 1:进入睡眠 0: 唤醒 */
#define CAN_CMR_SRR ((unsigned char)0x10) /*!< 自接收请求 1: 0: */
#define CAN_CMR_EFF ((unsigned char)0x80) /*!< 扩展模式 1:扩展帧 0: 标准帧 */
/************************** CAN_SR 寄存器位定义********************************/
#define CAN_SR_BBS ((unsigned char)0x01) /*!< 接收缓存器状态1: 满 0: 空 */
#define CAN_SR_DOS ((unsigned char)0x02) /*!< 数据溢出状态 1: 溢出 0: 空缺 */
#define CAN_SR_TBS ((unsigned char)0x04) /*!< 发送缓存器状态1: 释放 0: 锁定 */
#define CAN_SR_TCS ((unsigned char)0x08) /*!< 发送完毕状态1: 完毕 0: 未完毕 */
#define CAN_SR_RS ((unsigned char)0x10) /*!< 接收状态1: 接收 0: 空闲 */
#define CAN_SR_TS ((unsigned char)0x20) /*!< 发送状态1: 发送 0: 空闲*/
#define CAN_SR_ES ((unsigned char)0x40) /*!< 出错状态1:出错 0: 正常 */
#define CAN_SR_BS ((unsigned char)0x80) /*!< 总线状态1: 关闭 0: 开启 */
/************************** CAN_IR 中断寄存器位定义****************************/
#define CAN_IR_RI ((unsigned char)0x01) /*!< 接收中断 */
#define CAN_IR_TI ((unsigned char)0x02) /*!< 发送中断 */
#define CAN_IR_EI ((unsigned char)0x04) /*!< 错误中断 */
#define CAN_IR_DOI ((unsigned char)0x08) /*!< 数据溢出中断 */
#define CAN_IR_WUI ((unsigned char)0x10) /*!< 唤醒中断 */
#define CAN_IR_EPI ((unsigned char)0x20) /*!< 错误消极中断 */
#define CAN_IR_ALI ((unsigned char)0x40) /*!< 仲裁丢失中断 */
#define CAN_IR_BEI ((unsigned char)0x80) /*!< 总线错误中断 */
/************************* CAN_IER 中断使能寄存器位定义************************/
#define CAN_IER_RIE ((unsigned char)0x01) /*!< 接收中断使能 */
#define CAN_IER_TIE ((unsigned char)0x02) /*!< 发送中断使能 */
#define CAN_IER_EIE ((unsigned char)0x04) /*!< 错误中断使能 */
#define CAN_IER_DOIE ((unsigned char)0x08) /*!< 数据溢出中断使能 */
#define CAN_IER_WUIE ((unsigned char)0x10) /*!< 唤醒中断使能 */
#define CAN_IER_EPIE ((unsigned char)0x20) /*!< 错误消极中断使能 */
#define CAN_IER_ALIE ((unsigned char)0x40) /*!< 仲裁丢失中断使能 */
#define CAN_IER_BEIE ((unsigned char)0x80) /*!< 总线错误中断使能 */
typedef enum
{
CAN1MBaud=0, // 1 MBit/sec
CAN800kBaud, // 800 kBit/sec
CAN500kBaud, // 500 kBit/sec
CAN250kBaud, // 250 kBit/sec
CAN125kBaud, // 125 kBit/sec
CAN100kBaud, // 100 kBit/sec
CAN50kBaud, // 50 kBit/sec
CAN40kBaud, // 40 kBit/sec
} CanBPS_t;
typedef enum
{
CAN_MODE_NORMAL=0,
CAN_MODE_LISEN,
CAN_MODE_LOOPBACK,
CAN_MODE_LOOPBACKANLISEN,
} CanMode_t;
typedef struct
{
unsigned int MOD;
unsigned int CMR;
unsigned int SR;
unsigned int IR;
unsigned int IER;
unsigned int reserved0;
unsigned int BTR0;
unsigned int BTR1;
unsigned int OCR;
unsigned int reserved[2];
unsigned int ALC;
unsigned int ECC ;
unsigned int EWLR;
unsigned int RXERR;
unsigned int TXERR;
unsigned int IDE_RTR_DLC;
unsigned int ID[4];
unsigned int BUF[8];
unsigned int RMC;
unsigned int RBSA;
unsigned int CDR;
} CAN_TypeDef;
typedef struct
{
unsigned char CAN_Prescaler; /* 波特率分频系数1 to 63. */
unsigned char CAN_Mode; /*0x10:睡眠0x08:单,双滤波 0x40:正常工作0x20:只听 0x01:复位*/
unsigned char CAN_SJW; /*同步跳转宽度 */
unsigned char CAN_BS1; /*时间段1计数值*/
unsigned char CAN_BS2; /*时间段2计数值*/
} CAN_InitTypeDef;
typedef struct
{
unsigned char IDE; /*0: 使用标准标识符1: 使用扩展标识符*/
unsigned char RTR; /*0: 数据帧 1: 远程帧*/
unsigned char MODE; /* 0- 双滤波器模式;1-单滤波器模式*/
unsigned long First_Data; /*双滤波器模式下信息第一个数据字节*/
unsigned long Data_Mask; /*双滤波器模式下信息第一个数据字节屏蔽*/
unsigned long ID; /*验收代码*/
/*
双滤波器- 扩展帧: 2个滤波器的前16位,分别放在ID 的前16位和 ID的后16位.
双滤波器- 标准帧: 2个滤波器的11位,分别放在ID 的前16位和 ID的后16位,第1个滤波器同时使用First_Data和Data_Mask
单滤波器- 扩展帧: 使用29位, 放在ID 的后29位.
单滤波器- 标准帧: 使用11位, 放在ID 的后11位.
*/
unsigned long IDMASK; /*验收屏蔽*/
} CAN_FilterInitTypeDef;
typedef struct
{
unsigned long StdId; /* 11位ID*/
unsigned long ExtId; /*29位ID**/
unsigned char IDE; /*IDE: 标识符选择
该位决定发送邮箱中报文使用的标识符类型
0: 使用标准标识符
1: 使用扩展标识符*/
unsigned char RTR; /*远程发送请求
0: 数据帧
1: 远程帧*/
unsigned char DLC; /*数据帧长度*/
unsigned char Data[8]; /*8字节数据*/
} CanMsg;
unsigned char CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_Transmit(CAN_TypeDef* CANx, CanMsg* TxMessage);
void CAN_Receive(CAN_TypeDef* CANx, CanMsg* RxMessage);
unsigned char can_set_reset_mode(CAN_TypeDef* CANx);
unsigned char can_set_start(CAN_TypeDef* CANx);
typedef enum {
CAN_ID0 = 0,
CAN_ID1,
CAN_NUM,
} eCanID;
typedef struct {
uint32_t baud_rate;
uint32_t msgboxsz;
uint32_t sndboxnumber;
uint32_t mode : 8;
uint32_t privmode : 8;
uint32_t reserved : 16;
uint32_t ticks;
} CanConfigure_t;
typedef struct {
uint32_t id;
int irq;
CAN_TypeDef *pcan;
SemaphoreHandle_t xRxMutex;
SemaphoreHandle_t xRev;
SemaphoreHandle_t xSend;
SemaphoreHandle_t xTxMutex;
TaskHandle_t xTxThread;
QueueHandle_t tx_done;
List_t rxRevList;
List_t rxFreeList;
List_t txSendList;
List_t txFreeList;
} CanPort_t;
CanPort_t *xCanOpen(uint32_t id);
void vCanClose(CanPort_t *cap);
void vCanSetFilter(CanPort_t *cap, CAN_FilterInitTypeDef * CAN_FilterInitStruct);
int iCanWrite(CanPort_t *cap, CanMsg* messages, int nmsgs, TickType_t xBlockTime);
int iCanRead(CanPort_t *cap, CanMsg* messages, int nmsgs, TickType_t xBlockTime);
void vCanInit(CanPort_t *cap, CanBPS_t baud, CanMode_t mode);
int iCanGetReceiveErrorCount(CanPort_t *cap);
int iCanGetTransmitErrorCount(CanPort_t *cap);
int can_demo(void);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _CIRC_BUF_H
#define _CIRC_BUF_H
#ifdef __cplusplus
extern "C" {
#endif
struct circ_buf {
char *buf;
int head;
int tail;
};
/* Return count in buffer. */
#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
/* Return space available, 0..size-1. We always leave one free char
as a completely full buffer has head == tail, which is the same as
empty. */
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
/* Return count up to the end of the buffer. Carefully avoid
accessing head and tail more than once, so they can change
underneath us without returning inconsistent results. */
static __INLINE int CIRC_CNT_TO_END(uint32_t head, uint32_t tail, uint32_t size)
{
int end = (size) - (tail);
int n = ((head) + end) & ((size)-1);
return n < end ? n : end;
}
/* Return space available up to the end of the buffer. */
static __INLINE int CIRC_SPACE_TO_END(uint32_t head, uint32_t tail, uint32_t size)
{
int end = (size) - 1 - (head);
int n = (end + (tail)) & ((size) - 1);
return n <= end ? n : end + 1;
}
#ifdef __cplusplus
}
#endif
#endif /* _LINUX_CIRC_BUF_H */

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#ifndef _CLOCK_H
#define _CLOCK_H
#ifdef __cplusplus
extern "C" {
#endif
#define MAX_CLK_SOURCE_NUM 4
#define MAX_CLK_ENABLE_BITS 4
typedef enum {
CLK_XTAL32K = 0,
CLK_XTAL24M,
CLK_240MHZ,
CLK_12MHZ,
CLK_6MHZ,
CLK_CPUPLL,
CLK_SYSPLL,
CLK_VPUPLL,
CLK_DDRPLL,//<2F><><EFBFBD><EFBFBD>DDR PLL
CLK_DDR,
CLK_CPU,
CLK_H2X,
CLK_AHB,
CLK_APB,
CLK_RTC,
CLK_SPI0,
CLK_SPI1,
CLK_SDMMC0,
CLK_LCD,
CLK_UART1,
CLK_UART2,
CLK_UART3,
CLK_TIMER,
CLK_MFC,
CLK_PWM,
CLK_CAN0,
CLK_CAN1,
CLK_ADC,
CLK_I2S,
CLK_I2S1,
}eClockID;
typedef enum {
FIXED_CLOCK = 0,
FIXED_FACTOR_CLOCK,
PLL_CLOCK,
SYS_CLOCK,
}eClockType;
typedef enum {
DIVMODE_NOZERO = 0, /* div = div ? div : 1 */
DIVMODE_PLUSONE, /* div = div + 1 */
DIVMODE_DOUBLE, /* div = div * 2 */
DIVMODE_EXPONENT, /* div = 1 << div */
DIVMODE_PONEDOUBLE, /* div = (div + 1) * 2 */
}eDivMode;
void vClkInit(void);
uint32_t ulClkGetRate(uint32_t clkid);
void vClkSetRate(uint32_t clkid, uint32_t freq);
void vClkEnable(uint32_t clkid);
void vClkDisable(uint32_t clkid);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _DMA_H
#define _DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#define DMA_INT_TC (1 << 0)
#define DMA_INT_ERR (1 << 1)
enum DMA_HW_HS_MAP{
SPI0_RX = 0,
SPI0_TX,
SPI1_RX,
SPI1_TX,
I2C0_RX,
I2C0_TX,
I2C1_RX,
I2C1_TX,
UART0_RX,
UART0_TX,
UART1_RX,
UART1_TX,
UART2_RX,
UART2_TX,
UART3_RX,
UART3_TX,
I2S_RX,
I2S_TX,
I2S1_RX,
I2S1_TX,
SDMMC0_RTX,
};
enum dma_transfer_direction {
DMA_MEM_TO_MEM,
DMA_MEM_TO_DEV,
DMA_DEV_TO_MEM,
DMA_DEV_TO_DEV,
DMA_TRANS_NONE,
};
enum dma_buswidth {
DMA_BUSWIDTH_1_BYTE = 0,
DMA_BUSWIDTH_2_BYTES = 1,
DMA_BUSWIDTH_4_BYTES = 2,
};
struct dma_config {
enum dma_transfer_direction direction;
int src_id;
int dst_id;
unsigned int src_addr;
unsigned int dst_addr;
enum dma_buswidth src_addr_width;
enum dma_buswidth dst_addr_width;
u32 src_maxburst;
u32 dst_maxburst;
u32 transfer_size;
int blkint_en;
};
struct dma_lli {
unsigned int src_addr;
unsigned int dst_addr;
unsigned int next_lli;
unsigned int control;
};
struct dma_chan {
int chan_id;
int in_use;
void (*irq_callback)(void *param, unsigned int mask);
void *callback_param;
struct dma_lli *lli;
};
struct dma_chan *dma_request_channel(int favorite_ch);
void dma_release_channel(struct dma_chan *chan);
int dma_config_channel(struct dma_chan *chan, struct dma_config *config);
int dma_register_complete_callback(struct dma_chan *chan,
void (*callback)(void *param, unsigned int mask),
void *callback_param);
int dma_start_channel(struct dma_chan *chan);
int dma_stop_channel(struct dma_chan *chan);
int dma_init(void);
int dma_m2mcpy(unsigned int dst_addr, unsigned int src_addr, int size);
#ifdef __cplusplus
}
#endif
#endif

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/****************************************************************************
* include/audio/automount.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (c) <2014-2015>, <Huawei Technologies Co., Ltd>
* All rights reserved.
*
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Notice of Export Control Law
* ===============================================
* Huawei LiteOS may be subject to applicable export control laws and regulations,
* which might include those applicable to Huawei LiteOS of U.S. and the country in
* which you are located.
* Import, export and usage of Huawei LiteOS in any manner by you shall be in
* compliance with such applicable export control laws and regulations.
****************************************************************************/
#ifndef __INCLUDE_AUDIO_AUTOMOUNT_H
#define __INCLUDE_AUDIO_AUTOMOUNT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "stdint.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************
* Automounter configuration
* CONFIG_FS_AUTOMOUNTER - Enables automount support
*
* Prequisites:
* CONFIG_SCHED_WORKQUEUE - Work queue support is required
* And others that would only matter if you are working in a very minimal
* configuration.
*/
/* Helper macros ************************************************************/
#define AUTOMOUNT_ATTACH(s,isr,arg) ((s)->attach(s,isr,arg))
#define AUTOMOUNT_DETACH(s) ((s)->attach(s,NULL,NULL))
#define AUTOMOUNT_ENABLE(s) ((s)->enable(s,true))
#define AUTOMOUNT_DISABLE(s) ((s)->enable(s,false))
#define AUTOMOUNT_INSERTED(s) ((s)->inserted(s))
/****************************************************************************
* Public Types
****************************************************************************/
/* This is the type of the automount media change handler. The lower level
* code will intercept the interrupt and provide the upper level with the
* private data that was provided when the interrupt was attached and will
* also provide an indication if the media was inserted or removed.
*/
struct automount_lower_s; /* Forward reference. Defined below */
typedef CODE int
(*automount_handler_t)(FAR const struct automount_lower_s *lower,
FAR void *arg, bool inserted);
/* A reference to a structure of this type must be passed to the FS
* automounter. This structure provides information about the volume to be
* mounted and provides board-specific hooks.
*
* Memory for this structure is provided by the caller. It is not copied
* by the automounter and is presumed to persist while the automounter
* is active.
*/
struct automount_lower_s
{
/* Volume characterization */
FAR const char *fstype; /* Type of file system */
FAR const char *blockdev; /* Path to the block device */
FAR const char *mountpoint; /* Location to mount the volume */
/* Debounce delay in system clock ticks. Automount operation will not
* be performed until the insertion/removal state has been unchanges
* for this duration.
*/
uint32_t ddelay;
/* Unmount delay time in system clock ticks. If a volume has open
* references at the time that the media is removed, then we will be
* unable to unmount it. In that case, hopefully, the clients of the
* mount will eventually fail with file access errors and eventually close
* their references. So, at some time later, it should be possible to
* unmount the volume. This delay specifies the time between umount
* retries.
*/
uint32_t udelay;
/* Interrupt related operations all hidden behind callbacks to isolate the
* automounter from differences in interrupt handling by varying boards
* and MCUs. Board interrupts should be configured both insertion and
* removal of the media can be detected.
*
* attach - Attach or detach the media change interrupt handler to the
* board level interrupt
* enable - Enable or disable the media change interrupt
*/
CODE int (*attach)(FAR const struct automount_lower_s *lower,
automount_handler_t isr, FAR void *arg);
CODE void (*enable)(FAR const struct automount_lower_s *lower,
bool enable);
CODE bool (*inserted)(FAR const struct automount_lower_s *lower);
};
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: automount_initialize
*
* Description:
* Configure the automounter.
*
* Input Parameters:
* lower - Persistent board configuration data
*
* Returned Value:
* A void* handle. The only use for this handle is with automount_uninitialize().
* NULL is returned on any failure.
*
****************************************************************************/
FAR void *automount_initialize(FAR const struct automount_lower_s *lower);
/****************************************************************************
* Name: automount_uninitialize
*
* Description:
* Stop the automounter and free resources that it used. NOTE that the
* mount is left in its last state mounted/unmounted state.
*
* Input Parameters:
* handle - The value previously returned by automount_initialize();
*
* Returned Value:
* None
*
****************************************************************************/
void automount_uninitialize(FAR void *handle);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* __INCLUDE_AUDIO_AUTOMOUNT_H */

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/****************************************************************************
* include/fs/dirent.h
*
* Copyright (C) 2007, 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Copyright (c) <2014-2015>, <Huawei Technologies Co., Ltd>
* All rights reserved.
*
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Notice of Export Control Law
* ===============================================
* Huawei LiteOS may be subject to applicable export control laws and regulations,
* which might include those applicable to Huawei LiteOS of U.S. and the country in
* which you are located.
* Import, export and usage of Huawei LiteOS in any manner by you shall be in
* compliance with such applicable export control laws and regulations.
****************************************************************************/
#ifndef __INCLUDE_FS_DIRENT_H
#define __INCLUDE_FS_DIRENT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "vfs_config.h"
#include "sys/types.h"
#include "stdint.h"
#include "dirent.h"
#include "fs/fs.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/****************************************************************************
* Public Types
****************************************************************************/
/* The internal representation of type DIR is just a container for an inode
* reference, a position, a dirent structure, and file-system-specific
* information.
*
* For the root pseudo-file system, we need retain only the 'next' inode
* need for the next readdir() operation. We hold a reference on this
* inode so we know that it will persist until closedir is called.
*/
struct fs_pseudodir_s
{
struct inode *fd_next; /* The inode for the next call to readdir() */
};
typedef void *fs_dir_s;
#define DIRENT_MAGIC 0x11CBA828 /* Magic number to express the status of a dirent */
struct fs_dirent_s
{
/* This is the node that was opened by opendir. The type of the inode
* determines the way that the readdir() operations are performed. For the
* pseudo root pseudo-file system, it is also used to support rewind.
*
* We hold a reference on this inode so we know that it will persist until
* closedir() is called (although inodes linked to this inode may change).
*/
struct inode *fd_root;
/* At present, only mountpoints require special handling flags */
#ifndef CONFIG_DISABLE_MOUNTPOINT
unsigned int fd_flags;
#endif
/* This keeps track of the current directory position for telldir */
off_t fd_position;
/* Retained control information depends on the type of file system that
* provides is provides the mountpoint. Ideally this information should
* be hidden behind an opaque, file-system-dependent void *, but we put
* the private definitions in line here for now to reduce allocations.
*/
struct
{
/* Private data used by the built-in pseudo-file system */
struct fs_pseudodir_s pseudo;
/* Private data used by other file systems */
fs_dir_s fs_dir;
} u;
/* In any event, this the actual struct dirent that is returned by readdir */
struct dirent fd_dir; /* Populated when readdir is called */
int fd_status; /* Express the dirent is been opened or no */
};
/****************************************************************************
* Global Variables
****************************************************************************/
extern DIR *fdopendir(int);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* __INCLUDE_FS_DIRENT_H */

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/****************************************************************************
* include/fs/file.h
*
* Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved.
* Copyright (c) <2014-2015>, <Huawei Technologies Co., Ltd>
* All rights reserved.
*
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Notice of Export Control Law
* ===============================================
* Huawei LiteOS may be subject to applicable export control laws and regulations,
* which might include those applicable to Huawei LiteOS of U.S. and the country in
* which you are located.
* Import, export and usage of Huawei LiteOS in any manner by you shall be in
* compliance with such applicable export control laws and regulations.
****************************************************************************/
/**@defgroup fs Filesystem
*
*/
#ifndef __INCLUDE_FS_FILE_H
#define __INCLUDE_FS_FILE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "vfs_config.h"
#include "compiler.h"
#include "sys/types.h"
#include "stdarg.h"
#include "stdint.h"
#include "semaphore.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/****************************************************************************
* Global Function Prototypes
****************************************************************************/
struct filelist *sched_getfiles(void);
/* fs_inode.c ***************************************************************/
/****************************************************************************
* Name: fs_initialize
*
* Description:
* This is called from the OS initialization logic to configure the file
* system.
*
****************************************************************************/
void fs_initialize(void);
/* fs_files.c ***************************************************************/
/****************************************************************************
* Name: files_initlist
*
* Description:
* Initializes the list of files for a new task
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
void files_initlist(FAR struct filelist *list);
#endif
/****************************************************************************
* Name: files_releaselist
*
* Description:
* Release a reference to the file list
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
void files_releaselist(FAR struct filelist *list);
#endif
/****************************************************************************
* Name: file_dup2
*
* Description:
* Assign an inode to a specific files structure. This is the heart of
* dup2.
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
int file_dup2(FAR struct file *filep1, FAR struct file *filep2);
#endif
/* fs_filedup.c *************************************************************/
/****************************************************************************
* Name: fs_dupfd OR dup
*
* Description:
* Clone a file descriptor 'fd' to an arbitray descriptor number (any value
* greater than or equal to 'minfd'). If socket descriptors are
* implemented, then this is called by dup() for the case of file
* descriptors. If socket descriptors are not implemented, then this
* function IS dup().
*
* This alternative naming is used when dup could operate on both file and
* socket descritors to avoid drawing unused socket support into the link.
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
int fs_dupfd(int fd, int minfd);
#endif
/****************************************************************************
* Name: file_dup
*
* Description:
* Equivalent to the non-standard fs_dupfd() function except that it
* accepts a struct file instance instead of a file descriptor. Currently
* used only by file_vfcntl();
*
****************************************************************************/
int file_dup(FAR struct file *filep, int minfd);
/* fs_filedup2.c ************************************************************/
/****************************************************************************
* Name: fs_dupfd2 OR dup2
*
* Description:
* Clone a file descriptor to a specific descriptor number. If socket
* descriptors are implemented, then this is called by dup2() for the
* case of file descriptors. If socket descriptors are not implemented,
* then this function IS dup2().
*
* This alternative naming is used when dup2 could operate on both file and
* socket descritors to avoid drawing unused socket support into the link.
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
int fs_dupfd2(int fd1, int fd2);
#endif
/* fs/vfs/fs_ioctl.c ********************************************************/
/****************************************************************************
* Name: fs_ioctl
*
* Description:
* Perform device specific operations.
*
* Parameters:
* fd File/socket descriptor of device
* req The ioctl command
* arg The argument of the ioctl cmd
*
* Return:
* >=0 on success (positive non-zero values are cmd-specific)
* -1 on failure with errno set properly:
*
* EBADF
* 'fd' is not a valid descriptor.
* EFAULT
* 'arg' references an inaccessible memory area.
* EINVAL
* 'cmd' or 'arg' is not valid.
* ENOTTY
* 'fd' is not associated with a character special device.
* ENOTTY
* The specified request does not apply to the kind of object that the
* descriptor 'fd' references.
*
****************************************************************************/
#ifdef CONFIG_LIBC_IOCTL_VARIADIC
int fs_ioctl(int fd, int req, unsigned long arg);
#endif
/* fs_fdopen.c **************************************************************/
/****************************************************************************
* Name: fs_fdopen
*
* Description:
* This function does the core operations for fopen and fdopen. It is
* used by the OS to clone stdin, stdout, stderr
*
****************************************************************************/
#if CONFIG_NFILE_STREAMS > 0
struct tcb_s; /* Forward reference */
FAR struct file_struct *fs_fdopen(int fd, int oflags);
#endif
/* libc/stdio/lib_fflush.c *************************************************/
/****************************************************************************
* Name: lib_flushall
*
* Description:
* Called either (1) by the OS when a task exits, or (2) from fflush()
* when a NULL stream argument is provided.
*
****************************************************************************/
#if CONFIG_NFILE_STREAMS > 0
int lib_flushall(FAR struct streamlist *list);
#endif
/* libc/misc/lib_sendfile.c *************************************************/
/****************************************************************************
* Name: lib_sendfile
*
* Description:
* Transfer a file
*
****************************************************************************/
#ifdef CONFIG_NET_SENDFILE
ssize_t lib_sendfile(int outfd, int infd, off_t *offset, size_t count);
#endif
/* fs/fs_getfilep.c *********************************************************/
/****************************************************************************
* Name: fs_getfilep
*
* Description:
* Given a file descriptor, return the corresponding instance of struct
* file. NOTE that this function will currently fail if it is provided
* with a socket descriptor.
*
* Parameters:
* fd - The file descriptor
*
* Return:
* A point to the corresponding struct file instance is returned on
* success. On failure, NULL is returned and the errno value is
* set appropriately (EBADF).
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
FAR struct file *fs_getfilep(int fd);
#endif
/* fs/fs_read.c *************************************************************/
/****************************************************************************
* Name: file_read
*
* Description:
* Equivalent to the standard read() function except that is accepts a
* struct file instance instead of a file descriptor. Currently used
* only by net_sendfile() and aio_read();
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
ssize_t file_read(FAR struct file *filep, FAR void *buf, size_t nbytes);
#endif
/* fs/fs_write.c ************************************************************/
/****************************************************************************
* Name: file_write
*
* Description:
* Equivalent to the standard write() function except that is accepts a
* struct file instance instead of a file descriptor. Currently used
* only by aio_write();
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
ssize_t file_write(FAR struct file *filep, FAR const void *buf, size_t nbytes);
#endif
/* fs/fs_pread.c ************************************************************/
/****************************************************************************
* Name: file_pread
*
* Description:
* Equivalent to the standard pread function except that is accepts a
* struct file instance instead of a file descriptor. Currently used
* only by aio_read();
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
ssize_t file_pread(FAR struct file *filep, FAR void *buf, size_t nbytes,
off_t offset);
#endif
/* fs/fs_pwrite.c ***********************************************************/
/****************************************************************************
* Name: file_pwrite
*
* Description:
* Equivalent to the standard pwrite function except that is accepts a
* struct file instance instead of a file descriptor. Currently used
* only by aio_write();
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
ssize_t file_pwrite(FAR struct file *filep, FAR const void *buf,
size_t nbytes, off_t offset);
#endif
/* fs/fs_lseek.c ************************************************************/
/****************************************************************************
* Name: file_seek
*
* Description:
* Equivalent to the standard lseek() function except that is accepts a
* struct file instance instead of a file descriptor. Currently used
* only by net_sendfile()
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
off_t file_seek(FAR struct file *filep, off_t offset, int whence);
#endif
/* fs/fs_lseek64.c ************************************************************/
/****************************************************************************
* Name: file_seek64
*
* Description:
* Equivalent to the standard lseek64() function except that is accepts a
* struct file instance instead of a file descriptor. Currently used
* only by net_sendfile()
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
off64_t file_seek64(FAR struct file *filep, off64_t offset, int whence);
#endif
/* fs/fs_fsync.c ************************************************************/
/****************************************************************************
* Name: file_fsync
*
* Description:
* Equivalent to the standard fsync() function except that is accepts a
* struct file instance instead of a file descriptor. Currently used
* only by aio_fsync();
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
int file_fsync(FAR struct file *filep);
#endif
/* fs/fs_fcntl.c ************************************************************/
/****************************************************************************
* Name: file_vfcntl
*
* Description:
* Similar to the standard vfcntl function except that is accepts a struct
* struct file instance instead of a file descriptor. Currently used
* only by aio_fcntl();
*
****************************************************************************/
#if CONFIG_NFILE_DESCRIPTORS > 0
int file_vfcntl(FAR struct file *filep, int cmd, va_list ap);
#endif
void clear_fd(int fd);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* __INCLUDE_FS_FILE_H */

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#ifndef _GPIO_H
#define _GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
GPIOIRQ_TYPE_EDGE_BOTH,
GPIOIRQ_TYPE_EDGE_RISING,
GPIOIRQ_TYPE_EDGE_FALLING,
GPIOIRQ_TYPE_LEVEL_HIGH,
GPIOIRQ_TYPE_LEVEL_LOW,
} eGpioIrqType;
void gpio_request(unsigned gpio);
void gpio_direction_output(unsigned gpio, int value);
void gpio_direction_input(unsigned gpio);
void gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
int gpio_irq_request(unsigned gpio, int irq_type, ISRFunction_t irq_handler, void *param);
int gpio_irq_free(unsigned gpio);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HX170DEC_H_
#define _HX170DEC_H_
struct core_desc
{
u32 id; /* id of the core */
u32 *regs; /* pointer to user registers */
u32 size; /* size of register space */
};
#define HX170DEC_IOCGHWOFFSET 3
#define HX170DEC_IOCGHWIOSIZE 4
#define HX170DEC_IOC_MC_OFFSETS 7
#define HX170DEC_IOC_MC_CORES 8
#define HX170DEC_IOCS_DEC_PUSH_REG 9
#define HX170DEC_IOCS_PP_PUSH_REG 10
#define HX170DEC_IOCH_DEC_RESERVE 11
#define HX170DEC_IOCT_DEC_RELEASE 12
#define HX170DEC_IOCQ_PP_RESERVE 13
#define HX170DEC_IOCT_PP_RELEASE 14
#define HX170DEC_IOCX_DEC_WAIT 15
#define HX170DEC_IOCX_PP_WAIT 16
#define HX170DEC_IOCS_DEC_PULL_REG 17
#define HX170DEC_IOCS_PP_PULL_REG 18
#define HX170DEC_IOX_ASIC_ID 20
#define HX170DEC_IOC_MAXNR 29
long vdec_ioctl(unsigned int cmd, void *arg);
#endif /* !_HX170DEC_H_ */

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#ifndef _I2C_DW_H
#define _I2C_DW_H
#ifdef __cplusplus
extern "C" {
#endif
#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
I2C_FUNC_SMBUS_BYTE | \
I2C_FUNC_SMBUS_BYTE_DATA | \
I2C_FUNC_SMBUS_WORD_DATA | \
I2C_FUNC_SMBUS_BLOCK_DATA | \
I2C_FUNC_SMBUS_I2C_BLOCK)
#define DW_IC_CON_MASTER 0x1
#define DW_IC_CON_SPEED_STD 0x2
#define DW_IC_CON_SPEED_FAST 0x4
#define DW_IC_CON_SPEED_HIGH 0x6
#define DW_IC_CON_SPEED_MASK 0x6
#define DW_IC_CON_10BITADDR_SLAVE 0x8
#define DW_IC_CON_10BITADDR_MASTER 0x10
#define DW_IC_CON_RESTART_EN 0x20
#define DW_IC_CON_SLAVE_DISABLE 0x40
#define DW_IC_CON_STOP_DET_IFADDRESSED 0x80
#define DW_IC_CON_TX_EMPTY_CTRL 0x100
#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL 0x200
/*
* Registers offset
*/
#define DW_IC_CON 0x0
#define DW_IC_TAR 0x4
#define DW_IC_SAR 0x8
#define DW_IC_DATA_CMD 0x10
#define DW_IC_SS_SCL_HCNT 0x14
#define DW_IC_SS_SCL_LCNT 0x18
#define DW_IC_FS_SCL_HCNT 0x1c
#define DW_IC_FS_SCL_LCNT 0x20
#define DW_IC_HS_SCL_HCNT 0x24
#define DW_IC_HS_SCL_LCNT 0x28
#define DW_IC_INTR_STAT 0x2c
#define DW_IC_INTR_MASK 0x30
#define DW_IC_RAW_INTR_STAT 0x34
#define DW_IC_RX_TL 0x38
#define DW_IC_TX_TL 0x3c
#define DW_IC_CLR_INTR 0x40
#define DW_IC_CLR_RX_UNDER 0x44
#define DW_IC_CLR_RX_OVER 0x48
#define DW_IC_CLR_TX_OVER 0x4c
#define DW_IC_CLR_RD_REQ 0x50
#define DW_IC_CLR_TX_ABRT 0x54
#define DW_IC_CLR_RX_DONE 0x58
#define DW_IC_CLR_ACTIVITY 0x5c
#define DW_IC_CLR_STOP_DET 0x60
#define DW_IC_CLR_START_DET 0x64
#define DW_IC_CLR_GEN_CALL 0x68
#define DW_IC_ENABLE 0x6c
#define DW_IC_STATUS 0x70
#define DW_IC_TXFLR 0x74
#define DW_IC_RXFLR 0x78
#define DW_IC_SDA_HOLD 0x7c
#define DW_IC_TX_ABRT_SOURCE 0x80
#define DW_IC_ENABLE_STATUS 0x9c
#define DW_IC_CLR_RESTART_DET 0xa8
#define DW_IC_COMP_PARAM_1 0xf4
#define DW_IC_COMP_VERSION 0xf8
#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
#define DW_IC_COMP_TYPE 0xfc
#define DW_IC_COMP_TYPE_VALUE 0x44570140
#define DW_IC_INTR_RX_UNDER 0x001
#define DW_IC_INTR_RX_OVER 0x002
#define DW_IC_INTR_RX_FULL 0x004
#define DW_IC_INTR_TX_OVER 0x008
#define DW_IC_INTR_TX_EMPTY 0x010
#define DW_IC_INTR_RD_REQ 0x020
#define DW_IC_INTR_TX_ABRT 0x040
#define DW_IC_INTR_RX_DONE 0x080
#define DW_IC_INTR_ACTIVITY 0x100
#define DW_IC_INTR_STOP_DET 0x200
#define DW_IC_INTR_START_DET 0x400
#define DW_IC_INTR_GEN_CALL 0x800
#define DW_IC_INTR_RESTART_DET 0x1000
#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
DW_IC_INTR_TX_ABRT | \
DW_IC_INTR_STOP_DET)
#define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
DW_IC_INTR_TX_EMPTY)
#define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
DW_IC_INTR_RX_DONE | \
DW_IC_INTR_RX_UNDER | \
DW_IC_INTR_RD_REQ)
#define DW_IC_STATUS_ACTIVITY 0x1
#define DW_IC_STATUS_TFE BIT(2)
#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
#define DW_IC_SDA_HOLD_RX_SHIFT 16
#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
#define DW_IC_ERR_TX_ABRT 0x1
#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
/*
* status codes
*/
#define STATUS_IDLE 0x0
#define STATUS_WRITE_IN_PROGRESS 0x1
#define STATUS_READ_IN_PROGRESS 0x2
#define TIMEOUT 20 /* ms */
/*
* operation modes
*/
#define DW_IC_MASTER 0
#define DW_IC_SLAVE 1
/*
* Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
*
* Only expected abort codes are listed here
* refer to the datasheet for the full list
*/
#define ABRT_7B_ADDR_NOACK 0
#define ABRT_10ADDR1_NOACK 1
#define ABRT_10ADDR2_NOACK 2
#define ABRT_TXDATA_NOACK 3
#define ABRT_GCALL_NOACK 4
#define ABRT_GCALL_READ 5
#define ABRT_SBYTE_ACKDET 7
#define ABRT_SBYTE_NORSTRT 9
#define ABRT_10B_RD_NORSTRT 10
#define ABRT_MASTER_DIS 11
#define ARB_LOST 12
#define ABRT_SLAVE_FLUSH_TXFIFO 13
#define ABRT_SLAVE_ARBLOST 14
#define ABRT_SLAVE_RD_INTX 15
#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
#define DW_IC_RX_ABRT_SLAVE_RD_INTX (1UL << ABRT_SLAVE_RD_INTX)
#define DW_IC_RX_ABRT_SLAVE_ARBLOST (1UL << ABRT_SLAVE_ARBLOST)
#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO (1UL << ABRT_SLAVE_FLUSH_TXFIFO)
#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
DW_IC_TX_ABRT_10ADDR1_NOACK | \
DW_IC_TX_ABRT_10ADDR2_NOACK | \
DW_IC_TX_ABRT_TXDATA_NOACK | \
DW_IC_TX_ABRT_GCALL_NOACK)
/**
* struct dw_i2c_dev - private i2c-designware data
* @dev: driver model device node
* @base: IO registers pointer
* @cmd_complete: tx completion indicator
* @clk: input reference clock
* @slave: represent an I2C slave device
* @cmd_err: run time hadware error code
* @msgs: points to an array of messages currently being transferred
* @msgs_num: the number of elements in msgs
* @msg_write_idx: the element index of the current tx message in the msgs
* array
* @tx_buf_len: the length of the current tx buffer
* @tx_buf: the current tx buffer
* @msg_read_idx: the element index of the current rx message in the msgs
* array
* @rx_buf_len: the length of the current rx buffer
* @rx_buf: the current rx buffer
* @msg_err: error status of the current transfer
* @status: i2c master status, one of STATUS_*
* @abort_source: copy of the TX_ABRT_SOURCE register
* @irq: interrupt number for the i2c master
* @adapter: i2c subsystem adapter node
* @slave_cfg: configuration for the slave device
* @tx_fifo_depth: depth of the hardware tx fifo
* @rx_fifo_depth: depth of the hardware rx fifo
* @rx_outstanding: current master-rx elements in tx fifo
* @clk_freq: bus clock frequency
* @ss_hcnt: standard speed HCNT value
* @ss_lcnt: standard speed LCNT value
* @fs_hcnt: fast speed HCNT value
* @fs_lcnt: fast speed LCNT value
* @fp_hcnt: fast plus HCNT value
* @fp_lcnt: fast plus LCNT value
* @hs_hcnt: high speed HCNT value
* @hs_lcnt: high speed LCNT value
* @pm_qos: pm_qos_request used while holding a hardware lock on the bus
* @acquire_lock: function to acquire a hardware lock on the bus
* @release_lock: function to release a hardware lock on the bus
* @disable: function to disable the controller
* @disable_int: function to disable all interrupts
* @init: function to initialize the I2C hardware
* @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
*
* HCNT and LCNT parameters can be used if the platform knows more accurate
* values than the one computed based only on the input clock frequency.
* Leave them to be %0 if not used.
*/
struct dw_i2c_dev {
u32 base;
int irq;
QueueHandle_t cmd_complete;
struct i2c_adapter *slave;
u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
int cmd_err;
struct i2c_msg *msgs;
int msgs_num;
int msg_write_idx;
u32 tx_buf_len;
u8 *tx_buf;
int msg_read_idx;
u32 rx_buf_len;
u8 *rx_buf;
int msg_err;
unsigned int status;
u32 abort_source;
u32 flags;
struct i2c_adapter adapter;
u32 functionality;
u32 master_cfg;
u32 slave_cfg;
unsigned int tx_fifo_depth;
unsigned int rx_fifo_depth;
int rx_outstanding;
u32 clk_freq;
u32 sda_hold_time;
u32 sda_falling_time;
u32 scl_falling_time;
u16 ss_hcnt;
u16 ss_lcnt;
u16 fs_hcnt;
u16 fs_lcnt;
u16 fp_hcnt;
u16 fp_lcnt;
u16 hs_hcnt;
u16 hs_lcnt;
int (*acquire_lock)(struct dw_i2c_dev *dev);
void (*release_lock)(struct dw_i2c_dev *dev);
void (*disable)(struct dw_i2c_dev *dev);
void (*disable_int)(struct dw_i2c_dev *dev);
int (*init)(struct dw_i2c_dev *dev);
int mode;
};
#define ACCESS_SWAP 0x00000001
#define ACCESS_16BIT 0x00000002
#define ACCESS_INTR_MASK 0x00000004
#define MODEL_CHERRYTRAIL 0x00000100
int i2c_dw_init(int id);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _I2C_GPIO_H
#define _I2C_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
struct i2c_gpio_platform_data {
int devid;
unsigned int sda_pin;
unsigned int scl_pin;
int udelay;
int timeout;
unsigned int sda_is_open_drain:1;
unsigned int scl_is_open_drain:1;
unsigned int scl_is_output_only:1;
};
struct i2c_algo_bit_data {
void *data; /* private data for lowlevel routines */
void (*setsda) (void *data, int state);
void (*setscl) (void *data, int state);
int (*getsda) (void *data);
int (*getscl) (void *data);
/* local settings */
int udelay; /* half clock cycle time in us,
minimum 2 us for fast-mode I2C,
minimum 5 us for standard-mode I2C and SMBus,
maximum 50 us for SMBus */
int timeout; /* in jiffies */
};
void i2c_gpio_init(void);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _I2C_H
#define _I2C_H
#ifdef __cplusplus
extern "C" {
#endif
struct i2c_adapter;
/**
* struct i2c_msg - an I2C transaction segment beginning with START
* @addr: Slave address, either seven or ten bits. When this is a ten
* bit address, I2C_M_TEN must be set in @flags and the adapter
* must support I2C_FUNC_10BIT_ADDR.
* @flags: I2C_M_RD is handled by all adapters. No other flags may be
* provided unless the adapter exported the relevant I2C_FUNC_*
* flags through i2c_check_functionality().
* @len: Number of data bytes in @buf being read from or written to the
* I2C slave address. For read transactions where I2C_M_RECV_LEN
* is set, the caller guarantees that this buffer can hold up to
* 32 bytes in addition to the initial length byte sent by the
* slave (plus, if used, the SMBus PEC); and this value will be
* incremented by the number of block data bytes received.
* @buf: The buffer into which data is read, or from which it's written.
*
* An i2c_msg is the low level representation of one segment of an I2C
* transaction. It is visible to drivers in the @i2c_transfer() procedure,
* to userspace from i2c-dev, and to I2C adapter drivers through the
* @i2c_adapter.@master_xfer() method.
*
* Except when I2C "protocol mangling" is used, all I2C adapters implement
* the standard rules for I2C transactions. Each transaction begins with a
* START. That is followed by the slave address, and a bit encoding read
* versus write. Then follow all the data bytes, possibly including a byte
* with SMBus PEC. The transfer terminates with a NAK, or when all those
* bytes have been transferred and ACKed. If this is the last message in a
* group, it is followed by a STOP. Otherwise it is followed by the next
* @i2c_msg transaction segment, beginning with a (repeated) START.
*
* Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
* passing certain @flags may have changed those standard protocol behaviors.
* Those flags are only for use with broken/nonconforming slaves, and with
* adapters which are known to support the specific mangling options they
* need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
*/
struct i2c_msg {
uint16_t addr; /* slave address */
uint16_t flags;
#define I2C_M_RD 0x0001 /* read data, from slave to master */
/* I2C_M_RD is guaranteed to be 0x0001! */
#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_NOSTART */
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
uint16_t len; /* msg length */
uint8_t *buf; /* pointer to msg data */
};
/* To determine what functionality is present */
#define I2C_FUNC_I2C 0x00000001
#define I2C_FUNC_10BIT_ADDR 0x00000002
#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_IGNORE_NAK etc. */
#define I2C_FUNC_SMBUS_PEC 0x00000008
#define I2C_FUNC_NOSTART 0x00000010 /* I2C_M_NOSTART */
#define I2C_FUNC_SLAVE 0x00000020
#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
#define I2C_FUNC_SMBUS_QUICK 0x00010000
#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000
#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000
#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000
#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000
#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000
#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
#define I2C_FUNC_SMBUS_HOST_NOTIFY 0x10000000
#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
I2C_FUNC_SMBUS_WRITE_BYTE)
#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \
I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \
I2C_FUNC_SMBUS_WRITE_WORD_DATA)
#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \
I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \
I2C_FUNC_SMBUS_BYTE | \
I2C_FUNC_SMBUS_BYTE_DATA | \
I2C_FUNC_SMBUS_WORD_DATA | \
I2C_FUNC_SMBUS_PROC_CALL | \
I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
I2C_FUNC_SMBUS_I2C_BLOCK | \
I2C_FUNC_SMBUS_PEC)
/*
* Data for SMBus Messages
*/
#define I2C_SMBUS_BLOCK_MAX 32 /* As specified in SMBus standard */
union i2c_smbus_data {
uint8_t byte;
uint16_t word;
uint8_t block[I2C_SMBUS_BLOCK_MAX + 2]; /* block[0] is used for length */
/* and one more for user-space compatibility */
};
/* i2c_smbus_xfer read or write markers */
#define I2C_SMBUS_READ 1
#define I2C_SMBUS_WRITE 0
/* SMBus transaction types (size parameter in the above functions)
Note: these no longer correspond to the (arbitrary) PIIX4 internal codes! */
#define I2C_SMBUS_QUICK 0
#define I2C_SMBUS_BYTE 1
#define I2C_SMBUS_BYTE_DATA 2
#define I2C_SMBUS_WORD_DATA 3
#define I2C_SMBUS_PROC_CALL 4
#define I2C_SMBUS_BLOCK_DATA 5
#define I2C_SMBUS_I2C_BLOCK_BROKEN 6
#define I2C_SMBUS_BLOCK_PROC_CALL 7 /* SMBus 2.0 */
#define I2C_SMBUS_I2C_BLOCK_DATA 8
/*flags for the client struct: */
#define I2C_CLIENT_PEC 0x04 /* Use Packet Error Checking */
#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */
/* Must equal I2C_M_TEN below */
#define I2C_CLIENT_SLAVE 0x20 /* we are the slave */
#define I2C_CLIENT_HOST_NOTIFY 0x40 /* We want to use I2C host notify */
#define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */
#define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */
/* Must match I2C_M_STOP|IGNORE_NAK */
enum i2c_slave_event {
I2C_SLAVE_READ_REQUESTED,
I2C_SLAVE_WRITE_REQUESTED,
I2C_SLAVE_READ_PROCESSED,
I2C_SLAVE_WRITE_RECEIVED,
I2C_SLAVE_STOP,
};
typedef int (*i2c_slave_cb_t)(struct i2c_adapter *, enum i2c_slave_event, u8 *);
struct i2c_algorithm {
/* master_xfer should return the number of messages successfully
processed, or a negative value on error */
int (*master_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs,
int num);
int (*reg_slave)(struct i2c_adapter *adap);
int (*unreg_slave)(struct i2c_adapter *adap);
};
/*
* i2c_adapter is the structure used to identify a physical i2c bus along
* with the access algorithms necessary to access it.
*/
struct i2c_adapter {
const struct i2c_algorithm *algo; /* the algorithm to access the bus */
void *algo_data;
void *dw_dev;
int retries;
int timeout; /* in jiffies */
SemaphoreHandle_t xMutex;
i2c_slave_cb_t slave_cb; /* callback for slave mode */
int open_count;
unsigned short flags; /* div., see below */
unsigned short addr; /* chip address - NOTE: 7bit */
char name[16];
};
static __INLINE int i2c_slave_event(struct i2c_adapter *adap,
enum i2c_slave_event event, u8 *val)
{
return adap->slave_cb(adap, event, val);
}
void i2c_init(void);
int i2c_add_adapter(struct i2c_adapter *adap);
struct i2c_adapter *i2c_open(const char *i2cdev);
void i2c_close(struct i2c_adapter *adap);
int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
int i2c_slave_register(struct i2c_adapter *adap, u8 addr, i2c_slave_cb_t slave_cb);
int i2c_slave_unregister(struct i2c_adapter *adap);
#ifdef __cplusplus
}
#endif
#endif

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/*
* ark_i2s.h
*
*/
#ifndef __I2S_H
#define __I2S_H
/*
* I2S Controller Register and Bit Definitions
*/
#define I2S_SACR0 0x00 /* Global Control Register */
#define I2S_SACR1 0x04 /* Serial Audio I 2 S/MSB-Justified Control Register */
#define I2S_SASR0 0x0C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define I2S_SAIMR 0x14 /* Serial Audio Interrupt Mask Register */
#define I2S_SAICR 0x18 /* Serial Audio Interrupt Clear Register */
#define I2S_SADR 0x80 /* Serial Audio Data Register (TX and RX FIFO access Register). */
#define SACR0_RFIFIFIRSTBIT (1 << 26) /* rx fifo first bit */
#define SACR0_TFIFOFIRSTBIT (1 << 25) /* Tx fifo first bit */
#define SACR0_CHANLOCK (1 << 24) /* Channel lock(left first or right first) */
#define SACR0_SCBIT (1 << 23) /* */
#define SACR0_BITS (1 << 22) /* I2S Bit Select(16/32 bits) */
#define SACR0_SYNCINV (1 << 21) /* SYNC Clock Invert */
#define SACR0_RFTH_MASK (0x1F << 16)
#define SACR0_RFTH(x) ((x) << 16) /* Rx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_TFTH_MASK (0X1F << 8)
#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_STRF (1 << 7) /* DAC output clk edge select */
#define SACR0_RDMAEN (1 << 6) /* RX DMA Enable */
#define SACR0_ENLBF (1 << 5) /* Enable Loopback */
#define SACR0_RST (1 << 4) /* FIFO, i2s Register Reset */
#define SACR0_TDMAEN (1 << 3) /* TX DMA Enable */
#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
#define SACR0_SYNCD (1 << 1) /* Word Select(sync) Clock Direction */
#define SACR0_ENB (1 << 0) /* Enable I2S Link */
#define SACR1_DRPL (1 << 1) /* Disable Replaying Function */
#define SACR1_DREC (1 << 0) /* Disable Recording Function */
#define SASR0_RFL(x) ((x) << 16) /* Rx FIFO Level */
#define SASR0_TFL(x) ((x) << 8) /* Tx FIFO Level */
#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
#define SASR0_BSY (1 << 2) /* I2S Busy */
#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
#define SASR0_TNF (1 << 0) /* Tx FIFO Not Full */
#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
#define SAICR_RFS (1 << 4) /* Clear Rx FIFO Service Interrupt */
#define SAICR_TFS (1 << 3) /* Clear Tx FIFO Service Interrupt */
#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
struct ark_i2s_cfg {
int master;
int rates;
int channels;
int bits;
int lfirst; //0: right channel first; 1:left channel first;
};
struct ark_i2s_data {
unsigned int base;
unsigned int nco_reg;
int id;
int clkid;
int full_duplex;
struct ark_i2s_cfg cfg[2];
struct dma_chan *dma_txch;
struct dma_chan *dma_rxch;
SemaphoreHandle_t mutex;
void *extdata;
};
int ark_i2s_init(struct ark_i2s_data *i2s, int flags);
void ark_i2s_set_volume(struct ark_i2s_data *i2s,int lvol, int rvol);
int ark_i2s_set_rate(struct ark_i2s_data *i2s, int stream, unsigned int rate);
int ark_i2s_set_params(struct ark_i2s_data *i2s, int stream, int rates, int channels, int bits);
int ark_i2s_startup(struct ark_i2s_data *i2s, int stream);
void ark_i2s_stop(struct ark_i2s_data *i2s, int stream);
#endif

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#ifndef _ITU_H
#define _ITU_H
typedef enum {
ITU_Y_UV = 0,
ITU_YUYV,
} ITU_YUV_TYPE;
typedef enum {
ITU_YUV420 = 0,
ITU_YUV422,
} ITU_OUT_FMT;
typedef struct {
int in_width;
int in_height;
int out_x;
int out_y;
int out_width;
int out_height;
int out_format;
int yuv_type;
int itu601;
} ItuConfigPara;
int itu_init(void);
int itu_config(ItuConfigPara *para);
void itu_start(void);
void itu_stop(void);
#endif

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/*
* ark_lcd.h
*
*/
#ifndef _LCD_H
#define _LCD_H
typedef enum {
LCD_OSD0 = 0,
LCD_OSD1,
LCD_OSD_NUMS,
}LCD_OSD_LAYER;
typedef enum {
LCD_OSD_FORAMT_YUV420 = 0,
LCD_OSD_FORAMT_ARGB888,
LCD_OSD_FORAMT_RGB565,
LCD_OSD_FORAMT_RGB454,
LCD_OSD_FORAMT_NUMS,
}LCD_OSD_FORMAT;
typedef enum {
LCD_OSD_Y_U_V420 = 0,
LCD_OSD_Y_UV420,
}LCD_OSD_YUV420_MODE;
typedef struct {
int x;
int y;
int width;
int height;
int format;
int stride;
unsigned int yaddr;
unsigned int uaddr;
unsigned int vaddr;
} LcdOsdInfo;
#define LCD_VIDEO_LAYER LCD_OSD0
#define LCD_UI_LAYER LCD_OSD1
/* osd layer set func */
/************************************************************/
int ark_lcd_set_osd_size(LCD_OSD_LAYER osd, uint32_t width, uint32_t height);
int ark_lcd_set_osd_format(LCD_OSD_LAYER osd, LCD_OSD_FORMAT format);
int ark_lcd_set_osd_yaddr(LCD_OSD_LAYER osd, uint32_t yaddr);
int ark_lcd_set_osd_uaddr(LCD_OSD_LAYER osd, uint32_t yaddr);
int ark_lcd_set_osd_vaddr(LCD_OSD_LAYER osd, uint32_t yaddr);
int ark_lcd_osd_enable(LCD_OSD_LAYER osd, uint8_t enable);
int ark_lcd_get_osd_enable(LCD_OSD_LAYER osd);
/* Interface with default argument value, may be you need them. If you not sure, ingore them */
int ark_lcd_set_osd_possition(LCD_OSD_LAYER osd, uint32_t h, uint32_t v);
int ark_lcd_set_osd_h_offset(LCD_OSD_LAYER osd, uint32_t offset);
int ark_lcd_osd_coeff_enable(LCD_OSD_LAYER osd, uint8_t enable);
int ark_lcd_osd_set_coeff(LCD_OSD_LAYER osd, uint32_t value);
int ark_lcd_set_osd_mult_coef(LCD_OSD_LAYER osd, uint32_t value);
int ark_lcd_set_osd_yuv420_mode(LCD_OSD_LAYER osd, LCD_OSD_YUV420_MODE mode);
int ark_lcd_get_osd_yuv420_mode(LCD_OSD_LAYER osd, LCD_OSD_YUV420_MODE *mode);
/* after calling the osd layer set func, you should call */
/* this function to flush the parameters for atom option */
int ark_lcd_set_osd_sync(LCD_OSD_LAYER osd);
/************************************************************/
int ark_lcd_get_osd_size(LCD_OSD_LAYER osd, uint32_t *width, uint32_t *height);
int ark_lcd_get_osd_format(LCD_OSD_LAYER osd, LCD_OSD_FORMAT *format);
int ark_lcd_get_osd_yaddr(LCD_OSD_LAYER osd, uint32_t *yaddr);
uint32_t ark_lcd_get_virt_addr(void);
uint8_t *ark_lcd_get_fb_addr(uint8_t index);
int ark_lcd_enable(uint8_t enable);
int ark_lcd_wait_for_vsync(void);
int ark_lcd_set_osd_info_atomic(LCD_OSD_LAYER osd, LcdOsdInfo *info);
int ark_lcd_get_osd_info_atomic_isactive(LCD_OSD_LAYER osd);
int lcd_init(void);
void lcd_uninit(void);
void Cpulcd_Init(void);
#endif

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#ifndef _MMC_H
#define _MMC_H
#include "FreeRTOS.h"
#include "mmcsd_host.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* EXT_CSD fields
*/
#define EXT_CSD_FLUSH_CACHE 32 /* W */
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
#define EXT_CSD_HPI_MGMT 161 /* R/W */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
#define EXT_CSD_BKOPS_EN 163 /* R/W */
#define EXT_CSD_BKOPS_START 164 /* W */
#define EXT_CSD_SANITIZE_START 165 /* W */
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_BOOT_WP 173 /* R/W */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_PART_CONFIG 179 /* R/W */
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_POWER_CLASS 187 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_STRUCTURE 194 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
#define EXT_CSD_TRIM_MULT 232 /* RO */
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
#define EXT_CSD_HPI_FEATURES 503 /* RO */
/*
* EXT_CSD field definitions
*/
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
#define EXT_CSD_CMD_SET_SECURE (1<<1)
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
EXT_CSD_CARD_TYPE_HS_52)
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
/* DDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
| EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
/* SDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
EXT_CSD_CARD_TYPE_HS200_1_2V)
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
EXT_CSD_CARD_TYPE_HS400_1_2V)
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
#define EXT_CSD_TIMING_HS 1 /* High speed */
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
#define EXT_CSD_SEC_ER_EN BIT(0)
#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
#define EXT_CSD_SEC_GB_CL_EN BIT(4)
#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
#define EXT_CSD_RST_N_EN_MASK 0x3
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
#define EXT_CSD_NO_POWER_NOTIFICATION 0
#define EXT_CSD_POWER_ON 1
#define EXT_CSD_POWER_OFF_SHORT 2
#define EXT_CSD_POWER_OFF_LONG 3
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
#define EXT_CSD_PACKED_EVENT_EN BIT(3)
/*
* EXCEPTION_EVENT_STATUS field
*/
#define EXT_CSD_URGENT_BKOPS BIT(0)
#define EXT_CSD_DYNCAP_NEEDED BIT(1)
#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
#define EXT_CSD_PACKED_FAILURE BIT(3)
#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0)
#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1)
/*
* BKOPS status level
*/
#define EXT_CSD_BKOPS_LEVEL_2 0x2
/*
* MMC_SWITCH access modes
*/
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
/*
* extern function
*/
int mmc_send_op_cond(struct mmcsd_host *host, uint32_t ocr, uint32_t *rocr);
int32_t init_mmc(struct mmcsd_host *host, uint32_t ocr);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _MMCSD_CARD_H
#define _MMCSD_CARD_H
#include "mmcsd_host.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SD_SCR_BUS_WIDTH_1 (1 << 0)
#define SD_SCR_BUS_WIDTH_4 (1 << 2)
struct mmcsd_cid {
uint8_t mid; /* ManufacturerID */
uint8_t prv; /* Product Revision */
uint16_t oid; /* OEM/Application ID */
uint32_t psn; /* Product Serial Number */
uint8_t pnm[5]; /* Product Name */
uint8_t reserved1;/* reserved */
uint16_t mdt; /* Manufacturing Date */
uint8_t crc; /* CID CRC */
uint8_t reserved2;/* not used, always 1 */
};
struct mmcsd_csd {
uint8_t csd_structure; /* CSD register version */
uint8_t taac;
uint8_t nsac;
uint8_t tran_speed; /* max data transfer rate */
uint16_t card_cmd_class; /* card command classes */
uint8_t rd_blk_len; /* max read data block length */
uint8_t rd_blk_part;
uint8_t wr_blk_misalign;
uint8_t rd_blk_misalign;
uint8_t dsr_imp; /* DSR implemented */
uint8_t c_size_mult; /* CSD 1.0 , device size multiplier */
uint32_t c_size; /* device size */
uint8_t r2w_factor;
uint8_t wr_blk_len; /* max wtire data block length */
uint8_t wr_blk_partial;
uint8_t csd_crc;
};
struct sd_scr {
uint8_t sd_version;
uint8_t sd_bus_widths;
};
struct sdio_cccr {
uint8_t sdio_version;
uint8_t sd_version;
uint8_t direct_cmd:1, /* Card Supports Direct Commands during data transfer
only SD mode, not used for SPI mode */
multi_block:1, /* Card Supports Multi-Block */
read_wait:1, /* Card Supports Read Wait
only SD mode, not used for SPI mode */
suspend_resume:1, /* Card supports Suspend/Resume
only SD mode, not used for SPI mode */
s4mi:1, /* generate interrupts during a 4-bit
multi-block data transfer */
e4mi:1, /* Enable the multi-block IRQ during
4-bit transfer for the SDIO card */
low_speed:1, /* Card is a Low-Speed card */
low_speed_4:1; /* 4-bit support for Low-Speed cards */
uint8_t bus_width:1, /* Support SDIO bus width, 1:4bit, 0:1bit */
cd_disable:1, /* Connect[0]/Disconnect[1] the 10K-90K ohm pull-up
resistor on CD/DAT[3] (pin 1) of the card */
power_ctrl:1, /* Support Master Power Control */
high_speed:1; /* Support High-Speed */
};
struct sdio_cis {
uint16_t manufacturer;
uint16_t product;
uint16_t func0_blk_size;
uint32_t max_tran_speed;
};
/*
* SDIO function CIS tuple (unknown to the core)
*/
struct sdio_function_tuple {
struct sdio_function_tuple *next;
uint8_t code;
uint8_t size;
uint8_t *data;
};
#define sdio_function sdio_func
struct sdio_function;
typedef void (sdio_irq_handler_t)(struct sdio_function *);
#if 0
/*
* SDIO function devices
*/
struct sdio_function {
struct mmcsd_card *card; /* the card this device belongs to */
sdio_irq_handler_t *irq_handler; /* IRQ callback */
uint8_t num; /* function number */
uint8_t func_code; /* Standard SDIO Function interface code */
uint16_t manufacturer; /* manufacturer id */
uint16_t product; /* product id */
uint32_t max_blk_size; /* maximum block size */
uint32_t cur_blk_size; /* current block size */
uint32_t enable_timeout_val; /* max enable timeout in msec */
struct sdio_function_tuple *tuples;
void *priv;
};
#endif
/*
* SDIO function devices
*/
struct sdio_func {
struct mmcsd_card *card; /* the card this device belongs to */
sdio_irq_handler_t *irq_handler; /* IRQ callback */
uint8_t num; /* function number */
uint8_t func_code; /* Standard SDIO Function interface code */
uint16_t manufacturer; /* manufacturer id */
uint16_t product; /* product id */
uint32_t max_blk_size; /* maximum block size */
uint32_t cur_blk_size; /* current block size */
uint32_t enable_timeout_val; /* max enable timeout in msec */
struct sdio_function_tuple *tuples;
void *priv;
};
#define SDIO_MAX_FUNCTIONS 7
struct mmcsd_card {
struct mmcsd_host *host;
uint32_t rca; /* card addr */
uint32_t resp_cid[4]; /* card CID register */
uint32_t resp_csd[4]; /* card CSD register */
uint32_t resp_scr[2]; /* card SCR register */
uint16_t tacc_clks; /* data access time by ns */
uint32_t tacc_ns; /* data access time by clk cycles */
uint32_t max_data_rate; /* max data transfer rate */
uint32_t card_capacity; /* card capacity, unit:KB */
uint32_t card_blksize; /* card block size */
uint32_t card_blknr; /* card block number */
uint32_t erase_size; /* erase size in sectors */
uint16_t card_type;
#define CARD_TYPE_MMC 0 /* MMC card */
#define CARD_TYPE_SD 1 /* SD card */
#define CARD_TYPE_SDIO 2 /* SDIO card */
#define CARD_TYPE_SDIO_COMBO 3 /* SD combo (IO+mem) card */
uint16_t flags;
#define CARD_FLAG_HIGHSPEED (1 << 0) /* SDIO bus speed 50MHz */
#define CARD_FLAG_SDHC (1 << 1) /* SDHC card */
#define CARD_FLAG_SDXC (1 << 2) /* SDXC card */
struct sd_scr scr;
struct mmcsd_csd csd;
uint32_t hs_max_data_rate; /* max data transfer rate in high speed mode */
uint8_t sdio_function_num; /* totol number of SDIO functions */
struct sdio_cccr cccr; /* common card info */
struct sdio_cis cis; /* common tuple info */
struct sdio_function *sdio_function[SDIO_MAX_FUNCTIONS + 1]; /* SDIO functions (devices) */
};
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _MMSCD_CMD_H
#define _MMSCD_CMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* class 1 */
#define GO_IDLE_STATE 0 /* bc */
#define SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
#define ALL_SEND_CID 2 /* bcr R2 */
#define SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
#define SET_DSR 4 /* bc [31:16] RCA */
#define SWITCH 6 /* ac [31:0] See below R1b */
#define SELECT_CARD 7 /* ac [31:16] RCA R1 */
#define SEND_EXT_CSD 8 /* adtc R1 */
#define SEND_CSD 9 /* ac [31:16] RCA R2 */
#define SEND_CID 10 /* ac [31:16] RCA R2 */
#define READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
#define STOP_TRANSMISSION 12 /* ac R1b */
#define SEND_STATUS 13 /* ac [31:16] RCA R1 */
#define GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
#define SPI_READ_OCR 58 /* spi spi_R3 */
#define SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
/* class 2 */
#define SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
/* class 3 */
#define WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
/* class 4 */
#define SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
#define WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
#define WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
#define PROGRAM_CID 26 /* adtc R1 */
#define PROGRAM_CSD 27 /* adtc R1 */
/* class 6 */
#define SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
#define CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
#define SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
/* class 5 */
#define ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
#define ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
#define ERASE 38 /* ac R1b */
/* class 9 */
#define FAST_IO 39 /* ac <Complex> R4 */
#define GO_IRQ_STATE 40 /* bcr R5 */
/* class 7 */
#define LOCK_UNLOCK 42 /* adtc R1b */
/* class 8 */
#define APP_CMD 55 /* ac [31:16] RCA R1 */
#define GEN_CMD 56 /* adtc [0] RD/WR R1 */
/* SD commands type argument response */
/* class 0 */
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
/* class 10 */
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
/* Application commands */
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SD_APP_SEND_SCR 51 /* adtc R1 */
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */
/* SDIO commands type argument response */
#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
#define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
#define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
/* CMD52 arguments */
#define SDIO_ARG_CMD52_READ (0<<31)
#define SDIO_ARG_CMD52_WRITE (1u<<31)
#define SDIO_ARG_CMD52_FUNC_SHIFT 28
#define SDIO_ARG_CMD52_FUNC_MASK 0x7
#define SDIO_ARG_CMD52_RAW_FLAG (1u<<27)
#define SDIO_ARG_CMD52_REG_SHIFT 9
#define SDIO_ARG_CMD52_REG_MASK 0x1ffff
#define SDIO_ARG_CMD52_DATA_SHIFT 0
#define SDIO_ARG_CMD52_DATA_MASK 0xff
#define SDIO_R5_DATA(resp) ((resp)[0] & 0xff)
/* CMD53 arguments */
#define SDIO_ARG_CMD53_READ (0<<31)
#define SDIO_ARG_CMD53_WRITE (1u<<31)
#define SDIO_ARG_CMD53_FUNC_SHIFT 28
#define SDIO_ARG_CMD53_FUNC_MASK 0x7
#define SDIO_ARG_CMD53_BLOCK_MODE (1u<<27)
#define SDIO_ARG_CMD53_INCREMENT (1u<<26)
#define SDIO_ARG_CMD53_REG_SHIFT 9
#define SDIO_ARG_CMD53_REG_MASK 0x1ffff
#define SDIO_ARG_CMD53_LENGTH_SHIFT 0
#define SDIO_ARG_CMD53_LENGTH_MASK 0x1ff
#define SDIO_ARG_CMD53_LENGTH_MAX 511
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _MMCSD_CORE_H
#define _MMCSD_CORE_H
#include "FreeRTOS.h"
#include "mmcsd_host.h"
#include "mmcsd_card.h"
#include "mmcsd_cmd.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef MMCSD_DBG
#define mmcsd_dbg(fmt, ...) printf(fmt, ##__VA_ARGS__)
#else
#define mmcsd_dbg(fmt, ...)
#endif
struct mmcsd_data {
uint32_t blksize;
uint32_t blks;
uint32_t *buf;
int32_t err;
uint32_t flags;
#define DATA_DIR_WRITE (1 << 0)
#define DATA_DIR_READ (1 << 1)
#define DATA_STREAM (1 << 2)
unsigned int bytes_xfered;
struct mmcsd_cmd *stop; /* stop command */
struct mmcsd_req *mrq; /* associated request */
uint32_t timeout_ns;
uint32_t timeout_clks;
};
struct mmcsd_cmd {
uint32_t cmd_code;
uint32_t arg;
uint32_t resp[4];
uint32_t flags;
/*rsponse types
*bits:0~3
*/
#define RESP_MASK (0xF)
#define RESP_NONE (0)
#define RESP_R1 (1 << 0)
#define RESP_R1B (2 << 0)
#define RESP_R2 (3 << 0)
#define RESP_R3 (4 << 0)
#define RESP_R4 (5 << 0)
#define RESP_R6 (6 << 0)
#define RESP_R7 (7 << 0)
#define RESP_R5 (8 << 0) /*SDIO command response type*/
/*command types
*bits:4~5
*/
#define CMD_MASK (3 << 4) /* command type */
#define CMD_AC (0 << 4)
#define CMD_ADTC (1 << 4)
#define CMD_BC (2 << 4)
#define CMD_BCR (3 << 4)
#define resp_type(cmd) ((cmd)->flags & RESP_MASK)
/*spi rsponse types
*bits:6~8
*/
#define RESP_SPI_MASK (0x7 << 6)
#define RESP_SPI_R1 (1 << 6)
#define RESP_SPI_R1B (2 << 6)
#define RESP_SPI_R2 (3 << 6)
#define RESP_SPI_R3 (4 << 6)
#define RESP_SPI_R4 (5 << 6)
#define RESP_SPI_R5 (6 << 6)
#define RESP_SPI_R7 (7 << 6)
#define spi_resp_type(cmd) ((cmd)->flags & RESP_SPI_MASK)
/*
* These are the command types.
*/
#define cmd_type(cmd) ((cmd)->flags & CMD_MASK)
int32_t retries; /* max number of retries */
int32_t err;
struct mmcsd_data *data;
struct mmcsd_req *mrq; /* associated request */
};
struct mmcsd_req {
struct mmcsd_data *data;
struct mmcsd_cmd *cmd;
struct mmcsd_cmd *stop;
};
/*the following is response bit*/
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
#define R1_CC_ERROR (1 << 20) /* erx, c */
#define R1_ERROR (1 << 19) /* erx, c */
#define R1_UNDERRUN (1 << 18) /* ex, c */
#define R1_OVERRUN (1 << 17) /* ex, c */
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
#define R1_ERASE_RESET (1 << 13) /* sr, c */
#define R1_STATUS(x) (x & 0xFFFFE000)
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
#define R1_APP_CMD (1 << 5) /* sr, c */
#define R1_SPI_IDLE (1 << 0)
#define R1_SPI_ERASE_RESET (1 << 1)
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
#define R1_SPI_COM_CRC (1 << 3)
#define R1_SPI_ERASE_SEQ (1 << 4)
#define R1_SPI_ADDRESS (1 << 5)
#define R1_SPI_PARAMETER (1 << 6)
/* R1 bit 7 is always zero */
#define R2_SPI_CARD_LOCKED (1 << 8)
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
#define R2_SPI_ERROR (1 << 10)
#define R2_SPI_CC_ERROR (1 << 11)
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
#define R2_SPI_WP_VIOLATION (1 << 13)
#define R2_SPI_ERASE_PARAM (1 << 14)
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
#define CARD_BUSY 0x80000000 /* Card Power up status bit */
/* R5 response bits */
#define R5_COM_CRC_ERROR (1 << 15)
#define R5_ILLEGAL_COMMAND (1 << 14)
#define R5_ERROR (1 << 11)
#define R5_FUNCTION_NUMBER (1 << 9)
#define R5_OUT_OF_RANGE (1 << 8)
#define R5_STATUS(x) (x & 0xCB00)
#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12)
#define MMCSD_HOST_PLUGED 0
#define MMCSD_HOST_UNPLUGED 1
int mmcsd_wait_cd_changed(uint32_t timeout);
int mmcsd_wait_sdio_ready(int32_t timeout);
void mmcsd_host_lock(struct mmcsd_host *host);
void mmcsd_host_unlock(struct mmcsd_host *host);
void mmcsd_req_complete(struct mmcsd_host *host);
void mmcsd_send_request(struct mmcsd_host *host, struct mmcsd_req *req);
int32_t mmcsd_send_cmd(struct mmcsd_host *host, struct mmcsd_cmd *cmd, int retries);
int32_t mmcsd_go_idle(struct mmcsd_host *host);
int32_t mmcsd_spi_read_ocr(struct mmcsd_host *host, int32_t high_capacity, uint32_t *ocr);
int32_t mmcsd_all_get_cid(struct mmcsd_host *host, uint32_t *cid);
int32_t mmcsd_get_cid(struct mmcsd_host *host, uint32_t *cid);
int32_t mmcsd_get_csd(struct mmcsd_card *card, uint32_t *csd);
int32_t mmcsd_select_card(struct mmcsd_card *card);
int32_t mmcsd_deselect_cards(struct mmcsd_card *host);
int32_t mmcsd_spi_use_crc(struct mmcsd_host *host, int32_t use_crc);
void mmcsd_set_chip_select(struct mmcsd_host *host, int32_t mode);
void mmcsd_set_clock(struct mmcsd_host *host, uint32_t clk);
void mmcsd_set_bus_mode(struct mmcsd_host *host, uint32_t mode);
void mmcsd_set_bus_width(struct mmcsd_host *host, uint32_t width);
void mmcsd_set_data_timeout(struct mmcsd_data *data, const struct mmcsd_card *card);
uint32_t mmcsd_select_voltage(struct mmcsd_host *host, uint32_t ocr);
void mmcsd_change(struct mmcsd_host *host);
void mmcsd_change_from_isr(struct mmcsd_host *host);
void mmcsd_detect(void *param);
struct mmcsd_host *mmcsd_alloc_host(void);
void mmcsd_free_host(struct mmcsd_host *host);
int mmcsd_core_init(void);
int mmcsd_blk_init(void);
int32_t mmcsd_num_wr_blocks(struct mmcsd_card *card);
int mmcsd_req_blk(struct mmcsd_card *card, uint32_t sector, void *buf, size_t blks, uint8_t dir);
int32_t mmcsd_set_blksize(struct mmcsd_card *card);
struct mmcsd_card *mmcsd_get_sdmmc_card_info(void);
int mmcsd_wait_mmc_ready(uint32_t timeout);
#if DEVICE_TYPE_SELECT == EMMC_FLASH
int emmc_read(uint32_t offset, size_t size, uint8_t *data);
int emmc_write(uint32_t offset, size_t size, uint8_t *data);
#endif
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _MMCSD_HOST_H
#define _MMCSD_HOST_H
#include "FreeRTOS.h"
#include "semphr.h"
#include "task.h"
#ifdef __cplusplus
extern "C" {
#endif
struct mmcsd_io_cfg {
uint32_t clock; /* clock rate */
uint16_t vdd;
/* vdd stores the bit number of the selected voltage range from below. */
uint8_t bus_mode; /* command output mode */
#define MMCSD_BUSMODE_OPENDRAIN 1
#define MMCSD_BUSMODE_PUSHPULL 2
uint8_t chip_select; /* SPI chip select */
#define MMCSD_CS_IGNORE 0
#define MMCSD_CS_HIGH 1
#define MMCSD_CS_LOW 2
uint8_t power_mode; /* power supply mode */
#define MMCSD_POWER_OFF 0
#define MMCSD_POWER_UP 1
#define MMCSD_POWER_ON 2
uint8_t bus_width; /* data bus width */
#define MMCSD_BUS_WIDTH_1 0
#define MMCSD_BUS_WIDTH_4 2
#define MMCSD_BUS_WIDTH_8 3
};
struct mmcsd_host;
struct mmcsd_req;
struct mmcsd_host_ops {
void (*request)(struct mmcsd_host *host, struct mmcsd_req *req);
void (*set_iocfg)(struct mmcsd_host *host, struct mmcsd_io_cfg *io_cfg);
int32_t (*get_card_status)(struct mmcsd_host *host);
void (*enable_sdio_irq)(struct mmcsd_host *host, int32_t en);
};
struct mmcsd_host {
struct mmcsd_card *card;
const struct mmcsd_host_ops *ops;
uint32_t freq_min;
uint32_t freq_max;
struct mmcsd_io_cfg io_cfg;
uint32_t valid_ocr; /* current valid OCR */
#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */
#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */
#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */
#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */
#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */
#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */
#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */
#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */
#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */
#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */
#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */
#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */
#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */
#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */
#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */
#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */
uint32_t flags; /* define device capabilities */
#define MMCSD_BUSWIDTH_4 (1 << 0)
#define MMCSD_BUSWIDTH_8 (1 << 1)
#define MMCSD_MUTBLKWRITE (1 << 2)
#define MMCSD_HOST_IS_SPI (1 << 3)
#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI)
#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */
#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed */
uint32_t max_seg_size; /* maximum size of one dma segment */
uint32_t max_dma_segs; /* maximum number of dma segments in one request */
uint32_t max_blk_size; /* maximum block size */
uint32_t max_blk_count; /* maximum block count */
uint32_t spi_use_crc;
SemaphoreHandle_t bus_lock;
SemaphoreHandle_t sem_ack;
uint32_t sdio_irq_num;
SemaphoreHandle_t sdio_irq_sem;
TaskHandle_t sdio_irq_thread;
uint8_t transfer_err;
void *private_data;
};
static inline void mmcsd_delay_ms(uint32_t ms)
{
if (ms < 1000 / configTICK_RATE_HZ)
{
vTaskDelay(1);
}
else
{
vTaskDelay(ms/(1000 / configTICK_RATE_HZ));
}
}
#ifdef __cplusplus
}
#endif
#endif

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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
#ifndef _MMU_
#define _MMU_
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "../cp15/cp15.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
extern void MMU_Initialize(unsigned int *pTB);
extern void dma_flush_range(unsigned int ulStart, unsigned int ulEnd);
extern void dma_inv_range (unsigned int ulStart, unsigned int ulEnd);
extern void dma_clean_range(unsigned int ulStart, unsigned int ulEnd);
#define PHY_TO_VIRT(x) ((x))
#define VIRT_TO_PHY(x) ((x))
#define PHY_TO_UNCACHED_VIRT(x) ((unsigned int)(x) + 0x10000000UL)
#define UNCACHED_VIRT_TO_PHT(x) ((unsigned int)(x) - 0x10000000UL)
#endif /* #ifndef _MMU_ */

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#ifndef _PINCTRL_H
#define _PINCTRL_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PGRP_I2C0,
PGRP_I2C1,
PGRP_LCD_TTL_CH0,
PGRP_LCD_TTL_CH1,
PGRP_LCD_LVDS,
PGRP_LCD_SRGB,
PGRP_LCD_ITU601,
PGRP_UART0,
PGRP_UART1,
PGRP_UART2,
PGRP_UART3,
PGRP_SPI0,
PGRP_SPI1,
PGRP_PWM0,
PGRP_PWM1,
PGRP_PWM2,
PGRP_PWM3,
PGRP_PWM0_IN,
PGRP_PWM1_IN,
PGRP_PWM2_IN,
PGRP_PWM3_IN,
PGRP_SDMMC0,
PGRP_ITU_CH0,
PGRP_ITU_CH0_INV,
PGRP_ITU_CH1,
PGRP_ITU_CH1_INV,
PGRP_CAN0_CH0,
PGRP_CAN0_CH1,
PGRP_CAN0_CH2,
PGRP_CAN1_CH0,
PGRP_CAN1_CH1,
PGRP_CAN1_CH2,
PGRP_I2S0_PLAY,
PGRP_I2S0_RECORD,
PGRP_I2S1_PLAY,
PGRP_I2S1_RECORD,
PGRP_RCRT,
}ePingroupID;
typedef enum {
PAD_DRIVE_DEFAULT,
PAD_DRIVE_2MA,
PAD_DRIVE_4MA,
PAD_DRIVE_8MA,
PAD_DRIVE_12MA,
}ePadDrive;
void vPinctrlSetup(void);
void pinctrl_gpio_request(int gpio);
void pinctrl_set_group(int groupid);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _PWM_H
#define _PWM_H
typedef enum {
PWM_ID0 = 0,
PWM_ID1,
PWM_ID2,
PWM_ID3
} PWM_ID;
int pwm_config(int id, uint32_t duty_ns, uint32_t period_ns);
void pwm_enable(int id);
void pwm_disable(int id);
//240719 lj
void pwn_update_brightness(uint32_t duty_ns);
#endif

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#ifndef PWM_CAP_H_
#define PWM_CAP_H_
void pwm_Initial_Cap(UINT8 id);
double pwm_getCapVal(UINT8 id);
void pwm_enableCapIRQ(UINT8 id,UINT8 en);
double pwm_getCapVal(UINT8 id);
void pwm_cap_Int_Handler(void *para);
extern double capdata[125];
#define PWM_CAP_TIMES 1
#define PWM_CAP_INTERVAL 1//64
#define PWM_CAP_GLITCH 0x7//0xF
#define PWM_CAP_ENABLE 1
typedef enum{
PWM_CAP_CH0 = 0,
PWM_CAP_CH1,
PWM_CAP_CH2,
PWM_CAP_CH3,
}PWM_CAP_CH;
typedef enum{
PWM_CAP_NUM = 0,
PWM_CAP_EXIT,
}PWM_CAP_METHOD;
typedef enum{
PWM_CAP_UINT_1MS = 0,
PWM_CAP_UINT_10MS,
PWM_CAP_UINT_100MS,
PWM_CAP_UINT_1000MS = 4,
}PWM_CAP_BASED_UINT;
typedef enum{
PWM_CAP_NO_INT = 0,
PWM_CAP_ONCE_INT,
PWM_CAP_ONCE_FINISH_INT,
PWM_CAP_FINISH_ALL,
}PWM_CAP_INT_METHOD;
#endif

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#ifndef _PXP_H
#define _PXP_H
typedef enum {
PXP_SRC_FMT_ARGB8888 = 0x0, /* 32-bit pixels */
PXP_SRC_FMT_RGB888 = 0x1, /* 32-bit pixels (unpacked 24-bit format) */
PXP_SRC_FMT_RGB565 = 0x4, /* 16-bit pixels */
PXP_SRC_FMT_RGB555 = 0x5, /* 16-bit pixels */
PXP_SRC_FMT_YUV422 = 0x8, /* 16-bit pixels */
PXP_SRC_FMT_YUV420 = 0x9, /* 16-bit pixels */
PXP_SRC_FMT_UYVY1P422 = 0xa, /* 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
PXP_SRC_FMT_VYUY1P422 = 0xb, /* 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
PXP_SRC_FMT_YUV2P422 = 0xc, /* 16-bit pixels (2-plane UV interleaved bytes) */
PXP_SRC_FMT_YUV2P420 = 0xd, /* 16-bit pixels */
PXP_SRC_FMT_YVU2P422 = 0xe, /* 16-bit pixels (2-plane VU interleaved bytes) */
PXP_SRC_FMT_YVU2P420 = 0xf, /* 16-bit pixels */
} PXP_SRC_FMT;
typedef enum {
PXP_OUT_FMT_ARGB8888 = 0x0, /* 32-bit pixels */
PXP_OUT_FMT_RGB888 = 0x1, /* 32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) */
PXP_OUT_FMT_RGB888P = 0x2, /* 24-bit pixels (packed 24-bit format) */
PXP_OUT_FMT_ARGB1555 = 0x3, /* 16-bit pixels */
PXP_OUT_FMT_RGB565 = 0x4, /* 16-bit pixels */
PXP_OUT_FMT_RGB555 = 0x5, /* 16-bit pixels */
PXP_OUT_FMT_YUV444 = 0x7, /* 32-bit pixels (1-plane XYUV unpacked) */
PXP_OUT_FMT_UYVY1P422 = 0xa, /* 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
PXP_OUT_FMT_VYUY1P422 = 0xb, /* 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
PXP_OUT_FMT_YUV2P422 = 0xc, /* 16-bit pixels (2-plane UV interleaved bytes) */
PXP_OUT_FMT_YUV2P420 = 0xd, /* 16-bit pixels (2-plane VU) */
PXP_OUT_FMT_YVU2P422 = 0xe, /* 16-bit pixels (2-plane VU interleaved bytes) */
PXP_OUT_FMT_YVU2P420 = 0xf, /* 16-bit pixels (2-plane VU) */
} PXP_OUT_FMT;
/* clockwise rotate */
typedef enum {
PXP_ROTATE_0 = 0,
PXP_ROTATE_90 = 1,
PXP_ROTATE_180 = 2,
PXP_ROTATE_270 = 3,
} PXP_ROTATE;
int pxp_init(void);
int pxp_scaler_rotate(uint32_t s0buf, uint32_t s0ubuf, uint32_t s0vbuf,
int s0format, uint32_t s0width, uint32_t s0height,
uint32_t outbuf, uint32_t outbuf2, int outformat,
uint32_t outwidth, uint32_t outheight, int outangle);
int pxp_rotate(uint32_t s0buf, uint32_t s0ubuf, uint32_t s0vbuf,
int s0format, uint32_t s0width, uint32_t s0height,
uint32_t outbuf, uint32_t outbuf2, int outformat,
int outangle);
#endif

5
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#ifndef _REMOTE_H
#define _REMOTE_H
void RemoteKeyInit(void);
#endif

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#ifndef _RTC_H
#define _RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* The struct used to pass data via the following ioctl. Similar to the
* struct tm in <time.h>, but it needs to be here so that the kernel
* source is self contained, allowing cross-compiles, etc. etc.
*/
typedef struct rtc_time {
int tm_sec;
int tm_min;
int tm_hour;
int tm_mday;
int tm_mon;
int tm_year;
int tm_wday;
int tm_yday;
} SystemTime_t;
/*
* This data structure is inspired by the EFI (v0.92) wakeup
* alarm API.
*/
struct rtc_wkalrm {
unsigned char enabled; /* 0 = alarm disabled, 1 = alarm enabled */
unsigned char pending; /* 0 = alarm not pending, 1 = alarm pending */
struct rtc_time time; /* time the alarm is set to */
};
static inline int is_leap_year(unsigned int year)
{
return (!(year % 4) && (year % 100)) || !(year % 400);
}
int rtc_init(void);
int iGetLocalTime(SystemTime_t *tm);
void vSetLocalTime(SystemTime_t *tm);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _SD_H
#define _SD_H
#include "FreeRTOS.h"
#include "mmcsd_host.h"
#ifdef __cplusplus
extern "C" {
#endif
int mmcsd_send_if_cond(struct mmcsd_host *host, uint32_t ocr);
int mmcsd_send_app_op_cond(struct mmcsd_host *host, uint32_t ocr, uint32_t *rocr);
int mmcsd_get_card_addr(struct mmcsd_host *host, uint32_t *rca);
int32_t mmcsd_get_scr(struct mmcsd_card *card, uint32_t *scr);
int32_t init_sd(struct mmcsd_host *host, uint32_t ocr);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _SDIO_H
#define _SDIO_H
#include "FreeRTOS.h"
#include "mmcsd_host.h"
#include "mmcsd_card.h"
#include "sdio_func_ids.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Card Common Control Registers (CCCR)
*/
#define SDIO_REG_CCCR_CCCR_REV 0x00
#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
#define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 2.00 */
#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
#define SDIO_REG_CCCR_SD_REV 0x01
#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
#define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
#define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
#define SDIO_REG_CCCR_IO_EN 0x02
#define SDIO_REG_CCCR_IO_RDY 0x03
#define SDIO_REG_CCCR_INT_EN 0x04 /* Function/Master Interrupt Enable */
#define SDIO_REG_CCCR_INT_PEND 0x05 /* Function Interrupt Pending */
#define SDIO_REG_CCCR_IO_ABORT 0x06 /* function abort/card reset */
#define SDIO_REG_CCCR_BUS_IF 0x07 /* bus interface controls */
#define SDIO_BUS_WIDTH_1BIT 0x00
#define SDIO_BUS_WIDTH_4BIT 0x02
#define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */
#define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */
#define SDIO_BUS_ASYNC_INT 0x20
#define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
#define SDIO_REG_CCCR_CARD_CAPS 0x08
#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
#define SDIO_REG_CCCR_CIS_PTR 0x09 /* common CIS pointer (3 bytes) */
/* Following 4 regs are valid only if SBS is set */
#define SDIO_REG_CCCR_BUS_SUSPEND 0x0c
#define SDIO_REG_CCCR_FUNC_SEL 0x0d
#define SDIO_REG_CCCR_EXEC_FLAG 0x0e
#define SDIO_REG_CCCR_READY_FLAG 0x0f
#define SDIO_REG_CCCR_FN0_BLKSIZE 0x10 /* 2bytes, 0x10~0x11 */
#define SDIO_REG_CCCR_POWER_CTRL 0x12
#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
#define SDIO_REG_CCCR_SPEED 0x13
#define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
#define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */
/*
* Function Basic Registers (FBR)
*/
#define SDIO_REG_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
#define SDIO_REG_FBR_STD_FUNC_IF 0x00
#define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
#define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
#define SDIO_REG_FBR_STD_IF_EXT 0x01
#define SDIO_REG_FBR_POWER 0x02
#define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
#define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
#define SDIO_REG_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
#define SDIO_REG_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
#define SDIO_REG_FBR_CSA_DATA 0x0F
#define SDIO_REG_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
/* SDIO CIS Tuple code */
#define CISTPL_NULL 0x00
#define CISTPL_CHECKSUM 0x10
#define CISTPL_VERS_1 0x15
#define CISTPL_ALTSTR 0x16
#define CISTPL_MANFID 0x20
#define CISTPL_FUNCID 0x21
#define CISTPL_FUNCE 0x22
#define CISTPL_SDIO_STD 0x91
#define CISTPL_SDIO_EXT 0x92
#define CISTPL_END 0xff
/* SDIO device id */
#define SDIO_ANY_FUNC_ID 0xff
#define SDIO_ANY_MAN_ID 0xffff
#define SDIO_ANY_PROD_ID 0xffff
struct sdio_device_id
{
uint8_t func_code;
uint16_t manufacturer;
uint16_t product;
};
struct sdio_driver_t
{
char *name;
int32_t (*probe)(struct mmcsd_card *card);
int32_t (*remove)(struct mmcsd_card *card);
struct sdio_device_id *id;
};
int32_t sdio_io_send_op_cond(struct mmcsd_host *host,
uint32_t ocr,
uint32_t *cmd5_resp);
int32_t sdio_io_rw_direct(struct mmcsd_card *card,
int32_t rw,
uint32_t fn,
uint32_t reg_addr,
uint8_t *pdata,
uint8_t raw);
int32_t sdio_io_rw_extended(struct mmcsd_card *card,
int32_t rw,
uint32_t fn,
uint32_t addr,
int32_t op_code,
uint8_t *buf,
uint32_t blocks,
uint32_t blksize);
int32_t sdio_io_rw_extended_block(struct sdio_function *func,
int32_t rw,
uint32_t addr,
int32_t op_code,
uint8_t *buf,
uint32_t len);
uint8_t sdio_io_readb(struct sdio_function *func,
uint32_t reg,
int32_t *err);
int32_t sdio_io_writeb(struct sdio_function *func,
uint32_t reg,
uint8_t data);
uint16_t sdio_io_readw(struct sdio_function *func,
uint32_t addr,
int32_t *err);
int32_t sdio_io_writew(struct sdio_function *func,
uint16_t data,
uint32_t addr);
uint32_t sdio_io_readl(struct sdio_function *func,
uint32_t addr,
int32_t *err);
int32_t sdio_io_writel(struct sdio_function *func,
uint32_t data,
uint32_t addr);
int32_t sdio_io_read_multi_fifo_b(struct sdio_function *func,
uint32_t addr,
uint8_t *buf,
uint32_t len);
int32_t sdio_io_write_multi_fifo_b(struct sdio_function *func,
uint32_t addr,
uint8_t *buf,
uint32_t len);
int32_t sdio_io_read_multi_incr_b(struct sdio_function *func,
uint32_t addr,
uint8_t *buf,
uint32_t len);
int32_t sdio_io_write_multi_incr_b(struct sdio_function *func,
uint32_t addr,
uint8_t *buf,
uint32_t len);
int32_t init_sdio(struct mmcsd_host *host, uint32_t ocr);
int32_t sdio_attach_irq(struct sdio_function *func,
sdio_irq_handler_t *handler);
int32_t sdio_detach_irq(struct sdio_function *func);
void sdio_irq_wakeup(struct mmcsd_host *host);
void sdio_irq_wakeup_isr(struct mmcsd_host *host);
int32_t sdio_enable_func(struct sdio_function *func);
int32_t sdio_disable_func(struct sdio_function *func);
void sdio_set_drvdata(struct sdio_function *func, void *data);
void* sdio_get_drvdata(struct sdio_function *func);
int32_t sdio_set_block_size(struct sdio_function *func,
uint32_t blksize);
int32_t sdio_register_driver(struct sdio_driver_t *driver);
int32_t sdio_unregister_driver(struct sdio_driver_t *driver);
void sdio_init(void);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _SDIO_FUNC_IDS_H
#define _SDIO_FUNC_IDS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Standard SDIO Function Interfaces */
#define SDIO_FUNC_CODE_NONE 0x00 /* Not a SDIO standard interface */
#define SDIO_FUNC_CODE_UART 0x01 /* SDIO Standard UART */
#define SDIO_FUNC_CODE_BT_A 0x02 /* SDIO Type-A for Bluetooth standard interface */
#define SDIO_FUNC_CODE_BT_B 0x03 /* SDIO Type-B for Bluetooth standard interface */
#define SDIO_FUNC_CODE_GPS 0x04 /* SDIO GPS standard interface */
#define SDIO_FUNC_CODE_CAMERA 0x05 /* SDIO Camera standard interface */
#define SDIO_FUNC_CODE_PHS 0x06 /* SDIO PHS standard interface */
#define SDIO_FUNC_CODE_WLAN 0x07 /* SDIO WLAN interface */
#define SDIO_FUNC_CODE_ATA 0x08 /* Embedded SDIO-ATA standard interface */
/* manufacturer id, product io */
#define SDIO_MANUFACTURER_ID_MARVELL 0x02df
#define SDIO_PRODUCT_ID_MARVELL_88W8686 0x9103
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _SDMMC_H
#define _SDMMC_H
#define MMC_FEQ_MIN 400000
#define MMC_FEQ_MAX 25000000
#define CARD_UNPLUGED 1
#define CARD_PLUGED 0
enum {
TRANS_MODE_PIO = 0,
TRANS_MODE_IDMAC,
TRANS_MODE_EDMAC
};
struct dw_mci_dma_slave {
struct dma_chan *ch;
enum dma_transfer_direction direction;
};
#define SDMMC_CTRL 0x000
#define SDMMC_PWREN 0x004
#define SDMMC_CLKDIV 0x008
#define SDMMC_CLKSRC 0x00c
#define SDMMC_CLKENA 0x010
#define SDMMC_TMOUT 0x014
#define SDMMC_CTYPE 0x018
#define SDMMC_BLKSIZ 0x01c
#define SDMMC_BYTCNT 0x020
#define SDMMC_INTMASK 0x024
#define SDMMC_CMDARG 0x028
#define SDMMC_CMD 0x02c
#define SDMMC_RESP0 0x030
#define SDMMC_RESP1 0x034
#define SDMMC_RESP2 0x038
#define SDMMC_RESP3 0x03c
#define SDMMC_MINTSTS 0x040
#define SDMMC_RINTSTS 0x044
#define SDMMC_STATUS 0x048
#define SDMMC_FIFOTH 0x04c
#define SDMMC_CDETECT 0x050
#define SDMMC_WRTPRT 0x054
#define SDMMC_GPIO 0x058
#define SDMMC_TCBCNT 0x05c
#define SDMMC_TBBCNT 0x060
#define SDMMC_DEBNCE 0x064
#define SDMMC_USRID 0x068
#define SDMMC_VERID 0x06c
#define SDMMC_HCON 0x070
#define SDMMC_UHS_REG 0x074
#define SDMMC_RST_N 0x078
#define SDMMC_BMOD 0x080
#define SDMMC_PLDMND 0x084
#define SDMMC_DBADDR 0x088
#define SDMMC_IDSTS 0x08c
#define SDMMC_IDINTEN 0x090
#define SDMMC_DSCADDR 0x094
#define SDMMC_BUFADDR 0x098
#define SDMMC_FIFO 0x100
#define SDMMC_DATA(x) (x)
#define SDMMC_FIFO_DEPTH 32
/* Control register defines */
#define SDMMC_CTRL_USE_IDMAC BIT(25)
#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
#define SDMMC_CTRL_SEND_CCSD BIT(9)
#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
#define SDMMC_CTRL_READ_WAIT BIT(6)
#define SDMMC_CTRL_DMA_ENABLE BIT(5)
#define SDMMC_CTRL_INT_ENABLE BIT(4)
#define SDMMC_CTRL_DMA_RESET BIT(2)
#define SDMMC_CTRL_FIFO_RESET BIT(1)
#define SDMMC_CTRL_RESET BIT(0)
/* Clock Enable register defines */
#define SDMMC_CLKEN_LOW_PWR BIT(16)
#define SDMMC_CLKEN_ENABLE BIT(0)
/* time-out register defines */
#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
#define SDMMC_TMOUT_RESP_MSK 0xFF
/* card-type register defines */
#define SDMMC_CTYPE_8BIT BIT(16)
#define SDMMC_CTYPE_4BIT BIT(0)
#define SDMMC_CTYPE_1BIT 0
/* Interrupt status & mask register defines */
#define SDMMC_INT_SDIO BIT(16)
#define SDMMC_INT_EBE BIT(15)
#define SDMMC_INT_ACD BIT(14)
#define SDMMC_INT_SBE BIT(13)
#define SDMMC_INT_HLE BIT(12)
#define SDMMC_INT_FRUN BIT(11)
#define SDMMC_INT_HTO BIT(10)
#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
#define SDMMC_INT_DRTO BIT(9)
#define SDMMC_INT_RTO BIT(8)
#define SDMMC_INT_DCRC BIT(7)
#define SDMMC_INT_RCRC BIT(6)
#define SDMMC_INT_RXDR BIT(5)
#define SDMMC_INT_TXDR BIT(4)
#define SDMMC_INT_DATA_OVER BIT(3)
#define SDMMC_INT_CMD_DONE BIT(2)
#define SDMMC_INT_RESP_ERR BIT(1)
#define SDMMC_INT_CD BIT(0)
#define SDMMC_INT_ALL (~0)
#define SDMMC_INT_DATA_ERROR (SDMMC_INT_DCRC | SDMMC_INT_SBE | SDMMC_INT_EBE)
#define SDMMC_INT_STATUS_DATA (SDMMC_INT_DATA_OVER | SDMMC_INT_DATA_ERROR \
| SDMMC_INT_TXDR | SDMMC_INT_RXDR)
/* Common flag combinations */
#define SDMMC_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
SDMMC_INT_HTO | SDMMC_INT_SBE | \
SDMMC_INT_EBE | SDMMC_INT_HLE)
#define SDMMC_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
#define SDMMC_ERROR_FLAGS (SDMMC_DATA_ERROR_FLAGS | \
SDMMC_CMD_ERROR_FLAGS)
#define SDMMC_INT_ERROR 0xbfc2
/* Command register defines */
#define SDMMC_CMD_START BIT(31)
#define SDMMC_CMD_USE_HOLD_REG BIT(29)
#define SDMMC_CMD_VOLT_SWITCH BIT(28)
#define SDMMC_CMD_CCS_EXP BIT(23)
#define SDMMC_CMD_CEATA_RD BIT(22)
#define SDMMC_CMD_UPD_CLK BIT(21)
#define SDMMC_CMD_INIT BIT(15)
#define SDMMC_CMD_STOP BIT(14)
#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
#define SDMMC_CMD_SEND_STOP BIT(12)
#define SDMMC_CMD_STRM_MODE BIT(11)
#define SDMMC_CMD_DAT_WR BIT(10)
#define SDMMC_CMD_DAT_EXP BIT(9)
#define SDMMC_CMD_RESP_CRC BIT(8)
#define SDMMC_CMD_RESP_LONG BIT(7)
#define SDMMC_CMD_RESP_EXP BIT(6)
#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
/* Status register defines */
#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
#define SDMMC_STATUS_DMA_REQ BIT(31)
#define SDMMC_STATUS_BUSY BIT(9)
/* FIFOTH register defines */
#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
((r) & 0xFFF) << 16 | \
((t) & 0xFFF))
/* HCON register defines */
#define DMA_INTERFACE_IDMA (0x0)
#define DMA_INTERFACE_DWDMA (0x1)
#define DMA_INTERFACE_GDMA (0x2)
#define DMA_INTERFACE_NODMA (0x3)
#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
/* Internal DMAC interrupt defines */
#define SDMMC_IDMAC_INT_AI BIT(9)
#define SDMMC_IDMAC_INT_NI BIT(8)
#define SDMMC_IDMAC_INT_CES BIT(5)
#define SDMMC_IDMAC_INT_DU BIT(4)
#define SDMMC_IDMAC_INT_FBE BIT(2)
#define SDMMC_IDMAC_INT_RI BIT(1)
#define SDMMC_IDMAC_INT_TI BIT(0)
/* Internal DMAC bus mode bits */
#define SDMMC_IDMAC_ENABLE BIT(7)
#define SDMMC_IDMAC_FB BIT(1)
#define SDMMC_IDMAC_SWRESET BIT(0)
/* H/W reset */
#define SDMMC_RST_HWACTIVE 0x1
/* Version ID register define */
#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
/* Card read threshold */
#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
#define SDMMC_CARD_WR_THR_EN BIT(2)
#define SDMMC_CARD_RD_THR_EN BIT(0)
/* UHS-1 register defines */
#define SDMMC_UHS_18V BIT(0)
/* All ctrl reset bits */
#define SDMMC_CTRL_ALL_RESET_FLAGS \
(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
struct mmc_driver
{
uint32_t max_desc;
struct mmcsd_host *host;
struct mmcsd_req *req;
struct mmcsd_data *data;
struct mmcsd_cmd *cmd;
void* priv;
};
struct ark_mmc_obj;
/* DMA ops for Internal/External DMAC interface */
struct dw_mci_dma_ops {
/* DMA Ops */
int (*init)(struct ark_mmc_obj *mmc_obj);
int (*start)(struct ark_mmc_obj *mmc_obj, struct mmcsd_data *data);
void (*stop)(struct ark_mmc_obj *mmc_obj);
void (*cleanup)(struct ark_mmc_obj *mmc_obj);
void (*exit)(struct ark_mmc_obj *mmc_obj);
};
struct ark_mmc_obj
{
uint32_t id;
uint32_t irq;
uint32_t base;
uint32_t power_pin_gpio;
uint32_t fifoth_val;
uint32_t prev_blksz;
int result;
int use_dma;
int using_dma;
int dma_args[3];
struct dw_mci_dma_ops *dma_ops;
struct dw_mci_dma_slave *dms;
struct mmcsd_data *data;
QueueHandle_t transfer_completion;
char *tx_dummy_buffer;
char *rx_dummy_buffer;
int dummy_buffer_used;
void (*mmc_reset)(struct ark_mmc_obj *);
};
#endif /* _SDMMC_H */

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#ifndef USER_DATA_H
#define USER_DATA_H
#include "tkc/types_def.h"
/*
typedef struct pressure_t{
char mac_address[6]; //物理地址
uint8_t state; //状态 0未匹配/未学习 1已配对/已学习
uint8_t unit; //单位
uint8_t temp; //温度
uint8_t voltage; //电压
uint8_t blow_by_state; //漏气状态
uint8_t voltage_state; //低电压状态
uint8_t temp_state; //温度状态
uint16_t psi; //压强
}pressure_t;*/
typedef struct sfuddata_t{
uint8_t factory_reset; //出厂设置
uint8_t language; //语言
uint8_t display_unit; //单位
uint8_t theme; //当前主题
uint8_t theme_state; //主题状态
uint8_t light_value; //亮度
uint8_t bt_on_off; //蓝牙
uint8_t trip_uint; //trip_uint单位
uint8_t grade; //档位
uint16_t gas; //油量
uint32_t total_mileage; //里程数
char f_mac_address[9]; //物理地址
char r_mac_address[9]; //物理地址
uint32_t maintenance_mileage; //保养里程数max
uint32_t mileage_flag; //设置时当前的总里程数
uint8_t display_mileage; // 里程显示类型
uint8_t tcs_on_off; //tcs类型
uint8_t mile_state; //保养里程状态
uint8_t uuid_state; //uuid激活状态
uint8_t tp_state; //投屏开启状态
}SfudData_t;
typedef struct sfudmiledata_t{
uint32_t TRIP_mileage;//小计里程
uint32_t TOTAL_mileage;//总计里程
}SfudMileData_t;
void SaveDataToFlash(SfudData_t user_data);
void ReadDataToFlash(void);
SfudData_t* userData_getSfudSaved(void);
//extern daily_data_t custom_data;
void read_mileage(uint32_t trip_data,uint32_t total_data);
void SaveMileageData(uint32_t trip_data,uint32_t total_data);
void ReadMileageData(void);
#endif /*USER_DATA_H*/

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#ifndef _SPI_H
#define _SPI_H
#include "FreeRTOS.h"
#include "semphr.h"
#ifdef __cplusplus
extern "C" {
#endif
/* SPI mode flags */
#define SPI_CPHA BIT(0) /* clock phase */
#define SPI_CPOL BIT(1) /* clock polarity */
#define SPI_MODE_0 (0|0) /* (original MicroWire) */
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH BIT(2) /* CS active high */
#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
#define SPI_3WIRE BIT(4) /* SI/SO signals shared */
#define SPI_LOOP BIT(5) /* loopback mode */
#define SPI_SLAVE BIT(6) /* slave mode */
#define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */
#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */
#define SPI_RX_DUAL BIT(12) /* receive with 2 wires */
#define SPI_RX_QUAD BIT(13) /* receive with 4 wires */
#define SPI_READY BIT(14) /* Slave pulls low to pause */
#define SPI_NO_CS BIT(15) /* No chipselect */
#define SPI_DEFAULT_WORDLEN 8
/**
* SPI message structure
*/
struct spi_message
{
const void *send_buf;
void *recv_buf;
size_t length;
struct spi_message *next;
unsigned cs_take : 1;
unsigned cs_release : 1;
};
struct qspi_message
{
struct spi_message message;
/* instruction stage */
struct
{
uint8_t content;
uint8_t qspi_lines;
} instruction;
/* address and alternate_bytes stage */
struct
{
uint32_t content;
uint8_t size;
uint8_t qspi_lines;
} address, alternate_bytes;
/* dummy_cycles stage */
uint32_t dummy_cycles;
/* number of lines in qspi data stage, the other configuration items are in parent */
uint8_t qspi_data_lines;
};
/**
* SPI configuration structure
*/
struct spi_configuration
{
uint32_t mode;
uint32_t data_width;
uint32_t max_hz;
uint32_t qspi_max_hz;
uint32_t reserved;
};
/**
* struct spi_slave - Representation of a SPI slave
*/
struct spi_slave {
unsigned int bus;
unsigned int cs;
unsigned int mode;
unsigned int wordlen;
int (*xfer)(struct spi_slave *slave, struct spi_message *message);
int (*qspi_read)(struct spi_slave *slave, struct qspi_message *qspi_message);
int (*configure)(struct spi_slave *slave, struct spi_configuration *configuration);
SemaphoreHandle_t xMutex;
SemaphoreHandle_t xSfudMutex;
int open_count;
char name[16];
};
int ecspi_init(void);
int dwspi_init(void);
void spi_init(void);
int spi_add_slave(struct spi_slave *slave);
struct spi_slave *spi_open(const char *spidev);
void spi_close(struct spi_slave *slave);
int spi_send_then_recv(struct spi_slave *slave, const void *send_buf,
size_t send_length, void *recv_buf,
size_t recv_length);
int spi_transfer(struct spi_slave *slave, const void *send_buf,
void *recv_buf, size_t length);
int spi_configure(struct spi_slave *slave, struct spi_configuration *cfg);
int spi_recv(struct spi_slave *slave, void *recv_buf, size_t length);
int spi_send(struct spi_slave *slave, const void *send_buf, size_t length);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _SYSCTL_H
#define _SYSCTL_H
#ifdef __cplusplus
extern "C" {
#endif
#define SYS_BOOT_SAMPLE 0x0
#define SYS_BUS_CLK_CFG 0x40
#define SYS_BUS_CLK1_CFG 0x140
#define SYS_PER_CLK_CFG 0x44
#define SYS_SDMMC_CLK_CFG 0x48
#define SYS_VOU_CLK_CFG 0x4c
#define SYS_BUS_CLK_EN 0x50
#define SYS_BUS1_CLK_EN 0x54
#define SYS_PER_CLK_EN 0x58
#define SYS_SOFT_RST 0x5c
#define SYS_SOFT1_RST 0x60
#define SYS_SSP_CLK_CFG 0x64
#define SYS_TIMER_CLK_CFG 0x68
#define SYS_I2S_NCO_CFG 0x6c
#define SYS_DDRCTL_CFG 0x70
#define SYS_PERCTL_CFG 0x78
#define SYS_TIMER1_CLK_CFG 0x7c
#define SYS_ANA_CFG 0x80
#define SYS_ANA1_CFG 0x84
#define SYS_CPUPLL_CFG 0x88
#define SYS_SYSPLL_CFG 0x8c
#define SYS_ANA2_CFG 0x98
#define SYS_ANA3_CFG 0x9c
#define SYS_ANA4_CFG 0xa0
#define SYS_ANA5_CFG 0xa4
#define SYS_ANA6_CFG 0xa8
#define SYS_PAD_CTRL00 0xc0
#define SYS_PAD_CTRL01 0xc4
#define SYS_PAD_CTRL02 0xc8
#define SYS_PAD_CTRL03 0xcc
#define SYS_PAD_CTRL04 0xd0
#define SYS_PAD_CTRL05 0xd4
#define SYS_PAD_CTRL06 0xd8
#define SYS_PAD_CTRL07 0xdc
#define SYS_PAD_CTRL08 0x120
#define SYS_IO_DRIVER00 0xe0
#define SYS_IO_DRIVER01 0xe4
#define SYS_IO_DRIVER02 0xe8
#define SYS_IO_DRIVER03 0xec
#define SYS_IO_DRIVER04 0xf0
#define SYS_IO_DRIVER05 0xf4
#define SYS_IO_DRIVER06 0xf8
#define SYS_IO_DRIVER07 0xfc
enum sys_soft_reset{
//sys_soft0_reset
softreset_lcd=0,
softreset_dma,
softreset_jpeg,
softreset_usb,
softreset_card,
softreset_itu,
softreset_gpu,
softreset_pxp,
softreset_ssp,
softreset_ssp1,
softreset_i2c,
softreset_i2c1,
softreset_uart0,
softreset_uart1,
softreset_uart2,
softreset_uart3,
softreset_gpio,
softreset_timer0,
softreset_timer1,
softreset_timer2,
softreset_timer3,
softreset_pwm,
softreset_wdt,
softreset_i2s,
softreset_rtc,
softreset_adc,
softreset_rcrt,
softreset_aes,
softreset_icu,
softreset_ddr,
softreset_usbphy,
softreset_imc, //31
//sys_soft1_reset
softreset_can0, //0,
softreset_can1, //1
softreset_h2xdma, //2
softreset_h2xusb, //3
softreset_mipi, //4
softreset_usb_utmi, //5
softreset_vpu, //6,
softreset_i2s1, //8,
};
extern void vSysctlConfigure(uint32_t regoffset, uint32_t bitoffset, uint32_t mask, uint32_t val);
extern void sys_soft_reset (int reset_dev);
extern void sys_soft_reset_from_isr (int reset_dev);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _TIMER_H
#define _TIMER_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
TIMER_ID0 = 0,
TIMER_ID1,
TIMER_ID2,
TIMER_ID3,
} eTimerID;
#define TIMER_LOAD_COUNT(x) ((x) * 0x14 + 0x00)
#define TIMER_CURRENT_VAL(x) ((x) * 0x14 + 0x04)
#define TIMER_CTRL(x) ((x) * 0x14 + 0x08)
#define TIMER_EOI(x) ((x) * 0x14 + 0x0c)
#define TIMER_INT_STATUS(x) ((x) * 0x14 + 0x10)
#define TIMER_CTRL_INT_MASK (1ul << 2)
#define TIMER_CTRL_PERIODIC (1ul << 1)
#define TIMER_CTRL_ENABLE (1ul << 0)
void vTimerInit(uint32_t id, int32_t inten, int32_t periodic, uint32_t rate);
void vTimerEnable(uint32_t id);
void vTimerDisable(uint32_t id);
void vTimerClrInt(uint32_t id);
void vInitialiseTimerForRunTimeState(void);
uint32_t ulGetRunTimeCountValue(void);
void vInitialiseTimerForDelay(void);
void vTimerUdelay(uint32_t usec);
void vTimerMdelay(uint32_t msec);
void udelay(uint32_t usec);
void mdelay(uint32_t msec);
uint32_t get_timer(uint32_t base); /* us */
#ifdef __cplusplus
}
#endif
#endif

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/**
* \file
*
* \par Purpose
*
* Standard output methods for reporting debug information, warnings and
* errors, which can be easily be turned on/off.
*
* \par Usage
* -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually
* disable ALL traces; otherwise use DBGU_Configure().
* -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR()
* TRACE_FATAL() macros to output traces throughout the program.
* -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2
* and Fatal 1. Disable a group of traces by changing the value of
* TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL
* are not generated. To generate no trace, use the reserved value 0.
* -# Trace disabling can be static or dynamic. If dynamic disabling is selected
* the trace level can be modified in runtime. If static disabling is selected
* the disabled traces are not compiled.
*
* \par traceLevels Trace level description
* -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program,
* and which do not produce meaningful information otherwise.
* -# TRACE_INFO (4): Informational trace about the program execution. Should
* enable the user to see the execution flow.
* -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case
* it can be discarded safely; it may even be expected.
* -# TRACE_ERROR (2): Indicates an error which may not stop the program execution,
* but which indicates there is a problem with the code.
* -# TRACE_FATAL (1): Indicates a major error which prevents the program from going
* any further.
*/
#ifndef _TRACE_
#define _TRACE_
/*
* Headers
*/
//#include "pio.h"
#include <stdio.h>
#include "board.h"
/*
* Global Definitions
*/
/** Softpack Version */
#define SOFTPACK_VERSION "1.1"
#if defined(USE_ULOG)
/* using ulog compatible with trace */
#include <ulog.h>
#else
#define TRACE_LEVEL_DEBUG 5
#define TRACE_LEVEL_INFO 4
#define TRACE_LEVEL_WARNING 3
#define TRACE_LEVEL_ERROR 2
#define TRACE_LEVEL_FATAL 1
#define TRACE_LEVEL_NO_TRACE 0
/* By default, all traces are output except the debug one. */
#if !defined(TRACE_LEVEL)
#define TRACE_LEVEL TRACE_LEVEL_INFO
#endif
/* By default, trace level is static (not dynamic) */
#if !defined(DYN_TRACES)
#define DYN_TRACES 0
#endif
#if defined(NOTRACE)
#error "Error: NOTRACE has to be not defined !"
#endif
#undef NOTRACE
#if (DYN_TRACES==0)
#if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE)
#define NOTRACE
#endif
#endif
/* ------------------------------------------------------------------------------
* Global Macros
* ------------------------------------------------------------------------------
*/
extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) ;
/**
* Initializes the DBGU for ISP project
*
* \param mode DBGU mode.
* \param baudrate DBGU baudrate.
* \param mck Master clock frequency.
*/
#ifndef DYNTRACE
#define DYNTRACE 0
#endif
#if (TRACE_LEVEL==0) && (DYNTRACE==0)
#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {}
#else
#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \
const Pin pinsDBGU[] = {PINS_DBGU}; \
PIO_Configure(pinsDBGU, PIO_LISTSIZE(pinsDBGU)); \
DBGU_Configure( baudrate, mck ) ; \
}
#endif
/**
* Outputs a formatted string using 'printf' if the log level is high
* enough. Can be disabled by defining TRACE_LEVEL=0 during compilation.
* \param ... Additional parameters depending on formatted string.
*/
#if defined(NOTRACE)
/* Empty macro */
#define TRACE_DEBUG(...) { }
#define TRACE_INFO(...) { }
#define TRACE_WARNING(...) { }
#define TRACE_ERROR(...) { }
#define TRACE_FATAL(...) { while(1); }
#define TRACE_DEBUG_WP(...) { }
#define TRACE_INFO_WP(...) { }
#define TRACE_WARNING_WP(...) { }
#define TRACE_ERROR_WP(...) { }
#define TRACE_FATAL_WP(...) { while(1); }
#elif (DYN_TRACES == 1)
/* Trace output depends on dwTraceLevel value */
#define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } }
#define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } }
#define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } }
#define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } }
#define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } }
#define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } }
#define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } }
#define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } }
#define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } }
#define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } }
#else
/* Trace compilation depends on TRACE_LEVEL value */
#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG)
#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); }
#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); }
#else
#define TRACE_DEBUG(...) { }
#define TRACE_DEBUG_WP(...) { }
#endif
#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)
#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); }
#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); }
#else
#define TRACE_INFO(...) { }
#define TRACE_INFO_WP(...) { }
#endif
#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING)
#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); }
#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); }
#else
#define TRACE_WARNING(...) { }
#define TRACE_WARNING_WP(...) { }
#endif
#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR)
#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); }
#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); }
#else
#define TRACE_ERROR(...) { }
#define TRACE_ERROR_WP(...) { }
#endif
#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL)
#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); }
#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); }
#else
#define TRACE_FATAL(...) { while(1); }
#define TRACE_FATAL_WP(...) { while(1); }
#endif
#endif
/**
* Exported variables
*/
/** Depending on DYN_TRACES, dwTraceLevel is a modifable runtime variable or a define */
#if !defined(NOTRACE) && (DYN_TRACES == 1)
extern uint32_t dwTraceLevel ;
#endif
#endif //defined(USE_ULOG)
#endif //#ifndef TRACE_H

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MXC_A27-PCB4.5-270S/ArkmicroFiles/libcpu-amt630hv100/include/uart.h Normal file
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#ifndef _UART_H
#define _UART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "FreeRTOS.h"
#include "semphr.h"
#include "circ_buf.h"
typedef enum {
UART_ID0 = 0,
UART_ID1,
UART_ID2,
UART_ID3,
UART_NUM,
} eUartID;
typedef struct {
uint32_t id;
uint32_t regbase;
int fifosize;
struct circ_buf rxbuf;
struct circ_buf txbuf;
SemaphoreHandle_t xMutex;
SemaphoreHandle_t xRev;
SemaphoreHandle_t xSend;
}UartPort_t;
extern void vDebugConsoleInitialise(void);
extern UartPort_t *xUartOpen(uint32_t id);
extern void vUartInit(UartPort_t *uap, uint32_t baud, uint32_t flags);
extern void vUartClose(UartPort_t *uap);
extern int iUartWrite(UartPort_t *uap, uint8_t *buf, size_t len, TickType_t xBlockTime);
int iUartRead(UartPort_t *uap, uint8_t *buf, size_t len, TickType_t xBlockTime);
int uart_rx_demo(void);
#ifdef __cplusplus
}
#endif
#endif

45
MXC_A27-PCB4.5-270S/ArkmicroFiles/libcpu-amt630hv100/include/vdec.h Normal file
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/*
* Video Decoder (VDEC) - System peripherals registers.
*
* Copyright (C) 2009 Hantro Products Oy.
*
* Based on SAMA5D4 datasheet.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef VDEC_H
#define VDEC_H
#define VDEC_IDR 0x00 /* ID Register (read-only) */
#define VDEC_IDR_BUILD_VER 0xf /* Build Version is 0x02. */
#define VDEC_IDR_MINOR_VER (0xff << 4) /* Minor Version is 0x88. */
#define VDEC_IDR_MAJOR_VER (0xf << 12) /* Major Version is 0x08. */
#define VDEC_IDR_PROD_ID (0xffff << 16) /* Product ID is 0x6731. */
#define VDEC_DIR 0x04 /* Decoder Interrupt Register */
#define VDEC_DIR_DE 1 /* 1: Enable decoder; 0: Disable decoder. */
#define VDEC_DIR_ID 0x10 /* 1: Disable interrupts for decoder; 0: Enable interrupts. */
#define VDEC_DIR_ABORT 0x20
#define VDEC_DIR_ISET 0x100 /* Decoder Interrupt Set. 0: Clears the Decoder Interrupt. */
#define VDEC_PPIR 0xF0 /* Post Processor Interrupt Register */
#define VDEC_PPIR_PPE 1 /* 1: Enable post-processor; 0: Disable post-processor */
#define VDEC_PPIR_ID 0x10 /* 1: Disable interrupts for post-processor; 0: Enable interrupts. */
#define VDEC_PPIR_ISET 0x100 /* Post-processor Interrupt Set. 0: Clears the post-processor Interrupt. */
int vdec_init(void);
#endif

20
MXC_A27-PCB4.5-270S/ArkmicroFiles/libcpu-amt630hv100/include/wdt.h Normal file
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#ifndef _WDT_H
#define _WDT_H
#ifdef __cplusplus
extern "C" {
#endif
int wdt_set_heartbeat(unsigned int timeout);
void wdt_stop(void);
void wdt_start(void);
void ark_wdt_keepalive(void);
int wdt_init(void);
void wdt_cpu_reboot(void);
#ifdef __cplusplus
}
#endif
#endif