155 lines
6.4 KiB
C
155 lines
6.4 KiB
C
/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2013, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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/** \file */
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/**
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* \addtogroup mmu MMU Initialization
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*
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* \section Usage
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*
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* Translation Lookaside Buffers (TLBs) are an implementation technique that caches translations or
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* translation table entries. TLBs avoid the requirement for every memory access to perform a translation table
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* lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a
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* similar way to the requirements for caches, the architecture only defines certain principles for TLBs:
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*
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* The MMU supports memory accesses based on memory sections or pages:
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* Supersections Consist of 16MB blocks of memory. Support for Supersections is optional.
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* -# Sections Consist of 1MB blocks of memory.
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* -# Large pages Consist of 64KB blocks of memory.
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* -# Small pages Consist of 4KB blocks of memory.
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*
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* Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry.
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* Memory region attributes
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* Each TLB entry has an associated set of memory region attributes. These control accesses to the caches,
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* how the write buffer is used, and if the memory region is Shareable and therefore must be kept coherent.
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*
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* Related files:\n
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* \ref mmu.c\n
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* \ref mmu.h \n
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*/
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/*------------------------------------------------------------------------------ */
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/* Headers */
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/*------------------------------------------------------------------------------ */
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#include <chip.h>
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/*------------------------------------------------------------------------------ */
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/* Exported functions */
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/*------------------------------------------------------------------------------ */
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/**
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* \brief Initializes MMU.
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* \param pTB Address of the translation table.
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*/
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void MMU_Initialize(uint32_t *pTB)
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{
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unsigned int index;
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unsigned int addr;
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/* Reset table entries */
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for (index = 0; index < 4096; index++)
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pTB[index] = 0;
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/* interrupt vector address (after remap) 0x0000_0000 */
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pTB[0x000] = (0x200 << 20)| // Physical Address
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// ( 1 << 12)| // TEX[0]
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( 3 << 10)| // Access in supervisor mode (AP)
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( 0xF << 5)| // Domain 0xF
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( 1 << 4)| // (XN)
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( 0 << 3)| // C bit : cachable => YES
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( 0 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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/* SRAM address (after remap) 0x0030_0000 */
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pTB[0x003] = (0x003 << 20)| // Physical Address
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// ( 1 << 12)| // TEX[0]
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( 3 << 10)| // Access in supervisor mode (AP)
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( 0xF << 5)| // Domain 0xF
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( 1 << 4)| // (XN)
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( 0 << 3)| // C bit : cachable => YES
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( 0 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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/* DDRAM address (after remap) 0x2000_0000 */
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for(addr = 0x200; addr < 0x240; addr++)
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pTB[addr] = (addr << 20)| // Physical Address
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( 1 << 18)| // 16MB Supersection
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( 3 << 10)| // Access in supervisor mode (AP)
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( 1 << 12)| // TEX[0]
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( 0 << 5)| // Domain 0x0, Supersection only support domain 0
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( 0 << 4)| // (XN)
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( 1 << 3)| // C bit : cachable => YES
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( 1 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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/* DDRAM non-cache address (after remap) 0x3000_0000 */
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for(addr = 0x300; addr < 0x340; addr++)
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pTB[addr] = ((addr - 0x100) << 20)| // Physical Address
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( 1 << 18)| // 16MB Supersection
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( 3 << 10)| // Access in supervisor mode (AP)
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( 1 << 12)| // TEX[0]
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( 0 << 5)| // Domain 0x0, Supersection only support domain 0
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( 0 << 4)| // (XN)
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( 0 << 3)| // C bit : cachable => YES
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( 0 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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// periph address 0x60000000 ~ 0x80000000
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for(addr = 0x600; addr < 0x800; addr++)
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pTB[addr] = (addr << 20)| // Physical Address
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( 3 << 10)| // Access in supervisor mode (AP)
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( 0xF << 5)| // Domain 0xF
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( 1 << 4)| // (XN)
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( 0 << 3)| // C bit : cachable => NO
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( 0 << 2)| // B bit : write-back => NO
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( 2 << 0); // Set as 1 Mbyte section
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CP15_WriteTTB((unsigned int)pTB);
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/* Program the domain access register */
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CP15_WriteDomainAccessControl(0xC0000003); // only domain 0 & 15: access are not checked
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}
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void dma_inv_range(UINT32 ulStart, UINT32 ulEnd)
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{
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CP15_invalidate_dcache_for_dma (ulStart, ulEnd);
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}
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void dma_clean_range(UINT32 ulStart, UINT32 ulEnd)
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{
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CP15_clean_dcache_for_dma (ulStart, ulEnd);
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}
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// flush<73><68>clean and invalidate
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void dma_flush_range(UINT32 ulStart, UINT32 ulEnd)
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{
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CP15_flush_dcache_for_dma (ulStart, ulEnd);
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}
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