120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
#ifndef _MMCSD_HOST_H
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#define _MMCSD_HOST_H
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct mmcsd_io_cfg {
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uint32_t clock; /* clock rate */
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uint16_t vdd;
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/* vdd stores the bit number of the selected voltage range from below. */
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uint8_t bus_mode; /* command output mode */
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#define MMCSD_BUSMODE_OPENDRAIN 1
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#define MMCSD_BUSMODE_PUSHPULL 2
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uint8_t chip_select; /* SPI chip select */
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#define MMCSD_CS_IGNORE 0
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#define MMCSD_CS_HIGH 1
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#define MMCSD_CS_LOW 2
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uint8_t power_mode; /* power supply mode */
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#define MMCSD_POWER_OFF 0
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#define MMCSD_POWER_UP 1
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#define MMCSD_POWER_ON 2
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uint8_t bus_width; /* data bus width */
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#define MMCSD_BUS_WIDTH_1 0
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#define MMCSD_BUS_WIDTH_4 2
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#define MMCSD_BUS_WIDTH_8 3
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};
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struct mmcsd_host;
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struct mmcsd_req;
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struct mmcsd_host_ops {
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void (*request)(struct mmcsd_host *host, struct mmcsd_req *req);
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void (*set_iocfg)(struct mmcsd_host *host, struct mmcsd_io_cfg *io_cfg);
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int32_t (*get_card_status)(struct mmcsd_host *host);
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void (*enable_sdio_irq)(struct mmcsd_host *host, int32_t en);
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};
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struct mmcsd_host {
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struct mmcsd_card *card;
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const struct mmcsd_host_ops *ops;
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uint32_t freq_min;
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uint32_t freq_max;
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struct mmcsd_io_cfg io_cfg;
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uint32_t valid_ocr; /* current valid OCR */
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#define VDD_165_195 (1 << 7) /* VDD voltage 1.65 - 1.95 */
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#define VDD_20_21 (1 << 8) /* VDD voltage 2.0 ~ 2.1 */
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#define VDD_21_22 (1 << 9) /* VDD voltage 2.1 ~ 2.2 */
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#define VDD_22_23 (1 << 10) /* VDD voltage 2.2 ~ 2.3 */
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#define VDD_23_24 (1 << 11) /* VDD voltage 2.3 ~ 2.4 */
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#define VDD_24_25 (1 << 12) /* VDD voltage 2.4 ~ 2.5 */
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#define VDD_25_26 (1 << 13) /* VDD voltage 2.5 ~ 2.6 */
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#define VDD_26_27 (1 << 14) /* VDD voltage 2.6 ~ 2.7 */
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#define VDD_27_28 (1 << 15) /* VDD voltage 2.7 ~ 2.8 */
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#define VDD_28_29 (1 << 16) /* VDD voltage 2.8 ~ 2.9 */
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#define VDD_29_30 (1 << 17) /* VDD voltage 2.9 ~ 3.0 */
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#define VDD_30_31 (1 << 18) /* VDD voltage 3.0 ~ 3.1 */
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#define VDD_31_32 (1 << 19) /* VDD voltage 3.1 ~ 3.2 */
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#define VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */
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#define VDD_33_34 (1 << 21) /* VDD voltage 3.3 ~ 3.4 */
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#define VDD_34_35 (1 << 22) /* VDD voltage 3.4 ~ 3.5 */
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#define VDD_35_36 (1 << 23) /* VDD voltage 3.5 ~ 3.6 */
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uint32_t flags; /* define device capabilities */
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#define MMCSD_BUSWIDTH_4 (1 << 0)
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#define MMCSD_BUSWIDTH_8 (1 << 1)
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#define MMCSD_MUTBLKWRITE (1 << 2)
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#define MMCSD_HOST_IS_SPI (1 << 3)
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#define controller_is_spi(host) (host->flags & MMCSD_HOST_IS_SPI)
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#define MMCSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */
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#define MMCSD_SUP_HIGHSPEED (1 << 5) /* support high speed */
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uint32_t max_seg_size; /* maximum size of one dma segment */
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uint32_t max_dma_segs; /* maximum number of dma segments in one request */
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uint32_t max_blk_size; /* maximum block size */
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uint32_t max_blk_count; /* maximum block count */
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uint32_t spi_use_crc;
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SemaphoreHandle_t bus_lock;
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SemaphoreHandle_t sem_ack;
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uint32_t sdio_irq_num;
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SemaphoreHandle_t sdio_irq_sem;
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TaskHandle_t sdio_irq_thread;
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uint8_t transfer_err;
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void *private_data;
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};
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static inline void mmcsd_delay_ms(uint32_t ms)
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{
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if (ms < 1000 / configTICK_RATE_HZ)
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{
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vTaskDelay(1);
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}
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else
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{
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vTaskDelay(ms/(1000 / configTICK_RATE_HZ));
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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