99 lines
3.5 KiB
C
99 lines
3.5 KiB
C
#include "mmu.h"
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//#pragma data_alignment=16384
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//__no_init unsigned int mmu_tlb_table[4096];
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//#define _MMUTT_STARTADDRESS ((unsigned int)mmu_tlb_table)
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#define _MMUTT_STARTADDRESS ((unsigned int)0x30c000)
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/**
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* \brief Initializes MMU.
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* \param pTB Address of the translation table.
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*/
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void MMU_Initialize(unsigned int *pTB)
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{
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unsigned int index;
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unsigned int addr;
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/* Reset table entries */
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for (index = 0; index < 4096; index++)
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pTB[index] = 0;
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/* interrupt vector address (after remap) 0x0000_0000 */
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pTB[0x000] = (0x200 << 20)| // Physical Address
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// ( 1 << 12)| // TEX[0]
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( 3 << 10)| // Access in supervisor mode (AP)
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( 0xF << 5)| // Domain 0xF
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( 1 << 4)| // (XN)
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( 0 << 3)| // C bit : cachable => YES
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( 0 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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/* SRAM address (after remap) 0x0030_0000 */
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pTB[0x003] = (0x003 << 20)| // Physical Address
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( 1 << 18)| // 16MB Supersection
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( 3 << 10)| // Access in supervisor mode (AP)
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( 1 << 12)| // TEX[0]
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( 0 << 5)| // Domain 0x0, Supersection only support domain 0
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( 0 << 4)| // (XN)
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( 1 << 3)| // C bit : cachable => YES
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( 1 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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/* DDRAM address (after remap) 0x2000_0000 */
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for(addr = 0x200; addr < 0x220; addr++)
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pTB[addr] = (addr << 20)| // Physical Address
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( 1 << 18)| // 16MB Supersection
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( 3 << 10)| // Access in supervisor mode (AP)
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( 1 << 12)| // TEX[0]
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( 0 << 5)| // Domain 0x0, Supersection only support domain 0
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( 0 << 4)| // (XN)
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( 1 << 3)| // C bit : cachable => YES
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( 1 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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/* DDRAM non-cache address (after remap) 0x3000_0000 */
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for(addr = 0x300; addr < 0x320; addr++)
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pTB[addr] = ((addr - 0x100) << 20)| // Physical Address
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( 1 << 18)| // 16MB Supersection
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( 3 << 10)| // Access in supervisor mode (AP)
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( 1 << 12)| // TEX[0]
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( 0 << 5)| // Domain 0x0, Supersection only support domain 0
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( 0 << 4)| // (XN)
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( 0 << 3)| // C bit : cachable => YES
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( 0 << 2)| // B bit : write-back => YES
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( 2 << 0); // Set as 1 Mbyte section
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// periph address 0x60000000 ~ 0x80000000
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for(addr = 0x600; addr < 0x800; addr++)
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pTB[addr] = (addr << 20)| // Physical Address
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( 3 << 10)| // Access in supervisor mode (AP)
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( 0xF << 5)| // Domain 0xF
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( 1 << 4)| // (XN)
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( 0 << 3)| // C bit : cachable => NO
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( 0 << 2)| // B bit : write-back => NO
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( 2 << 0); // Set as 1 Mbyte section
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CP15_WriteTTB((unsigned int)pTB);
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/* Program the domain access register */
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CP15_WriteDomainAccessControl(0xC0000003); // only domain 0 & 15: access are not checked
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}
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void MMU_Init(void)
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{
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if(CP15_IsIcacheEnabled())
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CP15_DisableIcache();
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if(CP15_IsDcacheEnabled())
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CP15_DisableDcache();
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if(CP15_IsMMUEnabled())
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CP15_DisableMMU();
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MMU_Initialize((unsigned int*)_MMUTT_STARTADDRESS);
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CP15_EnableMMU();
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CP15_EnableIcache();
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CP15_EnableDcache();
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}
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