478 lines
13 KiB
C
478 lines
13 KiB
C
/*
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**********************************************************************
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Copyright (c)2009 Arkmicro Technologies Inc. All Rights Reserved
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Filename: boot.c
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Version : 1.00
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Date : 2010.06.29
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Author : Donier
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Abstract: Ark2116 SoC boot rom code file.
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Note : The size the code(*.bin) loaded should never exceed 10K Bytes.
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History : From the ark2116 SoC boot rom code file.
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***********************************************************************
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*/
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#include "typedef.h"
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#include "amt630h.h"
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#include "BootModeSel.h"
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#include "UartPrint.h"
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#include "timer.h"
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#include "mmu.h"
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#include "sysinfo.h"
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#include "spi.h"
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#define PROJECT_FOR_DDR_INIT 0
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#define PROJECT_FOR_SPIFLASH_LOADER 1
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#define PROJECT_FOR_SD_UPDATE 2
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#define PROJECT_FOR_JTAG_UPDATE 3
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#define PROJECT_FOR_EMMC_LOADER 4
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#define PROJECT_FOR_LAUNCH_EMMC 5
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#define PROJECT_PURPOSE PROJECT_FOR_JTAG_UPDATE
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#if PROJECT_PURPOSE == PROJECT_FOR_EMMC_LOADER || PROJECT_PURPOSE == PROJECT_FOR_LAUNCH_EMMC
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#if DEVICE_TYPE_SELECT != EMMC_FLASH
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#error "you should select emmc flash device type!"
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#endif
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#endif
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//ok //err//ok //ok //err//ok //ok
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#define SYSPLL_CLK 400 //550//600//550//400//500//300//400
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#define CPUPLL_CLK 550 //550//550//550//550//500//550//550
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#define DDRPLL_CLK 600 //700//700//700//600//700//700//700 （RGB屏超过600M低温卡死，lvds屏正常）
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#define VPUPLL_CLK 240 //240//240//240//240//240//240//240
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#define CLK_APB_FREQ (SYSPLL_CLK * 1000000 / 2)
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#define OSC_FREQ 24000000
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#define tref 1560 //(unsigned int)((3900*DDR_CLK)/1000)
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#define cas 6
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#define twl 5
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#define tmrd 4
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#define tras 19 //13 //(unsigned int)((45*DDR_CLK)/1000)
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#define trc 28 //16 //(unsigned int)((60*DDR_CLK)/1000)
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#define trcd 6 //(unsigned int)((15*DDR_CLK)/1000)
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#define trfc 45 //37 //(unsigned int)((105*DDR_CLK)/1000)
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#define trp 6 //(unsigned int)((15*DDR_CLK)/1000)
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#define trrd 5 //(unsigned int)((10*DDR_CLK)/1000)
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#define twr 6 //(unsigned int)((15*DDR_CLK)/1000)
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#define twtr 4 //(unsigned int)((8*DDR_CLK)/1000)
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#define txp 4
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#define txsr 200
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#define tesr 6
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#define tfaw 18 //(unsigned int)((45*DDR_CLK)/1000)
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extern void SetSysPLL(unsigned int freq);
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extern void SetCpuPLL(unsigned int freq);
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extern void SetDDRPLL(unsigned int freq);
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extern void SetVPUPLL(unsigned int freq);
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extern void SetXclkAHBclkAPBclk(void);
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extern void SetSpiclk(void);
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extern void SetGpuclk(void);
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extern void SetMfcclk(void);
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extern void SwitchTo24MHz(void);
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extern void updateFromSD(int chipid);
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extern void FlashBurn(void *buf, unsigned int offset, unsigned int size);
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extern int wdt_init(unsigned int clk_freq);
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extern int EmmcInit(int chipid);
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extern void launchEMMC(int chipid);
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extern int EmmcBurn(void *buf, unsigned int offset, unsigned int size, int show_progress);
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static void delay(volatile UINT32 count )
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{
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while(count--);
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}
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void ddr_rd_clk_config()
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{
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unsigned int i;
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rSYS_DDRCTL1_CFG = 0x01; //reset pll
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delay(1000);
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rSYS_DDRCTL1_CFG = 0x00; //enable pll
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delay(100000);
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i = 0x01 << 1 | 200 << 8;
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rSYS_DDRCTL1_CFG = i;
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delay(100000);
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}
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void ddr_training_one(void)
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{
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int value = 0;
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rSYS_DDRCTL_CFG = (1<<15);
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// value = (0x1c<<0) |(0x1c<<8)|(0x30<<16);
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// value = (0x1c<<0) |(0x1c<<8)|(0x18<<16); fail 25
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// value = (0x1c<<0) |(0x1c<<8)|(0x20<<16); 25 ok
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// value = (0x1c<<0) |(0x1c<<8)|(0x28<<16); 25 ok
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// value = (0x1c<<0) |(0x1c<<8)|(0x30<<16);
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// value = (0x1c<<0) |(0x1c<<8)|(0x26<<16); //4 ok
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// value = (0x1c<<0) |(0x1c<<8)|(0x20<<16); //1 ok
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// value = (0x1c<<0) |(0x1c<<8)|(0x30<<16); //4 ok 0514
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value = (0x1c<<0) |(0x1c<<8)|(0x33<<16); //4 ok
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// value = (0x1c<<0) |(0x1c<<8)|(0x3b<<16); //4 ok
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rSYS_DDRCTL1_CFG =value;
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rSYS_DDRCTL2_CFG =value;
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}
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#if 0
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#define DDR_TOTAL 0x10000
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int DDR3_RW_Test(void)
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{
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unsigned int i=0;
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unsigned int data_char;
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for (i=0; i<DDR_TOTAL; i++)
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{
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(*(volatile unsigned int *)(0x20000000 + (i*4))) =i+0x04;
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//PrintVariableValueHex("write is %x",i+4);
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}
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for (i=0; i<DDR_TOTAL;i++)
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{
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data_char =(*(volatile unsigned int *)(0x20000000 + (i*4 )));
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// PrintVariableValueHex("read is %x",data_char);
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if(data_char!=(i+0x04))
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// if(data_char!=0x55aabbcc)
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{
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// SendUartString("\r\nddr error\r\n");
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// PrintVariableValueHex("read is ",data_char);
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// PrintVariableValueHex("addr is ",(0x20000000 + (i*4 )));
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break;
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}
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// PrintVariableValueHex("datachar11",data_char);
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}
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SendUartString("ddr1 test1 end \n");
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if(i==DDR_TOTAL)
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{
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SendUartString("ddr1 test1 ok \n");
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}
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for (i=0; i<DDR_TOTAL; i++)
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{
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(*(volatile unsigned int *)(0x20000000 + (i*4))) = 0x20000000 + (i*4);
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//PrintVariableValueHex("write is ",i+4);
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data_char =(*(volatile unsigned int *)(0x20000000 + (i*4 )));
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if(data_char!=(0x20000000 + (i*4 )))
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{
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// SendUartString("\ddr error\n");
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// PrintVariableValueHex("read is",data_char);
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// PrintVariableValueHex("addr is ",(0x20000000 + (i*4 )));
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break;
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}
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}
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SendUartString("\nddr1 test2 end \n");
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if(i==DDR_TOTAL)
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{
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SendUartString("ddr1 test2 ok \n");
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return 1;
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}
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return 0;
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}
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void ddr_training(void)
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{
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int i=0;
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int j=0;
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int value =0 ;
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unsigned int result;
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rSYS_DDRCTL_CFG = (1<<15);
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//printk("rd_dly:(0x08----0x30);qs_dly:(0x00------0x40)\r\n");
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//printk("rd_dly: ");
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//for(j=0x08;j<0x30;j=j+1)
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//printk(" %2d",j);
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//printk("\r\n");
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for(j=0x18; j<0x30; j++)
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// for(i=0x00;i<0x40;i++)
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{
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//printk(" 0x%2x ",i);
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for(i=0x00;i<0x40;i++)
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//for(j=0x18;j<0x30;j++)
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{
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udelay(3);
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//j = 0x18;
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udelay(3);
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value = i |(i<<8)|(j<<16); //|i<<16 ;
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*(volatile unsigned int *)0x60000074 =value;
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*(volatile unsigned int *)0x600000b0 =value;
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udelay(3000);
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result = DDR3_RW_Test();
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udelay(3000);
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if(result)
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SendUartString("O");
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else
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SendUartString("X");
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udelay(3);
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}
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SendUartString("\r\n");
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}
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}
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#endif
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void ddr3_sdramc_init(void)
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{
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unsigned long i;
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//unsigned int rdata=0;
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//i = rSYS_DDRCTL1_CFG;
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//i &= ~((0xFF << 24) |(0xFF << 16) | (0x7F << 8) | 0x7F);
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//i |= (0x40 << 24) |(0x40 << 8) | 0x40;
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//rSYS_DDRCTL1_CFG = i;
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ddr_training_one();
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rSYS_DDRCTL3_CFG = (0x0 <<11 | 0x01 <<10);
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//ddr initialization
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// i= 0x2;
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// READ_DELAY_REG = i;
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//active_chip qos burst stop auto_power_down power_down_cycle row col
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i = 0x0 << 21 | 0x0 <<18 | 0x2 << 15 | 0x0 <<14 | 0x0 <<13 | 0x0 << 7 | 0x2 <<3 | 0x2<< 0;
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MEM_CFG_REG = i;
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// mem_width bank_bit cke_init dqm_init clk_cfg
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i = 0x0 <<6 | 0x0 << 4 | 0x0 <<3 | 0x0 <<2 | 0x0 << 0;
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MEM_CFG2_REG = i;
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// ref timeout
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i = 0x1 << 0;
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MEM_CFG3_REG = i;
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//addr_fmt addr_match addr_mask
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i = 0x1 << 16 | 0x20 <<8 | 0xfc << 0;
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CHIP_CFG_REG = i;
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//wr_block | early_resp
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i= 0x0<<2 | 0x0 << 0;
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FEA_CTL_REG = i;
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//tref
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i= tref;
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//i= 0x300;
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REF_PRD_REG = i;
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//cas
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i= cas<<1;
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TCAS_REG = i;
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//twl
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//i= 0x1<< 0;
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i= twl<< 0;
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TWL_REG = i;
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//tmrd
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//i= 0x10<< 0;
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i= tmrd<< 0;
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TMRD_REG = i;
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//tras
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i= (tras)<< 0;
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TRAS_REG = i;
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//trc
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i= trc << 0;
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TRC_REG = i;
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//trcd schelue rcd
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//i= 0x2<< 0 | 0x2<<3;
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i= trcd<< 0 | (trcd-3)<<8;
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TRCD_REG = i;
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//schelue trfc trfc
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//i= 15<<5|18<< 0;
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i= (trfc-3)<<8|trfc<< 0;
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TRFC_REG = i;
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//trp
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//i= 0x3<< 0 | 0x2 << 3;
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i= trp<< 0 | (trp-3) << 8;
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TRP_REG = i;
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//trrd
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//i= 0x6<< 0;
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i= trrd<< 0;
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TRRD_REG = i;
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//twr
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i= twr<< 0;
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TWR_REG = i;
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//twtr
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//i= 0x7<< 0;
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i= twtr<< 0;
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TWTR_REG = i;
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//txp
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//i= 0x40<< 0;
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i= txp<< 0;
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TXP_REG = i;
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//txsr
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//i= 199<< 0;
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i= txsr<< 0;
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TXSR_REG = i;
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//tesr
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i= tesr<< 0;
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TESR_REG = i;
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//tfaw
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i= tfaw<< 0|(tfaw-3)<<8;
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TFAW_REG = i;
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//
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// //precharge
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DIR_CMD_REG = 0x000c0000 ; //direct_cmd_reg nop
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DIR_CMD_REG = 0x00000000 ; //direct_cmd_reg precharge
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DIR_CMD_REG = 0x000a0000 ; //direct_cmd_reg xmodereg2 set
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DIR_CMD_REG = 0x000b0000 ; //direct_cmd_reg xmodereg3 set
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DIR_CMD_REG = 0x00090000 |(0<<6)|(1<<2); //direct_cmd_reg xmodereg set
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// DIR_CMD_REG = 0x00080952 ; //direct_cmd_reg modereg set
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DIR_CMD_REG = 0x00080962 ; //direct_cmd_reg modereg set
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DIR_CMD_REG = 0x00000000 ; //direct_cmd_reg precharge
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DIR_CMD_REG = 0x00040000 ; //direct_cmd_reg autorefresh
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DIR_CMD_REG = 0x00040000 ; //direct_cmd_reg autorefresh
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// DIR_CMD_REG = 0x00080852 ; //direct_cmd_reg modereg set
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DIR_CMD_REG = 0x00080862 ; //direct_cmd_reg modereg set
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// DIR_CMD_REG = 0x00090380 ; //direct_cmd_reg xmodereg1 set
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// DIR_CMD_REG = 0x00090000 ; //direct_cmd_reg xmodereg1 set
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MEM_CMD_REG = 0x00000000 ; //mem_cmd_reg go
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while ((MEM_STA_REG &0x01)!=0x01);
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//ddr_training(); //Only for test.
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// *(volatile unsigned int *)0x60000074 = 0x9; //0x6;//0xD;
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}
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void updateFromJtag(void)
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{
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unsigned int loader_addr = 0x20000000;
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#if DEVICE_TYPE_SELECT == EMMC_FLASH
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unsigned int launch_addr = 0x20008000;
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#endif
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unsigned int stepldr_addr = 0x20010000;
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unsigned int app_addr = 0x20100000;
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UpFileHeader *header = (UpFileHeader *)app_addr;
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SysInfo *sysinfo = GetSysInfo();
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sysinfo->app_checksum = header->checksum;
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sysinfo->stepldr_offset = STEPLDRA_OFFSET;
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sysinfo->stepldr_size = STEPLDR_MAX_SIZE;
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sysinfo->update_status = UPDATE_STATUS_END;
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sysinfo->image_offset = IMAGE_OFFSET;
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sysinfo->loader_offset = LOADER_OFFSET;
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sysinfo->loader_size = LOADER_MAX_SIZE;
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#if DEVICE_TYPE_SELECT != EMMC_FLASH
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SendUartString("burn loader start... \r\n");
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FlashBurn((void*)loader_addr, LOADER_OFFSET, LOADER_MAX_SIZE);
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SendUartString("burn loader end. \r\n");
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SendUartString("burn stepldr start... \r\n");
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FlashBurn((void*)stepldr_addr, STEPLDRA_OFFSET, STEPLDR_MAX_SIZE);
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SendUartString("burn stepldr end. \r\n");
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SendUartString("burn app start... \r\n");
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FlashBurn((void*)app_addr, IMAGE_OFFSET, header->size);
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SendUartString("burn app end. \r\n");
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#else
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EmmcInit(0);
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SendUartString("burn launch start... \r\n");
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FlashBurn((void*)launch_addr, LOADER_OFFSET, LOADER_MAX_SIZE);
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SendUartString("burn launch end. \r\n");
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SendUartString("burn loader start... \r\n");
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EmmcBurn((void*)loader_addr, LOADER_OFFSET, LOADER_MAX_SIZE, 0);
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SendUartString("burn loader end. \r\n");
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SendUartString("burn stepldr start... \r\n");
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EmmcBurn((void*)stepldr_addr, STEPLDRA_OFFSET, STEPLDR_MAX_SIZE, 0);
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SendUartString("burn stepldr end. \r\n");
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SendUartString("burn app start... \r\n");
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EmmcBurn((void*)app_addr, IMAGE_OFFSET, header->size, 0);
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SendUartString("burn app end. \r\n");
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#endif
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SaveSysInfo(sysinfo);
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SendUartString("Update is finished. Please reset. \r\n");
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while(1);
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}
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void main(void)
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{
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unsigned int val;
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//set all io drive to 4ma(default 8ma).
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rSYS_IO_DRIVER00=0x55555555;
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rSYS_IO_DRIVER01=0x55555555;
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rSYS_IO_DRIVER02=0x55555555;
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rSYS_IO_DRIVER03=0x55555555;
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rSYS_IO_DRIVER04=0x55555555;
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rSYS_IO_DRIVER05=0x55555555;
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rSYS_IO_DRIVER06=0x55555555;
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#if PROJECT_PURPOSE == PROJECT_FOR_LAUNCH_EMMC
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timer_init();
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InitUart(115200);
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SendUartString("\nARK AMT630Hv100 launch emmc from norflash\r\n");
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wdt_init(OSC_FREQ);
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launchEMMC(0);
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#endif
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SwitchTo24MHz();
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timer_init();
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InitUart(115200);
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SendUartString("\nARK AMT630Hv100 AMTLDR 0906_700M\n");
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/*
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val = rSYS_ANA1_CFG;
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val |= (1 << 4)|(5 << 1);
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rSYS_ANA1_CFG = val;
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udelay(300);
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val = rSYS_ANA1_CFG;
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val &= ~(0x1 <<5);
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rSYS_ANA1_CFG = val;
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*/
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#if 1 //低电压2.8V复位
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rSYS_ANA1_CFG |= (1 << 4)|(5 << 1);
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udelay(300);
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rSYS_ANA1_CFG |= (1 << 5);
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udelay(100);
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#else //低电压2.5V复位
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rSYS_ANA1_CFG |= (1 << 4)|(0 << 1);
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udelay(3000);
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rSYS_ANA1_CFG |= (1 << 5);
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udelay(1000);
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#endif
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val = rSYS_ANA2_CFG;
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val = (0x3F <<6)|(1 << 2)|(1 << 0);
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rSYS_ANA2_CFG = val;
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SetSysPLL(SYSPLL_CLK);
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SetCpuPLL(CPUPLL_CLK);
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SetDDRPLL(DDRPLL_CLK);
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SetVPUPLL(VPUPLL_CLK);
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udelay(500);
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SetXclkAHBclkAPBclk();
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SetSpiclk();
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SetGpuclk();
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SetMfcclk();
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mdelay(50); //50
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#if PROJECT_PURPOSE == PROJECT_FOR_SPIFLASH_LOADER || PROJECT_PURPOSE == PROJECT_FOR_EMMC_LOADER
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wdt_init(CLK_APB_FREQ);
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#endif
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ddr3_sdramc_init();
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mdelay(50); //80//100
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SendUartString("\nDDR init over2!!_m50\n");
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SpiInit();
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#ifdef MMU_ENABLE
|
||
MMU_Init();
|
||
#endif
|
||
|
||
#if PROJECT_PURPOSE == PROJECT_FOR_DDR_INIT
|
||
while(1);
|
||
#elif PROJECT_PURPOSE == PROJECT_FOR_SPIFLASH_LOADER
|
||
bootFromSPI();
|
||
#elif PROJECT_PURPOSE == PROJECT_FOR_SD_UPDATE
|
||
SetDefaultSysInfo();
|
||
SaveSysInfo(0);
|
||
updateFromSD(0);
|
||
bootFromSPI();
|
||
#elif PROJECT_PURPOSE == PROJECT_FOR_JTAG_UPDATE
|
||
updateFromJtag();
|
||
#elif PROJECT_PURPOSE == PROJECT_FOR_EMMC_LOADER
|
||
bootFromEMMC(0);
|
||
#endif
|
||
}
|