339 lines
11 KiB
C
339 lines
11 KiB
C
#include "FreeRTOS.h"
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#include "board.h"
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#include "chip.h"
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#define PINCTL_REG_BASE REGS_SYSCTL_BASE
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#define MAX_PINS_PER_GROUP 32
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typedef struct {
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short muxio;
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short pinval;
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int drive;
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} xPin_t;
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typedef struct {
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int groupid;
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uint32_t mux_reg;
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uint32_t mux_offset;
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uint32_t mux_mask;
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uint32_t mux_val;
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short pins_num;
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xPin_t pins[MAX_PINS_PER_GROUP];
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} xPinGroup_t;
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/* typedef struct {
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} xPinFunction_t; */
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typedef struct {
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int reg;
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int offset;
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int mask;
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} xPinmap_t;
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static xPinmap_t amt630h_pin_map[] = {
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{0xc0, 0, 0x3},
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{0xc0, 2, 0x3},
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{0xc0, 4, 0x3},
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{0xc0, 6, 0x3},
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{0xc0, 8, 0x3},
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{0xc0, 10, 0x3},
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{0xc0, 12, 0x3},
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{0xc0, 14, 0x3},
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{0xc0, 16, 0x3},
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{0xc0, 18, 0x3},
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{0xc0, 20, 0x3},
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{0xc0, 22, 0x3},
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{0xc0, 24, 0x3},
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{0xc0, 26, 0x3},
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{0xc0, 28, 0x3},
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{0xc0, 30, 0x3},
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{0xc4, 0, 0x3},
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{0xc4, 2, 0x3},
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{0xc4, 4, 0x3},
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{0xc4, 6, 0x3},
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{0xc4, 8, 0x3},
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{0xc4, 10, 0x3},
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{0xc4, 12, 0x3},
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{0xc4, 14, 0x3},
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{0xc4, 16, 0x3},
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{0xc4, 18, 0x3},
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{0xc4, 20, 0x3},
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{0xc4, 22, 0x3},
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{0xc4, 24, 0x3},
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{0xc4, 26, 0x3},
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{0xc4, 28, 0x3},
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{0xc4, 30, 0x3},
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{0xc8, 0, 0x3},
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{0xc8, 2, 0x3},
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{0xc8, 4, 0x3},
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{0xc8, 6, 0x3},
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{0xc8, 8, 0x3},
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{0xc8, 10, 0x3},
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{0xc8, 12, 0x3},
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{0xc8, 14, 0x3},
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{0xc8, 16, 0x3},
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{0xc8, 18, 0x3},
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{0xc8, 20, 0x3},
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{0xc8, 22, 0x3},
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{0xc8, 24, 0x3},
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{0xc8, 26, 0x3},
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{0xc8, 28, 0x3},
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{0xc8, 30, 0x3},
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{0xcc, 0, 0x3},
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{0xcc, 2, 0x3},
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{0xcc, 4, 0x3},
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{0xcc, 6, 0x3},
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{0xcc, 8, 0x3},
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{0xcc, 10, 0x3},
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{0xcc, 12, 0x3},
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{0xcc, 14, 0x3},
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{0xcc, 16, 0x3},
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{0xcc, 18, 0x3},
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{0xcc, 20, 0x3},
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{0xcc, 22, 0x3},
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{0xcc, 24, 0x3},
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{0xcc, 26, 0x3},
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{0xcc, 28, 0x3},
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{0xcc, 30, 0x3},
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{0xd0, 0, 0x3},
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{0xd0, 2, 0x3},
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{0xd0, 4, 0x3},
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{0xd0, 6, 0x3},
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{0xd0, 8, 0x3},
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{0xd0, 10, 0x3},
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{0xd0, 12, 0x3},
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{0xd0, 14, 0x3},
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{0xd0, 16, 0x3},
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{0xd0, 18, 0x3},
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{0xd0, 20, 0x3},
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{0xd0, 22, 0x3},
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{0xd0, 24, 0x3},
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{0xd0, 26, 0x3},
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{0xd0, 28, 0x3},
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{0xd0, 30, 0x3},
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{0xd4, 0, 0x3},
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{0xd4, 2, 0x3},
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{0xd4, 4, 0x3},
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{0xd4, 6, 0x3},
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{0xd4, 8, 0x3},
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{0xd4, 10, 0x3},
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{0xd4, 12, 0x3},
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{0xd4, 14, 0x3},
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{0xd4, 16, 0x3},
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{0xd4, 18, 0x3},
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{0xd4, 20, 0x3},
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{0xd4, 22, 0x3},
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{0xd4, 24, 0x3},
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{0xd4, 26, 0x3},
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{0xd4, 28, 0x3},
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{0xd4, 30, 0x3},
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{0xd8, 4, 0x3},
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{0xd8, 0, 0x3},
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{0xd8, 6, 0x3},
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{0xd8, 2, 0x3},
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{0xd8, 8, 0x3},
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{0xd8, 10, 0x3},
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/* pad not mux with gpio */
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};
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#define PIN_NUM ARRAY_SIZE(amt630h_pin_map)
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static xPinGroup_t pin_groups[] = {
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/* scl sda */
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{.groupid = PGRP_I2C0, .pins_num = 2, .pins = {{48, 1}, {49, 1}}},
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/* scl sda */
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{.groupid = PGRP_I2C1, .pins_num = 2, .pins = {{50, 1}, {51, 1}}},
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{.groupid = PGRP_LCD_TTL_CH0, .pins_num = 28,
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/* de clk vynsc hsync */
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.pins = {{88, 1}, {89, 1, PAD_DRIVE_2MA}, {90, 0}, {91, 0},
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{64, 1}, {65, 1}, {66, 1}, {67, 1}, {68, 1}, {69, 1}, {70, 1}, {71, 1}, /* B0-B7 */
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{72, 1}, {73, 1}, {74, 1}, {75, 1}, {76, 1}, {77, 1}, {78, 1}, {79, 1}, /* G0-G7 */
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{80, 1}, {81, 1}, {82, 1}, {83, 1}, {84, 1}, {85, 1}, {86, 1}, {87, 1},}}, /* R0-R7 */
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{.groupid = PGRP_LCD_TTL_CH1, .pins_num = 28,
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/* de clk vynsc hsync */
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.pins = {{12, 1}, {13, 1}, {14, 1}, {15, 1},
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{64, 1}, {65, 1}, {66, 1}, {67, 1}, {68, 1}, {69, 1}, {70, 1}, {71, 1}, /* r0-r7 */
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{72, 1}, {73, 1}, {74, 1}, {75, 1}, {84, 3}, {85, 3}, {86, 3}, {87, 3}, /* g0-g7 */
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{88, 3}, {89, 3}, {90, 3}, {91, 3}, {8, 1}, {9, 1}, {10, 1}, {11, 1},}}, /* b0-b7 */
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{.groupid = PGRP_LCD_LVDS, .pins_num = 10,
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/* dp dn clkp clkn cp cn bp bn */
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.pins = {{64, 2}, {65, 2}, {66, 2}, {67, 2}, {68, 2}, {69, 2}, {70, 2}, {71, 2},
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/* ap an */
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{72, 2}, {73, 2}, }},
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{.groupid = PGRP_LCD_SRGB, .pins_num = 8,
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.pins = {{74, 1}, {75, 1}, {76, 1}, {77, 1}, {78, 1}, {79, 1}, {80, 1}, {81, 1},}}, /* d0-d7 */
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/* 由于uart0有些平台rx没有接上拉电阻，需要将rx脚配置成gpio，防止收到随机数据导致异常 */
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{.groupid = PGRP_UART0, .pins_num = 2, .pins = {{38, 1}, {39, 1}}},
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/* rx tx */
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{.groupid = PGRP_UART1, .pins_num = 2, .pins = {{40, 1}, {41, 1}}},
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/* rx tx */
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{.groupid = PGRP_UART2, .pins_num = 2, .pins = {{42, 1}, {43, 1}}},
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/* rx tx */
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{.groupid = PGRP_UART3, .pins_num = 2, .pins = {{44, 1}, {45, 1}}},
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/* cs clk d0 d1 d2 d3 */
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{.groupid = PGRP_SPI0, .pins_num = 5, .pins = {/*{32, 1},*/ {33, 1}, {34, 1}, {35, 1}, {36, 1}, {37, 1}}},
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/* cs clk txd rxd */
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{.groupid = PGRP_SPI1, .pins_num = 3, .pins = {/*{23, 1},*/ {24, 1}, {25, 1}, {26, 1}}},
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{.groupid = PGRP_SDMMC0, .pins_num = 7, .pins = {{16, 1}, {17, 1}, {18, 1}, {19, 1},
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{20, 1}, {21, 1}, {22, 1}}},
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{.groupid = PGRP_PWM0, .pins_num = 1, .pins = {{0, 1}}},
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{.groupid = PGRP_PWM1, .pins_num = 1, .pins = {{1, 1}}},
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{.groupid = PGRP_PWM2, .pins_num = 1, .pins = {{6, 1}}},
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{.groupid = PGRP_PWM3, .pins_num = 1, .pins = {{47, 1}}},//47
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{.groupid = PGRP_PWM0_IN, .pins_num = 1, .pins = {{4, 0}},//pin18 GPIO4
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.mux_reg = 0x60000120, .mux_offset = 12, .mux_mask = 0x3, .mux_val = 0},
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{.groupid = PGRP_PWM1_IN, .pins_num = 1, .pins = {{5, 0}},//pin19 GPIO5
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.mux_reg = 0x60000120, .mux_offset = 14, .mux_mask = 0x3, .mux_val = 0},
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{.groupid = PGRP_PWM2_IN, .pins_num = 1, .pins = {{6, 0}},//pin47 GPIO6
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.mux_reg = 0x60000120, .mux_offset = 28, .mux_mask = 0x3, .mux_val = 0},
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{.groupid = PGRP_PWM3_IN, .pins_num = 1, .pins = {{7, 0}},//pin48 GPIO7
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.mux_reg = 0x60000120, .mux_offset = 30, .mux_mask = 0x3, .mux_val = 0},
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{.groupid = PGRP_ITU_CH0, .pins_num = 11,
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.pins = {{1, 0}, {2, 0}, {3, 0}, {4, 0}, {96, 0}, {97, 0}, {98, 0}, {99, 0}, /* d0-d7 */
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{100, 0}, {101, 0}, {0, 0}}, /* hs, vs, clk */
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.mux_reg = 0x600000dc, .mux_offset = 16, .mux_mask = 0x7, .mux_val = 2},
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{.groupid = PGRP_ITU_CH0_INV, .pins_num = 11,
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.pins = {{1, 0}, {2, 0}, {3, 0}, {4, 0}, {96, 0}, {97, 0}, {98, 0}, {99, 0}, /* d0-d7 */
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{100, 0}, {101, 0}, {0, 0}}, /* hs, vs, clk */
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.mux_reg = 0x600000dc, .mux_offset = 16, .mux_mask = 0x7, .mux_val = 6},
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{.groupid = PGRP_ITU_CH1, .pins_num = 11,
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.pins = {{8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, {14, 0}, {15, 0}, /* d0-d7 */
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{59, 0}, {60, 0}, {61, 0}}, /* hs, vs, clk */
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.mux_reg = 0x600000dc, .mux_offset = 16, .mux_mask = 0x7, .mux_val = 3},
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{.groupid = PGRP_ITU_CH1_INV, .pins_num = 11,
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.pins = {{8, 0}, {9, 0}, {10, 0}, {11, 0}, {12, 0}, {13, 0}, {14, 0}, {15, 0}, /* d0-d7 */
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{59, 0}, {60, 0}, {61, 0}}, /* hs, vs, clk */
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.mux_reg = 0x600000dc, .mux_offset = 16, .mux_mask = 0x7, .mux_val = 7},
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/* tx rx */
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{.groupid = PGRP_CAN0_CH0, .pins_num = 2, .pins = {{0, 2}, {1, 2}},
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.mux_reg = 0x600000dc, .mux_offset = 19, .mux_mask = 0x3, .mux_val = 1},
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{.groupid = PGRP_CAN0_CH1, .pins_num = 2, .pins = {{12, 2}, {13, 2}},
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.mux_reg = 0x600000dc, .mux_offset = 19, .mux_mask = 0x3, .mux_val = 2},
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{.groupid = PGRP_CAN0_CH2, .pins_num = 2, .pins = {{96, 2}, {97, 2}},
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.mux_reg = 0x600000dc, .mux_offset = 19, .mux_mask = 0x3, .mux_val = 3},
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{.groupid = PGRP_CAN1_CH0, .pins_num = 2, .pins = {{2, 2}, {3, 2}},
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.mux_reg = 0x600000dc, .mux_offset = 21, .mux_mask = 0x3, .mux_val = 1},
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{.groupid = PGRP_CAN1_CH1, .pins_num = 2, .pins = {{14, 2}, {15, 2}},
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.mux_reg = 0x600000dc, .mux_offset = 21, .mux_mask = 0x3, .mux_val = 2},
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{.groupid = PGRP_CAN1_CH2, .pins_num = 2, .pins = {{98, 2}, {99, 2}},
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.mux_reg = 0x600000dc, .mux_offset = 21, .mux_mask = 0x3, .mux_val = 3},
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{.groupid = PGRP_I2S0_PLAY, .pins_num = 4, .pins = {{52, 1, PAD_DRIVE_2MA}, {54, 1, PAD_DRIVE_2MA}, {55, 1, PAD_DRIVE_2MA}, {56, 1, PAD_DRIVE_2MA}}},
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{.groupid = PGRP_I2S0_RECORD, .pins_num = 4, .pins = {{52, 1, PAD_DRIVE_2MA}, {53, 1, PAD_DRIVE_2MA}, {55, 1, PAD_DRIVE_2MA}, {56, 1, PAD_DRIVE_2MA}}},
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{.groupid = PGRP_I2S1_PLAY, .pins_num = 4, .pins = {{23, 1, PAD_DRIVE_2MA}, {24, 1, PAD_DRIVE_2MA}, {25, 1, PAD_DRIVE_2MA}, {26, 1, PAD_DRIVE_2MA}},
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//bit2: select i2s1 function(bit[2] 0:ssp1_interface; 1:i2s1_interface).
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//bit3: i2s1 data pin output(bit[3] 0:input, 1:output).
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.mux_reg = REGS_SYSCTL_BASE + SYS_PAD_CTRL08, .mux_offset = 2, .mux_mask = 0x3, .mux_val = 3},
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{.groupid = PGRP_I2S1_RECORD, .pins_num = 4, .pins = {{23, 1, PAD_DRIVE_2MA}, {24, 1, PAD_DRIVE_2MA}, {25, 1, PAD_DRIVE_2MA}, {26, 1, PAD_DRIVE_2MA}},
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//bit2: select i2s1 function(bit[2] 0:ssp1_interface; 1:i2s1_interface).
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//bit3: i2s1 data pin input(bit[3] 0:input, 1:output).
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.mux_reg = REGS_SYSCTL_BASE + SYS_PAD_CTRL08, .mux_offset = 2, .mux_mask = 0x3, .mux_val = 1},
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{.groupid = PGRP_RCRT, .pins_num = 1, .pins = {{57, 1}}},
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};
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#define GROUP_NUM ARRAY_SIZE(pin_groups)
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static __INLINE void pinctrl_set_pin(int npin, int val, int drive)
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{
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xPinmap_t *pctrl;
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uint32_t reg;
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if (npin >= PIN_NUM)
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return;
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pctrl = &amt630h_pin_map[npin];
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reg = readl(PINCTL_REG_BASE + pctrl->reg);
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reg &= ~(pctrl->mask << pctrl->offset);
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reg |= val << pctrl->offset;
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writel(reg, PINCTL_REG_BASE + pctrl->reg);
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if (drive != PAD_DRIVE_DEFAULT) {
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uint32_t drv_reg = SYS_IO_DRIVER00 + npin / 16 * 4;
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uint32_t offset = (npin % 16) * 2;
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uint32_t drv_val = drive - 1;
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vSysctlConfigure(drv_reg, offset, 3, drv_val);
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}
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}
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void pinctrl_gpio_request(int gpio)
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{
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pinctrl_set_pin(gpio, 0, PAD_DRIVE_DEFAULT);
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}
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void pinctrl_set_group(int groupid)
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{
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int i, j;
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xPinGroup_t *pgrp;
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uint32_t reg;
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for (i = 0; i < GROUP_NUM; i++) {
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pgrp = &pin_groups[i];
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if (pgrp->groupid == groupid) {
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configASSERT(pgrp->pins_num <= MAX_PINS_PER_GROUP);
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for (j = 0; j < pgrp->pins_num; j++)
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pinctrl_set_pin(pgrp->pins[j].muxio, pgrp->pins[j].pinval,
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pgrp->pins[j].drive);
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if (pgrp->mux_reg) {
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reg = readl(pgrp->mux_reg);
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reg &= ~(pgrp->mux_mask << pgrp->mux_offset);
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reg |= pgrp->mux_val << pgrp->mux_offset;
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writel(reg, pgrp->mux_reg);
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}
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break;
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}
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}
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}
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void vPinctrlSetup(void)
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{
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#ifdef HW_I2C0_SUPPORT
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pinctrl_set_group(PGRP_I2C0);
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#endif
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#ifdef HW_I2C1_SUPPORT
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pinctrl_set_group(PGRP_I2C1);
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#endif
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pinctrl_set_group(PGRP_UART0);
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pinctrl_set_group(PGRP_UART2);
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#ifdef PWM_CAP_SUPPORT
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pinctrl_set_group(PGRP_PWM2_IN);
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#endif
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#if 0
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/* 高速串口先初始化再配置pad脚(放在vUartInit()函数中初始化)，否则在初始化过程中收到数据会导致串口出错 */
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pinctrl_set_group(PGRP_UART1);
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pinctrl_set_group(PGRP_UART3);
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#endif
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pinctrl_set_group(PGRP_SPI0);
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pinctrl_set_group(PGRP_SPI1);
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pinctrl_set_group(PGRP_SDMMC0);
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#ifdef REMOTE_SUPPORT
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pinctrl_set_group(PGRP_RCRT);
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#endif
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#if LCD_INTERFACE_TYPE == LCD_INTERFACE_TTL
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pinctrl_set_group(PGRP_LCD_TTL_CH0);
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#elif LCD_INTERFACE_TYPE == LCD_INTERFACE_LVDS
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pinctrl_set_group(PGRP_LCD_LVDS);
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#endif
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pinctrl_set_group(PGRP_ITU_CH1_INV);
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pinctrl_set_group(PGRP_CAN0_CH0);
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#ifdef AUDIO_REPLAY
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#if (AUDIO_REPLAY_I2S == I2S_ID1)
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pinctrl_set_group(PGRP_I2S1_PLAY);
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#else
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pinctrl_set_group(PGRP_I2S0_PLAY);
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#endif
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#endif
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#ifdef AUDIO_RECORD
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#if (AUDIO_RECORD_I2S == I2S_ID1)
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pinctrl_set_group(PGRP_I2S1_RECORD);
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#else
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pinctrl_set_group(PGRP_I2S0_RECORD);
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#endif
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#endif
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pinctrl_set_group(PGRP_PWM2);
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pinctrl_set_group(PGRP_PWM3);
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}
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