298 lines
11 KiB
C
298 lines
11 KiB
C
/*
|
|
**********************************************************************
|
|
Copyright (c)2007 Arkmicro Technologies Inc. All Rights Reserved
|
|
Filename: sdmmc.h
|
|
Version : 1.1
|
|
Date : 2008.01.08
|
|
Author : wx(Modify by Salem)
|
|
Abstract: ark1610 soc sd driver
|
|
History :
|
|
***********************************************************************
|
|
*/
|
|
#ifndef SDMMC_H
|
|
#define SDMMC_H
|
|
|
|
|
|
#define SD_DEBUG 0
|
|
|
|
|
|
typedef unsigned long ulong;
|
|
typedef ulong lbaint_t;
|
|
|
|
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
|
|
|
|
|
|
#define SDMMC_RW_SUCCES 0
|
|
#define SDMMC_RW_TIMEOUT -1
|
|
#define SDMMC_RW_DMAREAD_FAIL -2
|
|
#define SDMMC_RW_DMAWRITE_FAIL -3
|
|
#define SDMMC_RW_CMDTIMEROUT -4
|
|
|
|
|
|
#define PWREN_ON 0x00000000 //turn on all card power
|
|
#define PWREN_OFF 0xFFFFFFFF //turn off all card power
|
|
#define CLK_CLKEN 0x0000ffff //
|
|
#define CLK_CLKDIS 0x00000000 // disable clk
|
|
#define CLK_DIV_INITIAL 0x00000010 //initial choose frequency
|
|
#define CLK_DIV_NORMAL 0x00000000 //data transfers clk frequency
|
|
#define CLK_SRC 0x00000000 //
|
|
#define CMD_CHANG_CLK 0x80202000 //chang clk
|
|
#define CMD_INITIAL_CLK 0x80008000 //initial clk before work
|
|
#define CMD0_GO_IDLE 0x80000000 //go idle
|
|
#define CMD1_MATCH_VCC 0x80000041 //turn on for match vcc
|
|
#define CMD2_CID 0x800001c2 //initial card get CID
|
|
#define CMD3_RCA 0x80000143 //comfire RCA to card
|
|
#define CMD6_SWTICH 0x80000346 //switch function
|
|
#define CMD7_SELECT_CARD 0x80000147 //select card
|
|
#define CMD8_SPEC 0x80000048 //confire specfic
|
|
#define CMD9_CSD 0x800001c9 //get CSD
|
|
#define CMD10_CID 0x800001ca //get CID at transfers
|
|
#define CMD12_STOP_STEARM 0x8000004c //stop block transfers
|
|
#define CMD13_STATUS_CARD 0x8000014D //get card status
|
|
#define CMD15_INACTIVE 0x8000000F //make card to inactive
|
|
#define CMD16_SET_BLOCKLEN 0x80000150 //set card block length
|
|
#define CMD17_READ_SINGLE 0x80000351 //single block read
|
|
#define CMD18_READ_MUL 0x80001352 //multipe block read
|
|
#define CMD23_PRE_ERASE 0x80000157 //pre erase for write
|
|
#define CMD24_WRITE_SINGLE 0x80000758 //single block write
|
|
#define CMD25_WRITE_MUL 0x80000759 //multipe block write
|
|
#define CMD27_PROG_CSD 0x8000065b //programme csd
|
|
#define CMD28_SET_PROTECT 0x8000015c //set protect
|
|
#define CMD29_CLR_PROTECT 0x8000015d //clearn protect
|
|
#define CMD30_SEND_WRITE 0x8000025e //get the status about protect
|
|
#define CMD32_ERASESD_START 0x80000160 //set start erase SD card address
|
|
#define CMD33_ERASESD_END 0x80000161 //set end erase SD card address
|
|
#define CMD38_ERASE 0x80000166 //confirm erase
|
|
#define CMD41_MATCH_VCC 0x80000169 //FOR SD
|
|
#define CMD55_APP 0x80000177 //APP CMD
|
|
#define ACMD6_WID 0x80000146 //set bus width
|
|
#define ACMD13_GET_STATUS 0x8000024d //get status 512 bit
|
|
#define ACMD42_DISCON_DATA3 0x8000016a //make data3 disconnect
|
|
#define ACMD51_GET_CSR 0x80000273 //get card csr
|
|
//=======================MMC set bus==========================
|
|
#define CMD6_SWITH 0x80000446 //set bus width
|
|
//================================================
|
|
|
|
#define MMC_ERASE_ARG 0x00000000
|
|
|
|
|
|
#define MMC_CMD_GO_IDLE_STATE 0
|
|
#define MMC_CMD_SEND_OP_COND 1
|
|
#define MMC_CMD_ALL_SEND_CID 2
|
|
#define MMC_CMD_SET_RELATIVE_ADDR 3
|
|
#define MMC_CMD_SET_DSR 4
|
|
#define MMC_CMD_SWITCH 6
|
|
#define MMC_CMD_SELECT_CARD 7
|
|
#define MMC_CMD_SEND_EXT_CSD 8
|
|
#define MMC_CMD_SEND_CSD 9
|
|
#define MMC_CMD_SEND_CID 10
|
|
#define MMC_CMD_STOP_TRANSMISSION 12
|
|
#define MMC_CMD_SEND_STATUS 13
|
|
#define MMC_CMD_SET_BLOCKLEN 16
|
|
#define MMC_CMD_READ_SINGLE_BLOCK 17
|
|
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
|
|
#define MMC_CMD_SEND_TUNING_BLOCK 19
|
|
#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
|
|
#define MMC_CMD_SET_BLOCK_COUNT 23
|
|
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
|
|
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
|
|
#define MMC_CMD_ERASE_GROUP_START 35
|
|
#define MMC_CMD_ERASE_GROUP_END 36
|
|
#define MMC_CMD_ERASE 38
|
|
#define MMC_CMD_APP_CMD 55
|
|
#define MMC_CMD_SPI_READ_OCR 58
|
|
#define MMC_CMD_SPI_CRC_ON_OFF 59
|
|
#define MMC_CMD_RES_MAN 62
|
|
|
|
#define MMC_CMD62_ARG1 0xefac62ec
|
|
#define MMC_CMD62_ARG2 0xcbaea7
|
|
|
|
|
|
#define SD_CMD_SEND_RELATIVE_ADDR 3
|
|
#define SD_CMD_SWITCH_FUNC 6
|
|
#define SD_CMD_SEND_IF_COND 8
|
|
#define SD_CMD_SWITCH_UHS18V 11
|
|
|
|
#define SD_CMD_APP_SET_BUS_WIDTH 6
|
|
#define SD_CMD_APP_SD_STATUS 13
|
|
#define SD_CMD_ERASE_WR_BLK_START 32
|
|
#define SD_CMD_ERASE_WR_BLK_END 33
|
|
#define SD_CMD_APP_SEND_OP_COND 41
|
|
#define SD_CMD_APP_SEND_SCR 51
|
|
|
|
#define MMC_RSP_PRESENT (1 << 0)
|
|
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
|
|
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
|
|
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
|
|
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
|
|
|
|
#define MMC_RSP_NONE (0)
|
|
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
|
#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
|
|
MMC_RSP_BUSY)
|
|
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
|
|
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
|
|
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
|
|
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
|
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
|
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
|
|
|
#define OCR_BUSY 0x80000000
|
|
#define OCR_HCS 0x40000000
|
|
#define OCR_S18R 0x1000000
|
|
#define OCR_VOLTAGE_MASK 0x007FFF80
|
|
#define OCR_ACCESS_MODE 0x60000000
|
|
|
|
#define MMC_STATUS_MASK (~0x0206BF7F)
|
|
#define MMC_STATUS_SWITCH_ERROR (1 << 7)
|
|
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
|
|
#define MMC_STATUS_CURR_STATE (0xf << 9)
|
|
#define MMC_STATUS_ERROR (1 << 19)
|
|
|
|
#define MMC_STATE_PRG (7 << 9)
|
|
|
|
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
|
|
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
|
|
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
|
|
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
|
|
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
|
|
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
|
|
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
|
|
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
|
|
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
|
|
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
|
|
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
|
|
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
|
|
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
|
|
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
|
|
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
|
|
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
|
|
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
|
|
|
|
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
|
|
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
|
|
addressed by index which are
|
|
1 in value field */
|
|
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
|
|
addressed by index, which are
|
|
1 in value field */
|
|
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
|
|
|
|
#define SD_SWITCH_CHECK 0
|
|
#define SD_SWITCH_SWITCH 1
|
|
|
|
/*
|
|
* EXT_CSD fields
|
|
*/
|
|
#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
|
|
#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
|
|
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
|
|
#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
|
|
#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
|
|
#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
|
|
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
|
|
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
|
|
#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
|
|
#define EXT_CSD_WR_REL_PARAM 166 /* R */
|
|
#define EXT_CSD_WR_REL_SET 167 /* R/W */
|
|
#define EXT_CSD_RPMB_MULT 168 /* RO */
|
|
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
|
|
#define EXT_CSD_BOOT_BUS_WIDTH 177
|
|
#define EXT_CSD_PART_CONF 179 /* R/W */
|
|
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
|
|
#define EXT_CSD_HS_TIMING 185 /* R/W */
|
|
#define EXT_CSD_REV 192 /* RO */
|
|
#define EXT_CSD_CARD_TYPE 196 /* RO */
|
|
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
|
|
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
|
|
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
|
|
#define EXT_CSD_BOOT_MULT 226 /* RO */
|
|
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
|
|
|
|
/*
|
|
* EXT_CSD field definitions
|
|
*/
|
|
|
|
#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
|
|
#define EXT_CSD_CMD_SET_SECURE (1 << 1)
|
|
#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
|
|
|
|
#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
|
|
#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
|
|
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
|
|
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
|
|
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
|
|
| EXT_CSD_CARD_TYPE_DDR_1_2V)
|
|
|
|
#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
|
|
/* SDR mode @1.8V I/O */
|
|
#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
|
|
/* SDR mode @1.2V I/O */
|
|
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
|
|
EXT_CSD_CARD_TYPE_HS200_1_2V)
|
|
|
|
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
|
|
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
|
|
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
|
|
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
|
|
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
|
|
#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
|
|
|
|
#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
|
|
#define EXT_CSD_TIMING_HS 1 /* HS */
|
|
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
|
|
|
|
#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
|
|
#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
|
|
#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
|
|
#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
|
|
|
|
#define EXT_CSD_BOOT_ACK(x) (x << 6)
|
|
#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
|
|
#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
|
|
|
|
#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
|
|
#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
|
|
#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
|
|
|
|
#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
|
|
#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
|
|
#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
|
|
|
|
#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
|
|
|
|
#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
|
|
#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
|
|
|
|
#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
|
|
|
|
#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
|
|
#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
|
|
|
|
|
|
#define MMC_DATA_READ 1
|
|
#define MMC_DATA_WRITE 2
|
|
|
|
/* Maximum block size for MMC */
|
|
#define MMC_MAX_BLOCK_LEN 512
|
|
|
|
struct mmc_cmd {
|
|
USHORT cmdidx;
|
|
UINT resp_type;
|
|
UINT cmdarg;
|
|
UINT response[4];
|
|
};
|
|
|
|
struct mmc_data {
|
|
union {
|
|
char *dest;
|
|
const char *src; /* src buffers don't get written to */
|
|
};
|
|
UINT flags;
|
|
UINT blocks;
|
|
UINT blocksize;
|
|
};
|
|
|
|
#endif
|
|
|