165 lines
7.0 KiB
C
165 lines
7.0 KiB
C
/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2011, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#ifndef _CP15_H
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#define _CP15_H
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/*----------------------------------------------------------------------------
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* Definition
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*----------------------------------------------------------------------------*/
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#define CP15_L4_BIT 15 // Determines if the T bit is set when load instructions
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// change the PC:
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// 0 = loads to PC set the T bit
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// 1 = loads to PC do not set T bit
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#define CP15_RR_BIT 14 // RR bit Replacement strategy for Icache and Dcache:
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// 0 = Random replacement
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// 1 = Round-robin replacement.
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#define CP15_V_BIT 13 // V bit Location of exception vectors:
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// 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C
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// 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C
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#define CP15_I_BIT 12 // I bit Icache enable/disable:
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// 0 = Icache disabled
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// 1 = Icache enabled
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#define CP15_R_BIT 9 // R bit ROM protection
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#define CP15_S_BIT 8 // S bit System protection
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#define CP15_B_BIT 7 // B bit Endianness:
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// 0 = Little-endian operation
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// 1 = Big-endian operation.
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#define CP15_C_BIT 2 // C bit Dcache enable/disable:
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// 0 = cache disabled
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// 1 = cache enabled
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#define CP15_A_BIT 1 // A bit Alignment fault enable/disable:
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// 0 = Data address alignment fault checking disabled
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// 1 = Data address alignment fault checking enabled
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#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled.
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// 0 = disabled
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// 1 = enabled
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/** No access Any access generates a domain fault. */
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#define CP15_DOMAIN_NO_ACCESS 0x00
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/** Client Accesses are checked against the access permission bits in the section or page descriptor. */
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#define CP15_DOMAIN_CLIENT_ACCESS 0x01
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/** Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated. */
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#define CP15_DOMAIN_MANAGER_ACCESS 0x03
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#define CP15_ICache 1
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#define CP15_DCache 0
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#define CP15_PMCNTENSET_ENABLE 31
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#define CP15_PMCR_DIVIDER 3
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#define CP15_PMCR_RESET 2
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#define CP15_PMCR_ENABLE 0
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/*------------------------------------------------------------------------------ */
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/* Exported functions */
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/*------------------------------------------------------------------------------ */
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extern unsigned int CP15_ReadID(void);
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extern unsigned int CP15_ReadControl(void);
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extern void CP15_ExclusiveCache(void);
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extern void CP15_NonExclusiveCache(void);
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extern void CP15_ISB(void);
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extern void CP15_DSB(void);
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extern void CP15_DMB(void);
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extern void CP15_SelectDCache(void);
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extern void CP15_SelectICache(void);
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extern void CP15_WriteControl(unsigned int value);
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extern void CP15_WriteTTB(unsigned int value);
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extern void CP15_WriteDomainAccessControl(unsigned int value);
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extern void CP15_InvalidateIcacheInnerSharable(void);
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extern void CP15_InvalidateBTBinnerSharable(void);
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extern void CP15_InvalidateIcache(void);
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extern void CP15_InvalidateIcacheByMva(void);
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extern void CP15_InvalidateBTB(void);
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extern void CP15_InvalidateBTBbyMva(uint32_t VA_Addr);
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extern void CP15_InvalidateDcacheBySetWay(void);
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extern void CP15_CleanDCacheBySetWay(void);
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extern void CP15_CleanInvalidateDCacheBySetWay(void);
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extern void CP15_InvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr );
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extern void CP15_CleanDCacheByMva(uint32_t startAddr, uint32_t endAddr );
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extern void CP15_CleanInvalidateDcacheByMva(uint32_t startAddr, uint32_t endAddr );
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extern void CP15_CleanDCacheUMva(void);
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extern void CP15_InvalidateTranslationTable(void);
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extern void CP15_coherent_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
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extern void CP15_invalidate_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
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extern void CP15_clean_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
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extern void CP15_flush_dcache_for_dma (uint32_t startAddr, uint32_t endAddr );
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extern void CP15_flush_kern_dcache_for_dma (uint32_t startAddr, uint32_t size );
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/*------------------------------------------------------------------------------ */
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/* Exported functions from CP15.c */
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/*------------------------------------------------------------------------------ */
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/** MMU (Status/Enable/Disable) */
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extern unsigned int CP15_IsMMUEnabled(void);
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extern void CP15_EnableMMU(void);
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extern void CP15_DisableMMU(void);
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/** I cache (Status/Enable/Disable) */
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extern unsigned int CP15_IsIcacheEnabled(void);
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extern void CP15_EnableIcache(void);
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extern void CP15_DisableIcache(void);
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/** D cache (Status/Enable/Disable) */
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extern unsigned int CP15_IsDcacheEnabled(void);
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extern void CP15_EnableDcache(void);
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extern void CP15_DisableDcache(void);
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extern void CP15_InvalidateTLB(void);
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extern void CP15_CacheClean(uint8_t CacheType);
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extern void CP15_CacheInvalidate(uint8_t CacheType);
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extern void CP15_CacheFlush(uint8_t CacheType);
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extern void CP15_InvalidateDCacheByVA(uint32_t S_Add, uint32_t E_Add);
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extern void CP15_CleanDCacheByVA(uint32_t S_Add, uint32_t E_Add);
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extern void CP15_FlushDCacheByVA(uint32_t S_Add, uint32_t E_Add);
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#endif // #ifndef _CP15_H
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