70 lines
1.0 KiB
C
70 lines
1.0 KiB
C
#ifndef _CLOCK_H
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#define _CLOCK_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MAX_CLK_SOURCE_NUM 4
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#define MAX_CLK_ENABLE_BITS 4
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typedef enum {
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CLK_XTAL32K = 0,
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CLK_XTAL24M,
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CLK_240MHZ,
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CLK_12MHZ,
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CLK_6MHZ,
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CLK_CPUPLL,
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CLK_SYSPLL,
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CLK_VPUPLL,
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CLK_DDRPLL,//Ôö¼ÓDDR PLL
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CLK_DDR,
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CLK_CPU,
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CLK_H2X,
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CLK_AHB,
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CLK_APB,
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CLK_RTC,
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CLK_SPI0,
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CLK_SPI1,
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CLK_SDMMC0,
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CLK_LCD,
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CLK_UART1,
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CLK_UART2,
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CLK_UART3,
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CLK_TIMER,
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CLK_MFC,
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CLK_PWM,
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CLK_CAN0,
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CLK_CAN1,
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CLK_ADC,
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CLK_I2S,
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CLK_I2S1,
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}eClockID;
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typedef enum {
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FIXED_CLOCK = 0,
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FIXED_FACTOR_CLOCK,
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PLL_CLOCK,
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SYS_CLOCK,
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}eClockType;
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typedef enum {
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DIVMODE_NOZERO = 0, /* div = div ? div : 1 */
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DIVMODE_PLUSONE, /* div = div + 1 */
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DIVMODE_DOUBLE, /* div = div * 2 */
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DIVMODE_EXPONENT, /* div = 1 << div */
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DIVMODE_PONEDOUBLE, /* div = (div + 1) * 2 */
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}eDivMode;
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void vClkInit(void);
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uint32_t ulClkGetRate(uint32_t clkid);
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void vClkSetRate(uint32_t clkid, uint32_t freq);
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void vClkEnable(uint32_t clkid);
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void vClkDisable(uint32_t clkid);
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#ifdef __cplusplus
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}
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#endif
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#endif
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