232 lines
6.8 KiB
C
232 lines
6.8 KiB
C
#ifndef _SDMMC_H
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#define _SDMMC_H
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#define MMC_FEQ_MIN 400000
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#define MMC_FEQ_MAX 25000000
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#define CARD_UNPLUGED 1
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#define CARD_PLUGED 0
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enum {
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TRANS_MODE_PIO = 0,
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TRANS_MODE_IDMAC,
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TRANS_MODE_EDMAC
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};
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struct dw_mci_dma_slave {
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struct dma_chan *ch;
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enum dma_transfer_direction direction;
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};
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#define SDMMC_CTRL 0x000
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#define SDMMC_PWREN 0x004
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#define SDMMC_CLKDIV 0x008
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#define SDMMC_CLKSRC 0x00c
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#define SDMMC_CLKENA 0x010
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#define SDMMC_TMOUT 0x014
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#define SDMMC_CTYPE 0x018
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#define SDMMC_BLKSIZ 0x01c
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#define SDMMC_BYTCNT 0x020
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#define SDMMC_INTMASK 0x024
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#define SDMMC_CMDARG 0x028
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#define SDMMC_CMD 0x02c
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#define SDMMC_RESP0 0x030
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#define SDMMC_RESP1 0x034
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#define SDMMC_RESP2 0x038
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#define SDMMC_RESP3 0x03c
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#define SDMMC_MINTSTS 0x040
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#define SDMMC_RINTSTS 0x044
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#define SDMMC_STATUS 0x048
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#define SDMMC_FIFOTH 0x04c
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#define SDMMC_CDETECT 0x050
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#define SDMMC_WRTPRT 0x054
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#define SDMMC_GPIO 0x058
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#define SDMMC_TCBCNT 0x05c
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#define SDMMC_TBBCNT 0x060
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#define SDMMC_DEBNCE 0x064
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#define SDMMC_USRID 0x068
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#define SDMMC_VERID 0x06c
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#define SDMMC_HCON 0x070
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#define SDMMC_UHS_REG 0x074
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#define SDMMC_RST_N 0x078
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#define SDMMC_BMOD 0x080
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#define SDMMC_PLDMND 0x084
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#define SDMMC_DBADDR 0x088
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#define SDMMC_IDSTS 0x08c
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#define SDMMC_IDINTEN 0x090
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#define SDMMC_DSCADDR 0x094
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_FIFO 0x100
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#define SDMMC_DATA(x) (x)
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#define SDMMC_FIFO_DEPTH 32
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/* Control register defines */
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#define SDMMC_CTRL_USE_IDMAC BIT(25)
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#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
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#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
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#define SDMMC_CTRL_SEND_CCSD BIT(9)
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#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
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#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
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#define SDMMC_CTRL_READ_WAIT BIT(6)
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#define SDMMC_CTRL_DMA_ENABLE BIT(5)
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#define SDMMC_CTRL_INT_ENABLE BIT(4)
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#define SDMMC_CTRL_DMA_RESET BIT(2)
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#define SDMMC_CTRL_FIFO_RESET BIT(1)
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#define SDMMC_CTRL_RESET BIT(0)
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/* Clock Enable register defines */
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#define SDMMC_CLKEN_LOW_PWR BIT(16)
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#define SDMMC_CLKEN_ENABLE BIT(0)
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/* time-out register defines */
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#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
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#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
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#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
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#define SDMMC_TMOUT_RESP_MSK 0xFF
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/* card-type register defines */
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#define SDMMC_CTYPE_8BIT BIT(16)
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#define SDMMC_CTYPE_4BIT BIT(0)
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#define SDMMC_CTYPE_1BIT 0
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/* Interrupt status & mask register defines */
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#define SDMMC_INT_SDIO BIT(16)
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#define SDMMC_INT_EBE BIT(15)
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#define SDMMC_INT_ACD BIT(14)
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#define SDMMC_INT_SBE BIT(13)
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#define SDMMC_INT_HLE BIT(12)
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#define SDMMC_INT_FRUN BIT(11)
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#define SDMMC_INT_HTO BIT(10)
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#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
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#define SDMMC_INT_DRTO BIT(9)
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#define SDMMC_INT_RTO BIT(8)
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#define SDMMC_INT_DCRC BIT(7)
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#define SDMMC_INT_RCRC BIT(6)
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#define SDMMC_INT_RXDR BIT(5)
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#define SDMMC_INT_TXDR BIT(4)
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#define SDMMC_INT_DATA_OVER BIT(3)
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#define SDMMC_INT_CMD_DONE BIT(2)
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#define SDMMC_INT_RESP_ERR BIT(1)
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#define SDMMC_INT_CD BIT(0)
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#define SDMMC_INT_ALL (~0)
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#define SDMMC_INT_DATA_ERROR (SDMMC_INT_DCRC | SDMMC_INT_SBE | SDMMC_INT_EBE)
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#define SDMMC_INT_STATUS_DATA (SDMMC_INT_DATA_OVER | SDMMC_INT_DATA_ERROR \
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| SDMMC_INT_TXDR | SDMMC_INT_RXDR)
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/* Common flag combinations */
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#define SDMMC_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
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SDMMC_INT_HTO | SDMMC_INT_SBE | \
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SDMMC_INT_EBE | SDMMC_INT_HLE)
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#define SDMMC_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
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SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
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#define SDMMC_ERROR_FLAGS (SDMMC_DATA_ERROR_FLAGS | \
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SDMMC_CMD_ERROR_FLAGS)
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#define SDMMC_INT_ERROR 0xbfc2
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/* Command register defines */
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#define SDMMC_CMD_START BIT(31)
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#define SDMMC_CMD_USE_HOLD_REG BIT(29)
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#define SDMMC_CMD_VOLT_SWITCH BIT(28)
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#define SDMMC_CMD_CCS_EXP BIT(23)
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#define SDMMC_CMD_CEATA_RD BIT(22)
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#define SDMMC_CMD_UPD_CLK BIT(21)
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#define SDMMC_CMD_INIT BIT(15)
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#define SDMMC_CMD_STOP BIT(14)
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#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
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#define SDMMC_CMD_SEND_STOP BIT(12)
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#define SDMMC_CMD_STRM_MODE BIT(11)
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#define SDMMC_CMD_DAT_WR BIT(10)
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#define SDMMC_CMD_DAT_EXP BIT(9)
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#define SDMMC_CMD_RESP_CRC BIT(8)
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#define SDMMC_CMD_RESP_LONG BIT(7)
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#define SDMMC_CMD_RESP_EXP BIT(6)
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#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
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/* Status register defines */
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#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
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#define SDMMC_STATUS_DMA_REQ BIT(31)
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#define SDMMC_STATUS_BUSY BIT(9)
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/* FIFOTH register defines */
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#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
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((r) & 0xFFF) << 16 | \
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((t) & 0xFFF))
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/* HCON register defines */
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#define DMA_INTERFACE_IDMA (0x0)
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#define DMA_INTERFACE_DWDMA (0x1)
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#define DMA_INTERFACE_GDMA (0x2)
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#define DMA_INTERFACE_NODMA (0x3)
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#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
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#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
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#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
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#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
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/* Internal DMAC interrupt defines */
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#define SDMMC_IDMAC_INT_AI BIT(9)
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#define SDMMC_IDMAC_INT_NI BIT(8)
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#define SDMMC_IDMAC_INT_CES BIT(5)
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#define SDMMC_IDMAC_INT_DU BIT(4)
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#define SDMMC_IDMAC_INT_FBE BIT(2)
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#define SDMMC_IDMAC_INT_RI BIT(1)
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#define SDMMC_IDMAC_INT_TI BIT(0)
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/* Internal DMAC bus mode bits */
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#define SDMMC_IDMAC_ENABLE BIT(7)
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#define SDMMC_IDMAC_FB BIT(1)
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#define SDMMC_IDMAC_SWRESET BIT(0)
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/* H/W reset */
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#define SDMMC_RST_HWACTIVE 0x1
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/* Version ID register define */
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#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
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/* Card read threshold */
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#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
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#define SDMMC_CARD_WR_THR_EN BIT(2)
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#define SDMMC_CARD_RD_THR_EN BIT(0)
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/* UHS-1 register defines */
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#define SDMMC_UHS_18V BIT(0)
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/* All ctrl reset bits */
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#define SDMMC_CTRL_ALL_RESET_FLAGS \
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(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
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struct mmc_driver
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{
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uint32_t max_desc;
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struct mmcsd_host *host;
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struct mmcsd_req *req;
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struct mmcsd_data *data;
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struct mmcsd_cmd *cmd;
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void* priv;
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};
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struct ark_mmc_obj;
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/* DMA ops for Internal/External DMAC interface */
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struct dw_mci_dma_ops {
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/* DMA Ops */
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int (*init)(struct ark_mmc_obj *mmc_obj);
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int (*start)(struct ark_mmc_obj *mmc_obj, struct mmcsd_data *data);
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void (*stop)(struct ark_mmc_obj *mmc_obj);
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void (*cleanup)(struct ark_mmc_obj *mmc_obj);
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void (*exit)(struct ark_mmc_obj *mmc_obj);
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};
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struct ark_mmc_obj
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{
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uint32_t id;
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uint32_t irq;
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uint32_t base;
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uint32_t power_pin_gpio;
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uint32_t fifoth_val;
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uint32_t prev_blksz;
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int result;
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int use_dma;
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int using_dma;
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int dma_args[3];
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struct dw_mci_dma_ops *dma_ops;
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struct dw_mci_dma_slave *dms;
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struct mmcsd_data *data;
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QueueHandle_t transfer_completion;
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char *tx_dummy_buffer;
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char *rx_dummy_buffer;
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int dummy_buffer_used;
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void (*mmc_reset)(struct ark_mmc_obj *);
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};
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#endif /* _SDMMC_H */
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