260 lines
9.8 KiB
C
260 lines
9.8 KiB
C
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/*
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******************************************************************************
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* @file fr30xx.h
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* @author FreqChip Firmware Team
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* @brief CMSIS fr30xx Device Peripheral Access Layer Header File.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Configuration of the Processor and Core Peripherals
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __FR30XX_H__
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#define __FR30XX_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @group Peripheral_interrupt_number_definition
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* @{
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*/
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#if defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
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typedef enum IRQn
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{
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/****** Cortex-M33 Processor Exceptions Numbers ************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M33 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M33 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M33 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M33 System Tick Interrupt */
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/****** CMSDK Specific Interrupt Numbers *******************************************************/
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TIMER0_IRQn = 0, /*!< */
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TIMER1_IRQn = 1, /*!< */
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TIMER2_IRQn = 2, /*!< */
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TIMER3_IRQn = 3, /*!< */
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DMA0_IRQn = 4,
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DMA1_IRQn = 5, /*!< */
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SDIOH0_IRQn = 6, /*!< */
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SDIOH1_IRQn = 7, /*!< */
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IPC_MCU_IRQn = 8, /*!< */
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USBOTG_IRQn = 9, /*!< */
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IIR_IRQn = 10, /*!< */
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BLEND_IRQn = 11, /*!< */
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FFT_IRQn = 12, /*!< */
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SEC_AES_IRQn = 13, /*!< */
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GPIOA_IRQn = 16, /*!< */
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GPIOB_IRQn = 17, /*!< */
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GPIOC_IRQn = 18, /*!< */
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GPIOD_IRQn = 19, /*!< */
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UART0_IRQn = 20, /*!< */
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UART1_IRQn = 21, /*!< */
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UART2_IRQn = 22, /*!< */
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UART3_IRQn = 23, /*!< */
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UART4_IRQn = 24,
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UART5_IRQn = 25,
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I2C0_IRQn = 26,
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I2C1_IRQn = 27,
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I2C2_IRQn = 28,
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I2C3_IRQn = 29,
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I2C4_IRQn = 30,
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I2C5_IRQn = 31,
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SPIM0_IRQn = 32,
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SPIM1_IRQn = 33,
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SPIM2_IRQn = 34,
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SPIS0_IRQn = 35,
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SPIS1_IRQn = 36,
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SPIMX8_0_IRQn = 37,
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SPIMX8_1_IRQn = 38,
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I2S0_IRQn = 39,
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I2S1_IRQn = 40,
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I2S2_IRQn = 41,
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PDM0_IRQn = 42,
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PDM1_IRQn = 43,
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PDM2_IRQn = 44,
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ADC_IRQn = 45,
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CODEC_IRQn = 46,
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SPDIF_IRQn = 47,
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SBCDEC_IRQn = 48,
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SBCENC_IRQn = 49,
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MP3DEC_IRQn = 50,
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PARALLEL_IRQn = 51,
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CALI_IRQn = 53,
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TRNG_IRQn = 54,
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TICK_IRQn = 55,
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TIMER4_IRQn = 60,
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TIMER5_IRQn = 61,
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IPC_DSP_IRQn = 63,
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YUV2RGB_IRQn = 64,
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PMU_IRQn = 65,
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}IRQn_Type;
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#endif // defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
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#ifdef __XTENSA__
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typedef enum IRQn
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{
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DSP_IPC_IRQn = 7,
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}IRQn_Type;
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#endif // __XTENSA__
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/**
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* @}
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*/
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#if defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
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/**
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* @brief Configuration of the Processor and Core Peripherals
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*/
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#define __CM33_REV 0x0003U /*!< Core revision r0p4 */
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#define __SAUREGION_PRESENT 0 /*!< SAU regions present */
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#define __MPU_PRESENT 1 /*!< MPU present */
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#define __VTOR_PRESENT 1 /*!< VTOR present */
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#define __FPU_PRESENT 1 /*!< FPU present or not */
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#define __DSP_PRESENT 1 /*!< DSP present or not */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#include "core_cm33.h"
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#if __SAUREGION_PRESENT == 1
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#include "arm_cmse.h"
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#endif
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#endif // defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
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#ifdef __XTENSA__
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#define __WEAK __attribute__((weak))
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#define __STATIC_INLINE __attribute__((always_inline))
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#endif // __XTENSA__
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/** @group Peripheral_memory_map
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* @{
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*/
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#define FLASH_DAC_BASE (0x08000000)
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#define DMAC0_BASE (0x10000000)
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#define USB_OTG_BASE (0x10010000)
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#define APB_BASE (0x10100000)
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#define SBC_DEC_BASE (0x10100000)
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#define SBC_ENC_BASE (0x10110000)
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#define MP3_DEC_BASE (0x10120000)
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#define CRC_BASE (0x10130000)
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#define EFUSE_SISO_BASE (0x10140000)
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#define EFUSE_PIPO_BASE (0x10150000)
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#define SYSTEM_TIMER_BASE (0x10160000)
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#define FREE_COUNTER_BASE (0x10170000)
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#define CAN0_BASE (0x10180000)
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#define CAN1_BASE (0x10190000)
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#define SEC_BASE (0x11000000)
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#define DSP_FLASH_DAC_BASE (0x28000000)
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#define PSRAM_DAC_BASE (0x38000000)
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#define SDIOH0_BASE (0x40000000)
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#define SDIOH1_BASE (0x40010000)
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#define DMAC1_BASE (0x40020000)
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#define BLEND_AHB0_BASE (0x40030000)
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#define BLEND_AHB1_BASE (0x40040000)
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#define GPIOA_BASE (0x50000000)
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#define GPIOB_BASE (0x50008000)
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#define UART0_BASE (0x50010000)
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#define UART1_BASE (0x50018000)
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#define I2C0_BASE (0x50020000)
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#define I2C1_BASE (0x50028000)
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#define SPIM0_BASE (0x50030000)
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#define SPIS0_BASE (0x50040000)
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#define PWM0_BASE (0x50050000)
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#define I2S0_BASE (0x50060000)
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#define PDM0_BASE (0x50070000)
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#define IIR_BASE (0x50080000)
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#define TRI_FUNC_BASE (0x50090000)
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#define FFT_BASE (0x500A0000)
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#define AHBC_CACHE_BASE (0x500B0000)
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#define PSRAM_OSPI_BASE (0x500B8000)
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#define SPIMX8_0_BASE (0x500C0000)
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#define PARALLEL_BASE (0x500D0000)
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#define GPIOC_BASE (0x50100000)
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#define GPIOD_BASE (0x50108000)
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#define UART2_BASE (0x50110000)
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#define UART3_BASE (0x50118000)
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#define I2C2_BASE (0x50120000)
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#define I2C3_BASE (0x50128000)
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#define SPIM1_BASE (0x50130000)
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#define SPIS1_BASE (0x50140000)
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#define PWM1_BASE (0x50150000)
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#define I2S1_BASE (0x50160000)
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#define PDM1_BASE (0x50170000)
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#define SPDIF_BASE (0x50180000)
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#define CODEC_BASE (0x50190000)
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#define SPIMX8_1_BASE (0x501C0000)
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#define DSP_CTRL_BASE (0x50200000)
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#define UART4_BASE (0x50210000)
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#define UART5_BASE (0x50218000)
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#define I2C4_BASE (0x50220000)
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#define I2C5_BASE (0x50228000)
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#define SPIM2_BASE (0x50230000)
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#define DSP_TIM0_BASE (0x50240000)
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#define DSP_TIM1_BASE (0x50240014)
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#define DSP_WDT_BASE (0x50250000)
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#define I2S2_BASE (0x50260000)
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#define PDM2_BASE (0x50270000)
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#define DSP_IPC_BASE (0x50280000)
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#define DSP_QSPI_BASE (0x50290000)
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#define YUV2RGB_BASE (0x502A0000)
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#define SYSTEM_REG_BASE (0xE0050000)
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#define TIM0_BASE (0xE0060000)
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#define TIM1_BASE (0xE0060014)
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#define TIM2_BASE (0xE0068000)
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#define TIM3_BASE (0xE0068014)
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#define FRSPIM_BASE (0xE0080000)
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#define IPC_BASE (0xE0090000)
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#define CALIB_BASE (0xE00A0000)
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#define FLASH_CACHE_BASE (0xE00B0000)
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#define FLASH_QSPI_BASE (0xE00C0000)
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#define TRNG_BASE (0xE00D0000)
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#define ADC_BASE (0xE00E0000)
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#define SARADC_BASE (0xE00F0000)
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/**
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* @}
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*/
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/* ########################## Oscillator Values adaptation ####################*/
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/**
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* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
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* This value is used by the system clock calculation.
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*/
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#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
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/**
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* @brief Internal High Speed oscillator (HSI) value.
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* This value is used by the system clock calculation.
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*/
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#define HSI_VALUE 24000000U /*!< Value of the Internal oscillator in Hz */
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/* Peripheral drive */
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#include "driver_common.h"
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/* System driver */
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#include "system_fr30xx.h"
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/* trim relative */
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#include "trim_fr30xx.h"
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#ifdef __cplusplus
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}
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#endif
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#endif // __FR30XX_H__
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