410 lines
14 KiB
C
410 lines
14 KiB
C
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/*
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******************************************************************************
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* @file driver_uart.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2021
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* @brief Header file of UART HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_UART_H__
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#define __DRIVER_UART_H__
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#include "fr30xx.h"
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/** @addtogroup UART_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* DATA/DLL Register */
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typedef union
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{
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uint32_t DATA;
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uint32_t DLL;
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}REG_DATA_DLL_t;
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/* IER/DLH Register */
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typedef union
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{
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struct
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{
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uint32_t ERBFI : 1;
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uint32_t ETBEI : 1;
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uint32_t ELSI : 1;
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uint32_t EDSSI : 1;
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uint32_t rsv_0 : 3;
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uint32_t PTIME : 1;
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uint32_t rsv_1 : 24;
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}IER;
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uint32_t DLH;
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}REG_IER_DLH_t;
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/* FCR/IID Register */
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typedef union
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{
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uint32_t FCR;
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uint32_t IID;
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}REG_FCR_IID_t;
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/* Line control Register */
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typedef union
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{
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struct
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{
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uint32_t DLS : 2;
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uint32_t STOP : 1;
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uint32_t PEN : 1;
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uint32_t EPS : 1;
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uint32_t SP : 1;
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uint32_t BC : 1;
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uint32_t DLAB : 1;
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uint32_t rsv_0 : 24;
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}Bits;
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uint32_t LCR_W;
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}REG_LCR_t;
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/* MODEM control Register */
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typedef struct
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{
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uint32_t rsv_0 : 1;
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uint32_t RTS : 1;
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uint32_t rsv_1 : 3;
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uint32_t AFCE : 1;
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uint32_t SIRE : 1;
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uint32_t rsv_2 : 25;
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}REG_MCR_t;
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/* Status Register */
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typedef union
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{
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struct
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{
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uint32_t DR : 1;
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uint32_t OE : 1;
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uint32_t PE : 1;
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uint32_t FE : 1;
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uint32_t BI : 1;
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uint32_t THRE : 1;
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uint32_t TEMT : 1;
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uint32_t RFE : 1;
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uint32_t rsv_0 : 24;
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}LSR_BIT;
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uint32_t LSR_DWORD;
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}REG_LSR_t;
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/* MODEM status Register */
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typedef struct
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{
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uint32_t rsv_0 : 4;
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uint32_t CTS : 1;
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uint32_t rsv_1 : 27;
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}REG_MSR_t;
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/* uart status Register */
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typedef struct
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{
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uint32_t rsv_0 : 1;
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uint32_t TFNF : 1;
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uint32_t TFE : 1;
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uint32_t RFNE : 1;
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uint32_t RFF : 1;
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uint32_t rsv_1 : 27;
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}REG_USR_t;
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/* DLF Register */
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typedef struct
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{
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uint32_t DLF : 6;
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uint32_t rsv_0 : 26;
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}REG_DLF_t;
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/* ------------------------------------------------*/
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/* UART Register */
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/* ------------------------------------------------*/
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typedef struct
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{
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volatile REG_DATA_DLL_t DATA_DLL; /* Offset 0x00 */
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volatile REG_IER_DLH_t IER_DLH; /* Offset 0x04 */
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volatile REG_FCR_IID_t FCR_IID; /* Offset 0x08 */
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volatile REG_LCR_t LCR; /* Offset 0x0C */
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volatile REG_MCR_t MCR; /* Offset 0x10 */
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volatile REG_LSR_t LSR; /* Offset 0x14 */
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volatile REG_MSR_t MSR; /* Offset 0x18 */
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volatile uint32_t rsv_0[24];
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volatile REG_USR_t USR; /* Offset 0x7C */
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volatile uint32_t rsv_1[16];
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volatile REG_DLF_t DLF; /* Offset 0xC0 */
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}struct_UART_t;
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#define UART0 ((struct_UART_t *)UART0_BASE)
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#define UART1 ((struct_UART_t *)UART1_BASE)
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#define UART2 ((struct_UART_t *)UART2_BASE)
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#define UART3 ((struct_UART_t *)UART3_BASE)
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#define UART4 ((struct_UART_t *)UART4_BASE)
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#define UART5 ((struct_UART_t *)UART5_BASE)
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/* ################################ Register Section END ################################## */
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/**
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* @}
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*/
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/** @addtogroup UART_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization<6F><6E>Config Section Start ################################ */
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/* Uart data length */
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typedef enum
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{
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UART_DATA_LENGTH_5BIT, /*!< 5-bit Word Length */
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UART_DATA_LENGTH_6BIT, /*!< 6-bit Word Length */
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UART_DATA_LENGTH_7BIT, /*!< 7-bit Word Length */
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UART_DATA_LENGTH_8BIT, /*!< 8-bit Word Length */
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}enum_DataLength_t;
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/* Stop bit */
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typedef enum
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{
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UART_STOPBITS_1, /*!< UART frame with 1 stop bit */
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UART_STOPBITS_2, /*!< UART frame with 2 stop bit */
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}enum_StopBit_t;
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/* Parity */
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typedef enum
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{
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UART_PARITY_NONE, /*!< No parity */
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UART_PARITY_ODD, /*!< Odd parity */
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UART_PARITY_EVEN, /*!< Even parity */
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UART_PARITY_0, /*!< 0 parity */
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UART_PARITY_1, /*!< 1 parity */
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}enum_Parity_t;
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/* FIFO Enable/Disable */
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typedef enum
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{
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UART_FIFO_DISABLE, /*!< FIFO Disable */
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UART_FIFO_ENABLE, /*!< FIFO Enable */
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}enum_UART_FIFO_t;
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/* AUTO FLOW Enable/Disable */
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typedef enum
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{
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UART_AUTO_FLOW_DISABLE, /*!< AUTO FLOW Disable */
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UART_AUTO_FLOW_ENABLE, /*!< AUTO FLOW Enable */
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}enum_UART_FLOW_t;
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/* Line Status index */
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typedef enum
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{
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STATUS_DR = 0x01, /*!< Data Ready */
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STATUS_OE = 0x02, /*!< Over Err */
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STATUS_PE = 0x04, /*!< Parity Err */
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STATUS_FE = 0x08, /*!< Frame Err */
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STATUS_BI = 0x10, /*!< Break ERR */
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STATUS_THRE = 0x20, /*!< Tx empty */
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STATUS_TEMT = 0x40, /*!< Tx Shift Register empty */
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STATUS_RFE = 0x80, /*!< Rx FIFO ERR */
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}enum_UART_LINE_STATUS_t;
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/* Interrupt Status index */
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typedef enum
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{
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INT_INDEX_MODEM = 0x0, /*!< modem status interrupt */
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INT_INDEX_NONE = 0x1, /*!< NONE */
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INT_INDEX_TXE = 0x2, /*!< Tx empty interrupt */
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INT_INDEX_RX = 0x4, /*!< Rx Threshold interrupt */
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INT_INDEX_LINE = 0x6, /*!< Line status interrupt */
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INT_INDEX_RX_TOUT = 0xC, /*!< Rx timeout interrupt */
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}enum_UART_INT_INDEX_t;
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/* FCR BIT position */
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typedef enum
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{
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FCR_FIFOE = 0x00,
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FCR_RFIFOR = 0x01,
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FCR_XFIFOR = 0x02,
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FCR_DMAM = 0x03,
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FCR_TET = 0x04,
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FCR_RT = 0x06,
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}enum_FCR_t;
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/*
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* @brief UART Init Structure definition
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*/
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typedef struct
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{
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uint32_t BaudRate; /*!< This parameter configures the UART communication baud rate. */
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uint32_t DataLength; /*!< Specifies the number of data bits transmitted or received in a frame.
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This parameter can be a value of @ref enum_DataLength_t. */
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uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
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This parameter can be a value of @ref enum_StopBit_t. */
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uint32_t Parity; /*!< Specifies the parity mode.
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This parameter can be a value of @ref enum_Parity_t. */
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uint32_t FIFO_Mode; /*!< Specifies the FIFO mode.
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This parameter can be a value of @ref enum_UART_FIFO_t. */
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uint32_t AUTO_FLOW; /*!< Specifies the AUTO FLOW.
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This parameter can be a value of @ref enum_UART_FLOW_t. */
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}struct_UARTInit_t;
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/*
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* @brief UART handle Structure definition
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*/
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typedef struct __UART_HandleTypeDef
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{
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struct_UART_t *UARTx; /*!< UART registers base address */
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struct_UARTInit_t Init; /*!< UART communication parameters */
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volatile uint32_t FCR_Shadow;
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void (*TxCpltCallback)(struct __UART_HandleTypeDef *huart); /* Tx complete Callback */
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void (*RxCpltCallback)(struct __UART_HandleTypeDef *huart); /* Rx complete Callback */
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volatile uint32_t u32_TxSize; /*!< UART Transmit parameters in interrupt */
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volatile uint32_t u32_TxCount;
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volatile uint8_t *p_TxData;
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volatile bool b_TxBusy;
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volatile uint32_t u32_RxSize; /*!< UART Receive parameters in interrupt */
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volatile uint32_t u32_RxCount;
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volatile uint8_t *p_RxData;
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volatile bool b_RxBusy;
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}UART_HandleTypeDef;
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/* ################################ Initialization<6F><6E>Config Section END ################################## */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Read/Write FIFO */
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#define __UART_READ_FIFO(__UART__) (__UART__->DATA_DLL.DATA)
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#define __UART_WRITE_FIFO(__UART__, __DATA__) (__UART__->DATA_DLL.DATA = __DATA__)
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/* Set line control */
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#define __UART_SET_LINE_CTRL(__UART__, __CTRL__) (__UART__->LCR.LCR_W = __CTRL__)
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/* __UART_IS_FIFO_Enable */
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/* __UART_FIFO_Enable */
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/* __UART_FIFO_Disable */
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/* __UART_TxFIFO_Reset */
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/* __UART_RxFIFO_Reset */
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#define __UART_IS_FIFO_Enable(__UART__) (__UART__->FCR_Shadow & 0x01)
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#define __UART_FIFO_Enable(__UART__) do{ __UART__->FCR_Shadow |= 0x01; \
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__UART__->FCR_Shadow |= 0x08; \
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__UART__->UARTx->FCR_IID.FCR = __UART__->FCR_Shadow; }while(0)
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#define __UART_FIFO_Disable(__UART__) do{ __UART__->FCR_Shadow &= ~0x01; \
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__UART__->FCR_Shadow &= ~0x08; \
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__UART__->UARTx->FCR_IID.FCR = __UART__->FCR_Shadow; }while(0)
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#define __UART_TxFIFO_Reset(__UART__) (__UART__->UARTx->FCR_IID.FCR = __UART__->FCR_Shadow | 0x04)
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#define __UART_RxFIFO_Reset(__UART__) (__UART__->UARTx->FCR_IID.FCR = __UART__->FCR_Shadow | 0x02)
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/* __LEVEL__ = 0: RxFIFO have 1 byte */
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/* __LEVEL__ = 1: RxFIFO 1/4 full */
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/* __LEVEL__ = 2: RxFIFO 1/2 full */
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/* __LEVEL__ = 3: Need 2 byte to full */
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#define __UART_RxFIFO_THRESHOLD(__UART__, __LEVEL__) do{ __UART__->FCR_Shadow &= ~0xC0; \
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__UART__->FCR_Shadow |= __LEVEL__ << FCR_RT; \
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__UART__->UARTx->FCR_IID.FCR = __UART__->FCR_Shadow; }while(0)
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/* __LEVEL__ = 0: TxFIFO empty */
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/* __LEVEL__ = 1: TxFIFO have 2 byte */
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/* __LEVEL__ = 2: TxFIFO 1/4 full */
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/* __LEVEL__ = 3: TxFIFO 1/2 full */
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#define __UART_TxFIFO_THRESHOLD(__UART__, __LEVEL__) do{ __UART__->FCR_Shadow &= ~0x30; \
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__UART__->FCR_Shadow |= __LEVEL__ << FCR_TET; \
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__UART__->UARTx->FCR_IID.FCR = __UART__->FCR_Shadow; }while(0)
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/* __UART_IS_RxFIFO_FULL */
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/* __UART_IS_RxFIFO_EMPTY */
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/* __UART_IS_TxFIFO_FULL */
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/* __UART_IS_TxFIFO_EMPTY */
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#define __UART_IS_RxFIFO_FULL(__UARTx__) (__UARTx__->USR.RFF == 1)
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#define __UART_IS_RxFIFO_EMPTY(__UARTx__) (__UARTx__->USR.RFNE == 0)
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#define __UART_IS_TxFIFO_FULL(__UARTx__) (__UARTx__->USR.TFNF == 0)
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#define __UART_IS_TxFIFO_EMPTY(__UARTx__) (__UARTx__->USR.TFE == 1)
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/* uart interrupt enable */
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/* uart interrupt disable */
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/* uart interrupt get id */
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#define __UART_INT_MODEM_ENABLE(__UARTx__) (__UARTx__->IER_DLH.IER.EDSSI = 1)
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#define __UART_INT_LINE_STATUS_ENABLE(__UARTx__) (__UARTx__->IER_DLH.IER.ELSI = 1)
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#define __UART_INT_RX_ENABLE(__UARTx__) (__UARTx__->IER_DLH.IER.ERBFI = 1)
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/* Tx empty interrupt and fifo enable */
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#define __UART_INT_TXE_ENABLE_FE(__UARTx__) do{__UARTx__->IER_DLH.IER.PTIME = 1; \
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__UARTx__->IER_DLH.IER.ETBEI = 1;}while(0)
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|
/* Tx empty interrupt and fifo disable */
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|
#define __UART_INT_TXE_ENABLE_FD(__UARTx__) do{__UARTx__->IER_DLH.IER.PTIME = 0; \
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__UARTx__->IER_DLH.IER.ETBEI = 1;}while(0)
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|
|
|
|||
|
|
#define __UART_INT_MODEM_DISABLE(__UARTx__) (__UARTx__->IER_DLH.IER.EDSSI = 0)
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|
#define __UART_INT_LINE_STATUS_DISABLE(__UARTx__) (__UARTx__->IER_DLH.IER.ELSI = 0)
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|
|
#define __UART_INT_RX_DISABLE(__UARTx__) (__UARTx__->IER_DLH.IER.ERBFI = 0)
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|
|
#define __UART_INT_TXE_DISABLE(__UARTx__) do{__UARTx__->IER_DLH.IER.PTIME = 0; \
|
|||
|
|
__UARTx__->IER_DLH.IER.ETBEI = 0;}while(0)
|
|||
|
|
|
|||
|
|
/* Get interrupt ID */
|
|||
|
|
#define __UART_INT_GET_ID(__UARTx__) (__UARTx__->FCR_IID.IID & 0xF)
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* __UART_IrDA_ENABLE */
|
|||
|
|
#define __UART_IrDA_ENABLE(__UARTx__) (__UARTx__->MCR.SIRE = 1)
|
|||
|
|
#define __UART_IrDA_DISABLE(__UARTx__) (__UARTx__->MCR.SIRE = 0)
|
|||
|
|
|
|||
|
|
/* flow control config */
|
|||
|
|
#define __UART_AUTO_FLOW_CONTROL_ENABLE(__UARTx__) do{__UARTx__->MCR.AFCE = 1; __UARTx__->MCR.RTS = 1;} while(0)
|
|||
|
|
#define __UART_AUTO_FLOW_CONTROL_DISABLE(__UARTx__) (__UARTx__->MCR.AFCE = 0)
|
|||
|
|
#define __UART_RTS_ACTIVE(__UARTx__) (__UARTx__->MCR.RTS = 1)
|
|||
|
|
#define __UART_RTS_INACTIVE(__UARTx__) (__UARTx__->MCR.RTS = 0)
|
|||
|
|
#define __UART_IS_CTS_ACTIVE(__UARTx__) (__UARTx__->MSR.CTS == 1)
|
|||
|
|
|
|||
|
|
/* __UART_DLL_DLH_ACCESS_ENABLE */
|
|||
|
|
/* __UART_DLL_DLH_ACCESS_DISABLE */
|
|||
|
|
#define __UART_DLL_DLH_ACCESS_ENABLE(__UARTx__) (__UARTx__->LCR.Bits.DLAB = 1)
|
|||
|
|
#define __UART_DLL_DLH_ACCESS_DISABLE(__UARTx__) (__UARTx__->LCR.Bits.DLAB = 0)
|
|||
|
|
|
|||
|
|
/* __UART_GET_STATUS */
|
|||
|
|
#define __UART_GET_STATUS(__UARTx__) (__UARTx__->LSR.LSR_DWORD)
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* Exported functions --------------------------------------------------------*/
|
|||
|
|
|
|||
|
|
/* uart_IRQHandler */
|
|||
|
|
void uart_IRQHandler(UART_HandleTypeDef *huart);
|
|||
|
|
|
|||
|
|
/* uart_init */
|
|||
|
|
void uart_init(UART_HandleTypeDef *huart);
|
|||
|
|
|
|||
|
|
/* uart_transmit */
|
|||
|
|
/* uart_receive */
|
|||
|
|
void uart_transmit(UART_HandleTypeDef *huart, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
void uart_receive(UART_HandleTypeDef *huart, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
|
|||
|
|
/* uart_transmit_IT */
|
|||
|
|
/* uart_receive_IT */
|
|||
|
|
void uart_transmit_IT(UART_HandleTypeDef *huart, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
void uart_receive_IT(UART_HandleTypeDef *huart, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
|
|||
|
|
/* uart_config_baudRate */
|
|||
|
|
void uart_config_baudRate(UART_HandleTypeDef *huart);
|
|||
|
|
|
|||
|
|
#endif
|