483 lines
17 KiB
C
483 lines
17 KiB
C
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/*
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******************************************************************************
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* @file driver_dma.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2021
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* @brief Header file of DMA HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_DMA_H__
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#define __DRIVER_DMA_H__
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#include "fr30xx.h"
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#define DMA_CHANNELS_MAX (8)
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/** @addtogroup DMA_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* Linked List Pointer Register for Channel */
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typedef struct
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{
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uint32_t LMS : 2; // Starting Address In Memory.
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uint32_t LOC : 30; // List Master Select.
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}REG_LLP_t;
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/* Control Register for Channel */
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typedef struct
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{
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uint32_t INT_EN : 1; // Interrupt Enable.
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uint32_t DST_TR_WIDTH : 3; // Destination Transfer Width.
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uint32_t SRC_TR_WIDTH : 3; // Source Transfer Width.
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uint32_t DINC : 2; // Destination Address Increment.
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uint32_t SINC : 2; // Source Address Increment.
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uint32_t DEST_MSIZE : 3; // Destination Burst Transaction Length.
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uint32_t SRC_MSIZE : 3; // Source Burst Transaction Length.
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uint32_t SRC_GATHER_EN : 1; // Source gather enable.
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uint32_t DST_SCATTER_EN : 1; // Destination scatter enable.
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uint32_t rsv_0 : 1; //
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uint32_t TT_FC : 3; // Transfer Type and Flow Control.
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uint32_t DMS : 2; // Destination Master Select.
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uint32_t SMS : 2; // Source Master Select.
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uint32_t LLP_DST_EN : 1; // Block chaining is enabled on the destination
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uint32_t LLP_SRC_EN : 1; // Block chaining is enabled on the source
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uint32_t rsv_1 : 3; //
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}REG_CTL1_t;
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/* Control Register for Channel */
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typedef struct
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{
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uint32_t BLOCK_TS : 24; // Block Transfer Size.
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uint32_t rsv_0 : 7;
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uint32_t DONE : 1; // Done bit.
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}REG_CTL2_t;
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/* Configuration Register for Channel */
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typedef struct
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{
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uint32_t rsv_0 : 5;
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uint32_t CH_PRIOR : 3; // Channel Priority.
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uint32_t CH_SUSP : 1; // Channel Suspend.
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uint32_t FIFO_EMPTY : 1; // Channel FIFO status.
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uint32_t HS_SEL_DST : 1; // Destination Software or Hardware Handshaking Select.
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uint32_t HS_SEL_SRC : 1; // Source Software or Hardware Handshaking Select.
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uint32_t LOCK_CH_L : 2;
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uint32_t LOCK_B_L : 2;
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uint32_t LOCK_CH : 1;
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uint32_t LOCK_B : 1;
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uint32_t DST_HS_POL : 1; // Destination Handshaking Interface Polarity.
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uint32_t SRC_HS_POL : 1; // Source Handshaking Interface Polarity.
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uint32_t MAX_ABRST : 10;
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uint32_t RELOAD_SRC : 1; // Automatic Source Reload.
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uint32_t RELOAD_DST : 1;
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}REG_CFG1_t;
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/* Configuration Register for Channel */
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typedef struct
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{
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uint32_t FCMODE : 1;
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uint32_t FIFO_MODE : 1;
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uint32_t PROTCTL : 3;
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uint32_t DS_UPD_EN : 1;
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uint32_t SS_UPD_EN : 1;
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uint32_t SRC_PER : 4;
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uint32_t DEST_PER : 4;
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uint32_t rsv_0 : 17;
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}REG_CFG2_t;
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/* Source Gath Register for Channel */
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typedef struct
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{
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uint32_t SGI : 20;
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uint32_t SGC : 12;
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}REG_SGR_t;
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/* Destination Scatter Register for Channel */
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typedef struct
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{
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uint32_t DSI : 20;
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uint32_t DSC : 12;
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}REG_DSR_t;
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/* -------------------------------------------*/
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/* DAM Channel Register */
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/* -------------------------------------------*/
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typedef struct
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{
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volatile uint32_t SAR; // offset 0x00. Source Address for Channel
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volatile uint32_t rsv_0; // offset 0x04
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volatile uint32_t DAR; // offset 0x08. Destination Address Register for Channel
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volatile uint32_t rsv_1; // offset 0x0C
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volatile REG_LLP_t LLP; // offset 0x10. Linked List Pointer Register for Channel
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volatile uint32_t rsv_2; // offset 0x14
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volatile REG_CTL1_t CTL1; // offset 0x18. Control Register for Channel
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volatile REG_CTL2_t CTL2; // offset 0x1C. Control Register for Channel
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volatile uint32_t SSTAT; // offset 0x20. Source Status Register for Channel
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volatile uint32_t rsv_3; // offset 0x24
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volatile uint32_t DSTAT; // offset 0x28. Destination Status Register for Channel
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volatile uint32_t rsv_4; // offset 0x2C
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volatile uint32_t SSTATAR; // offset 0x30. Source Status Address Register for Channel
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volatile uint32_t rsv_5; // offset 0x34
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volatile uint32_t DSTATAR; // offset 0x38. Destination Status Address Register for Channel
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volatile uint32_t rsv_6; // offset 0x3C
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volatile REG_CFG1_t CFG1; // offset 0x40. Configuration Register for Channel
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volatile REG_CFG2_t CFG2; // offset 0x44. Configuration Register for Channel
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volatile REG_SGR_t SGR; // offset 0x48. Source Gather Register for Channel
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volatile uint32_t rsv_7; // offset 0x4C
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volatile REG_DSR_t DSR; // offset 0x50. Destination Scatter Register for Channel
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volatile uint32_t rsv_8; // offset 0x54
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}dma_channel_t;
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/* -------------------------------------------*/
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/* DAM Interrupt Register */
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/* -------------------------------------------*/
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typedef struct
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{
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volatile uint32_t RawTfr;
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volatile uint32_t rsv_0;
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volatile uint32_t RawBlock;
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volatile uint32_t rsv_1;
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volatile uint32_t RawSrcTran;
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volatile uint32_t rsv_2;
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volatile uint32_t RawDstDran;
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volatile uint32_t rsv_3;
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volatile uint32_t RawErr;
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volatile uint32_t rsv_4;
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volatile uint32_t StatusTfr;
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volatile uint32_t rsv_5;
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volatile uint32_t StatusBlock;
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volatile uint32_t rsv_6;
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volatile uint32_t StatusSrcTran;
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volatile uint32_t rsv_7;
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volatile uint32_t StatusDstTran;
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volatile uint32_t rsv_8;
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volatile uint32_t StatusErr;
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volatile uint32_t rsv_9;
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volatile uint32_t MaskTfr;
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volatile uint32_t rsv_10;
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volatile uint32_t MaskBlock;
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volatile uint32_t rsv_11;
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volatile uint32_t MaskSrcTran;
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volatile uint32_t rsv_12;
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volatile uint32_t MaskDstTran;
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volatile uint32_t rsv_13;
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volatile uint32_t MaskErr;
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volatile uint32_t rsv_14;
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volatile uint32_t ClearTfr;
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volatile uint32_t rsv_15;
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volatile uint32_t ClearBlock;
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volatile uint32_t rsv_16;
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volatile uint32_t ClearSrcTran;
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volatile uint32_t rsv_17;
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volatile uint32_t ClearDstTran;
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volatile uint32_t rsv_18;
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volatile uint32_t ClearErr;
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volatile uint32_t rsv_19;
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volatile uint32_t StatusInt;
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volatile uint32_t rsv_20;
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}dma_interrupt_t;
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/* ------------------------------------------------*/
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/* DAM Software Handshake Register */
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/* ------------------------------------------------*/
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typedef struct
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{
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volatile uint32_t ReqSrcReg;
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volatile uint32_t rsv_0;
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volatile uint32_t ReqDstReg;
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volatile uint32_t rsv_1;
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volatile uint32_t SglRqSrcReg;
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volatile uint32_t rsv_2;
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volatile uint32_t SglRqDstReg;
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volatile uint32_t rsv_3;
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volatile uint32_t LstSrcReg;
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volatile uint32_t rsv_4;
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volatile uint32_t LstDstReg;
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volatile uint32_t rsv_5;
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}dma_software_handshake_t;
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/* -------------------------------------------*/
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/* DAM Miscellaneous Register */
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/* -------------------------------------------*/
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typedef struct
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{
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volatile uint32_t DMA_EN : 1;
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volatile uint32_t rsv_0 : 31;
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}REG_DmaCfg_t;
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typedef struct
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{
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volatile REG_DmaCfg_t DmaCfgReg;
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volatile uint32_t rsv_0;
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volatile uint32_t ChEnReg;
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}dma_miscellaneous_t;
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typedef struct
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{
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dma_channel_t Channels[DMA_CHANNELS_MAX];
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dma_interrupt_t Int_Reg;
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dma_software_handshake_t Software_Handshake_Reg;
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dma_miscellaneous_t Misc_Reg;
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}struct_DMA_t;
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#define DMA0 ((struct_DMA_t *)DMAC0_BASE)
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#define DMA1 ((struct_DMA_t *)DMAC1_BASE)
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/* ################################ Register Section END ################################ */
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/**
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* @}
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*/
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/** @addtogroup DMA_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization, Config Section Start ################################ */
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typedef enum
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{
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DMA_Channel0,
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DMA_Channel1,
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DMA_Channel2,
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DMA_Channel3,
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DMA_Channel4,
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DMA_Channel5,
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DMA_Channel6,
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DMA_Channel7,
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}dma_channel_select_t;
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enum dma_data_flow_t
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{
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DMA_M2M_DMAC, // Memory to Memory and Flow Controller is dmac
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DMA_M2P_DMAC, // Memory to Peripheral and Flow Controller is dmac
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DMA_P2M_DMAC, // Peripheral to Memory and Flow Controller is dmac
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DMA_P2P_DMAC, // Peripheral to Peripheral and Flow Controller is dmac
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DMA_P2M_PER, // Peripheral to Memory and Flow Controller is Peripheral
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DMA_P2P_SRCPER, // Peripheral to Peripheral and Flow Controller is Source Peripheral
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DMA_M2P_PER, // Memory to Peripheral and Flow Controller is Peripheral
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DMA_P2P_DSTPER, // Peripheral to Peripheral and Flow Controller is Destination Peripheral
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};
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enum dma_addr_inc_t
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{
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DMA_ADDR_INC_INC, // Increments the source/destination address
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DMA_ADDR_INC_DEC, // Decrements the source/destination address
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DMA_ADDR_INC_NO_CHANGE, // No change the source/destination address
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};
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enum dma_transfer_width_t
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{
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DMA_TRANSFER_WIDTH_8,
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DMA_TRANSFER_WIDTH_16,
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DMA_TRANSFER_WIDTH_32,
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};
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typedef enum
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{
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DMA_BURST_LEN_1,
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DMA_BURST_LEN_4,
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DMA_BURST_LEN_8,
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DMA_BURST_LEN_16,
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DMA_BURST_LEN_32,
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DMA_BURST_LEN_64,
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DMA_BURST_LEN_128,
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DMA_BURST_LEN_256,
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}dma_burst_len_t;
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enum dma_ahb_master_t
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{
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DMA_AHB_MASTER_1, /* access to 0x00000000~0x1FFFFFFF space */
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DMA_AHB_MASTER_2, /* access to 0x20000000~ space */
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DMA_AHB_MASTER_3, /* access to 0x20000000~ space */
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DMA_AHB_MASTER_4, /* access to 0x20000000~ space */
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};
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/**
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* @brief DMA Initialization Structure definition
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*/
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typedef struct
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{
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uint8_t Data_Flow; /* This parameter can be a value of @ref dma_data_flow_t */
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uint8_t Request_ID; /* This parameter can be a value of @ref dma_requeat_id_t */
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uint8_t Source_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
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uint8_t Desination_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
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uint8_t Source_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
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uint8_t Desination_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
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uint8_t Source_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
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uint8_t Desination_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
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uint8_t Source_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
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uint8_t Desination_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
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}dma_InitParameter_t;
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/**
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* @brief DAM handle Structure definition
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*/
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typedef struct
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{
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struct_DMA_t *DMAx; /* DMA registers base address */
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dma_channel_select_t Channel; /* DMA registers base address */
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/* This parameter can be a value of @ref dma_channel_select_t */
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dma_InitParameter_t Init; /* DMA initialization parameters */
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}DMA_HandleTypeDef;
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/**
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* @brief DMA Link List Item Structure
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*/
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typedef struct DMA_NextLink
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{
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uint32_t SrcAddr; /* source address */
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uint32_t DstAddr; /* desination address */
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struct DMA_NextLink *Next; /* Next Link */
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REG_CTL1_t CTL1; /* Control Register for Channel */
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REG_CTL2_t CTL2; /* Control Register for Channel */
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}DMA_LLI_InitTypeDef;
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/**
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* @brief DMA Initialization Structure definition
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*/
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typedef struct
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{
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uint32_t SrcAddr; /* source address */
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uint32_t DstAddr; /* desination address */
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uint32_t NextLink; /* Next Link Address */
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uint32_t Data_Flow; /* This parameter can be a value of @ref dma_data_flow_t */
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uint32_t Request_ID; /* This parameter can be a value of @ref dma_requeat_id_t */
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uint8_t Source_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
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uint8_t Desination_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
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uint32_t Source_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
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uint32_t Desination_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
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uint32_t Source_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
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uint32_t Desination_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
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uint32_t Source_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
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uint32_t Desination_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
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uint32_t Size; /* This parameter can be a 12-bit Size */
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uint8_t gather_enable; /* Enable Source Gather or not */
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uint8_t scatter_enable; /* Enable Destination Scatter or not */
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}dma_LinkParameter_t;
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/* ################################ Initialization, Config Section END ################################ */
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/**
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||
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* @}
|
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* set DATA flow selection */
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#define __DMA_DATA_FLOW_CONTROL_SET(__DMAC__, __CHANNEL__, SEL) (__DMAC__->Channels[__CHANNEL__].CTL1.TT_FC = SEL)
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/* APB Master selection configuration */
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#define __DMA_SRC_MASTER_SET(__DMAC__, __CHANNEL__, SEL) (__DMAC__->Channels[__CHANNEL__].CTL1.SMS = SEL)
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#define __DMA_DES_MASTER_SET(__DMAC__, __CHANNEL__, SEL) (__DMAC__->Channels[__CHANNEL__].CTL1.DMS = SEL)
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||
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|
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/* Address increment configuration */
|
||
|
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#define __DMA_SRC_ADDR_INC_SET(__DMAC__, __CHANNEL__, INC) (__DMAC__->Channels[__CHANNEL__].CTL1.SINC = INC)
|
||
|
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#define __DMA_DES_ADDR_INC_SET(__DMAC__, __CHANNEL__, INC) (__DMAC__->Channels[__CHANNEL__].CTL1.DINC = INC)
|
||
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|
||
|
|
/* Gather function enable,disable */
|
||
|
|
#define __DMA_GATHER_FUNC_ENABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.SRC_GATHER_EN = 1)
|
||
|
|
#define __DMA_GATHER_FUNC_DISABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.SRC_GATHER_EN = 0)
|
||
|
|
/* Gather count, Gather interval */
|
||
|
|
#define __DMA_GATHER_COUNT(__DMAC__, __CHANNEL__, __COUNT__) (__DMAC__->Channels[__CHANNEL__].SGR.SGC = __COUNT__)
|
||
|
|
#define __DMA_GATHER_INTERVAL(__DMAC__, __CHANNEL__, __INTERVAL__) (__DMAC__->Channels[__CHANNEL__].SGR.SGI = __INTERVAL__)
|
||
|
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|
||
|
|
/* Scatter function enable,disable */
|
||
|
|
#define __DMA_SCATTER_FUNC_ENABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.DST_SCATTER_EN = 1)
|
||
|
|
#define __DMA_SCATTER_FUNC_DISABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.DST_SCATTER_EN = 0)
|
||
|
|
/* Scatter count, Gather interval */
|
||
|
|
#define __DMA_SCATTER_COUNT(__DMAC__, __CHANNEL__, __COUNT__) (__DMAC__->Channels[__CHANNEL__].DSR.DSC = __COUNT__)
|
||
|
|
#define __DMA_SCATTER_INTERVAL(__DMAC__, __CHANNEL__, __INTERVAL__) (__DMAC__->Channels[__CHANNEL__].DSR.DSI = __INTERVAL__)
|
||
|
|
|
||
|
|
/* Exported functions --------------------------------------------------------*/
|
||
|
|
|
||
|
|
/* dma_init */
|
||
|
|
void dma_init(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_start */
|
||
|
|
void dma_start(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DstAddr, uint32_t Size);
|
||
|
|
|
||
|
|
/* dma_start_interrupt */
|
||
|
|
void dma_start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DstAddr, uint32_t Size);
|
||
|
|
|
||
|
|
/* dma_linked_list_init */
|
||
|
|
void dma_linked_list_init(DMA_LLI_InitTypeDef *link, dma_LinkParameter_t *param);
|
||
|
|
|
||
|
|
/* dma_linked_list_start */
|
||
|
|
void dma_linked_list_start(DMA_HandleTypeDef *hdma, DMA_LLI_InitTypeDef *link, dma_LinkParameter_t *param);
|
||
|
|
|
||
|
|
/* dma_linked_list_start_IT */
|
||
|
|
void dma_linked_list_start_IT(DMA_HandleTypeDef *hdma, DMA_LLI_InitTypeDef *link, dma_LinkParameter_t *param);
|
||
|
|
|
||
|
|
/* dma_tfr_interrupt_enable */
|
||
|
|
void dma_tfr_interrupt_enable(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_tfr_interrupt_disable */
|
||
|
|
void dma_tfr_interrupt_disable(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_get_tfr_Status */
|
||
|
|
bool dma_get_tfr_Status(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_clear_tfr_Status */
|
||
|
|
void dma_clear_tfr_Status(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_error_interrupt_enable */
|
||
|
|
void dma_error_interrupt_enable(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_error_interrupt_disable */
|
||
|
|
void dma_error_interrupt_disable(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_get_error_Status */
|
||
|
|
bool dma_get_error_Status(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
/* dma_clear_error_Status */
|
||
|
|
void dma_clear_error_Status(DMA_HandleTypeDef *hdma);
|
||
|
|
|
||
|
|
#endif
|