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demo工程暂存 优化菜单界面UI和功能

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Li Jie
2024-04-29 16:32:24 +08:00
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293
MCU/components/drivers/device/fr30xx/armcc/startup_fr30xx.s Normal file
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;************************* (C) COPYRIGHT 2023 FreqChip ***************************
;* File Name : startup_fr30xx.s
;* Author : FreqChip Firmware Team
;* Version : V1.0.0
;* Date : 2022
;* Description : fr30xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M33 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*********************************************************************************
;* @attention
;*
;* Copyright (c) 2022 FreqChip.
;* All rights reserved.
;*******************************************************************************
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00019000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD SecureFault_Handler ; -9 Secure Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD timer0_irq ; 0 Interrupt 0
DCD timer1_irq ; 1 Interrupt 1
DCD timer2_irq ; 2 timer2
DCD timer3_irq ; 3 timer3
DCD dma0_irq ; 4 dma0
DCD dma1_irq ; 5 dma1
DCD sdioh0_irq ; 6 sdioh
DCD sdioh1_irq ; 7 sdiod
DCD ipc_mcu_irq ; 8 ipc mcu
DCD usbotg_irq ; 9 usbotg
DCD iir_irq ; 10 iir
DCD blend_irq ; 11 trigfunc
DCD fft_irq ; 12 fft
DCD sec_aes_irq ; 13 Interrupt 13
DCD Interrupt14_Handler ; 14 Interrupt 14
DCD Interrupt15_Handler ; 15 Interrupt 15
DCD gpioa_irq ; 16 GPIOA
DCD gpiob_irq ; 17 GPIOB
DCD gpioc_irq ; 18 GPIOC
DCD gpiod_irq ; 19 GPIOD
DCD uart0_irq ; 20 uart0
DCD uart1_irq ; 21 uart1
DCD uart2_irq ; 22 uart2
DCD uart3_irq ; 23 uart3
DCD uart4_irq ; 24 uart4
DCD uart5_irq ; 25 uart5
DCD i2c0_irq ; 26 i2c0
DCD i2c1_irq ; 27 i2c1
DCD i2c2_irq ; 28 i2c2
DCD i2c3_irq ; 29 i2c3
DCD i2c4_irq ; 30 i2c4
DCD i2c5_irq ; 31 i2c5
DCD spim0_irq ; 32 spim0
DCD spim1_irq ; 33 spim1
DCD spim2_irq ; 34 spim2
DCD spis0_irq ; 35 spis0
DCD spis1_irq ; 36 spis1
DCD spimx8_0_irq ; 37 spimx8_0
DCD spimx8_1_irq ; 38 spimx8_1
DCD i2s0_irq ; 39 i2s0
DCD i2s1_irq ; 40 i2s1
DCD i2s2_irq ; 41 i2s2
DCD pdm0_irq ; 42 pdm0
DCD pdm1_irq ; 43 pdm1
DCD pdm2_irq ; 44 pdm2
DCD adc_irq ; 45 adc
DCD codec_irq ; 46 codec
DCD spdif_irq ; 47 spdif
DCD sbc_dec_irq ; 48 sbc_dec
DCD sbc_enc_irq ; 49 sbc_enc
DCD mp3dec_irq ; 50 mp3dec
DCD parallel0_irq ; 51 parallel0
DCD Interrupt52_Handler ; 52 Interrupt 52
DCD cali_irq ; 53 cali
DCD trng_irq ; 54 trng
DCD tick_irq ; 55 Interrupt 55
DCD Interrupt56_Handler ; 56 Interrupt 56
DCD Interrupt57_Handler ; 57 Interrupt 57
DCD Interrupt58_Handler ; 58 Interrupt 58
DCD Interrupt59_Handler ; 59 Interrupt 59
DCD timer4_irq ; 60 timer4
DCD timer5_irq ; 61 timer5
DCD Interrupt62_Handler ; 62 Interrupt 62
DCD ipc_dsp_irq ; 63 Interrupt 63
DCD yuv2rgb_irq ; 64 yuv2rgb
DCD pmu_irq ; 65 pmu
DCD 0xAA55AA55 ; app check data
DCD 0x00000001 ; app version
DCD 0 ; code length
; SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =__stack_limit
MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SecureFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler timer0_irq
Set_Default_Handler timer1_irq
Set_Default_Handler timer2_irq
Set_Default_Handler timer3_irq
Set_Default_Handler dma0_irq
Set_Default_Handler dma1_irq
Set_Default_Handler sdioh0_irq
Set_Default_Handler sdioh1_irq
Set_Default_Handler ipc_mcu_irq
Set_Default_Handler usbotg_irq
Set_Default_Handler iir_irq
Set_Default_Handler blend_irq
Set_Default_Handler fft_irq
Set_Default_Handler sec_aes_irq
Set_Default_Handler Interrupt14_Handler
Set_Default_Handler Interrupt15_Handler
Set_Default_Handler gpioa_irq
Set_Default_Handler gpiob_irq
Set_Default_Handler gpioc_irq
Set_Default_Handler gpiod_irq
Set_Default_Handler uart0_irq
Set_Default_Handler uart1_irq
Set_Default_Handler uart2_irq
Set_Default_Handler uart3_irq
Set_Default_Handler uart4_irq
Set_Default_Handler uart5_irq
Set_Default_Handler i2c0_irq
Set_Default_Handler i2c1_irq
Set_Default_Handler i2c2_irq
Set_Default_Handler i2c3_irq
Set_Default_Handler i2c4_irq
Set_Default_Handler i2c5_irq
Set_Default_Handler spim0_irq
Set_Default_Handler spim1_irq
Set_Default_Handler spim2_irq
Set_Default_Handler spis0_irq
Set_Default_Handler spis1_irq
Set_Default_Handler spimx8_0_irq
Set_Default_Handler spimx8_1_irq
Set_Default_Handler i2s0_irq
Set_Default_Handler i2s1_irq
Set_Default_Handler i2s2_irq
Set_Default_Handler pdm0_irq
Set_Default_Handler pdm1_irq
Set_Default_Handler pdm2_irq
Set_Default_Handler adc_irq
Set_Default_Handler codec_irq
Set_Default_Handler spdif_irq
Set_Default_Handler sbc_dec_irq
Set_Default_Handler sbc_enc_irq
Set_Default_Handler mp3dec_irq
Set_Default_Handler parallel0_irq
Set_Default_Handler Interrupt52_Handler
Set_Default_Handler cali_irq
Set_Default_Handler trng_irq
Set_Default_Handler tick_irq
Set_Default_Handler Interrupt56_Handler
Set_Default_Handler Interrupt57_Handler
Set_Default_Handler Interrupt58_Handler
Set_Default_Handler Interrupt59_Handler
Set_Default_Handler timer4_irq
Set_Default_Handler timer5_irq
Set_Default_Handler Interrupt62_Handler
Set_Default_Handler ipc_dsp_irq
Set_Default_Handler yuv2rgb_irq
Set_Default_Handler pmu_irq
ALIGN
; User setup Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

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MCU/components/drivers/device/fr30xx/fr30xx.h Normal file
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/*
******************************************************************************
* @file fr30xx.h
* @author FreqChip Firmware Team
* @brief CMSIS fr30xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Configuration of the Processor and Core Peripherals
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 FreqChip.
* All rights reserved.
******************************************************************************
*/
#ifndef __FR30XX_H__
#define __FR30XX_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @group Peripheral_interrupt_number_definition
* @{
*/
#if defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
typedef enum IRQn
{
/****** Cortex-M33 Processor Exceptions Numbers ************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M33 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M33 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M33 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M33 System Tick Interrupt */
/****** CMSDK Specific Interrupt Numbers *******************************************************/
TIMER0_IRQn = 0, /*!< */
TIMER1_IRQn = 1, /*!< */
TIMER2_IRQn = 2, /*!< */
TIMER3_IRQn = 3, /*!< */
DMA0_IRQn = 4,
DMA1_IRQn = 5, /*!< */
SDIOH0_IRQn = 6, /*!< */
SDIOH1_IRQn = 7, /*!< */
IPC_MCU_IRQn = 8, /*!< */
USBOTG_IRQn = 9, /*!< */
IIR_IRQn = 10, /*!< */
BLEND_IRQn = 11, /*!< */
FFT_IRQn = 12, /*!< */
SEC_AES_IRQn = 13, /*!< */
GPIOA_IRQn = 16, /*!< */
GPIOB_IRQn = 17, /*!< */
GPIOC_IRQn = 18, /*!< */
GPIOD_IRQn = 19, /*!< */
UART0_IRQn = 20, /*!< */
UART1_IRQn = 21, /*!< */
UART2_IRQn = 22, /*!< */
UART3_IRQn = 23, /*!< */
UART4_IRQn = 24,
UART5_IRQn = 25,
I2C0_IRQn = 26,
I2C1_IRQn = 27,
I2C2_IRQn = 28,
I2C3_IRQn = 29,
I2C4_IRQn = 30,
I2C5_IRQn = 31,
SPIM0_IRQn = 32,
SPIM1_IRQn = 33,
SPIM2_IRQn = 34,
SPIS0_IRQn = 35,
SPIS1_IRQn = 36,
SPIMX8_0_IRQn = 37,
SPIMX8_1_IRQn = 38,
I2S0_IRQn = 39,
I2S1_IRQn = 40,
I2S2_IRQn = 41,
PDM0_IRQn = 42,
PDM1_IRQn = 43,
PDM2_IRQn = 44,
ADC_IRQn = 45,
CODEC_IRQn = 46,
SPDIF_IRQn = 47,
SBCDEC_IRQn = 48,
SBCENC_IRQn = 49,
MP3DEC_IRQn = 50,
PARALLEL_IRQn = 51,
CALI_IRQn = 53,
TRNG_IRQn = 54,
TICK_IRQn = 55,
TIMER4_IRQn = 60,
TIMER5_IRQn = 61,
IPC_DSP_IRQn = 63,
YUV2RGB_IRQn = 64,
PMU_IRQn = 65,
}IRQn_Type;
#endif // defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
#ifdef __XTENSA__
typedef enum IRQn
{
DSP_IPC_IRQn = 7,
}IRQn_Type;
#endif // __XTENSA__
/**
* @}
*/
#if defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
/**
* @brief Configuration of the Processor and Core Peripherals
*/
#define __CM33_REV 0x0003U /*!< Core revision r0p4 */
#define __SAUREGION_PRESENT 0 /*!< SAU regions present */
#define __MPU_PRESENT 1 /*!< MPU present */
#define __VTOR_PRESENT 1 /*!< VTOR present */
#define __FPU_PRESENT 1 /*!< FPU present or not */
#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include "core_cm33.h"
#if __SAUREGION_PRESENT == 1
#include "arm_cmse.h"
#endif
#endif // defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
#ifdef __XTENSA__
#define __WEAK __attribute__((weak))
#define __STATIC_INLINE __attribute__((always_inline))
#endif // __XTENSA__
/** @group Peripheral_memory_map
* @{
*/
#define FLASH_DAC_BASE (0x08000000)
#define DMAC0_BASE (0x10000000)
#define USB_OTG_BASE (0x10010000)
#define APB_BASE (0x10100000)
#define SBC_DEC_BASE (0x10100000)
#define SBC_ENC_BASE (0x10110000)
#define MP3_DEC_BASE (0x10120000)
#define CRC_BASE (0x10130000)
#define EFUSE_SISO_BASE (0x10140000)
#define EFUSE_PIPO_BASE (0x10150000)
#define SYSTEM_TIMER_BASE (0x10160000)
#define FREE_COUNTER_BASE (0x10170000)
#define CAN0_BASE (0x10180000)
#define CAN1_BASE (0x10190000)
#define SEC_BASE (0x11000000)
#define DSP_FLASH_DAC_BASE (0x28000000)
#define PSRAM_DAC_BASE (0x38000000)
#define SDIOH0_BASE (0x40000000)
#define SDIOH1_BASE (0x40010000)
#define DMAC1_BASE (0x40020000)
#define BLEND_AHB0_BASE (0x40030000)
#define BLEND_AHB1_BASE (0x40040000)
#define GPIOA_BASE (0x50000000)
#define GPIOB_BASE (0x50008000)
#define UART0_BASE (0x50010000)
#define UART1_BASE (0x50018000)
#define I2C0_BASE (0x50020000)
#define I2C1_BASE (0x50028000)
#define SPIM0_BASE (0x50030000)
#define SPIS0_BASE (0x50040000)
#define PWM0_BASE (0x50050000)
#define I2S0_BASE (0x50060000)
#define PDM0_BASE (0x50070000)
#define IIR_BASE (0x50080000)
#define TRI_FUNC_BASE (0x50090000)
#define FFT_BASE (0x500A0000)
#define AHBC_CACHE_BASE (0x500B0000)
#define PSRAM_OSPI_BASE (0x500B8000)
#define SPIMX8_0_BASE (0x500C0000)
#define PARALLEL_BASE (0x500D0000)
#define GPIOC_BASE (0x50100000)
#define GPIOD_BASE (0x50108000)
#define UART2_BASE (0x50110000)
#define UART3_BASE (0x50118000)
#define I2C2_BASE (0x50120000)
#define I2C3_BASE (0x50128000)
#define SPIM1_BASE (0x50130000)
#define SPIS1_BASE (0x50140000)
#define PWM1_BASE (0x50150000)
#define I2S1_BASE (0x50160000)
#define PDM1_BASE (0x50170000)
#define SPDIF_BASE (0x50180000)
#define CODEC_BASE (0x50190000)
#define SPIMX8_1_BASE (0x501C0000)
#define DSP_CTRL_BASE (0x50200000)
#define UART4_BASE (0x50210000)
#define UART5_BASE (0x50218000)
#define I2C4_BASE (0x50220000)
#define I2C5_BASE (0x50228000)
#define SPIM2_BASE (0x50230000)
#define DSP_TIM0_BASE (0x50240000)
#define DSP_TIM1_BASE (0x50240014)
#define DSP_WDT_BASE (0x50250000)
#define I2S2_BASE (0x50260000)
#define PDM2_BASE (0x50270000)
#define DSP_IPC_BASE (0x50280000)
#define DSP_QSPI_BASE (0x50290000)
#define YUV2RGB_BASE (0x502A0000)
#define SYSTEM_REG_BASE (0xE0050000)
#define TIM0_BASE (0xE0060000)
#define TIM1_BASE (0xE0060014)
#define TIM2_BASE (0xE0068000)
#define TIM3_BASE (0xE0068014)
#define FRSPIM_BASE (0xE0080000)
#define IPC_BASE (0xE0090000)
#define CALIB_BASE (0xE00A0000)
#define FLASH_CACHE_BASE (0xE00B0000)
#define FLASH_QSPI_BASE (0xE00C0000)
#define TRNG_BASE (0xE00D0000)
#define ADC_BASE (0xE00E0000)
#define SARADC_BASE (0xE00F0000)
/**
* @}
*/
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the system clock calculation.
*/
#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the system clock calculation.
*/
#define HSI_VALUE 24000000U /*!< Value of the Internal oscillator in Hz */
/* Peripheral drive */
#include "driver_common.h"
/* System driver */
#include "system_fr30xx.h"
/* trim relative */
#include "trim_fr30xx.h"
#ifdef __cplusplus
}
#endif
#endif // __FR30XX_H__

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MCU/components/drivers/device/fr30xx/system_fr30xx.c Normal file
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/*
******************************************************************************
* @file system_fr30xx.c
* @author FreqChip Firmware Team
* @version V1.0.0
* @date 2021
* @brief Device Peripheral Access Layer System Source File.
******************************************************************************
* @attention
*
* Copyright (c) 2021 FreqChip.
* All rights reserved.
*
******************************************************************************
*/
#include "fr30xx.h"
static uint32_t System_CORE_HSCLK = 24000000;
static uint32_t System_SPLLCLK;
static uint32_t System_AUPLLCLK;
uint32_t SystemCoreClock = 24000000;
static uint32_t SystemDSPClock = 24000000;
static uint32_t System_LPRCCLK = 57000;
static uint32_t system_prevent_sleep_label = SYSTEM_PREVENT_SLEEP_TYPE_DISABLE;
/*********************************************************************
* @fn SystemInit
*
* @brief System Misc Init.
*/
void SystemInit(void)
{
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* free counter enable */
__SYSTEM_FREE_COUNTER_CLK_ENABLE();
}
/*********************************************************************
* @fn System_CORE_HSCLK_CFG
*
* @brief CORE HSCLK config.
*/
void System_CORE_HSCLK_config(System_CORE_HSCLKConfig_t *COREHConfig)
{
if (COREHConfig->CORE_HSCLK_Source == CORE_HSCLK_SEL_HES)
{
__SYSTEM_CORE_HIGH_CLK_SELECT_OSC();
System_CORE_HSCLK = HSE_VALUE;
}
else
{
__SYSTEM_CORE_HIGH_CLK_SELECT_RC();
System_CORE_HSCLK = HSI_VALUE;
}
}
/*********************************************************************
* @fn System_SPLL_config
*
* @brief SPLL config.
*
* @param PLLConfig : SPLL config parameter.
* @param fu32_timeout : Wait for SPLL stable timeout, unit 5us.
*
* @return -1: SPLL stable timeout.
* 0: succeed.
*/
int System_SPLL_config(System_PLLConfig_t *PLLConfig, uint32_t fu32_timeout)
{
int PLL_stability_flag = 0;
#define SPLL_ANALOG_POWER_ENABLE (0XC04B1820)
#define SPLL_ANALOG_POWER_DISABLE (0XC04B1827)
#define SPLL_ANALOG_POWER_ENABLE_WITHOUT_M (0X404B1820)
if (PLLConfig->PowerEn)
{
SYSTEM->SPLLConfig3.PLL_N = PLLConfig->PLL_N;
SYSTEM->SPLLConfig3.PLL_M = PLLConfig->PLL_M;
if (PLLConfig->PLL_M)
SYSTEM->SPLLConfig0 = SPLL_ANALOG_POWER_ENABLE;
else
SYSTEM->SPLLConfig0 = SPLL_ANALOG_POWER_ENABLE_WITHOUT_M;
/* Wait for PLL stability timeout, unit 5us */
for (int i = 0; i < fu32_timeout; i++)
{
system_delay_us(5);
if (SYSTEM->SPLLConfig1 & 0x08)
{
PLL_stability_flag = 1;
break;
}
}
if (PLL_stability_flag)
{
__SYSTEM_SPLL_CLK_DIV2_ENABLE();
System_SPLLCLK = (PLLConfig->PLL_N*HSE_VALUE) + ((double)PLLConfig->PLL_M*HSE_VALUE)/0xFFFF;
}
else
{
System_SPLLCLK = 0;
return -1;
}
}
else
{
SYSTEM->SPLLConfig0 = SPLL_ANALOG_POWER_DISABLE;
System_SPLLCLK = 0;
}
return 0;
}
/*********************************************************************
* @fn System_AUPLL_config
*
* @brief AUPLL config.
*
* @param PLLConfig : AUPLL config parameter.
* @param fu32_timeout : Wait for AUPLL stable timeout, unit 5us.
*
* @return -1: AUPLL stable timeout.
* 0: succeed.
*/
int System_AUPLL_config(System_PLLConfig_t *PLLConfig, uint32_t fu32_timeout)
{
int PLL_stability_flag = 0;
#define AUPLL_ANALOG_POWER_ENABLE (0XC04B1820)
#define AUPLL_ANALOG_POWER_DISABLE (0XC04B1827)
#define AUPLL_ANALOG_POWER_ENABLE_WITHOUT_M (0X404B1820)
if (PLLConfig->PowerEn)
{
SYSTEM->AUPLLConfig3.PLL_N = PLLConfig->PLL_N;
SYSTEM->AUPLLConfig3.PLL_M = PLLConfig->PLL_M;
if (PLLConfig->PLL_M)
SYSTEM->AUPLLConfig0 = AUPLL_ANALOG_POWER_ENABLE;
else
SYSTEM->AUPLLConfig0 = AUPLL_ANALOG_POWER_ENABLE_WITHOUT_M;
/* Wait for PLL stability timeout, unit 5us */
for (int i = 0; i < fu32_timeout; i++)
{
system_delay_us(5);
if (SYSTEM->AUPLLConfig1 & 0x08)
{
PLL_stability_flag = 1;
break;
}
}
if (PLL_stability_flag)
{
System_AUPLLCLK = (PLLConfig->PLL_N*HSE_VALUE) + ((double)PLLConfig->PLL_M*HSE_VALUE)/0xFFFF;
}
else
{
System_SPLLCLK = 0;
return -1;
}
}
else
{
SYSTEM->AUPLLConfig0 = AUPLL_ANALOG_POWER_DISABLE;
System_AUPLLCLK = 0;
}
return 0;
}
/*********************************************************************
* @fn System_MCU_clock_Config
*
* @brief MCU clock congfig.
*/
void System_MCU_clock_Config(System_ClkConfig_t *ClkConfig)
{
/* MCU clock source select CORE_HSCLK */
if (ClkConfig->MCU_Clock_Source == MCU_CLK_SEL_CORE_HSCLK)
{
__SYSTEM_MCU_CLK_DIV(ClkConfig->MCU_DIV);
__SYSTEM_MCU_CLK_SELECT_COREH();
SystemDSPClock = System_CORE_HSCLK;
SystemCoreClock = System_CORE_HSCLK / ClkConfig->MCU_DIV;
}
/* MCU clock source select SPLLCLK */
else
{
__SYSTEM_SOC_CLK_DIV(ClkConfig->SOC_DIV);
__SYSTEM_MCU_CLK_DIV(ClkConfig->MCU_DIV);
__SYSTEM_MCU_CLK_SELECT_SPLL();
SystemDSPClock = System_SPLLCLK / ClkConfig->SOC_DIV;
SystemCoreClock = SystemDSPClock / ClkConfig->MCU_DIV;
}
__SYSTEM_APB0_CLK_RATIO(ClkConfig->APB0_DIV);
__SYSTEM_APB1_CLK_RATIO(ClkConfig->APB1_DIV);
__SYSTEM_APB2_CLK_RATIO(ClkConfig->APB2_DIV);
__SYSTEM_APB3_CLK_RATIO(ClkConfig->APB3_DIV);
}
/*********************************************************************
* @fn System_get_CoreClock/
* System_get_DSPClock/
* System_get_CORE_HSCLK/
* System_get_SPLLCLK/
* System_get_AUPLLCLK/
*
* @brief get system clock.unit HZ.
*/
__RAM_CODE uint32_t system_get_CoreClock(void)
{
return SystemCoreClock;
}
uint32_t system_get_DSPClock(void)
{
return SystemDSPClock;
}
uint32_t system_get_CORE_HSCLK(void)
{
return System_CORE_HSCLK;
}
uint32_t system_get_SPLLCLK(void)
{
return System_SPLLCLK;
}
uint32_t system_get_AUPLLCLK(void)
{
return System_AUPLLCLK;
}
uint32_t system_get_LPRCCLK(void)
{
return System_LPRCCLK;
}
void system_set_LPRCCLK(uint32_t clk)
{
System_LPRCCLK = clk;
}
/*********************************************************************
* @fn system_get_peripheral_clock
*
* @brief get peripheral clock. unit HZ
*
* @param fe_peripheral : peripheral select.
*
* @return peripheral clock unit HZ.
*/
uint32_t system_get_peripheral_clock(per_clock_index_t peripheral)
{
uint32_t PerClock;
switch (peripheral)
{
case PER_CLK_UARTx:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.UART_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.UART_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.UART_CLK_DIV + 1);
}break;
case PER_CLK_GPIOx:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.GPIO_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.GPIO_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.GPIO_CLK_DIV + 1);
}break;
case PER_CLK_I2Cx:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.I2C_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.I2C_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.I2C_CLK_DIV + 1);
}break;
case PER_CLK_TIMER01:{
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.TIMER01_CLK_DIV + 1);
}break;
case PER_CLK_TIMER23:{
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.TIMER23_CLK_DIV + 1);
}break;
case PER_CLK_SPIS:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV0.SSIS_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.SSIS_CLK_DIV + 1);
}break;
case PER_CLK_SPIMX8_0:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV0.MSPI0_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.MSPI0_CLK_DIV + 1);
}break;
case PER_CLK_SPIMX8_1:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV0.MSPI1_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.MSPI1_CLK_DIV + 1);
}break;
case PER_CLK_PWM:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV2.PWM_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.PWM_CLK_DIV + 1);
}break;
case PER_CLK_PDM0:
case PER_CLK_PDM1:
case PER_CLK_PDM2:
{
uint32_t PDMx_CLK_SEL, PDMx_CLK_DIV;
if (peripheral == PER_CLK_PDM0) {
PDMx_CLK_SEL = SYSTEM->ClockSEL1.PDM0_CLK_SEL;
PDMx_CLK_DIV = SYSTEM->AudioClockDIV.PDM0_CLK_DIV;
}
else if (peripheral == PER_CLK_PDM1){
PDMx_CLK_SEL = SYSTEM->ClockSEL1.PDM1_CLK_SEL;
PDMx_CLK_DIV = SYSTEM->AudioClockDIV.PDM1_CLK_DIV;
}
else{
PDMx_CLK_SEL = SYSTEM->ClockSEL1.PDM2_CLK_SEL;
PDMx_CLK_DIV = SYSTEM->AudioClockDIV.PDM2_CLK_DIV;
}
/* clock from HCLK */
if (PDMx_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (PDMx_CLK_DIV + 1);
/* clock from AUPLL */
else if (PDMx_CLK_SEL == 1)
PerClock = system_get_AUPLLCLK() / (PDMx_CLK_DIV + 1);
}break;
case PER_CLK_SDIOH0:
{
/* clock from HCLK */
if (SYSTEM->ClockSEL0.SDIOH0_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.SDIOH0_CLK_DIV + 1);
/* clock from SPLL */
else if (SYSTEM->ClockSEL0.SDIOH0_CLK_SEL == 1)
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH0_CLK_DIV + 1);
/* clock from AUPLL */
else
PerClock = system_get_AUPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH0_CLK_DIV + 1);
}break;
case PER_CLK_SDIOH1:
{
/* clock from HCLK */
if (SYSTEM->ClockSEL0.SDIOH1_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.SDIOH1_CLK_DIV + 1);
/* clock from SPLL */
else if (SYSTEM->ClockSEL0.SDIOH1_CLK_SEL == 1)
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH1_CLK_DIV + 1);
/* clock from AUPLL */
else
PerClock = system_get_AUPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH1_CLK_DIV + 1);
}break;
case PER_CLK_CANx:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.MCAN_CLK_SEL)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV2.MCAN_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.MCAN_CLK_DIV + 1);
}break;
case PER_CLK_I2Sx:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL1.I2S_CLK_SEL == 2)
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->AudioClockDIV.I2S_CLK_DIV + 1);
else if (SYSTEM->ClockSEL1.I2S_CLK_SEL == 1)
PerClock = (system_get_SPLLCLK()) / (SYSTEM->AudioClockDIV.I2S_CLK_DIV + 1);
else if (SYSTEM->ClockSEL1.I2S_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->AudioClockDIV.I2S_CLK_DIV + 1);
}break;
case PER_CLK_OSPI:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.OSPI_CLK_SEL == 2)
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->BlockClockDIV0.OSPI_CLK_DIV + 1);
else if(SYSTEM->ClockSEL0.OSPI_CLK_SEL == 1)
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.OSPI_CLK_DIV + 1);
else if(SYSTEM->ClockSEL0.OSPI_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.OSPI_CLK_DIV + 1);
}break;
case PER_CLK_QSPI0:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.QSPI0_CLK_SEL == 2)
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->BlockClockDIV0.QSPI0_CLK_DIV + 1);
else if(SYSTEM->ClockSEL0.QSPI0_CLK_SEL == 1)
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.QSPI0_CLK_DIV + 1);
else if(SYSTEM->ClockSEL0.QSPI0_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.QSPI0_CLK_DIV + 1);
}break;
case PER_CLK_QSPI1:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.QSPI1_CLK_SEL == 2)
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->BlockClockDIV0.QSPI1_CLK_DIV + 1);
else if(SYSTEM->ClockSEL0.QSPI1_CLK_SEL == 1)
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.QSPI1_CLK_DIV + 1);
else if(SYSTEM->ClockSEL0.QSPI1_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.QSPI1_CLK_DIV + 1);
}break;
case PER_CLK_SPIMx:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.SSIM_CLK_SEL == 1)
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV1.SSIM_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.SSIM_CLK_DIV + 1);
}break;
case PER_CLK_SBC:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL1.SBC_CLK_SEL == 1)
PerClock = system_get_SPLLCLK() / (SYSTEM->AudioClockDIV.SBC_CLK_DIV + 1);
else
PerClock = system_get_CORE_HSCLK() / (SYSTEM->AudioClockDIV.SBC_CLK_DIV + 1);
}break;
case PER_CLK_PARALLEL:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL0.PARALLEL_CLK_SEL == 2)
PerClock = (system_get_AUPLLCLK()/2) / (SYSTEM->BlockClockDIV1.PARALLEL_CLK_DIV + 1);
else if (SYSTEM->ClockSEL0.PARALLEL_CLK_SEL == 1)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.PARALLEL_CLK_DIV + 1);
else if (SYSTEM->ClockSEL0.PARALLEL_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.PARALLEL_CLK_DIV + 1);
}break;
case PER_CLK_SPDIF:
{
/* clock from SPLL */
if (SYSTEM->ClockSEL1.SPDIF_CLK_SEL == 2)
PerClock = (system_get_AUPLLCLK()/2) / (SYSTEM->AudioClockDIV.SPDIF_CLK_DIV + 1);
else if(SYSTEM->ClockSEL1.SPDIF_CLK_SEL == 1)
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->AudioClockDIV.SPDIF_CLK_DIV + 1);
else if(SYSTEM->ClockSEL1.SPDIF_CLK_SEL == 0)
PerClock = system_get_CORE_HSCLK() / (SYSTEM->AudioClockDIV.SPDIF_CLK_DIV + 1);
}break;
default: PerClock = 0;break;
}
return PerClock;
}
/*********************************************************************
* @fn system_dmac_request_id_config
*
* @brief dmac request id config.
*
* @param fe_source : dma request source.
* @param fe_id : user select request id.
*
* @return None.
*/
void system_dmac_request_id_config(dmac_request_source_t fe_source, dmac_request_id_t fe_id)
{
uint8_t lu8_RequestSource;
uint8_t lu8_RequestIDReg;
lu8_RequestIDReg = fe_source / 4;
lu8_RequestSource = fe_source % 4;
SYSTEM->DmacHsCfg[lu8_RequestIDReg] &= ~(0x1F << lu8_RequestSource * 8);
SYSTEM->DmacHsCfg[lu8_RequestIDReg] |= fe_id << (lu8_RequestSource * 8);
}
/*********************************************************************
* @fn system_delay_us
*
* @brief system delay unit us, use system free counter.
*
* @param fu32_delay: delay unit us.
*/
__RAM_CODE void system_delay_us(uint32_t fu32_delay)
{
uint32_t backups_tack = FREE_COUNTER_VALUE;
while(backups_tack - FREE_COUNTER_VALUE < fu32_delay);
}
/*********************************************************************
* @fn system_cache_enable
*
* @brief cache enable.
*
* @param invalid_ram : true: invalidating the cache SRAM.
* false: hold the cache SRAM.
*/
__RAM_CODE void system_cache_enable(bool invalid_ram)
{
uint32_t prim;
// manul enable the cache and invalidating the SRAM
prim = __get_PRIMASK();
__disable_irq();
switch (*(volatile uint32_t *)(FLASH_CACHE_BASE + 4) & 0x03) {
case 0x01: // enabling
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x03) != 0x02);
case 0x02: // enabled
break;
case 0x03: // disabling
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x03) != 0x00);
default:
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x38;
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3c;
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x10) == 0);
if(invalid_ram)
{
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3e;
while((*(volatile uint32_t *)FLASH_CACHE_BASE) & 0x02);
}
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3d;
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x03) != 0x02);
break;
}
if(!prim)
{
__enable_irq();
}
}
/*********************************************************************
* @fn system_cache_disable
*
* @brief cache disable.
*
*/
__RAM_CODE void system_cache_disable(void)
{
uint32_t prim;
// manul disable the cache
prim = __get_PRIMASK();
__disable_irq();
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3c;
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x38;
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+0x04)) & 0x03) != 0x00);
if(!prim)
{
__enable_irq();
}
}
void system_prevent_sleep_set(uint32_t type)
{
GLOBAL_INT_DISABLE();
system_prevent_sleep_label |= type;
GLOBAL_INT_RESTORE();
}
void system_prevent_sleep_clear(uint32_t type)
{
GLOBAL_INT_DISABLE();
system_prevent_sleep_label &= (~type);
GLOBAL_INT_RESTORE();
}
uint32_t system_prevent_sleep_get(void)
{
return system_prevent_sleep_label;
}
void system_reset(void)
{
__disable_irq();
// reboot
iwdt_Init_t iwdt_env;
iwdt_env.iwdt_Count = 300;
iwdt_env.iwdt_Timeout = 10;
iwdt_env.iwdt_int_Enable = WDT_INT_DISABLE;
iwdt_init(iwdt_env);
iwdt_Enable();
// ool_write(PMU_REG_IOLDO1_CTRL_0, (ool_read(PMU_REG_IOLDO1_CTRL_0) & 0xf0) | 0x01);
while(1);
}
/* ====================================================================================================== */
/* =============================== GLOBAL interrupt controller ===================================== */
/* ====================================================================================================== */
void GLOBAL_INT_START(void)
{
__asm (
"CPSIE i \n"
);
}
void GLOBAL_INT_STOP(void)
{
__asm (
"CPSID i \n"
);
}
__RAM_CODE void CPU_SR_Restore(uint32_t org_base_pri)
{
__asm (
"MSR BASEPRI, %[org]\n"
:
: [org]"r"(org_base_pri)
:
);
}
__RAM_CODE uint32_t CPU_SR_Save(uint32_t new_basepri)
{
uint32_t old_basepri;
__asm (
"MRS R4, BASEPRI\n"
"MSR BASEPRI, %[new]\n"
"MOV %[old], R4 \n"
: [old]"=r"(old_basepri)
: [new]"r"(new_basepri)
: "r4"
);
return old_basepri;
}

1755
MCU/components/drivers/device/fr30xx/system_fr30xx.h Normal file
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81
MCU/components/drivers/device/fr30xx/trim_fr30xx.c Normal file
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/*
******************************************************************************
* @file trim_fr30xx.c
* @author FreqChip Firmware Team
* @version V1.0.0
* @date 2023
* @brief Config Chip analog/digit/RF using Chip Probing(CP) and
Final Test(FT) trim parameters.
******************************************************************************
* @attention
*
* Copyright (c) 2022 FreqChip.
* All rights reserved.
******************************************************************************
*/
#include "fr30xx.h"
#include "crc32.h"
static struct_ADC_Cal_Param_t ADC_Cal_Param;
/*********************************************************************
* @fn trim_cp_config
*
* @brief Config Chip analog/digit/RF using Chip Probing(CP) trim parameters.
*
* @param none.
* @return none.
*/
void trim_cp_config(void)
{
/* ------------------------- */
/* FT trim */
/* ------------------------- */
}
/*********************************************************************
* @fn trim_ft_config
*
* @brief Config Chip analog/digit/RF using Final Test(FT) trim parameters.
*
* @param none.
* @return none.
*/
void trim_ft_config(void)
{
uint32_t FT_CRC;
struct_FT_Trim_t FT_Trim_Param;
flash_OTP_read(QSPI0,0x1000,sizeof(FT_Trim_Param),(uint8_t*)&FT_Trim_Param);
FT_CRC = crc32(0x00000000, (void *)&FT_Trim_Param, (uint32_t)&FT_Trim_Param.u32_crc - (uint32_t)&FT_Trim_Param);
if(FT_CRC == FT_Trim_Param.u32_crc)
{
if(FT_Trim_Param.u16_Version == 0xA001)
{
/* configure IOLDO output to 3.3v */
ool_write(PMU_REG_IOLDO1_CTRL_0, 0x0a);
/* config SBG */
ool_write(PMU_REG_SBG_CFG,FT_Trim_Param.u16_ioldo);
//Get the adc calibration value
ADC_Cal_Param.u16_slopeA = FT_Trim_Param.Param.V1.u16_SlopeA;
ADC_Cal_Param.u16_slopeB = FT_Trim_Param.Param.V1.u16_SlopeB;
ADC_Cal_Param.s32_constantA = FT_Trim_Param.Param.V1.s32_ConstantA;
ADC_Cal_Param.s32_constantB = FT_Trim_Param.Param.V1.s32_ConstantB;
}
}
}
/*********************************************************************
* @fn trim_get_adc_cal_param
*
* @brief get adc ft calibration param.
*/
struct_ADC_Cal_Param_t *trim_get_adc_cal_param(void)
{
return &ADC_Cal_Param;
}

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/*
******************************************************************************
* @file trim_fr30xx.h
* @author FreqChip Firmware Team
* @version V1.0.0
* @date 2023
* @brief Header file of trim HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 FreqChip.
* All rights reserved.
******************************************************************************
*/
#ifndef __TRIM_FR1010_H__
#define __TRIM_FR1010_H__
#include "fr30xx.h"
/** @addtogroup trim_Parameter_Section
* @{
*/
/* ################################ trim Parameter Section Start ################################ */
/*--------------------------------------------------*/
/* CP trim Parameter */
/*--------------------------------------------------*/
typedef __PACKED_STRUCT
{
/* --------- vendor-specific --------- */
volatile uint32_t Version : 2;
volatile uint32_t BBG_CODE : 5;
volatile uint32_t SYSLDO_CODE : 4;
volatile uint32_t BFB_CODE : 3;
volatile uint32_t DLDO_CODE : 3;
volatile uint32_t IOLDO_CODE : 3;
volatile uint32_t SBG_CODE : 4;
volatile uint32_t PKVDD_CODE : 4;
volatile uint32_t rsv_0 : 2;
volatile uint32_t LOT_ID : 10;
volatile uint32_t WaferID : 5;
volatile uint32_t XY : 16;
volatile uint32_t Year_Week : 14;
volatile uint32_t rsv_1 : 20;
/* --------- vendor-specific END--------- */
}struct_CP_Trim_t;
/*--------------------------------------------------*/
/* FT trim Parameter */
/*--------------------------------------------------*/
typedef struct
{
uint16_t u16_Version;
uint16_t u16_ioldo;
union {
struct{
int32_t s32_ConstantA;
int32_t s32_ConstantB;
uint16_t u16_SlopeA;
uint16_t u16_SlopeB;
}V1;
}Param;
uint32_t u32_crc;
}struct_FT_Trim_t;
typedef struct
{
uint32_t u16_slopeA;
uint32_t u16_slopeB;
int32_t s32_constantA;
int32_t s32_constantB;
}struct_ADC_Cal_Param_t;
/* ################################ trim Parameter Section END ################################## */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void trim_cp_config(void);
void trim_ft_config(void);
bool ft_trim_get_param(void);
struct_ADC_Cal_Param_t *trim_get_adc_cal_param(void);
#endif // __TRIM_FR1010_H__