demo工程暂存 优化菜单界面UI和功能

MCU/components/modules/dsp/dsp.c

@@ -0,0 +1,211 @@
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fr30xx.h"
+
+#include "dsp.h"
+
+#include "FreeRTOS.h"
+#include "ff.h"
+
+#define LOAD_CODE_FRAME_SIZE_FROM_FS            512
+#define LOAD_CODE_FRAME_SIZE_FROM_FLASH         256
+
+bool dsp_load_code_from_fs(char *path)
+{
+    struct bin_header {
+        uint32_t start;
+        uint32_t length;
+    } header;
+
+    FRESULT res;
+    FIL fstt;    
+    uint32_t length;
+    uint32_t *ptr;
+    uint32_t *buffer, *_buffer;
+    bool ret = true;
+    
+    res=f_open(&fstt, path, FA_OPEN_EXISTING | FA_READ);
+    if ( res != FR_OK ) {
+        return false;
+    }
+    else {
+        buffer = (void *)pvPortMalloc(LOAD_CODE_FRAME_SIZE_FROM_FS);
+        
+        /* get text section storage information */
+        f_read(&fstt, (void *)&header, sizeof(struct bin_header), &length);
+        if (length != sizeof(struct bin_header)) {
+            goto error;
+        }
+        
+        /* read text section storage into IRAM */
+        ptr = (void *)DSP_IRAM_2_MCU_SRAM(header.start);
+        while (header.length) {
+            uint32_t _length;
+            length = header.length > LOAD_CODE_FRAME_SIZE_FROM_FS ? LOAD_CODE_FRAME_SIZE_FROM_FS : header.length;
+            _buffer = buffer;
+            f_read(&fstt, (void *)_buffer, length, &_length);
+            if (length != _length) {
+                ret = false;
+                goto error;
+            }
+            while (_length) {
+                *ptr++ = *_buffer++;
+                _length -= 4;
+            }
+            header.length -= length;
+        }
+        
+        /* get RO and RW section storage information */
+        f_read(&fstt, (void *)&header, sizeof(struct bin_header), &length);
+        if (length != sizeof(struct bin_header)) {
+            ret = false;
+            goto error;
+        }
+        
+        /* read text section storage into DRAM */
+        ptr = (void *)DSP_DRAM_2_MCU_SRAM(header.start);
+        while (header.length) {
+            uint32_t _length;
+            length = header.length > LOAD_CODE_FRAME_SIZE_FROM_FS ? LOAD_CODE_FRAME_SIZE_FROM_FS : header.length;
+            _buffer = buffer;
+            f_read(&fstt, (void *)_buffer, length, &_length);
+            if (length != _length) {
+                ret = false;
+                goto error;
+            }
+            while (_length) {
+                *ptr++ = *_buffer++;
+                _length -= 4;
+            }
+            header.length -= length;
+        }
+    }
+    
+error:
+    vPortFree(buffer);
+    f_close(&fstt);
+    
+    return ret;
+}
+
+bool dsp_load_code_from_internal_flash(uint32_t address, uint32_t length)
+{
+    struct bin_header {
+        uint32_t start;
+        uint32_t length;
+    } header;
+ 
+    uint32_t sub_length, _sub_length;
+    uint32_t *ptr;
+    uint32_t *buffer, *_buffer;
+    bool ret = true;
+
+    buffer = (void *)pvPortMalloc(LOAD_CODE_FRAME_SIZE_FROM_FLASH);
+    
+    /* get text section storage information */
+    flash_read(QSPI0, address, sizeof(struct bin_header), (void *)&header);
+    address += sizeof(struct bin_header);
+    
+    /* read text section storage into IRAM */
+    ptr = (void *)DSP_IRAM_2_MCU_SRAM(header.start);
+    while (header.length) {
+        sub_length = header.length > LOAD_CODE_FRAME_SIZE_FROM_FLASH ? LOAD_CODE_FRAME_SIZE_FROM_FLASH : header.length;
+        _sub_length = sub_length;
+        _buffer = buffer;
+        flash_read(QSPI0, address, sub_length, (void *)_buffer);
+        while (sub_length) {
+            *ptr++ = *_buffer++;
+            sub_length -= 4;
+        }
+        header.length -= _sub_length;
+        address += _sub_length;
+    }
+    
+    /* get RO and RW section storage information */
+    flash_read(QSPI0, address, sizeof(struct bin_header), (void *)&header);
+    address += sizeof(struct bin_header);
+    
+    /* read text section storage into DRAM */
+    ptr = (void *)DSP_DRAM_2_MCU_SRAM(header.start);
+    while (header.length) {
+        sub_length = header.length > LOAD_CODE_FRAME_SIZE_FROM_FLASH ? LOAD_CODE_FRAME_SIZE_FROM_FLASH : header.length;
+        _sub_length = sub_length;
+        _buffer = buffer;
+        flash_read(QSPI0, address, sub_length, (void *)_buffer);
+        while (sub_length) {
+            *ptr++ = *_buffer++;
+            sub_length -= 4;
+        }
+        header.length -= _sub_length;
+        address += _sub_length;
+    }
+    
+error:
+    vPortFree(buffer);
+    
+    return ret;
+}
+
+bool dsp_load_rw_from_internal_flash(uint32_t address, uint32_t length)
+{
+    struct bin_header {
+        uint32_t start;
+        uint32_t length;
+    } header;
+ 
+    uint32_t sub_length, _sub_length;
+    uint32_t *ptr;
+    uint32_t *buffer, *_buffer;
+    bool ret = true;
+
+    buffer = (void *)pvPortMalloc(LOAD_CODE_FRAME_SIZE_FROM_FLASH);
+    
+    /* get text section storage information */
+    flash_read(QSPI0, address, sizeof(struct bin_header), (void *)&header);
+    address += sizeof(struct bin_header);
+
+    /* jump to RW header */
+    address += header.length;
+    
+    /* get RO and RW section storage information */
+    flash_read(QSPI0, address, sizeof(struct bin_header), (void *)&header);
+    address += sizeof(struct bin_header);
+    
+    /* read text section storage into DRAM */
+    ptr = (void *)DSP_DRAM_2_MCU_SRAM(header.start);
+    while (header.length) {
+        sub_length = header.length > LOAD_CODE_FRAME_SIZE_FROM_FLASH ? LOAD_CODE_FRAME_SIZE_FROM_FLASH : header.length;
+        _sub_length = sub_length;
+        _buffer = buffer;
+        flash_read(QSPI0, address, sub_length, (void *)_buffer);
+        while (sub_length) {
+            *ptr++ = *_buffer++;
+            sub_length -= 4;
+        }
+        header.length -= _sub_length;
+        address += _sub_length;
+    }
+    
+error:
+    vPortFree(buffer);
+    
+    return ret;
+}
+
+/* release DSP clock and keep DSP in suspend mode */
+void dsp_prepare(void)
+{
+    *(volatile uint32_t *)&SYSTEM->DSPClockEnable = 0xffffffff;
+    SYSTEM->DSPCTRL.DSP_RUNSTALL = 1;
+}
+
+void dsp_run(uint32_t vector)
+{
+    SYSTEM->DSPVectorConfig.DSP_VEC_TBL = vector;
+    SYSTEM->DSPVectorConfig.DSP_VEC_SEL = 1;
+    SYSTEM->DSPCTRL.DSP_DBGEN    = 1;
+    SYSTEM->DSPCTRL.DSP_NIDEN    = 1;
+    SYSTEM->DSPCTRL.DSP_SPIDEN   = 1;
+    SYSTEM->DSPCTRL.DSP_RUNSTALL = 0;
+}

MCU/components/modules/dsp/dsp.h

@@ -0,0 +1,53 @@
+#ifndef _DSP_H
+#define _DSP_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "fr30xx.h"
+
+#define DSP_IRAM_BASE_ADDR                  0x78400000
+#define DSP_IMEM_MCU_BASE_ADDR              0x1FFC0000
+#define DSP_DRAM_BASE_ADDR                  0x781E0000
+#define DSP_DRAM_MCU_BASE_ADDR              0x200C0000
+#define DSP_IRAM_SIZE                       0x00020000
+#define DSP_DRAM_SIZE                       0x00040000
+
+#define DSP_IRAM_2_MCU_SRAM(x)              ((uint32_t)(x) - DSP_IRAM_BASE_ADDR + DSP_IMEM_MCU_BASE_ADDR)
+#define DSP_DRAM_2_MCU_SRAM(x)              ((uint32_t)(x) - DSP_DRAM_BASE_ADDR + DSP_DRAM_MCU_BASE_ADDR)
+#define MCU_SRAM_2_DSP_DRAM(x)              ((uint32_t)(x) - DSP_DRAM_MCU_BASE_ADDR + DSP_DRAM_BASE_ADDR)
+
+//__INLINE void dsp_reset_vector_set(uint32_t vector)
+//{
+//    SYSTEM->DSPVectorConfig.DSP_VEC_TBL = vector;
+//    SYSTEM->DSPVectorConfig.DSP_VEC_SEL = 1;
+//}
+
+//__INLINE void dsp_reset(void)
+//{
+//    SYSTEM->DSPRegReset.DSP_MAS_SFT_RST = 1;
+//}
+
+//__INLINE void dsp_release(void)
+//{
+//    SYSTEM->DSPRegReset.DSP_MAS_SFT_RST = 0;
+//}
+
+//__INLINE void dsp_run(void)
+//{
+//    SYSTEM->DSPCTRL.DSP_RUNSTALL = 0;
+//}
+
+//__INLINE void dsp_stall(void)
+//{
+//    SYSTEM->DSPCTRL.DSP_RUNSTALL = 1;
+//}
+
+bool dsp_load_code_from_fs(char *path);
+bool dsp_load_code_from_internal_flash(uint32_t address, uint32_t length);
+bool dsp_load_rw_from_internal_flash(uint32_t address, uint32_t length);
+
+void dsp_prepare(void);
+void dsp_run(uint32_t vector);
+
+#endif  // _DSP_H

MCU/components/modules/dsp/dsp_mem.c

@@ -0,0 +1,59 @@
+#include "dsp.h"
+#include "dsp_rpmsg.h"
+
+void *dsp_mem_alloc(uint32_t size)
+{
+    void *result;
+    
+    rpmsg_sync_invoke(rpmsg_get_remote_instance(), RPMSG_SYNC_FUNC_MEM_ALLOC, (void *)&size, (uint32_t *)&result);
+
+    return (void*)DSP_DRAM_2_MCU_SRAM(result);
+}
+
+void dsp_mem_free(void *ptr)
+{
+    void *buffer = (void *)MCU_SRAM_2_DSP_DRAM(ptr);
+
+    rpmsg_sync_invoke(rpmsg_get_remote_instance(), RPMSG_SYNC_FUNC_MEM_FREE, (void *)&buffer, NULL);
+}
+
+uint32_t dsp_mem32_read(uint32_t address)
+{
+    uint32_t value;
+    
+    rpmsg_sync_invoke(rpmsg_get_remote_instance(), RPMSG_SYNC_FUNC_MEM_READ, (void *)&address, &value);
+
+    return value;
+}
+
+void dsp_mem32_write(uint32_t address, uint32_t value)
+{
+    struct rpmsg_sync_msg_mem_write_t sync_msg;
+    
+    sync_msg.address = address;
+    sync_msg.value = value;
+
+    rpmsg_sync_invoke(rpmsg_get_remote_instance(), RPMSG_SYNC_FUNC_MEM_READ, (void *)&sync_msg, NULL);
+}
+
+void dsp_cache_attr_set(uint32_t icache_attr, uint32_t dcache_attr, uint8_t icache_ways, uint8_t dcache_ways)
+{
+    struct rpmsg_sync_msg_cache_attr_t sync_msg;
+    
+    sync_msg.icache_ways = icache_ways;
+    sync_msg.dcache_ways = dcache_ways;
+    sync_msg.icache_attr = icache_attr;
+    sync_msg.dcache_attr = dcache_attr;
+
+    rpmsg_sync_invoke(rpmsg_get_remote_instance(), RPMSG_SYNC_FUNC_CACHE_ATTR, (void *)&sync_msg, NULL);
+}
+
+void dsp_mem_get_usage(uint32_t *curr_free, uint32_t *min_free)
+{
+    struct rpmsg_sync_msg_mem_usage_t mem_usage;
+    
+    mem_usage.curr_free = curr_free;
+    mem_usage.min_free = min_free;
+
+    rpmsg_sync_invoke(rpmsg_get_remote_instance(), RPMSG_SYNC_FUNC_MEM_USAGE, (void *)&mem_usage, NULL);
+}

MCU/components/modules/dsp/dsp_mem.h

@@ -0,0 +1,15 @@
+#ifndef _DSP_MEM_H
+#define _DSP_MEM_H
+
+#include <stdint.h>
+
+void *dsp_mem_alloc(uint32_t size);
+void dsp_mem_free(void *ptr);
+void dsp_mem_get_usage(uint32_t *curr_free, uint32_t *min_free);
+
+uint32_t dsp_mem32_read(uint32_t address);
+void dsp_mem32_write(uint32_t address, uint32_t value);
+
+void dsp_cache_attr_set(uint32_t icache_attr, uint32_t dcache_attr, uint8_t icache_ways, uint8_t dcache_ways);
+
+#endif  // _DSP_MEM_H

MCU/components/modules/dsp/dsp_rpmsg.h

@@ -0,0 +1,35 @@
+#ifndef _DSP_RPMSG_H
+#define _DSP_RPMSG_H
+
+#include <stdint.h>
+
+#include "rpmsg.h"
+
+#define RPMSG_SYNC_FUNC_MEM_ALLOC           RPMSG_SYNC_FUNC_MSG(RPMSG_SYNC_FUNC_TYPE_DSP, 0x0001)
+#define RPMSG_SYNC_FUNC_MEM_FREE            RPMSG_SYNC_FUNC_MSG(RPMSG_SYNC_FUNC_TYPE_DSP, 0x0002)
+#define RPMSG_SYNC_FUNC_DSP_CHG_FRQ         RPMSG_SYNC_FUNC_MSG(RPMSG_SYNC_FUNC_TYPE_DSP, 0x0003)  // DSP request to change working frequency
+#define RPMSG_SYNC_FUNC_MEM_READ            RPMSG_SYNC_FUNC_MSG(RPMSG_SYNC_FUNC_TYPE_DSP, 0x0004)
+#define RPMSG_SYNC_FUNC_MEM_WRITE           RPMSG_SYNC_FUNC_MSG(RPMSG_SYNC_FUNC_TYPE_DSP, 0x0005)
+#define RPMSG_SYNC_FUNC_CACHE_ATTR          RPMSG_SYNC_FUNC_MSG(RPMSG_SYNC_FUNC_TYPE_DSP, 0x0006)
+#define RPMSG_SYNC_FUNC_MEM_USAGE           RPMSG_SYNC_FUNC_MSG(RPMSG_SYNC_FUNC_TYPE_DSP, 0x0007)
+
+struct rpmsg_sync_msg_mem_write_t {
+    uint32_t address;
+    uint32_t value;
+};
+
+struct rpmsg_sync_msg_cache_attr_t {
+    uint32_t icache_attr;
+    uint32_t dcache_attr;
+    uint8_t icache_ways;
+    uint8_t dcache_ways;
+};
+
+struct rpmsg_sync_msg_mem_usage_t {
+    uint32_t *curr_free;
+    uint32_t *min_free;
+};
+
+void dsp_rpmsg_handler(struct rpmsg_lite_instance *rpmsg, struct rpmsg_msg_t *msg);
+
+#endif  // _DSP_RPMSG_H