294 lines
14 KiB
ArmAsm
294 lines
14 KiB
ArmAsm
;************************* (C) COPYRIGHT 2023 FreqChip ***************************
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;* File Name : startup_fr30xx.s
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;* Author : FreqChip Firmware Team
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;* Version : V1.0.0
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;* Date : 2022
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;* Description : fr30xx Devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Configure the clock system
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M33 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;*********************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2022 FreqChip.
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;* All rights reserved.
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;*******************************************************************************
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;<h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;</h>
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Stack_Size EQU 0x00001000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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__stack_limit
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Stack_Mem SPACE Stack_Size
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__initial_sp
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;<h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;</h>
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Heap_Size EQU 0x00019000
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IF Heap_Size != 0 ; Heap is provided
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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ENDIF
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; -14 NMI Handler
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DCD HardFault_Handler ; -13 Hard Fault Handler
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DCD MemManage_Handler ; -12 MPU Fault Handler
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DCD BusFault_Handler ; -11 Bus Fault Handler
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DCD UsageFault_Handler ; -10 Usage Fault Handler
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DCD SecureFault_Handler ; -9 Secure Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; -5 SVCall Handler
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DCD DebugMon_Handler ; -4 Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; -2 PendSV Handler
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DCD SysTick_Handler ; -1 SysTick Handler
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; Interrupts
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DCD timer0_irq ; 0 Interrupt 0
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DCD timer1_irq ; 1 Interrupt 1
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DCD timer2_irq ; 2 timer2
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DCD timer3_irq ; 3 timer3
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DCD dma0_irq ; 4 dma0
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DCD dma1_irq ; 5 dma1
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DCD sdioh0_irq ; 6 sdioh
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DCD sdioh1_irq ; 7 sdiod
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DCD ipc_mcu_irq ; 8 ipc mcu
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DCD usbotg_irq ; 9 usbotg
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DCD iir_irq ; 10 iir
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DCD blend_irq ; 11 trigfunc
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DCD fft_irq ; 12 fft
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DCD sec_aes_irq ; 13 Interrupt 13
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DCD Interrupt14_Handler ; 14 Interrupt 14
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DCD Interrupt15_Handler ; 15 Interrupt 15
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DCD gpioa_irq ; 16 GPIOA
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DCD gpiob_irq ; 17 GPIOB
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DCD gpioc_irq ; 18 GPIOC
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DCD gpiod_irq ; 19 GPIOD
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DCD uart0_irq ; 20 uart0
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DCD uart1_irq ; 21 uart1
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DCD uart2_irq ; 22 uart2
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DCD uart3_irq ; 23 uart3
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DCD uart4_irq ; 24 uart4
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DCD uart5_irq ; 25 uart5
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DCD i2c0_irq ; 26 i2c0
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DCD i2c1_irq ; 27 i2c1
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DCD i2c2_irq ; 28 i2c2
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DCD i2c3_irq ; 29 i2c3
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DCD i2c4_irq ; 30 i2c4
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DCD i2c5_irq ; 31 i2c5
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DCD spim0_irq ; 32 spim0
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DCD spim1_irq ; 33 spim1
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DCD spim2_irq ; 34 spim2
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DCD spis0_irq ; 35 spis0
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DCD spis1_irq ; 36 spis1
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DCD spimx8_0_irq ; 37 spimx8_0
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DCD spimx8_1_irq ; 38 spimx8_1
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DCD i2s0_irq ; 39 i2s0
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DCD i2s1_irq ; 40 i2s1
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DCD i2s2_irq ; 41 i2s2
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DCD pdm0_irq ; 42 pdm0
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DCD pdm1_irq ; 43 pdm1
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DCD pdm2_irq ; 44 pdm2
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DCD adc_irq ; 45 adc
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DCD codec_irq ; 46 codec
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DCD spdif_irq ; 47 spdif
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DCD sbc_dec_irq ; 48 sbc_dec
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DCD sbc_enc_irq ; 49 sbc_enc
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DCD mp3dec_irq ; 50 mp3dec
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DCD parallel0_irq ; 51 parallel0
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DCD Interrupt52_Handler ; 52 Interrupt 52
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DCD cali_irq ; 53 cali
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DCD trng_irq ; 54 trng
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DCD tick_irq ; 55 Interrupt 55
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DCD Interrupt56_Handler ; 56 Interrupt 56
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DCD Interrupt57_Handler ; 57 Interrupt 57
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DCD Interrupt58_Handler ; 58 Interrupt 58
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DCD Interrupt59_Handler ; 59 Interrupt 59
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DCD timer4_irq ; 60 timer4
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DCD timer5_irq ; 61 timer5
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DCD Interrupt62_Handler ; 62 Interrupt 62
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DCD ipc_dsp_irq ; 63 Interrupt 63
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DCD yuv2rgb_irq ; 64 yuv2rgb
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DCD pmu_irq ; 65 pmu
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DCD 0xAA55AA55 ; app check data
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DCD 0x00000001 ; app version
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DCD 0 ; code length
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; SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =__stack_limit
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MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Macro to define default exception/interrupt handlers.
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; Default handler are weak symbols with an endless loop.
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; They can be overwritten by real handlers.
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MACRO
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Set_Default_Handler $Handler_Name
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$Handler_Name PROC
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EXPORT $Handler_Name [WEAK]
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B .
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ENDP
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MEND
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; Default exception/interrupt handler
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Set_Default_Handler NMI_Handler
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Set_Default_Handler HardFault_Handler
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Set_Default_Handler MemManage_Handler
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Set_Default_Handler BusFault_Handler
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Set_Default_Handler UsageFault_Handler
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Set_Default_Handler SecureFault_Handler
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Set_Default_Handler SVC_Handler
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Set_Default_Handler DebugMon_Handler
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Set_Default_Handler PendSV_Handler
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Set_Default_Handler SysTick_Handler
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Set_Default_Handler timer0_irq
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Set_Default_Handler timer1_irq
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Set_Default_Handler timer2_irq
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Set_Default_Handler timer3_irq
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Set_Default_Handler dma0_irq
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Set_Default_Handler dma1_irq
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Set_Default_Handler sdioh0_irq
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Set_Default_Handler sdioh1_irq
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Set_Default_Handler ipc_mcu_irq
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Set_Default_Handler usbotg_irq
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Set_Default_Handler iir_irq
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Set_Default_Handler blend_irq
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Set_Default_Handler fft_irq
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Set_Default_Handler sec_aes_irq
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Set_Default_Handler Interrupt14_Handler
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Set_Default_Handler Interrupt15_Handler
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Set_Default_Handler gpioa_irq
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Set_Default_Handler gpiob_irq
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Set_Default_Handler gpioc_irq
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Set_Default_Handler gpiod_irq
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Set_Default_Handler uart0_irq
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Set_Default_Handler uart1_irq
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Set_Default_Handler uart2_irq
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Set_Default_Handler uart3_irq
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Set_Default_Handler uart4_irq
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Set_Default_Handler uart5_irq
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Set_Default_Handler i2c0_irq
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Set_Default_Handler i2c1_irq
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Set_Default_Handler i2c2_irq
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Set_Default_Handler i2c3_irq
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Set_Default_Handler i2c4_irq
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Set_Default_Handler i2c5_irq
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Set_Default_Handler spim0_irq
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Set_Default_Handler spim1_irq
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Set_Default_Handler spim2_irq
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Set_Default_Handler spis0_irq
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Set_Default_Handler spis1_irq
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Set_Default_Handler spimx8_0_irq
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Set_Default_Handler spimx8_1_irq
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Set_Default_Handler i2s0_irq
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Set_Default_Handler i2s1_irq
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Set_Default_Handler i2s2_irq
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Set_Default_Handler pdm0_irq
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Set_Default_Handler pdm1_irq
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Set_Default_Handler pdm2_irq
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Set_Default_Handler adc_irq
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Set_Default_Handler codec_irq
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Set_Default_Handler spdif_irq
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Set_Default_Handler sbc_dec_irq
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Set_Default_Handler sbc_enc_irq
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Set_Default_Handler mp3dec_irq
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Set_Default_Handler parallel0_irq
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Set_Default_Handler Interrupt52_Handler
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Set_Default_Handler cali_irq
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Set_Default_Handler trng_irq
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Set_Default_Handler tick_irq
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Set_Default_Handler Interrupt56_Handler
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Set_Default_Handler Interrupt57_Handler
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Set_Default_Handler Interrupt58_Handler
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Set_Default_Handler Interrupt59_Handler
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Set_Default_Handler timer4_irq
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Set_Default_Handler timer5_irq
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Set_Default_Handler Interrupt62_Handler
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Set_Default_Handler ipc_dsp_irq
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Set_Default_Handler yuv2rgb_irq
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Set_Default_Handler pmu_irq
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ALIGN
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; User setup Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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