289 lines
12 KiB
C
289 lines
12 KiB
C
/*
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******************************************************************************
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* @file driver_sbc_dec.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2021
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* @brief Header file of SBC DEC module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_SBC_DEC_H__
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#define __DRIVER_SBC_DEC_H__
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#include "fr30xx.h"
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#define SBCD_INFIFO_DEEPTH 128
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#define SBCD_OUTLFIFO_DEEPTH 256
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#define SBCD_OUTRFIFO_DEEPTH 256
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/** @addtogroup SBC_CODEC_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* SBC DEC CTRL REGISTER 0x00*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t DEC_EN : 1;//sbc decoder enable
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uint32_t DEC_LR_SWAP : 1;//swap decoder left and rignt channel enable
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uint32_t DEC_OUTL_FLOW_CTRL : 1;//whether use the left outfifo almost full status to control whether to read the infifo
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uint32_t DEC_OUTR_FLOW_CTRL : 1;//whether use the right outfifo almost full status to control whether to read the infifo
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uint32_t DEC_RESET : 1;//decoder reset
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uint32_t DEC_IN_FIFO_RESET : 1;//decoder infifo reset
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uint32_t DEC_OUTL_FIFO_RESET : 1;//decoder left outfifo reset
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uint32_t DEC_OUTR_FIFO_RESET : 1;//decoder right outfifo reset
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uint32_t IN_DMA_EN : 1;//infifo dma enable
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uint32_t OUT_DMA_EN : 1;//outfifo dma enable
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uint32_t OUTL_FIFO_EN : 1;//outfifo status select left fifo
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uint32_t OUTR_FIFO_EN : 1;//outfifo status select right fifo
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uint32_t RSV : 20;
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} Bits;
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} REG_SBCD_CTRL_t;
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/* SBC DEC IN FIFO REG REGISTER 0x04*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t SBC_IN : 8;//sbc encoded data in
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uint32_t RSV : 24;
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} Bits;
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} REG_SBCD_INFIFO_REG_t;
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/* SBC DEC OUT FIFO REG REGISTER 0x08*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t PCM_RIGHT_DATA : 16;//sbc encoded data in
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uint32_t PCM_LEFT_DATA : 16;
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} Bits;
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} REG_SBCD_OUTFIFO_REG_t;
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/* SBC DEC INT EN REGISTER 0x0C*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t INFF_FULL_INT_EN : 1;//input fifo full interrupt enbale
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uint32_t INFF_EMPTY_INT_EN : 1;//input fifo empty interrupt enbale
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uint32_t INFF_ALEMPTY_INT_EN : 1;//input fifo almost empty interrupt enbale
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uint32_t RSV1 : 1;
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uint32_t OUTLFF_FULL_INT_EN : 1;//output left fifo full interrupt enbale
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uint32_t OUTLFF_EMPTY_INT_EN : 1;//output left fifo empty interrupt enbale
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uint32_t OUTLFF_ALFULL_INT_EN : 1;//output left fifo almost full interrupt enbale
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uint32_t RSV2 : 1;
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uint32_t OUTRFF_FULL_INT_EN : 1;//output right fifo full interrupt enbale
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uint32_t OUTRFF_EMPTY_INT_EN : 1;//output right fifo empty interrupt enbale
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uint32_t OUTRFF_ALFULL_INT_EN : 1;//output right fifo amlost full interrupt enbale
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uint32_t RSV3 : 1;
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uint32_t CRC_ERR_INT_EN : 1;//crc error flag interrupt enable
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uint32_t RSV4 : 19;
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} Bits;
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} REG_SBCD_INTEN_REG_t;
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/* SBC DEC INT STATUS REGISTER 0x10*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t INFF_FULL_INT_STS : 1;//input fifo full interrupt status
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uint32_t INFF_EMPTY_INT_STS : 1;//input fifo empty interrupt status
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uint32_t INFF_ALEMPTY_INT_STS : 1;//input fifo almost empty interrupt status
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uint32_t RSV1 : 1;
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uint32_t OUTLFF_FULL_INT_STS : 1;//output left fifo full interrupt status
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uint32_t OUTLFF_EMPTY_INT_STS : 1;//output left fifo empty interrupt status
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uint32_t OUTLFF_ALFULL_INT_STS : 1;//output left fifo almost full interrupt status
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uint32_t RSV2 : 1;
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uint32_t OUTRFF_FULL_INT_STS : 1;//output right fifo full interrupt status
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uint32_t OUTRFF_EMPTY_INT_STS : 1;//output right fifo empty interrupt status
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uint32_t OUTRFF_ALFULL_INT_STS : 1;//output right fifo almost full interrupt status
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uint32_t RSV3 : 1;
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uint32_t CRC_ERR_INT_STS : 1;//crc interrupt status ,write 1 to cleat this bit
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uint32_t RSV4 : 19;
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} Bits;
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} REG_SBCD_INTS_REG_t;
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/* SBC DEC FIFO STATE REGISTER 0x14 */
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t INFIFO_FULL : 1;//infifo full flag
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uint32_t INFIFO_EMPTY : 1;//infifo empty flag
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uint32_t INFIFO_ALEMPTY : 1;//infifo almost empty flag
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uint32_t RSV1 : 1;
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uint32_t OUTLFIFO_FULL : 1;//outlfifo full flag
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uint32_t OUTLFIFO_EMPTY : 1;//outlfifo empty flag
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uint32_t OUTLFIFO_ALFULL : 1;//outlfifo almost full flag
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uint32_t RSV2 : 1;
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uint32_t OUTRFIFO_FULL : 1;//outrfifo full flag
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uint32_t OUTRFIFO_EMPTY : 1;//outrfifo empty flag
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uint32_t OUTRFIFO_ALFULL : 1;//outrfifo almost full flag
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uint32_t RSV : 21;
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} Bits;
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} REG_SBCD_FIFO_STATE_t;
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/* SBC DEC FIFO INWDS 0x18*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t INFIFO_WC : 8;//input fifo words count
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uint32_t RSV : 24;//
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} Bits;
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} REG_SBCD_FIFO_INWDS_t;
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/* SBC DEC FIFO OUTWDS 0x1C*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t OUTLFIFO_WC : 8;//output left fifo words pointer
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uint32_t RSV1 : 8;
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uint32_t OUTRFIFO_WC : 8;//output right fifo words pointer
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uint32_t RSV2 : 8;
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} Bits;
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} REG_SBCD_FIFO_OUTWDS_t;
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/*SBC FIFO LEVEL 0x20*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t INFIFO_ALEMPTY_LEVEL : 7;//output left fifo words pointer
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uint32_t RSV1 : 1;
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uint32_t OUTLFIFO_ALFULL_LEVEL : 8;//output right fifo words pointer
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uint32_t OUTRFIFO_ALFULL_LEVEL : 8;//output right fifo words pointer
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uint32_t RSV2 : 8;
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} Bits;
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} REG_SBCD_FIFO_LEVEL_t;
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typedef struct
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{
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volatile REG_SBCD_CTRL_t SBCD_CTRL; /* Offset 0x00 */
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volatile REG_SBCD_INFIFO_REG_t SBCD_INFIFO; /* Offset 0x04 */
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volatile REG_SBCD_OUTFIFO_REG_t SBCD_OUTFIFO; /* Offset 0x08 */
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volatile REG_SBCD_INTEN_REG_t SBCD_INTEN; /* Offset 0x0C */
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volatile REG_SBCD_INTS_REG_t SBCD_INTS; /* Offset 0x10 */
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volatile REG_SBCD_FIFO_STATE_t SBCD_FIFO_STATE; /* Offset 0x14 */
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volatile REG_SBCD_FIFO_INWDS_t SBCD_FIFO_INWDS; /* Offset 0x18 */
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volatile REG_SBCD_FIFO_OUTWDS_t SBCD_FIFO_OUTWDS; /* Offset 0x1C */
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volatile REG_SBCD_FIFO_LEVEL_t SBCD_FIFO_LEVEL; /* Offset 0x20 */
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}struct_SBCD_t;
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#define SBC_DEC ((struct_SBCD_t *)SBC_DEC_BASE)
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typedef enum{
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SBCD_MONO = 0,
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SBCD_STEREO,
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}enum_Ch_Mode_t ;
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t infifo_alempty_lvl : 7;
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uint32_t outlfifo_alfull_lvl : 8;
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uint32_t outrlfifo_alfull_lvl : 8;
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uint32_t input_dma_en : 1;
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uint32_t output_dma_en : 1;
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uint32_t outlfifo_en : 1;
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uint32_t outrfifo_en : 1;
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uint32_t ch_mode : 1;
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uint32_t RSV : 4;
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}Bits;
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}struct_SBCDec_Init_t;
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typedef struct __SBC_DEC_HandleTypeDef
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{
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struct_SBCDec_Init_t sbc_init;
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uint8_t *EncodeData;
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uint32_t DataSize;
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uint16_t *OrignData;
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uint32_t InputIndex;
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uint32_t OutIndex;
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void (*Callback)(struct __SBC_DEC_HandleTypeDef *hSbcDec); /*!< SBC decode finish Callback */
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}SBC_DEC_HandleTypeDef;
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typedef enum
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{
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INFF_FULL_INT = (1 << 0),
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INFF_EMPTY_INT = (1 << 1),
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INFF_ALEMPTY_INT = (1 << 2),
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OUTLF_FULL_INT = (1 << 4),
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OUTLF_EMPTY_INT = (1 << 5),
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OUTLF_ALFULL_INT = (1 << 6),
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OUTRF_FULL_INT = (1 << 8),
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OUTRF_EMPTY_INT = (1 << 9),
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OUTRF_ALFULL_INT = (1 << 10),
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CRC_ERR_INT = (1 << 12),
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}enum_isr_status_t ;
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typedef struct{
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uint8_t frequency;
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uint8_t block_mode;
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uint8_t block_len;
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uint8_t channels;
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uint8_t bit_pool;
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enum {
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MONO = 0,
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DUAL_CHANNEL = 1,
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STEREO = 2,
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JOINT_STEREO = 3
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} mode;
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enum {
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LOUDNESS = 0,
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SNR = 1
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} allocation;
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uint8_t subband_mode;
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uint8_t subbands;
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}struct_frame_info_t;
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#define __SBCD_INFIFO_IS_FULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.INFIFO_FULL == 1)
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#define __SBCD_INFIFO_IS_EMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.INFIFO_EMPTY == 1)
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#define __SBCD_INFIFO_IS_ALEMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.INFIFO_ALEMPTY == 1)
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#define __SBCD_OUTLFIFO_IS_FULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTLFIFO_FULL == 1)
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#define __SBCD_OUTLFIFO_IS_EMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTLFIFO_EMPTY == 1)
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#define __SBCD_OUTLFIFO_IS_ALFULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTLFIFO_ALFULL == 1)
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#define __SBCD_OUTRFIFO_IS_FULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTRFIFO_FULL == 1)
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#define __SBCD_OUTRFIFO_IS_EMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTRFIFO_EMPTY == 1)
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#define __SBCD_OUTRFIFO_IS_ALFULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTRFIFO_ALFULL == 1)
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#define __SBCD_GET_ISR_STS() (SBC_DEC->SBCD_INTS.Word)
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#define __SBCD_INFIFO_EMPTY_DISABLE() (SBC_DEC->SBCD_INTEN.Bits.INFF_EMPTY_INT_EN = 0)
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/* sbc decoder initialize */
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void sbc_dec_init(SBC_DEC_HandleTypeDef *hSbcDec);
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/* sbc decoder get packed frame info */
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int sbc_dec_get_packed_frame_info(uint8_t *data, struct_frame_info_t frame_info);
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/* sbc decoder handle function in sbc decoder isr */
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void sbcdec_IRQHandler(SBC_DEC_HandleTypeDef *hSbcDec);
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/* sbc decoder play data with isr */
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void sbc_dec_playdata_IT(SBC_DEC_HandleTypeDef *hSbcDec, uint8_t *fp_Data, uint32_t fu32_Size, uint16_t *fp_Data_Out);
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#endif
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