235 lines
10 KiB
C
235 lines
10 KiB
C
/*
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******************************************************************************
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* @file driver_sd_device.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2022
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* @brief Header file of SD device HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_SD_DEVICE_H__
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#define __DRIVER_SD_DEVICE_H__
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#include "fr30xx.h"
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/** @addtogroup SD_device_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* Capability0 Register */
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typedef struct
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{
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uint32_t ProgramDone : 1;
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uint32_t rsv_0 : 1;
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uint32_t CardInitDone : 1;
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uint32_t AddressOutRange : 1;
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uint32_t AddressMisalign : 1;
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uint32_t RpmbDisable : 1;
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uint32_t EraseParam : 1;
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uint32_t CardECCFailed : 1;
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uint32_t CCError : 1;
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uint32_t Error : 1;
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uint32_t MMC_IRQ_Trigger : 1;
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uint32_t CMDDataOutputEdge : 1;
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uint32_t CMD32_CMD33_Enable : 1;
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uint32_t BootSequenceSupport : 1;
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uint32_t SwitchError : 1;
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uint32_t SendBootACK : 1;
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uint32_t WP_Violation : 1;
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uint32_t WP_Erase_Skip : 1;
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uint32_t CID_CSD_Overwrite : 1;
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uint32_t AKE_Seq_Error : 1;
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uint32_t Card_ECC_Disabled : 1;
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uint32_t StreamThresholdSize : 3;
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uint32_t PermanentWriteProtect : 1;
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uint32_t TemporaryWriteProtect : 1;
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uint32_t WPCommandsEnabled : 1;
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uint32_t ALLOW_AKE : 1;
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uint32_t SECURED_MODE : 1;
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uint32_t AKE_SEQ_OK : 1;
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uint32_t ASSD_Disable : 1;
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uint32_t BootDataReady : 1;
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}REG_SDDevice_Control_t;
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/* Command Register */
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typedef struct
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{
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uint32_t Application : 1;
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uint32_t BlockSize : 12;
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uint32_t CommandIndex : 6;
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uint32_t CurrentBusWidth : 2;
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uint32_t CurrentSpeed : 3;
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uint32_t CardState : 4;
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uint32_t EraseSequence : 1;
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uint32_t rsv_0 : 3;
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}REG_SDDevice_Command_t;
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/* Password Length Register */
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typedef struct
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{
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uint32_t PWDS_LEN : 8;
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uint32_t LockUnlockEnable : 1;
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uint32_t rsv_0 : 23;
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}REG_PasswordLength_t;
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/* -------------------------------------------------*/
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/* SD Device Register */
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/* -------------------------------------------------*/
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typedef struct
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{
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volatile REG_SDDevice_Control_t Control; /* Offset 0x00 */
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volatile REG_SDDevice_Command_t Command; /* Offset 0x04 */
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volatile uint32_t Argument; /* Offset 0x08 */
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volatile uint32_t BlockCount; /* Offset 0x0C */
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volatile uint32_t DMA1Address; /* Offset 0x10 */
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volatile uint32_t DMA1Control; /* Offset 0x14 */
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volatile uint32_t DMA2Address; /* Offset 0x18 */
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volatile uint32_t DMA2Control; /* Offset 0x1C */
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volatile uint32_t EraseWriteBlockStart; /* Offset 0x20 */
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volatile uint32_t EraseWriteblockEnd; /* Offset 0x24 */
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volatile REG_PasswordLength_t PasswordLength; /* Offset 0x28 */
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volatile uint32_t SecureBlockCount; /* Offset 0x2C */
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volatile uint32_t rsv_0[3];
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volatile uint32_t IntStatus; /* Offset 0x3C */
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volatile uint32_t IntStatusEn; /* Offset 0x40 */
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volatile uint32_t IntSignalEn; /* Offset 0x44 */
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volatile uint32_t CardAddress; /* Offset 0x48 */
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volatile uint32_t CardData; /* Offset 0x4C */
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volatile uint32_t IOREADY; /* Offset 0x50 */
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volatile uint32_t Function1Control; /* Offset 0x54 */
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volatile uint32_t Function2Control; /* Offset 0x58 */
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volatile uint32_t SDIOCCCRControl; /* Offset 0x5C */
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volatile uint32_t SDIOFBRxControl[8]; /* Offset 0x60 ~ 0x7C */
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volatile uint32_t CardSize; /* Offset 0x80 */
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volatile uint32_t CardOCR; /* Offset 0x84 */
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volatile uint32_t Control2; /* Offset 0x88 */
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volatile uint32_t rsv_1;
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volatile uint32_t Function3Control; /* Offset 0x90 */
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volatile uint32_t Function4Control; /* Offset 0x94 */
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volatile uint32_t Function5Control; /* Offset 0x98 */
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volatile uint32_t IntStatus2; /* Offset 0x9C */
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volatile uint32_t IntStatusEn2; /* Offset 0xA0 */
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volatile uint32_t IntSignal2; /* Offset 0xA4 */
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volatile uint32_t Password_127_96; /* Offset 0xA8 */
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volatile uint32_t Password_95_64; /* Offset 0xAC */
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volatile uint32_t Password_63_32; /* Offset 0xB0 */
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volatile uint32_t Passowrd_31_0; /* Offset 0xB4 */
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volatile uint32_t ADMAErrorStatus; /* Offset 0xB8 */
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volatile uint32_t RCA; /* Offset 0xBC */
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volatile uint32_t Debug[7]; /* Offset 0xC0 ~ 0xD8 */
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volatile uint32_t AHBMasterBurstSize; /* Offset 0xDC */
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volatile uint32_t Argument2; /* Offset 0xE0 */
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}struct_SD_Device_t;
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#define SD_DEVICE ((struct_SD_Device_t *)SDIOD0_BASE)
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/* ################################ Register Section END ################################## */
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/**
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* @}
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*/
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/** @addtogroup SD_device_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization<6F><6E>Config Section Start ################################ */
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/* SD device interrupt status mask */
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typedef enum
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{
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INT_TRANSFER_COMP = 0x00000001,
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INT_DMA1 = 0x00000002,
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INT_SLEEP_AWAKE = 0x00000004,
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INT_WRITE_START = 0x00000008,
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INT_READ_START = 0x00000010,
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INT_PASSWORD_SET = 0x00000020,
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INT_PASSWORD_RESET = 0x00000040,
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INT_LOCK_CARD = 0x00000080,
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INT_UNLOCK_CARD = 0x00000100,
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INT_FORCE_ERASE = 0x00000200,
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INT_ERASE = 0x00000400,
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INT_CMD11 = 0x00000800,
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INT_CMD0_CMD52 = 0x00001000,
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INT_CMD6_CHECK = 0x00002000,
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INT_CMD6_SWITCH = 0x00004000,
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INT_PROGRAM_CSD = 0x00008000,
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INT_ACMD23 = 0x00010000,
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INT_CMD20 = 0x00020000,
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/* 0x00040000 */
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INT_CMD4 = 0x00080000,
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INT_BOOT_START = 0x00100000,
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INT_FUNCTION1_RESET = 0x00200000,
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INT_FUNCTION2_RESET = 0x00400000,
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INT_CMD11_CLK_STOP = 0x00800000,
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INT_CMD11_CLK_START = 0x01000000,
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INT_PROGRAM_START = 0x02000000,
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INT_CMD40 = 0x04000000,
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INT_CMD_R1b = 0x08000000,
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INT_FUNCTIONX_ERROR = 0x10000000,
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INT_FUNCTIONX_ABORT = 0x20000000,
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INT_LRST = 0x40000000,
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INT_BOOT_COMPLETE = 0x80000000,
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}enum_SD_Device_Status_t;
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/* ################################ Initialization<6F><6E>Config Section END ################################## */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* ----------------------*/
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/* Control control */
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/* ----------------------*/
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/* Program Done */
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#define __SD_D_SET_PROGRAM_DONE(__SDx__) (__SDx__->Control.ProgramDone = 1)
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/* Card Init Done */
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#define __SD_D_CARD_INIT_DONE(__SDx__) (__SDx__->Control.CardInitDone = 1)
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/* Address Out of Range */
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#define __SD_D_ADDR_OUT_RANGE(__SDx__) (__SDx__->Control.AddressOutRange = 1)
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/* Address Misalign */
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#define __SD_D_ADDR_MISALIGN(__SDx__) (__SDx__->Control.AddressMisalign = 1)
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/* Command and Data Output at the falling edge */
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/* Command and Data Output at the Rising edge */
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#define __SD_D_FALLING_EDGE_OUTPUT(__SDx__) (__SDx__->Control.CMDDataOutputEdge = 0)
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#define __SD_D_RISING_EDGE_OUTPUT(__SDx__) (__SDx__->Control.CMDDataOutputEdge = 1)
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/* support/nonsupport CMD32 CMD33 */
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#define __SD_D_CMD32_CMD33_ENABLE(__SDx__) (__SDx__->Control.CMD32_CMD33_Enable = 0)
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#define __SD_D_CMD32_CMD33_DISABLE(__SDx__) (__SDx__->Control.CMD32_CMD33_Enable = 1)
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/* Stream Threshold Size */
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#define __SD_D_SET_STREAM_THRESHOLD_SIZE(__SDx__, __SIZE__) (__SDx__->Control.StreamThresholdSize = __SIZE__)
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/* Set card address */
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/* Set card data */
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#define __SD_D_SET_CARD_ADDR(__SDx__, __ADDR__) (__SDx__->CardAddress = __ADDR__)
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#define __SD_D_SET_CARD_DATA(__SDx__, __DATA__) (__SDx__->CardData = __DATA__)
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/* get interrupt status */
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#define __SD_D_GET_INT_STATUS(__SDx__) (__SDx__->IntStatus)
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/* clear interrupt status */
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#define __SD_D_CLR_INT_STATUS(__SDx__, __STATUS__) (__SDx__->IntStatus |= __STATUS__)
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/* interrupt Status enable/disable */
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#define __SD_D_INT_STATUS_ENABLE(__SDx__, __STATUS__) (__SDx__->IntStatusEn |= (__STATUS__))
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#define __SD_D_INT_STATUS_DISABLE(__SDx__, __STATUS__) (__SDx__->IntStatusEn &= ~(__STATUS__))
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#define __SD_D_INT_STATUS_ALL_ENABLE(__SDx__) (__SDx__->IntStatusEn = 0xFFFFFFFF)
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#define __SD_D_INT_STATUS_ALL_DISABLE(__SDx__) (__SDx__->IntStatusEn = 0x00000000)
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/* interrupt Signal enable/disable */
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#define __SD_D_INT_ENABLE(__SDx__, __STATUS__) (__SDx__->IntSignalEn |= (__STATUS__))
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#define __SD_D_INT_DISABLE(__SDx__, __STATUS__) (__SDx__->IntSignalEn &= ~(__STATUS__))
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/* Exported functions --------------------------------------------------------*/
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#endif
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