153 lines
5.1 KiB
C
153 lines
5.1 KiB
C
/*
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******************************************************************************
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* @file driver_iir.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2022
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* @brief Header file of IIR module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_IIR_H__
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#define __DRIVER_IIR_H__
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#include "fr30xx.h"
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/** @addtogroup IIR_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* IIR CTRL */
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typedef struct
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{
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uint32_t N_DIV : 7;
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uint32_t rsv_0 : 1;
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uint32_t ORDER_SEL : 2;
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uint32_t rsv_1 : 6;
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uint32_t NODE_SEL : 2;
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uint32_t rsv_2 : 6;
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uint32_t NBYTE_SEL : 2;
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uint32_t ESV4 : 6;
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} REG_IIR_CTRL_t;
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/* IIR THR FIFO */
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typedef struct
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{
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uint32_t THR_TX_FIFO : 6;
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uint32_t rsv_0 : 10;
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uint32_t THR_RX_FIFO : 6;
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uint32_t rsv_1 : 10;
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} REG_IIR_THR_FIFO_t;
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typedef struct
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{
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volatile uint32_t IIR_COEF[20]; /* Offser 0x00-0x4c*/
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volatile REG_IIR_CTRL_t IIR_CTRL; /* Offset 0x50*/
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volatile REG_IIR_THR_FIFO_t IIR_THR_FIFO; /* Offset 0x54*/
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volatile uint32_t rsv_0;
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volatile uint32_t rsv_1;
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volatile uint32_t IIR_SOFTRST; /* Offset 0x60*/
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volatile uint32_t rsv_2[5];
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volatile uint32_t IIR_STATUS; /* Offset 0x78*/
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volatile uint32_t rsv_3;
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volatile uint32_t IIR_FIFO; /* Offset 0x80*/
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}struct_IIR_t;
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#define IIR_FILTER ((struct_IIR_t *)IIR_BASE)
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/* ################################ Register Section END ################################## */
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/**
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* @}
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*/
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/** @addtogroup IIR_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization_Config Section Start ################################ */
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/* FIFO Status */
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typedef enum
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{
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TX_FIFO_FULL = 0x01,
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TX_FIFO_EMPTY = 0x02,
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TX_FIFO_AL_EMPTY = 0x04,
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RX_FIFO_FULL = 0x08,
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RX_FIFO_EMPTY = 0x10,
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RX_FIFO_AL_FULL = 0x20,
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}enum_IIR_INT_Index_t;
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/* Nbytes Select */
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typedef enum{
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IIR_BYTE_1,
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IIR_BYTE_2,
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IIR_BYTE_3,
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IIR_BYTE_ALL,
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}enum_Nbytes_sel_t;
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/* Node Select */
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typedef enum{
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THE_FIRST_STAGE_OUTPUT,
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THE_SENCOND_STAGE_OUTPUT,
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THE_THIRD_STAGE_OUTPUT,
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THE_FOURTH_STAGE_OUTPUT,
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}enum_Node_Sel_t;
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/* Order Select */
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typedef enum{
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ORDER_2,
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ORDER_4,
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ORDER_6,
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ORDER_8,
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}enum_Order_Sel_t;
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typedef struct
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{
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uint32_t IIRCoef[20]; /*!< Specifies the internal Feedback coefficient.
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This parameter The value can be a value 0~0xFFFFFF*/
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uint8_t N_Div; /*!< Specifies the internal read/write tx and rx FIFO is relative The frequency division factor of the system clock.
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This parameter The value should be greater than 2*(order_sel + 1)*5 */
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uint8_t Order_Sel; /*!< Specifies the internal Filter order configuration.
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This parameter can be a value of @ref enum_Order_Sel_t */
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uint8_t Node_Sel; /*!< Specifies the internal Filter order configuration.
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This parameter can be a value of @ref enum_Node_Sel_t */
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uint8_t Nbytes_Sel; /*!< Specifies the internal Filter order configuration.
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This parameter can be a value of @ref enum_Nbytes_sel_t */
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}IIR_InitTypeDef;
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/* ################################ Initialization_Config Section END ################################## */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* RxFIFO/TxFIFO Threshold level */
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#define __IIR_RxFIFO_THRESHOLD_LEVEL(__LEVEL__) (IIR_FILTER->IIR_THR_FIFO.THR_RX_FIFO = __LEVEL__)
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#define __IIR_TxFIFO_THRESHOLD_LEVEL(__LEVEL__) (IIR_FILTER->IIR_THR_FIFO.THR_TX_FIFO = __LEVEL__)
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/* SOFTRST Set and Clear */
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#define __IIR_SOFTRST_SET() (IIR_FILTER->IIR_SOFTRST = 0)
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#define __IIR_SOFTRST_CLEAR() (IIR_FILTER->IIR_SOFTRST = 1)
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/* Get FIFO status */
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#define __IIR_GET_FIFO_STATUS(__STATUS__) (IIR_FILTER->IIR_STATUS & __STATUS__)
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/* Exported functions ---------------------------------------------------------*/
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/* iir_init */
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void iir_init(IIR_InitTypeDef *hiir);
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/* iir_filter_start */
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void iir_filter_start(uint32_t *fp_Data_In, uint32_t *fp_Data_Out, uint32_t fu32_Size);
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#endif
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