264 lines
11 KiB
C
264 lines
11 KiB
C
/*
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******************************************************************************
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* @file driver_parallel_interface.H
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2021
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* @brief Header file of parallel_interface HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_PARALLEL_INTERFACE_H__
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#define __DRIVER_PARALLEL_INTERFACE_H__
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#include "fr30xx.h"
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/** @addtogroup Parallel_Interface_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* parallel interface config */
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typedef struct
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{
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uint32_t DC_POLARITY : 1;
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uint32_t CS_POLARITY : 1;
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uint32_t MODE : 1;
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uint32_t PARA_WIDTH : 1;
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uint32_t rsv_0 : 28;
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}REG_INTERFACE_CFG_t;
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/* Write/Read clock Config */
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typedef struct
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{
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uint32_t WRITE_CLK_CFG : 3;
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uint32_t rsv_0 : 1;
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uint32_t READ_CLK_CFG : 4;
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uint32_t WR_L_LEN : 3;
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uint32_t rsv_1 : 1;
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uint32_t WR_H_LEN : 3;
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uint32_t rsv_2 : 17;
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}REG_WR_CLK_t;
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/* Data transmission Configuration */
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typedef struct
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{
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uint32_t DATA_TRANS_SEQ_0 : 2;
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uint32_t DATA_TRANS_SEQ_1 : 2;
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uint32_t DATA_TRANS_SEQ_2 : 2;
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uint32_t DATA_TRANS_SEQ_3 : 2;
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uint32_t rsv_1 :24;
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}REG_DATA_CFG_t;
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/* DMA Configuration */
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typedef struct
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{
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uint32_t DMA_TX_LEVEL : 5;
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uint32_t DMA_ENABLE : 1;
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uint32_t rsv_0 : 26;
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}REG_DMA_t;
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/* -------------------------------------------*/
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/* parallel Register */
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/* -------------------------------------------*/
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typedef struct
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{
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volatile REG_INTERFACE_CFG_t INTF_CFG; /* offset 0x00 */
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volatile uint32_t CSX; /* offset 0x04 */
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volatile REG_WR_CLK_t CRM; /* offset 0x08 */
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volatile uint32_t BUS_STATUS; /* offset 0x0C */
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volatile uint32_t CFG; /* offset 0x10 */
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volatile uint32_t DATA_WR_LEN; /* offset 0x14 */
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volatile REG_DATA_CFG_t DATA_CFG; /* offset 0x18 */
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volatile uint32_t TX_FIFO; /* offset 0x1C */
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volatile uint32_t RD_REQ; /* offset 0x20 */
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volatile uint32_t DAT_RD; /* offset 0x24 */
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volatile uint32_t TXFF_AEMP_LV; /* offset 0x28 */
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volatile uint32_t TXFF_CLR; /* offset 0x2C */
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volatile uint32_t INT_CONTROL; /* offset 0x30 */
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volatile uint32_t INT_STATUS; /* offset 0x34 */
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volatile REG_DMA_t DMA; /* offset 0x38 */
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}struct_Parallel_t;
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#define PARALLEL0 ((struct_Parallel_t *)PARALLEL_BASE)
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/* ################################ Register Section END ################################ */
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/**
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* @}
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*/
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/** @addtogroup Parallel_Interface_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization_Config Section Start ################################ */
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/** @defgroup PARALLEL_FIFO PARALLEL FIFO
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* @{
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*/
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#define PARALLEL_FIFO_DEPTH 32
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/**
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* @}
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*/
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/* mode select */
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typedef enum
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{
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MODE_8080,
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MODE_6800,
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}enum_Parallel_MODE_t;
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/* data bus width */
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typedef enum
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{
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DATA_BUS_8_BIT,
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DATA_BUS_16_BIT,
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}enum_DATA_BUS_t;
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/* read clock division */
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typedef enum
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{
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RDCLK_DIV_1,
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RDCLK_DIV_2,
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RDCLK_DIV_3,
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RDCLK_DIV_4,
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RDCLK_DIV_6,
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RDCLK_DIV_8,
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RDCLK_DIV_16,
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RDCLK_DIV_32,
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RDCLK_DIV_64,
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}enum_RDCLK_DIV_t;
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/* write clock division */
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typedef enum
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{
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WDCLK_DIV_1,
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WDCLK_DIV_2,
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WDCLK_DIV_3,
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WDCLK_DIV_4,
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WDCLK_DIV_6,
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WDCLK_DIV_8,
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}enum_WDCLK_DIV_t;
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/* interrupt index */
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typedef enum
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{
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INT_TXFIFO_FULL = 0x00000001,
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INT_TXFIFO_EMPTY = 0x00000002,
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INT_TXFIFO_LEVEMPT = 0x00000004,
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}enum_INT_t;
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/**
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* @brief parallel Initialization Structure definition
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*/
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typedef struct
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{
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uint32_t ParallelMode; /* This parameter can be a value of @ref enum_Parallel_MODE_t */
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uint32_t DataBusSelect; /* This parameter can be a value of @ref enum_DATA_BUS_t */
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uint32_t ReadClock; /* This parameter can be a value of @ref enum_RDCLK_DIV_t */
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uint32_t WriteClock; /* This parameter can be a value of @ref enum_WDCLK_DIV_t */
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}str_ParallelInit_t;
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/**
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* @brief parallel handle Structure definition
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*/
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typedef struct
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{
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struct_Parallel_t *PARALLELx; /*!< PARALLEL registers base address */
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str_ParallelInit_t Init; /*!< PARALLEL communication parameters */
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}PARALLEL_HandTypeDef;
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/* ################################ Initialization_Config Section END ################################ */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Parallel tx fifo level */ /* fu8_level: 0 ~ 31 */
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#define __PARALLEL_TX_FIFO_ALMOST_EMPTY_LEVEL(__PARALLELx__, __LEVEL__) (__PARALLELx__->TXFF_AEMP_LV = __LEVEL__)
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/* Parallel tx fifo reset */
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/* Parallel tx fifo release */
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#define __PARALLEL_TX_FIFO_RESET(__PARALLELx__) (__PARALLELx__->TXFF_CLR = 0x07)
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#define __PARALLEL_TX_FIFO_RELEASE(__PARALLELx__) (__PARALLELx__->TXFF_CLR = 0x00)
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/* Parallel writer CMD */
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#define __PARALLEL_WR_CMD(__PARALLELx__ , __CMD__) (__PARALLELx__->CFG = __CMD__)
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#define __PARALLEL_WR_PARAM(__PARALLELx__ , __DATA__) (__PARALLELx__->CFG = 0x10000 | __DATA__)
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/* Parallel get interrupt status */
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#define __PARALLEL_INT_STATUS(__PARALLELx__) (__PARALLELx__->INT_STATUS)
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/* Parallel interrupt Status enable/disable */
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#define __PARALLEL_INT_STATUS_ENABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL |= (__STATUS__))
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#define __PARALLEL_INT_STATUS_DISABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL &= ~(__STATUS__))
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#define __PARALLEL_INT_STATUS_ALL_ENABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL = 0x0F)
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#define __PARALLEL_INT_STATUS_ALL_DISABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL = 0x00)
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/* Parallel bus status */
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#define __PARALLEL_IS_BUS_BUSY(__PARALLELx__) (__PARALLELx__->BUS_STATUS)
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/* Parallel bus status */
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#define __PARALLEL_RD_REQ(__PARALLELx__) (__PARALLELx__->RD_REQ = 0x1)
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/* Parallel_dma_requset_level */ /* fu8_level: 0 ~ 31 */
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#define __PARALLEL_DMA_TX_LEVEL(__PARALLELx__, __LEVEL__) (__PARALLELx__->DMA.DMA_TX_LEVEL = __LEVEL__)
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/* Parallel_dma ENABLE and DISABLE */
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#define __PARALLEL_DMA_ENABLE(__PARALLELx__) (__PARALLELx__->DMA.DMA_ENABLE = 1)
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#define __PARALLEL_DMA_DISABLE(__PARALLELx__) (__PARALLELx__->DMA.DMA_ENABLE = 0)
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/* Parallel_cs_set */
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/* Parallel_cs_release */
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#define __PARALLEL_CS_SET(__PARALLELx__) (__PARALLELx__->CSX = 0)
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#define __PARALLEL_CS_RELEASE(__PARALLELx__) (__PARALLELx__->CSX = 1)
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/* Parallel_set_bus_8bit */
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/* Parallel_set_bus_16bit */
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#define __PARALLEL_SET_BUS_8BIT(__PARALLELx__) (__PARALLELx__->INTF_CFG.PARA_WIDTH = DATA_BUS_8_BIT)
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#define __PARALLEL_SET_BUS_16BIT(__PARALLELx__) (__PARALLELx__->INTF_CFG.PARA_WIDTH = DATA_BUS_16_BIT)
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/* Parallel_wrclk_div */
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/* Parallel_rdclk_div */
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#define __PARALLEL_WRCLK_DIV(__PARALLELx__, __WDCLK_DIV__) (__PARALLELx__->CRM.WRITE_CLK_CFG = __WDCLK_DIV__)
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#define __PARALLEL_RDCLK_DIV(__PARALLELx__, __RDCLK_DIV__) (__PARALLELx__->CRM.READ_CLK_CFG = __RDCLK_DIV__)
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/* Parallel_wrclk_HighLength */
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/* Parallel_wrclk_LowLength */
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#define __PARALLEL_WRCLK_HIGHLENGTH(__PARALLELx__, __LENGTH__) (__PARALLELx__->CRM.WR_H_LEN = __LENGTH__)
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#define __PARALLEL_WRCLK_LOWLENGTH(__PARALLELx__, __LENGTH__) (__PARALLELx__->CRM.WR_L_LEN = __LENGTH__)
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/* Parallel_CS_Polarity */ /* fb_Polarity: 1: high active */
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/* Parallel_DC_Polarity */ /* 0: low active */
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#define __PARALLEL_CS_POLARITY(__PARALLELx__, __POLARITY__) (__PARALLELx__->INTF_CFG.CS_POLARITY = __POLARITY__)
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#define __PARALLEL_DC_POLARITY(__PARALLELx__, __FB_POLARITY__) (__PARALLELx__->INTF_CFG.DC_POLARITY = __POLARITY__)
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/* __PARALLEL_Set_WR_LEN */
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#define __PARALLEL_SET_WR_LEN(__PARALLELx__, __LEVEL__) (__PARALLELx__->DATA_WR_LEN = __LEVEL__)
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/* Exported functions ---------------------------------------------------------------*/
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/* parallel_init */
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void parallel_init(PARALLEL_HandTypeDef *hparallel);
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/* Parallel_write_cmd */
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/* Parallel_write_param */
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/* Parallel_write_data */
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void Parallel_write_cmd(PARALLEL_HandTypeDef *hparallel, uint8_t fp8_CMD);
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void Parallel_write_param(PARALLEL_HandTypeDef *hparallel, uint16_t fu16_Data);
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void Parallel_write_data(PARALLEL_HandTypeDef *hparallel, uint32_t *fp32_WriteBuffer, uint32_t fu32_WriteNum);
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/* Parallel_read_data_8bit */
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/* Parallel_read_data_16bit */
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void Parallel_read_data_8bit(PARALLEL_HandTypeDef *hparallel, uint8_t fu8_Param, uint8_t *fp8_ReadBuffer, uint32_t fu32_ReadNum);
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void Parallel_read_data_16bit(PARALLEL_HandTypeDef *hparallel, uint8_t fu8_Param, uint16_t *fp16_ReadBuffer, uint32_t fu32_ReadNum);
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#endif
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