307 lines
12 KiB
C
307 lines
12 KiB
C
/*
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******************************************************************************
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* @file driver_sbc_enc.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2021
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* @brief Header file of SBC ENC module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_SBC_ENC_H__
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#define __DRIVER_SBC_ENC_H__
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#include "fr30xx.h"
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#define SBCE_INFIFO_DEEPTH 256
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#define SBCE_OUTFIFO_DEEPTH 128
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/** @addtogroup SBC_ENC_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* SBC ENC CTRL REGISTER 0x00*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t ENC_EN : 1;//sbc encoder enable
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uint32_t ENC_LR_SWAP : 1;//swap encoder left and rignt channel enable
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uint32_t ENC_INL_FLOW_CTRL : 1;//bypass in left fifo status
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uint32_t ENC_INR_FLOW_CTRL : 1;//bypass in right fifo status
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uint32_t ENC_RESET : 1;//encoder reset
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uint32_t ENC_OUT_FIFO_RESET : 1;//encoder outfifo reset
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uint32_t ENC_INL_FIFO_RESET : 1;//encoder left infifo reset
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uint32_t ENC_INR_FIFO_RESET : 1;//encoder right infifo reset
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uint32_t IN_DMA_EN : 1;//infifo dma enable
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uint32_t OUT_DMA_EN : 1;//outfifo dma enable
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uint32_t INL_FIFO_EN : 1;//infifo status select left fifo
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uint32_t INR_FIFO_EN : 1;//infifo status select right fifo
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uint32_t RSV : 20;
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} Bits;
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} REG_SBCE_CTRL_t;
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/* SBC ENC CONFIG REGISTER 0x04*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t SMP_FRQ : 2;//sbc encoder sample frequncy 00->16KHz, 01->32KHz, 10->44.1KHz, 11->48KHz
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uint32_t BLK_LEN : 2;//block length 00->4 01->8 10->12 11->16
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uint32_t RSV1 : 1;
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uint32_t CH_MODE : 1;//0->mono 1->dual
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uint32_t RSV2 : 26;
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} Bits;
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} REG_SBCE_CFG_t;
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/* SBC ENC IN FIFO REG REGISTER 0x08*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t ENC_FFL : 16;//left channel input data
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uint32_t ENC_FFR : 16;//right channel input data
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} Bits;
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} REG_SBCE_INFIFO_REG_t;
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/* SBC ENC OUT FIFO REG REGISTER 0x0C*/
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/* SBC ENC INT EN REGISTER 0x10*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t OUTFF_FULL_INT_EN : 1;//output fifo full interrupt enbale
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uint32_t OUTFF_EMPTY_INT_EN : 1;//output fifo empty interrupt enbale
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uint32_t OUTFF_ALFULL_INT_EN : 1;//output fifo almost full interrupt enbale
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uint32_t RSV1 : 1;
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uint32_t INLFF_FULL_INT_EN : 1;//input left fifo full interrupt enbale
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uint32_t INLFF_EMPTY_INT_EN : 1;//input left fifo empty interrupt enbale
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uint32_t INLFF_ALEMPTY_INT_EN : 1;//input left fifo almost empty interrupt enbale
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uint32_t RSV2 : 1;
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uint32_t INRFF_FULL_INT_EN : 1;//input right fifo full interrupt enbale
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uint32_t INRFF_EMPTY_INT_EN : 1;//input right fifo empty interrupt enbale
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uint32_t INRFF_ALEMPTY_INT_EN : 1;//input right fifo amlost empty interrupt enbale
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uint32_t RSV3 : 21;
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} Bits;
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} REG_SBCE_INTEN_REG_t;
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/* SBC ENC INT STATUS REGISTER 0x14*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t OUTFF_FULL_INT_STS : 1;//output fifo full interrupt status
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uint32_t OUTFF_EMPTY_INT_STS : 1;//output fifo empty interrupt status
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uint32_t OUTFF_ALFULL_INT_STS : 1;//output fifo almost full interrupt status
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uint32_t RSV1 : 1;
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uint32_t INLFF_FULL_INT_STS : 1;//input left fifo full interrupt status
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uint32_t INLFF_EMPTY_INT_STS : 1;//input left fifo empty interrupt status
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uint32_t INLFF_ALEMPTY_INT_STS : 1;//input left fifo almost empty interrupt status
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uint32_t RSV2 : 1;
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uint32_t INRFF_FULL_INT_STS : 1;//input right fifo full interrupt status
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uint32_t INRFF_EMPTY_INT_STS : 1;//input right fifo empty interrupt status
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uint32_t INRFF_ALEMPTY_INT_STS : 1;//input right fifo almost empty interrupt status
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uint32_t RSV3 : 21;
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} Bits;
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} REG_SBCE_INTS_REG_t;
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/* SBC ENC FIFO STATE REGISTER 0x18 */
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t OUTFIFO_FULL : 1;//outfifo full flag
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uint32_t OUTFIFO_EMPTY : 1;//outfifo empty flag
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uint32_t OUTFIFO_ALFULL : 1;//outfifo almost empty flag
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uint32_t RSV1 : 1;
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uint32_t INLFIFO_FULL : 1;//inlfifo full flag
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uint32_t INLFIFO_EMPTY : 1;//inlfifo empty flag
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uint32_t INLFIFO_ALEMPTY : 1;//inlfifo almost full flag
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uint32_t RSV2 : 1;
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uint32_t INRFIFO_FULL : 1;//inrfifo full flag
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uint32_t INRFIFO_EMPTY : 1;//inrfifo empty flag
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uint32_t INRFIFO_ALEMPTY : 1;//inrfifo almost full flag
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uint32_t RSV : 21;
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} Bits;
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} REG_SBCE_FIFO_STATE_t;
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/* SBC ENC FIFO INWDS 0x1C*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t ENC_INLFFWDS_CNT : 9;//input left fifo words count
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uint32_t RSV1 : 7;
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uint32_t ENC_INRFFWDS_CNT : 9;//input right fifo words count
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uint32_t RSV2 : 7;
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} Bits;
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} REG_SBCE_FIFO_INWDS_t;
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/* SBC ENC FIFO OUTWDS 0x20*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t ENC_OUTFFWDS_CNT : 8;//output fifo words pointer
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uint32_t RSV1 : 24;
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} Bits;
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} REG_SBCE_FIFO_OUTWDS_t;
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/*SBC ENC INPUT FIFO LEVEL 0x24*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t INLFIFO_ALEMPTY_LEVEL : 8;//output left fifo words pointer
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uint32_t RSV1 : 8;
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uint32_t INRFIFO_ALEMPTY_LEVEL : 8;//output left fifo words pointer
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uint32_t RSV2 : 8;
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} Bits;
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} REG_SBCE_INFIFO_LEVEL_t;
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/*SBC ENC OUTPUT FIFO LEVEL 0x28*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t OUTFIFO_ALFULL_LEVEL : 8;//output fifo almost full level
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uint32_t RSV : 24;
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} Bits;
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} REG_SBCE_OUTFIFO_LEVEL_t;
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typedef struct
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{
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volatile REG_SBCE_CTRL_t SBCE_CTRL; /* Offset 0x00 */
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volatile REG_SBCE_CFG_t SBCE_CFG; /* Offset 0x04 */
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volatile REG_SBCE_INFIFO_REG_t SBCE_INFIFO; /* Offset 0x08 */
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volatile uint32_t SBCE_OUTFIFO; /* Offset 0x0C */
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volatile REG_SBCE_INTEN_REG_t SBCE_INTEN; /* Offset 0x10 */
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volatile REG_SBCE_INTS_REG_t SBCE_INTS; /* Offset 0x14 */
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volatile REG_SBCE_FIFO_STATE_t SBCE_FIFO_STATE; /* Offset 0x18 */
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volatile REG_SBCE_FIFO_INWDS_t SBCE_FIFO_INWDS; /* Offset 0x1C */
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volatile REG_SBCE_FIFO_OUTWDS_t SBCE_FIFO_OUTWDS; /* Offset 0x20 */
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volatile REG_SBCE_INFIFO_LEVEL_t SBCE_INFIFO_LVL; /* Offset 0x24 */
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volatile REG_SBCE_OUTFIFO_LEVEL_t SBCE_OUTFF_LVL; /* Offset 0x28 */
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}struct_SBCE_t;
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#define SBC_ENC ((struct_SBCE_t *)SBC_ENC_BASE)
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typedef enum{
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SBCE_MONO = 0,
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SBCE_STEREO = 1,
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}enum_pcm_channel_mode_t ;
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typedef enum{
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BLOCK_4 = 0,
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BLOCK_8 = 1,
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BLOCK_12 = 2,
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BLOCK_16 = 3,
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}enum_pcm_block_length_t ;
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typedef enum{
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SP_16KHz = 0,
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SP_32KHz = 1,
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SP_44_1KHz = 2,
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SP_48KHz = 3,
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}enum_pcm_sample_freq_t ;
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typedef struct{
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uint32_t input_dma_en;
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uint32_t output_dma_en;
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uint32_t inlfifo_dma_en;
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uint32_t inrfifo_dma_en;
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}struct_SBCE_DMA_cfg_t;
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t inlfifo_alempty_lvl : 8;
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uint32_t inrfifo_alempty_lvl : 8;
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uint32_t outlfifo_alfull_lvl : 8;
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uint32_t output_dma_en : 1;
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uint32_t input_dma_en : 1;
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uint32_t sample_freq : 2;
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uint32_t ch_mode : 1;
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uint32_t blk_len : 2;
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uint32_t RSV : 1;
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}Bits;
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}struct_SBCENC_Init_t;
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typedef struct{
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uint32_t outfifo_full_int_en;
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uint32_t outfifo_empty_int_en;
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uint32_t outfifo_alfull_int_en;
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uint32_t inlff_full_int_en;
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uint32_t inlff_empty_int_en;
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uint32_t inlff_alempty_int_en;
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uint32_t inrff_full_int_en;
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uint32_t inrff_empty_int_en;
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uint32_t inrff_alempty_int_en;
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}struct_SBCE_ISR_cfg_t;
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typedef struct __SBC_ENC_HandleTypeDef
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{
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struct_SBCENC_Init_t SbcEncInit;
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uint16_t *OrignlData;
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uint32_t gDataInIndex;
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uint8_t *EncodedData;
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uint32_t gDataOutIndex;
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uint32_t OrignlDataSize;
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void (*Callback)(struct __SBC_ENC_HandleTypeDef *hSbcEnc); /*!< SBC encode finish Callback */
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}SBC_ENC_HandleTypeDef ;
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typedef enum
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{
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OUTFF_FULL_INT = (1 << 0),
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OUTFF_EMPTY_INT = (1 << 1),
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OUTFF_ALFULL_INT = (1 << 2),
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INLF_FULL_INT = (1 << 4),
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INLF_EMPTY_INT = (1 << 5),
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INLF_ALEMPTY_INT = (1 << 6),
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INRF_FULL_INT = (1 << 8),
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INRF_EMPTY_INT = (1 << 9),
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INRF_ALEMPTY_INT = (1 << 10),
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}enum_sbce_isr_status_t ;
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#define __SBCE_OUTFIFO_IS_FULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.OUTFIFO_FULL == 1)
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#define __SBCE_OUTFIFO_IS_EMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.OUTFIFO_EMPTY == 1)
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#define __SBCE_OUTFIFO_IS_ALFULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.OUTFIFO_ALFULL == 1)
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#define __SBCE_INLFIFO_IS_FULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.INLFIFO_FULL == 1)
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#define __SBCE_INLFIFO_IS_EMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INLFIFO_EMPTY == 1)
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#define __SBCE_INLFIFO_IS_ALEMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INLFIFO_ALEMPTY == 1)
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#define __SBCE_INRFIFO_IS_FULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.INRFIFO_FULL == 1)
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#define __SBCE_INRFIFO_IS_EMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INRFIFO_EMPTY == 1)
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#define __SBCE_INRFIFO_IS_ALEMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INRFIFO_ALEMPTY == 1)
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#define __SBCE_GET_ISR_STS() (SBC_ENC->SBCE_INTS.Word)
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#define __SBCE_GET_OUT_RESULT_WORD() (SBC_ENC->SBCE_OUTFIFO)
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#define __SBCE_INLFF_EMPTY_INT_DISABLE() (SBC_ENC->SBCE_INTEN.Bits.INLFF_EMPTY_INT_EN = 0)
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void sbc_enc_init(SBC_ENC_HandleTypeDef *hSbcEnc);
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void sbc_encoder_enc_IT(SBC_ENC_HandleTypeDef *hSbcEnc, uint16_t *fp_Data_In, uint32_t fu32_size, uint8_t *fp_Data_Out);
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void sbcenc_IRQHandler(SBC_ENC_HandleTypeDef *hSbcEnc);
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#endif
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