407 lines
15 KiB
C
407 lines
15 KiB
C
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#include <stdbool.h>
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#include "FreeRTOS.h"
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#include "task.h"
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#include "co_util.h"
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#include "fr30xx.h"
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#define FLASH_POWER_DOWN 0
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#define DEBUG_TIMING 0
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#define DEBUG_UART_BASE UART3_BASE
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/* Constants required to manipulate the core. Registers first... */
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#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
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/* ...then bits in the registers. */
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#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
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uint8_t rwip_calc_sleep_time(int32_t *sleep_duration);
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/* base: BIT0~27 is valid, unit is 312.5us; fine: 0~624, unit is 0.5us */
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void rwip_counter_get(uint32_t *base, uint16_t *fine);
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void low_power_save_cpu(void);
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void low_power_restore_cpu(void);
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void rwip_wakeup_start(void);
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bool rwip_wakeup_is_ongoing(void);
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/*
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* The number of SysTick increments that make up one tick period.
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*/
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#if ( configUSE_TICKLESS_IDLE == 1 )
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extern uint32_t ulTimerCountsForOneTick;
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#endif /* configUSE_TICKLESS_IDLE */
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/*
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* The maximum number of tick periods that can be suppressed is limited by the
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* 24 bit resolution of the SysTick timer.
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*/
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#if ( configUSE_TICKLESS_IDLE == 1 )
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extern uint32_t xMaximumPossibleSuppressedTicks;
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#endif /* configUSE_TICKLESS_IDLE */
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/*
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* Compensate for the CPU cycles that pass while the SysTick is stopped (low
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* power functionality only.
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*/
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#if ( configUSE_TICKLESS_IDLE == 1 )
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extern uint32_t ulStoppedTimerCompensation;
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#endif /* configUSE_TICKLESS_IDLE */
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__RAM_CODE uint32_t ms_2_lpcycles(uint32_t ms)
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{
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uint32_t lpcycles;
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uint32_t tmp_low, tmp_high;
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mul_64(&tmp_low, &tmp_high, system_get_LPRCCLK(), ms);
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lpcycles = simple_div_64(tmp_low, tmp_high, 1000);
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return(lpcycles);
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}
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__RAM_CODE uint32_t us_2_lpcycles(uint32_t us)
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{
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uint32_t lpcycles;
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uint32_t tmp_low, tmp_high;
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mul_64(&tmp_low, &tmp_high, system_get_LPRCCLK(), us);
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lpcycles = simple_div_64(tmp_low, tmp_high, 1000000);
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return(lpcycles);
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}
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__RAM_CODE uint32_t lpcycles_2_us(uint32_t lp_cyc)
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{
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uint32_t us;
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uint32_t tmp_low, tmp_high;
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mul_64(&tmp_low, &tmp_high, 1000000, lp_cyc);
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us = simple_div_64(tmp_low, tmp_high, system_get_LPRCCLK());
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return(us);
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}
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__RAM_CODE void low_power_enter_sleep(void)
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{
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#if DEBUG_TIMING
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*(volatile uint32_t *)0x50110000 = 'e';
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#endif
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ool_write(PMU_REG_SW_OP, 0x01);
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}
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__RAM_CODE void low_power_enter(void)
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{
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uint32_t org_value;
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org_value = ool_read32(0xfc);
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if (org_value & 0x01) {
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ool_write32(0xfc/*PMU_REG_CPU_RESET_VECTOR*/, (uint32_t)low_power_restore_cpu | 0x01);
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}
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else {
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ool_write32(0xfc/*PMU_REG_CPU_RESET_VECTOR*/, (uint32_t)low_power_restore_cpu & (~0x01));
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}
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low_power_save_cpu();
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}
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__RAM_CODE __WEAK bool user_deep_sleep_check(void)
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{
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return true;
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}
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__RAM_CODE __WEAK void user_entry_before_sleep(void)
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{
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}
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__RAM_CODE __WEAK void user_entry_after_sleep(void)
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{
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}
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__RAM_CODE __WEAK void user_entry_after_sleep_user(void)
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{
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}
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#if DEBUG_TIMING
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__RAM_CODE __STATIC_INLINE void init_uart_for_debug(void)
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{
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__SYSTEM_UART2_CLK_ENABLE();
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*(volatile uint32_t *)0xE005012c = 0x00009911;
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*(volatile uint32_t *)(DEBUG_UART_BASE+0x0c) = 0x03;
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*(volatile uint32_t *)(DEBUG_UART_BASE+0x1c) = 0x09;
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*(volatile uint32_t *)(DEBUG_UART_BASE+0x08) = 0x09;
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/* baudrate */
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*(volatile uint32_t *)(DEBUG_UART_BASE+0x0c) = 0x83;
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*(volatile uint32_t *)(DEBUG_UART_BASE+0x00) = 0x01;
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*(volatile uint32_t *)(DEBUG_UART_BASE+0x04) = 0x00;
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*(volatile uint32_t *)(DEBUG_UART_BASE+0xc0) = 0x28;
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*(volatile uint32_t *)(DEBUG_UART_BASE+0x0c) = 0x03;
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}
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#endif
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volatile TickType_t latest_idle_time;
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__RAM_CODE void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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{
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uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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latest_idle_time = xExpectedIdleTime;
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/* Make sure the Sleep LP counter does not overflow RTC . */
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if( xExpectedIdleTime > (0x01FFFFFF / portTICK_RATE_MS) )
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{
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xExpectedIdleTime = 0x01FFFFFF / portTICK_RATE_MS;
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}
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/* Enter a critical section but don't use the taskENTER_CRITICAL()
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* method as that will mask interrupts that should exit sleep mode. */
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__disable_irq();
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__DSB();
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__ISB();
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/* Stop the SysTick momentarily. The time the SysTick is stopped for
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* is accounted for as best it can be, but using the tickless mode will
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* inevitably result in some tiny drift of the time maintained by the
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* kernel with respect to calendar time. */
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portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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/* If a context switch is pending or a task is waiting for the scheduler
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* to be unsuspended then abandon the low power entry. */
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if ( eTaskConfirmSleepModeStatus() == eAbortSleep )
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{
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/* Restart SysTick. */
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portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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/* Re-enable interrupts - see comments above __disable_irq() call
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* above. */
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__enable_irq();
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}
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else
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{
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int ms = xExpectedIdleTime * portTICK_RATE_MS;
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bool deep_sleep = false;
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if ((ms < 20)
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|| (system_prevent_sleep_get()!=0)
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|| (user_deep_sleep_check()==false)) { // enter light sleep mode
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/* Make sure the SysTick reload value does not overflow the counter. */
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if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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{
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xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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}
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/* Calculate the reload value required to wait xExpectedIdleTime
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* tick periods. -1 is used because this code will execute part way
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* through one of the tick periods. */
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ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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if( ulReloadValue > ulStoppedTimerCompensation )
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{
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ulReloadValue -= ulStoppedTimerCompensation;
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}
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/* Set the new reload value. */
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portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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/* Clear the SysTick count flag and set the count value back to
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* zero. */
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Restart SysTick. */
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portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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__DSB();
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__WFI();
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__ISB();
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/* Disable the SysTick clock without reading the
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* portNVIC_SYSTICK_CTRL_REG register to ensure the
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* portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
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* the time the SysTick is stopped for is accounted for as best it can
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* be, but using the tickless mode will inevitably result in some tiny
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* drift of the time maintained by the kernel with respect to calendar
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* time*/
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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/* Determine if the SysTick clock has already counted to zero and
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* been set back to the current reload value (the reload back being
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* correct for the entire expected idle time) or if the SysTick is yet
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* to count to zero (in which case an interrupt other than the SysTick
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* must have brought the system out of sleep mode). */
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if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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{
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uint32_t ulCalculatedLoadValue;
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/* The tick interrupt is already pending, and the SysTick count
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* reloaded with ulReloadValue. Reset the
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* portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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* period. */
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ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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/* As the pending tick will be processed as soon as this
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* function exits, the tick value maintained by the tick is stepped
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* forward by one less than the time spent waiting. */
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ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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}
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else
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{
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/* Something other than the tick interrupt ended the sleep.
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* Work out how long the sleep lasted rounded to complete tick
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* periods (not the ulReload value which accounted for part
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* ticks). */
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ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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/* How many complete tick periods passed while the processor
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* was waiting? */
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ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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/* The reload value is set to whatever fraction of a single tick
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* period remains. */
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portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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}
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}
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else { // enter deep sleep mode
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uint32_t sleep_us;
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uint32_t escaped_system_tick, tail_system_tick;
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uint32_t before_counter, after_counter;
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deep_sleep = true;
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#if DEBUG_TIMING
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*(volatile uint32_t *)DEBUG_UART_BASE = 'a';
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#endif
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/* remove time consumed during wake up procedure (from PMU IRQ to __enable_irq) */
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ms -= 10;
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/*
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* 1. record start RTC counter, used to calculate actual sleep time
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* 2. setup target RTC counter
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*/
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{
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uint32_t target_counter;
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#if DEBUG_TIMING
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*(volatile uint32_t *)DEBUG_UART_BASE = 'b';
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#endif
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ool_write(PMU_REG_RTC_CTRL, ool_read(PMU_RTC_SAMPLE_BIT) | PMU_RTC_SAMPLE_BIT);
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while (ool_read(PMU_REG_RTC_CTRL) & PMU_RTC_SAMPLE_BIT);
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#if DEBUG_TIMING
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*(volatile uint32_t *)DEBUG_UART_BASE = 'c';
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#endif
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before_counter = ool_read32(PMU_REG_RTC_COUNTER_0);
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target_counter = before_counter + ms_2_lpcycles(ms);
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ool_write32(PMU_REG_ALARM_B_COUNTER_0, target_counter);
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ool_write(PMU_REG_RTC_CTRL, ool_read(PMU_RTC_SAMPLE_BIT) | PMU_RTC_ALARM_B_EN_BIT);
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}
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/* notice APP layer that system will enter deep sleep mode */
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user_entry_before_sleep();
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/* prepare for deep sleep mode */
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uint32_t reset_vector = SCB->VTOR;
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uint32_t rtos_priorities = portNVIC_SHPR3_REG;
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ool_write(PMU_REG_STATUS, PMU_STATUS_DEEP_SLEEP);
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escaped_system_tick = ulTimerCountsForOneTick - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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#if DEBUG_TIMING
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*(volatile uint32_t *)DEBUG_UART_BASE = 'd';
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#endif
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low_power_enter();
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/* FPU settings */
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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__SYSTEM_FREE_COUNTER_CLK_ENABLE();
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#if DEBUG_TIMING
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init_uart_for_debug();
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*(volatile uint32_t *)DEBUG_UART_BASE = '1';
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#endif
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//init internal flash
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__SYSTEM_PFC_CLK_ENABLE();
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__SYSTEM_QSPI0_CLK_ENABLE();
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__SYSTEM_APB_CLK_ENABLE();
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__SYSTEM_APB1_CLK_ENABLE();
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system_cache_enable(true);
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flash_init_controller(QSPI0, FLASH_RD_TYPE_DUAL, FLASH_WR_TYPE_SINGLE);
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flash_set_baudrate(QSPI0, QSPI_BAUDRATE_DIV_4);
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#if DEBUG_TIMING
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*(volatile uint32_t *)DEBUG_UART_BASE = '2';
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#endif
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ool_write(PMU_REG_STATUS, PMU_STATUS_NORAML);
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SCB->VTOR = reset_vector;
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portNVIC_SHPR3_REG = rtos_priorities;
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#if DEBUG_TIMING
|
||
|
|
*(volatile uint32_t *)DEBUG_UART_BASE = '3';
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* notice APP layer that system has recovery from deep sleep mode */
|
||
|
|
user_entry_after_sleep();
|
||
|
|
|
||
|
|
{
|
||
|
|
uint32_t target;
|
||
|
|
ool_write(PMU_REG_RTC_CTRL, (ool_read(PMU_RTC_SAMPLE_BIT) & (~PMU_RTC_ALARM_B_EN_BIT)) | PMU_RTC_SAMPLE_BIT | PMU_RTC_ALARM_B_CLR_BIT);
|
||
|
|
while (ool_read(PMU_REG_RTC_CTRL) & PMU_RTC_SAMPLE_BIT);
|
||
|
|
after_counter = ool_read32(PMU_REG_RTC_COUNTER_0);
|
||
|
|
}
|
||
|
|
#if DEBUG_TIMING
|
||
|
|
*(volatile uint32_t *)DEBUG_UART_BASE = '4';
|
||
|
|
#endif
|
||
|
|
sleep_us = lpcycles_2_us(after_counter - before_counter);
|
||
|
|
sleep_us += 180;
|
||
|
|
#if DEBUG_TIMING
|
||
|
|
*(volatile uint32_t *)DEBUG_UART_BASE = '5';
|
||
|
|
#endif
|
||
|
|
/*
|
||
|
|
* 1. how many ticks have passed during sleep mode, ulCompleteTickPeriods
|
||
|
|
* 2. how many system ticks left in the following RTOS tick, tail_system_tick
|
||
|
|
*/
|
||
|
|
ulCompleteTickPeriods = pdMS_TO_TICKS(sleep_us / 1000);
|
||
|
|
tail_system_tick = (pdMS_TO_TICKS(sleep_us % 1000) * ulTimerCountsForOneTick) / 1000;
|
||
|
|
tail_system_tick += escaped_system_tick;
|
||
|
|
if (tail_system_tick >= ulTimerCountsForOneTick) {
|
||
|
|
tail_system_tick -= ulTimerCountsForOneTick;
|
||
|
|
ulCompleteTickPeriods++;
|
||
|
|
}
|
||
|
|
|
||
|
|
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
|
||
|
|
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1 - tail_system_tick;
|
||
|
|
#if DEBUG_TIMING
|
||
|
|
*(volatile uint32_t *)DEBUG_UART_BASE = '6';
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
|
||
|
|
* again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
|
||
|
|
* value. */
|
||
|
|
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
||
|
|
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
||
|
|
vTaskStepTick( ulCompleteTickPeriods );
|
||
|
|
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
|
||
|
|
|
||
|
|
#if DEBUG_TIMING
|
||
|
|
*(volatile uint32_t *)DEBUG_UART_BASE = '7';
|
||
|
|
#endif
|
||
|
|
/* Exit with interrupts enabled. */
|
||
|
|
__enable_irq();
|
||
|
|
|
||
|
|
if (deep_sleep == true) {
|
||
|
|
user_entry_after_sleep_user();
|
||
|
|
}
|
||
|
|
|
||
|
|
#if DEBUG_TIMING
|
||
|
|
*(volatile uint32_t *)DEBUG_UART_BASE = '8';
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|