155 lines
5.1 KiB
C
155 lines
5.1 KiB
C
/*
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******************************************************************************
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* @file driver_cache.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2022
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* @brief Header file of cache HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_CACHE_H__
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#define __DRIVER_CACHE_H__
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#include "fr30xx.h"
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/** @addtogroup CACHE_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* Enabling Register 0 */
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typedef struct
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{
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uint32_t ENABLE : 1;
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uint32_t FLUSH : 1;
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uint32_t BANK_FLUSH : 1;
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uint32_t rsv : 29;
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} REG_Enabling_t;
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/* Control Register */
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typedef struct
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{
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uint32_t BIST_ACTIVE : 1;
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uint32_t BIST_END : 1;
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uint32_t BIST_OUT : 1;
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uint32_t WR_MODE : 2;
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uint32_t INST_POL : 1;
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uint32_t INST_ACTIVE : 1;
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uint32_t ADDR_RANG0_EN : 1;
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uint32_t ADDR_RANG0_POL : 1;
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uint32_t ADDR_RANG1_EN : 1;
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uint32_t ADDR_RANG1_POL : 1;
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uint32_t ADDR_RANG2_EN : 1;
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uint32_t ADDR_RANG2_POL : 1;
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uint32_t ADDR_RANG3_EN : 1;
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uint32_t ADDR_RANG3_POL : 1;
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uint32_t rsv : 17;
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} REG_Cache_Control_t;
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/* Address Range 0 defination*/
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typedef struct {
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uint32_t bank :16;
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uint32_t mask :16;
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} REG_ADDR_RANGE0_t;
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/* Address Range 1 defination*/
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typedef struct {
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uint32_t rsv_0 :8;
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uint32_t bank :8;
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uint32_t rsv_1 :8;
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uint32_t mask :8;
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} REG_ADDR_RANGE1_t;
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/* Address Range 2 defination*/
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typedef struct {
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uint32_t rsv_0 :8;
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uint32_t bank :8;
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uint32_t rsv_1 :8;
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uint32_t mask :8;
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} REG_ADDR_RANGE2_t;
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/* Address Range 3 defination*/
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typedef struct {
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uint32_t rsv_0 :8;
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uint32_t bank :8;
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uint32_t rsv_1 :8;
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uint32_t mask :8;
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} REG_ADDR_RANGE3_t;
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/* -----------------------------------------------*/
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/* CACHE Register */
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/* -----------------------------------------------*/
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typedef struct
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{
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volatile REG_Enabling_t ENABLING; /* Offset 0x00 */
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volatile REG_Cache_Control_t CTRL; /* Offset 0x04 */
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volatile uint32_t BANK_FLUSH_ADDR; /* Offset 0x08 */
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volatile uint32_t BANK_FLUSH_MASK; /* Offset 0x0C */
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volatile REG_ADDR_RANGE0_t ADDR_RANGE0; /* Offset 0x10 */
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volatile REG_ADDR_RANGE1_t ADDR_RANGE1; /* Offset 0x14 */
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volatile REG_ADDR_RANGE2_t ADDR_RANGE2; /* Offset 0x18 */
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volatile REG_ADDR_RANGE3_t ADDR_RANGE3; /* Offset 0x1C */
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}struct_CACHE_t;
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#define CACHE ((struct_CACHE_t *)AHBC_CACHE_BASE)
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/* ################################ Register Section END ################################## */
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/**
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* @}
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*/
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/** @addtogroup SPI_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initializatio Config Section Start ################################ */
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typedef enum {
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CACHE_WR_BYPASS,
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CACHE_WR_FLUSH,
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CACHE_WR_WRITE_THROUGH,
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} enum_CACHE_WR_MODE_T;
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typedef enum {
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CACHE_POL_NON_CACHABLE,
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CACHE_POL_CACHABLE,
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} enum_CACHE_POL_T;
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/* ################################ Initializatio Config Section END ################################## */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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#define __CACHE_ENABLE(__CACHE__) (__CACHE__->ENABLING.ENABLE = 1)
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#define __CACHE_DISABLE(__CACHE__) (__CACHE__->ENABLING.ENABLE = 0)
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#define __CACHE_FLUSH(__CACHE__) (__CACHE__->ENABLING.FLUSH = 1)
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#define __CACHE_BANK_FLUSH(__CACHE__) (__CACHE__->ENABLING.BANK_FLUSH = 1)
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#define __CACHE_BANK_FLUSH_DONE(__CACHE__) (__CACHE__->ENABLING.BANK_FLUSH == 0)
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#define __CACHE_BANK_FLUSH_ADDR_SET(__CACHE__, addr) (__CACHE__->BANK_FLUSH_ADDR = addr)
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#define __CACHE_BANK_FLUSH_MASK_SET(__CACHE__, mask) (__CACHE__->BANK_FLUSH_MASK = mask)
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#define __CACHE_BIST_START(__CACHE__) (__CACHE__->CTRL.BIST_ACTIVE = 1)
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#define __CACHE_BIST_END(__CACHE__) (__CACHE__->CTRL.BIST_END == 1)
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#define __CACHE_BIST_PASS(__CACHE__) (__CACHE__->CTRL.BIST_OUT == 0)
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#define __CACHE_WR_MODE_SET(__CACHE__, mode) (__CACHE__->CTRL.WR_MODE = mode)
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#define __CACHE_WR_MODE_GET(__CACHE__, mode) (__CACHE__->CTRL.WR_MODE)
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#define __CACHE_ADDR_RANGEx_ENABLE(__CACHE__, x) (__CACHE__->CTRL.ADDR_RANG##x##_EN = 1)
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#define __CACHE_ADDR_RANGEx_DISABLE(__CACHE__, x) (__CACHE__->CTRL.ADDR_RANG##x##_EN = 0)
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#define __CACHE_ADDR_RANGEx_POL_SET(__CACHE__, x, __pol) (__CACHE__->CTRL.ADDR_RANG##x##_POL = __pol)
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#define __CACHE_ADDR_RANGEx_BANK_SET(__CACHE__, x, __bank) (__CACHE__->ADDR_RANGE##x.bank = (__bank))
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#define __CACHE_ADDR_RANGEx_MASK_SET(__CACHE__, x, __mask) (__CACHE__->ADDR_RANGE##x.mask = (__mask))
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#endif // __DRIVER_CACHE_H__
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