592 lines
19 KiB
C
592 lines
19 KiB
C
#include "fr30xx.h"
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#define PMU_FSM_ON_DIV 0x04 //the follow tcnt based <((DIV+1))*40K_CLK(rc)>
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#define PMU_PMU_ON_CNT (0x18<<0)
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//the follow tcnt should <= PMU_PMU_ON_CNT
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#define PMU_BBG_ON_CNT (0x01<<0)
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#define PMU_SYSBUCK_ON_CNT (0x03<<0)
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#define PMU_IOBUCK_ON_CNT (0x03<<0)
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#define PMU_IOLDO1_ON_CNT (0x03<<0)
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#define PMU_IOLDO2_ON_CNT (0x03<<0)
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#define PMU_APPDLDO_ON_CNT (0x06<<0)
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#define PMU_DSPDLDO_ON_CNT (0x06<<0)
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#define PMU_PKSTPD_ON_CNT (0x0c<<0)
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#define PMU_MEMPK_ON_CNT (0x10<<0)
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#define PMU_MEMPD_ON_CNT (0x10<<0)
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#define PMU_OSCLDO_ON_CNT (0x06<<0)
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#define PMU_OSC_ON_CNT (0x08<<0)
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#define PMU_RC24PD_ON_CNT (0x10<<0)
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#define PMU_RAMPK_ON_CNT (0x18<<0)
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#define PMU_PMUISO_ON_CNT (0x17<<0)
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#define PMU_IOISO_ON_CNT (0x17<<0)
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#define PMU_IORTON_ON_CNT (0x17<<0)
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#define PMU_IOSNS_ON_CNT (0x17<<0)
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#define PMU_RSTN_ON_CNT (0x18<<0)
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#define PMU_FSM_OFF_DIV (0x00<<5) //the follow tcnt based <((DIV+1))*40K_CLK(rc)>
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#define PMU_PMU_OFF_CNT (0x06<<5)
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//the follow tcnt should <= PMU_PMU_OFF_CNT
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#define PMU_BBG_OFF_CNT (0x05<<5)
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#define PMU_SYSBUCK_OFF_CNT (0x04<<5)
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#define PMU_IOBUCK_OFF_CNT (0x01<<5)
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#define PMU_IOLDO1_OFF_CNT (0x01<<5)
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#define PMU_IOLDO2_OFF_CNT (0x01<<5)
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#define PMU_APPDLDO_OFF_CNT (0x03<<5)
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#define PMU_DSPDLDO_OFF_CNT (0x03<<5)
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#define PMU_PKSTPD_OFF_CNT (0x01<<5)
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#define PMU_MEMPK_OFF_CNT (0x01<<5)
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#define PMU_MEMPD_OFF_CNT (0x03<<5)
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#define PMU_OSCLDO_OFF_CNT (0x03<<5)
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#define PMU_OSC_OFF_CNT (0x01<<5)
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#define PMU_RC24PD_OFF_CNT (0x03<<5)
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#define PMU_RAMPK_OFF_CNT (0x01<<5)
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#define PMU_PMUISO_OFF_CNT (0x01<<5)
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#define PMU_IOISO_OFF_CNT (0x02<<5)
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#define PMU_IORTON_OFF_CNT (0x02<<5)
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#define PMU_IOSNS_OFF_CNT (0x02<<5)
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#define PMU_RSTN_OFF_CNT (0x01<<5)
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void pmu_init(void)
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{
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/* setup sleep and wakeup counters */
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ool_write(PMU_REG_FSM_TIMER , PMU_FSM_ON_DIV | PMU_FSM_OFF_DIV );
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ool_write(PMU_REG_PMU_ONOFF_CNT , PMU_PMU_ON_CNT | PMU_PMU_OFF_CNT );
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ool_write(PMU_REG_BBG_ONOFF_CNT , PMU_BBG_ON_CNT | PMU_BBG_OFF_CNT );
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ool_write(PMU_REG_SYSBUCK_ONOFF_CNT , PMU_SYSBUCK_ON_CNT | PMU_SYSBUCK_OFF_CNT);
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ool_write(PMU_REG_IOBUCK_ONOFF_CNT , PMU_IOBUCK_ON_CNT | PMU_IOBUCK_OFF_CNT );
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ool_write(PMU_REG_IOLDO1_ONOFF_CNT , PMU_IOLDO1_ON_CNT | PMU_IOLDO1_OFF_CNT );
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ool_write(PMU_REG_IOLDO2_ONOFF_CNT , PMU_IOLDO2_ON_CNT | PMU_IOLDO2_OFF_CNT );
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ool_write(PMU_REG_APPDLDO_ONOFF_CNT , PMU_APPDLDO_ON_CNT | PMU_APPDLDO_OFF_CNT);
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ool_write(PMU_REG_DSPDLDO_ONOFF_CNT , PMU_DSPDLDO_ON_CNT | PMU_DSPDLDO_OFF_CNT);
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ool_write(PMU_REG_PKSTPD_ONOFF_CNT , PMU_PKSTPD_ON_CNT | PMU_PKSTPD_OFF_CNT );
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ool_write(PMU_REG_MEMPK_ONOFF_CNT , PMU_MEMPK_ON_CNT | PMU_MEMPK_OFF_CNT );
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ool_write(PMU_REG_MEMPD_ONOFF_CNT , PMU_MEMPD_ON_CNT | PMU_MEMPD_OFF_CNT );
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ool_write(PMU_REG_OSCLDO_ONOFF_CNT , PMU_OSCLDO_ON_CNT | PMU_OSCLDO_OFF_CNT );
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ool_write(PMU_REG_OSC_ONOFF_CNT , PMU_OSC_ON_CNT | PMU_OSC_OFF_CNT );
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ool_write(PMU_REG_RC24PD_ONOFF_CNT , PMU_RC24PD_ON_CNT | PMU_RC24PD_OFF_CNT );
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ool_write(PMU_REG_RAMPK_ONOFF_CNT , PMU_RAMPK_ON_CNT | PMU_RAMPK_OFF_CNT );
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ool_write(PMU_REG_PMUISO_ONOFF_CNT , PMU_PMUISO_ON_CNT | PMU_PMUISO_OFF_CNT );
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ool_write(PMU_REG_IOISO_ONOFF_CNT , PMU_IOISO_ON_CNT | PMU_IOISO_OFF_CNT );
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ool_write(PMU_REG_IORTON_ONOFF_CNT , PMU_IORTON_ON_CNT | PMU_IORTON_OFF_CNT );
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ool_write(PMU_REG_IOSNS_ONOFF_CNT , PMU_IOSNS_ON_CNT | PMU_IOSNS_OFF_CNT );
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ool_write(PMU_REG_RSTN_ONOFF_CNT , PMU_RSTN_ON_CNT | PMU_RSTN_OFF_CNT );
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/* splite PKVDDH and PKVDD */
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ool_write(PMU_REG_PKVDDH_CTRL_0, 0x60);
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ool_write(PMU_REG_PKVDDH_CTRL_0, 0x70);
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/* shut down OSC buffer */
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ool_write(PMU_REG_OSC_CTRL_1, ool_read(PMU_REG_OSC_CTRL_1) & (~0x04));
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/* PLL analog clock enable */
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ool_write(PMU_REG_OSC_CTRL_1, ool_read(PMU_REG_OSC_CTRL_1)|0x0B);
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/* set PKVDD to 0.85v */
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ool_write(PMU_REG_PKVDD_CTRL, 0x7a);
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/* set PKVDDH to 1.1v, set RAMPKVDD to 0.7v */
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ool_write(PMU_REG_PKVDDH_CTRL_1, 0x34);
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/* buck load inductor will not be shorted */
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ool_write(PMU_REG_SYSBUCK_CTRL_1, 0x43);
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/* disable internal load of sys-buck and io-buck */
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ool_write(PMU_REG_IOBUCK_CTRL_4, 0x73);
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ool_write(PMU_REG_SYSBUCK_CTRL_4, 0x73);
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/*
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* IOLDO dynamic bias, used to avoid unexpect leakage when IOLDO
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* output configuration is large than VBAT input voltage
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*/
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ool_write(PMU_REG_IOLDO1_CTRL_1, ool_read(PMU_REG_IOLDO1_CTRL_1) | (1<<4));
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ool_write(PMU_REG_IOLDO2_CTRL_1, ool_read(PMU_REG_IOLDO2_CTRL_1) | (1<<4));
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/* enable BT sleep timer clock */
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ool_write(PMU_REG_CLK_EN, PMU_LP_TICK_CLK_EN_BIT);
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#if 0
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/* sleep and wake up is controlled by TICK */
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ool_write(PMU_REG_SLP_WK_SRC, PMU_SLP_TICK_EN_BIT | PMU_WK_TICK_EN_BIT);
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/*
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* BIT0: BB generate sleep signal en
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* BIT1: external interrupt wakeup BT timer enable
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*/
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ool_write(PMU_REG_TICK_CTRL, PMU_TICK_SLP_PMU_EN_BIT | PMU_EXT_WK_TICK_EN_BIT | PMU_IRQ_WK_TICK_EN_BIT);
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/* reset lp tick */
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ool_write(PMU_REG_RST, PMU_LP_TICK_SFT_RST_BIT);
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while (ool_read(PMU_REG_RST) & PMU_LP_TICK_SFT_RST_BIT);
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#else
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/* sleep and wake up is controlled by TICK */
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ool_write(PMU_REG_SLP_WK_SRC, PMU_SLP_CPU_EN_BIT | PMU_WK_IRQ_EN_BIT);
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/* release RTC clock */
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ool_write(PMU_REG_CLK_EN, ool_read(PMU_REG_CLK_EN) | PMU_RTC_CLK_EN_BIT);
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/* release interrupt mask of RTC alarm B */
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ool_write16(PMU_REG_INT_MASK, ool_read16(PMU_REG_INT_MASK) | PMU_RTC_B_INT_MSK_BIT);
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#endif
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/* disable power fsm */
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ool_write(0x85, 0xff);
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/* IO33 and IO18 always on */
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ool_write(0x63, 0x18);
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/* set mask of GPIO SNS & ISO */
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ool_write(0x64, ool_read(0x64) | 0x80 | 0x20); //bit7 : GPIO_SNS; bit5 : GPIO_ISO
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// /* configure PMU_PIN_8 output BBG_EN signal */
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// ool_write(PMU_REG_DIAG_CTRL, 0x82);
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//// ool_write16(PMU_REG_PIN_IOMUX_L, 0xffff);
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// ool_write(PMU_REG_PIN_IOMUX_H, 0x03);
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// /* disable input as default setting */
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// ool_write16(PMU_REG_PIN_INPUT_EN, 0x0000);
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/* remove internal cap of osc */
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ool_write(PMU_REG_OSC_CTRL_4, 0x20);
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}
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/******************************************************************************
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* @fn pmu_adc_power_ctrl
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*
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* @brief ADC power control. true: enable.
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* false: disable.
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*/
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void pmu_adc_power_ctrl(bool enable)
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{
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if (enable)
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ool_write(PMU_REG_ADC_CTL, ool_read(PMU_REG_ADC_CTL) | PMU_ADC_CTL_POWER_BIT);
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else
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ool_write(PMU_REG_ADC_CTL, ool_read(PMU_REG_ADC_CTL) & ~PMU_ADC_CTL_POWER_BIT);
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}
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/******************************************************************************
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* @fn pmu_vbe_power_ctrl
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*
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* @brief VBE(For temperature detection) power control. true: enable.
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* false: disable.
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*/
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void pmu_vbe_power_ctrl(bool enable)
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{
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if (enable)
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ool_write(PMU_REG_BBG_CTL, ool_read(PMU_REG_BBG_CTL) | PMU_BBG_CTL_VBE_EN_BIT);
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else
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ool_write(PMU_REG_BBG_CTL, ool_read(PMU_REG_BBG_CTL) & ~PMU_BBG_CTL_VBE_EN_BIT);
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}
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/******************************************************************************
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* @fn pmu_auldo_power_ctrl
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*
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* @brief audio ldo power control. true: enable.
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* false: disable.
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*/
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void pmu_auldo_power_ctrl(bool enable)
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{
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if (enable)
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ool_write(PMU_REG_AULDO_CTL, ool_read(PMU_REG_AULDO_CTL) & ~PMU_AULDO_CTL_PD_BIT);
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else
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ool_write(PMU_REG_AULDO_CTL, ool_read(PMU_REG_AULDO_CTL) | PMU_AULDO_CTL_PD_BIT);
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}
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/*********************************************************************
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* @fn pmu_enable_charge
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*
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* @brief enable charge function, and set charge current & voltage.
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*
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* @param cur - charge current, @ref enum_PMU_charge_current_t
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* @param vol - charge terminal voltage, @ref enum_PMU_charge_end_vol_t
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*
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* @return None.
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*/
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void pmu_charge_enable(enum_PMU_charge_current_t cur, enum_PMU_charge_end_vol_t vol)
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{
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/* charge reference select BBG */
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ool_write(PMU_REG_CHG_CFG_CD, ool_read(PMU_REG_CHG_CFG_CD) | PMU_CHG_CFG_REF_SEL_BIT);
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/* config charge voltage */
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ool_write(PMU_REG_CHG_CFG_CB, (ool_read(PMU_REG_CHG_CFG_CB)&0x8F) | (vol << PMU_CHG_CFG_END_VOL_POS));
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/* config charge current */
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ool_write(PMU_REG_CHG_CFG_C8, (ool_read(PMU_REG_CHG_CFG_C8)&0xC0) | (cur));
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/* enable charge */
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ool_write(PMU_REG_CHG_CFG_CD, ool_read(PMU_REG_CHG_CFG_CD) | PMU_CHG_CFG_ENABLE_BIT);
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}
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/*********************************************************************
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* @fn pmu_charge_disable
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*
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* @brief disable charge function.
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*/
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void pmu_charge_disable(void)
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{
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/* disable charge */
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ool_write(PMU_REG_CHG_CFG_CD, ool_read(PMU_REG_CHG_CFG_CD) & ~PMU_CHG_CFG_ENABLE_BIT);
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}
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/*********************************************************************
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* @fn pmu_charge_monitor_en
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*
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* @brief Charging in/out monitor interrupt enable.
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*/
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void pmu_charge_monitor_en(enum_PMU_charge_type_t charge_type)
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{
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if (charge_type == PMU_CHARGING_IN)
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ool_write(PMU_REG_ANA_LEVEL, ool_read(PMU_REG_ANA_LEVEL) & ~PMU_CHG_ACOK_LEVEL_BIT);
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else
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ool_write(PMU_REG_ANA_LEVEL, ool_read(PMU_REG_ANA_LEVEL) | PMU_CHG_ACOK_LEVEL_BIT);
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ool_write(PMU_REG_CLK_EN, ool_read(PMU_REG_CLK_EN) | PMU_FILTER_CLK_EN_BIT);
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ool_write(PMU_REG_CHG_ACOK_FILTER, 100);
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ool_write(PMU_REG_ANA_INT_EN, ool_read(PMU_REG_ANA_INT_EN) | PMU_CHG_ACOK_INT_EN_BIT);
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pmu_enable_isr(PMU_CHG_ACOK_INT_MASK_BIT);
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}
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/*********************************************************************
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* @fn pmu_battery_full_monitor_en
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*
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* @brief battery_full monitor interrupt enable
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*/
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void pmu_battery_full_monitor_en(enum_PMU_battery_type_t battery_type)
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{
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if (battery_type == PMU_BATTERY_FULL)
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ool_write(PMU_REG_ANA_LEVEL, ool_read(PMU_REG_ANA_LEVEL) & ~PMU_BATFULL_LEVEL_BIT);
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else
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ool_write(PMU_REG_ANA_LEVEL, ool_read(PMU_REG_ANA_LEVEL) | PMU_BATFULL_LEVEL_BIT);
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ool_write(PMU_REG_CLK_EN, ool_read(PMU_REG_CLK_EN) | PMU_FILTER_CLK_EN_BIT);
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ool_write(PMU_REG_BAT_FULL_FILTER, 200);
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ool_write(PMU_REG_ANA_INT_EN, ool_read(PMU_REG_ANA_INT_EN) | PMU_BATFULL_INT_EN_BIT);
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pmu_enable_isr(PMU_BATFULL_INT_MASK_BIT);
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}
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void pmu_set_pin_pull(enum_PMU_PINx_t bits, enum_PMU_GPIO_PULL_t type)
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{
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uint8_t en_reg = PMU_REG_PIN_PULL_EN;
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uint8_t pull_reg = PMU_REG_PIN_PULL_SEL;
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if(type == PMU_GPIO_NO_PULL) {
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ool_write16(en_reg, (ool_read16(en_reg) & (~bits)));
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}
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else {
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if(type == PMU_GPIO_PULL_UP) {
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ool_write16(pull_reg, (ool_read16(pull_reg) | bits));
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}
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else if(type == PMU_GPIO_PULL_DOWN) {
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ool_write16(pull_reg, (ool_read16(pull_reg) & (~bits)));
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}
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else {
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return;
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}
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ool_write16(en_reg, (ool_read16(en_reg) | bits));
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}
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}
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void pmu_set_pin_dir(enum_PMU_PINx_t bits, enum_PMU_GPIO_MODE_t dir)
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{
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uint8_t oe_reg = PMU_REG_PIN_OUTPUT_EN;
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uint8_t ie_reg = PMU_REG_PIN_INPUT_EN;
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if(dir == PMU_GPIO_MODE_INPUT) {
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ool_write16(oe_reg, ool_read16(oe_reg) | bits);
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ool_write16(ie_reg, ool_read16(ie_reg) | (bits << 2));
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}
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else {
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ool_write16(oe_reg, ool_read16(oe_reg) & (~bits));
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ool_write16(ie_reg, ool_read16(ie_reg) & (~bits << 2));
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}
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}
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void pmu_set_pin_value(enum_PMU_PINx_t bits, uint8_t value)
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{
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uint8_t data_reg = PMU_REG_PIN_DATA;
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if (value == 0)
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ool_write16(data_reg, (ool_read16(data_reg) & (~bits)));
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else
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ool_write16(data_reg, (ool_read16(data_reg) | bits));
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}
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uint8_t pmu_get_pin_value(enum_PMU_PINx_t bit)
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{
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uint8_t data_reg = PMU_REG_PIN_DATA;
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return ( (ool_read16(data_reg) & (1<<bit))>>bit );
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}
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void pmu_set_pin_xor_en(enum_PMU_PINx_t bits, bool en)
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{
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uint8_t xor_reg = PMU_REG_PIN_XOR_EN;
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if(en) {
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ool_write16(xor_reg, ool_read16(xor_reg) | (bits));
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}
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else {
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ool_write16(xor_reg, ool_read16(xor_reg) & (~bits));
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}
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}
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/*********************************************************************
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* @fn pmu_port_wakeup_func_set
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*
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* @brief PortPin wakeup function congfig
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*
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* @param bits: Select Pin. 0x01--PIN0 0x80--PIN7
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*/
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void pmu_port_wakeup_func_set(enum_PMU_PINx_t bits)
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{
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uint8_t last_status_reg = PMU_REG_PIN_LAST_V;
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uint8_t data_reg = PMU_REG_PIN_DATA;
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/* Config input Pull up */
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pmu_set_pin_pull(bits, PMU_GPIO_PULL_UP);
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pmu_set_pin_dir(bits, PMU_GPIO_MODE_INPUT);
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/* Read the current value and write */
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ool_write16(last_status_reg, ool_read16(data_reg));
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/* XOR Enable */
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pmu_set_pin_xor_en(bits, true);
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/* XOR interrupt enable */
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ool_write(PMU_REG_PIN_INT_EN, 0x01);
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}
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/*********************************************************************
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* @fn pmu_gpio_int_init
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*
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* @brief pmu pin wakeup function config. Compare with pmu_port_wakeup_func_set, this
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* function provides two parameter to set pull mode and initial value
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*
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* @param bits: Select Pin. 0x01--PIN0 0x80--PIN7
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* pull: pull mode selection, @ref enum_PMU_GPIO_PULL_t
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* init_value: initial value. Once the level of corresponding pin changes to opposite
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* level with initial value, PMU_GPIO_PMU_INT will be generated.
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*/
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void pmu_gpio_int_init(enum_PMU_PINx_t bits, enum_PMU_GPIO_PULL_t pull, uint8_t init_value)
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{
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uint8_t last_status_reg = PMU_REG_PIN_LAST_V;
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uint8_t data_reg = PMU_REG_PIN_DATA;
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/* Config input Pull up */
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pmu_set_pin_pull(bits, pull);
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pmu_set_pin_dir(bits, PMU_GPIO_MODE_INPUT);
|
|
|
|
/* Read the current value and write */
|
|
if (init_value) {
|
|
ool_write16(last_status_reg, ool_read16(last_status_reg) | bits);
|
|
}
|
|
else {
|
|
ool_write16(last_status_reg, ool_read16(last_status_reg) & (~bits));
|
|
}
|
|
|
|
/* XOR Enable */
|
|
pmu_set_pin_xor_en(bits, true);
|
|
|
|
/* XOR interrupt enable */
|
|
ool_write(PMU_REG_PIN_INT_EN, 0x01);
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn pmu_port_wakeup_func_clear
|
|
*
|
|
* @brief Get rtc current counter value
|
|
*
|
|
* @param bits: Select Pin. 0x01--PIN0 0x80--PIN7
|
|
*/
|
|
void pmu_port_wakeup_func_clear(enum_PMU_PINx_t bits)
|
|
{
|
|
/* XOR Disable */
|
|
pmu_set_pin_xor_en(bits, false);
|
|
}
|
|
|
|
void pmu_enable_isr(uint16_t isr_map)
|
|
{
|
|
ool_write16(PMU_REG_INT_MASK, ool_read16(PMU_REG_INT_MASK) | isr_map);
|
|
}
|
|
|
|
void pmu_disable_isr(uint16_t isr_map)
|
|
{
|
|
ool_write16(PMU_REG_INT_MASK, ool_read16(PMU_REG_INT_MASK) & (~isr_map));
|
|
}
|
|
|
|
uint16_t pmu_get_isr_state(void)
|
|
{
|
|
return ool_read16(PMU_REG_INT_STATUS);
|
|
}
|
|
|
|
void pmu_clear_isr_state(uint16_t state_map)
|
|
{
|
|
if (state_map & PMU_BATFULL_INT_STATUS_BIT) {
|
|
ool_write(PMU_REG_ANA_INT_CLR, ool_read(PMU_REG_ANA_INT_CLR) | PMU_BATFULL_INT_CLR_BIT);
|
|
}
|
|
|
|
if (state_map & PMU_CHG_ACOK_INT_STATUS_BIT) {
|
|
ool_write(PMU_REG_ANA_INT_CLR, ool_read(PMU_REG_ANA_INT_CLR) | PMU_CHG_ACOK_INT_CLR_BIT);
|
|
}
|
|
|
|
if (state_map & PMU_LVD_INT_STATUS_BIT) {
|
|
ool_write(PMU_REG_ANA_INT_CLR, ool_read(PMU_REG_ANA_INT_CLR) | PMU_LVD_INT_CLR_BIT);
|
|
}
|
|
|
|
if (state_map & PMU_WDT_INT_STATUS_BIT) {
|
|
ool_write(PMU_REG_RTC_CTRL, ool_read(PMU_REG_RTC_CTRL) | PMU_WDT_CLR_BIT);
|
|
}
|
|
|
|
if (state_map & PMU_RTC_A_INT_STATUS_BIT) {
|
|
ool_write(PMU_REG_RTC_CTRL, ool_read(PMU_REG_RTC_CTRL) | PMU_RTC_ALARM_A_CLR_BIT);
|
|
}
|
|
|
|
if (state_map & PMU_GPIO_PMU_INT_STATUS_BIT) {
|
|
// ool_write16(PMU_REG_PIN_XOR_CLR, ool_read16(PMU_REG_PIN_XOR_RESULT));
|
|
}
|
|
|
|
if (state_map & PMU_GPIO_GROUPH_INT_STATUS_BIT) {
|
|
ool_write(PMU_REG_WKUP_INT_CLR, ool_read(PMU_REG_WKUP_INT_CLR) | 0x01);
|
|
}
|
|
|
|
if (state_map & PMU_GPIO_GROUPL_INT_STATUS_BIT) {
|
|
ool_write(PMU_REG_WKUP_INT_CLR, ool_read(PMU_REG_WKUP_INT_CLR) | 0x02);
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
|
|
void pmu_lvd_enable(enum_PMU_LVD_THD_t thd)
|
|
{
|
|
uint8_t value;
|
|
|
|
value = ool_read(0xa3);
|
|
value &= 0x1f;
|
|
value |= (thd << 5);
|
|
ool_write(0xa3, value);
|
|
|
|
ool_write(PMU_REG_ANA_LAST_V, ool_read(PMU_REG_ANA_LAST_V) & (~PMU_ANA_LAST_LVD_V_BIT));
|
|
ool_write(PMU_REG_ANA_XOR_EN, ool_read(PMU_REG_ANA_XOR_EN) | PMU_ANA_XOR_LVD_EN_BIT);
|
|
ool_write(PMU_REG_ANA_INT_EN, ool_read(PMU_REG_ANA_INT_EN) | PMU_LVD_INT_EN_BIT);
|
|
|
|
pmu_enable_isr(PMU_LVD_INT_MSK_BIT);
|
|
}
|
|
|
|
void pmu_lvd_disable(void)
|
|
{
|
|
pmu_disable_isr(PMU_LVD_INT_MSK_BIT);
|
|
}
|
|
|
|
void pmu_adkey0_start(void)
|
|
{
|
|
/*adkey0 interrupt enable*/
|
|
ool_write(PMU_REG_ANA_INT_EN, PMU_KEY0_INT_EN_BIT);
|
|
/*adkey0 xor enable*/
|
|
ool_write16(PMU_REG_ANA_XOR_EN, ool_read(PMU_REG_ANA_XOR_EN) | 0x04);
|
|
/*enable adkey0*/
|
|
pmu_enable_isr(PMU_ADKEY0_INT_MSK_BIT);
|
|
|
|
ool_write(PMU_REG_ADKEY_CFG, 0xdb);
|
|
NVIC_EnableIRQ(PMU_IRQn);
|
|
}
|
|
|
|
void pmu_adkey1_start(void)
|
|
{
|
|
/*adkey1 interrupt enable*/
|
|
ool_write(PMU_REG_ANA_INT_EN, PMU_KEY1_INT_EN_BIT);
|
|
/*adkey1 xor enable*/
|
|
ool_write16(PMU_REG_ANA_XOR_EN, ool_read(PMU_REG_ANA_XOR_EN) | 0x08);
|
|
/*enable adkey1*/
|
|
pmu_enable_isr(PMU_ADKEY1_INT_MSK_BIT);
|
|
|
|
ool_write(PMU_REG_ADKEY_CFG, 0xdb);
|
|
NVIC_EnableIRQ(PMU_IRQn);
|
|
}
|
|
#endif
|
|
|
|
__WEAK void PMU_Battery_Full_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_Charge_Monitor_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void RTC_ALARMA_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void RTC_ALARMB_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_GPIO_PMU_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_GPIO_GROUPH_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_GPIO_GROUPL_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_LVD_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_ADKEY0_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_ADKEY1_IRQHandler(void)
|
|
{
|
|
}
|
|
|
|
__WEAK void PMU_IWDT_IRQhandler(void)
|
|
{
|
|
}
|
|
|
|
void pmu_irq(void)
|
|
{
|
|
uint16_t state_map = pmu_get_isr_state();
|
|
// printf("%s state%d \r\n",__func__,state_map);
|
|
// pmu_clear_isr_state(state_map);
|
|
|
|
if (state_map & PMU_BATFULL_INT_STATUS_BIT) {
|
|
PMU_Battery_Full_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_CHG_ACOK_INT_STATUS_BIT) {
|
|
PMU_Charge_Monitor_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_LVD_INT_STATUS_BIT) {
|
|
PMU_LVD_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_RTC_A_INT_STATUS_BIT) {
|
|
RTC_ALARMA_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_RTC_B_INT_STATUS_BIT) {
|
|
RTC_ALARMB_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_GPIO_PMU_INT_STATUS_BIT) {
|
|
PMU_GPIO_PMU_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_GPIO_GROUPH_INT_STATUS_BIT) {
|
|
PMU_GPIO_GROUPH_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_GPIO_GROUPL_INT_STATUS_BIT) {
|
|
PMU_GPIO_GROUPL_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_ADKEY0_INT_STATUS_BIT) {
|
|
PMU_ADKEY0_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_ADKEY1_INT_STATUS_BIT) {
|
|
PMU_ADKEY1_IRQHandler();
|
|
}
|
|
|
|
if (state_map & PMU_WDT_INT_STATUS_BIT) {
|
|
PMU_IWDT_IRQhandler();
|
|
}
|
|
pmu_clear_isr_state(state_map);
|
|
}
|