253 lines
8.4 KiB
C
253 lines
8.4 KiB
C
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/*
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******************************************************************************
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* @file driver_adc.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2021
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* @brief Header file of ADC HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_ADC_H__
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#define __DRIVER_ADC_H__
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#include "fr30xx.h"
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/** @addtogroup ADC_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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#define ADC_MAX_CHANNELS (8)
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#define ADC_MAX_IO_INPUT_MAP (4)
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/* Control Register for ADC */
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typedef struct
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{
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uint32_t ADC_ConvertEN : 1;
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uint32_t ADC_Reset : 1;
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uint32_t rsv_0 : 1;
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uint32_t ADC_SoftTrigger : 1;
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uint32_t rsv_1 : 28;
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}REG_ADC_Control_t;
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/* Config Register for ADC */
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typedef struct
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{
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uint32_t ADC_ChannelMax : 4;
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uint32_t ADC_ConvertMode : 1;
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uint32_t ADC_TriggerMode : 1;
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uint32_t ADC_FIFO_EN : 1;
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uint32_t rsv_0 : 1;
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uint32_t ADC_SoftTriggerChannel : 4;
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uint32_t rsv_1 : 20;
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}REG_ADC_Config_t;
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/* Timing Register for ADC */
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typedef struct
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{
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uint32_t Clock_DIV : 8;
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uint32_t rsv_0 : 8;
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uint32_t SetupCycle : 6;
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uint32_t SampleCycle : 5;
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uint32_t TimeoutCycle : 5;
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}REG_ADC_Timing_t;
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/* ----------------------------------------------*/
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/* ADC Registers */
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/* ----------------------------------------------*/
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typedef struct
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{
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volatile REG_ADC_Control_t Control; /* Offset 0x00 */
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volatile REG_ADC_Config_t Config; /* Offset 0x04 */
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volatile REG_ADC_Timing_t Timing; /* Offset 0x08 */
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volatile uint32_t rsv_0; /* Offset 0x0C */
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volatile uint32_t rsv_1; /* Offset 0x10 */
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volatile uint32_t rsv_2; /* Offset 0x14 */
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volatile uint32_t Channel_Status; /* Offset 0x18 */
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volatile uint32_t rsv_3; /* Offset 0x1C */
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volatile uint32_t ADC_INT_Enble; /* Offset 0x20 */
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volatile uint32_t ADC_INT_Status; /* Offset 0x24 */
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volatile uint32_t ADC_INT_Raws; /* Offset 0x28 */
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volatile uint32_t ACT0; /* Offset 0x2C */
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volatile uint32_t ACT1; /* Offset 0x30 */
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volatile uint32_t ChannelMap[8]; /* Offset 0x34 ~ 0x50 */
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volatile uint32_t rsv0[8];
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volatile uint32_t ChannelData[8]; /* Offset 0x74 ~ 0x90 */
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}struct_ADC_t;
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#define ADC ((struct_ADC_t *)ADC_BASE)
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/* ################################ Register Section END ################################ */
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/**
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* @}
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*/
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/** @addtogroup ADC_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization, Config Section Start ################################ */
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#define ADC_INT_CONVERT_ERR (0x10)
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#define ADC_INT_CHANNEL_VALID (0x08)
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#define ADC_ACT0_REF_1P2V (0x1A036)
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#define ADC_ACT0_REF_IOLDO (0xDA036)
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#define ADC_ACT1_VBE_EN (0x02)
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#define ADC_ACT1_VBAT_EN (0x04)
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#define ADC_ACT1_IS (0x40)
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/* ADC interrupt index */
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typedef enum
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{
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ADC_CHANNEL_MAP_PMU_P4, /* PMU P4 */
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ADC_CHANNEL_MAP_PMU_P5, /* PMU P5 */
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ADC_CHANNEL_MAP_PMU_P6, /* PMU P6 */
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ADC_CHANNEL_MAP_PMU_P7, /* PMU P7 */
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ADC_CHANNEL_MAP_VBE, /* VBE */
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ADC_CHANNEL_MAP_VBAT, /* 1/4 VBAT */
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}enum_ADC_Channel_Map_t;
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/* ADC interrupt index */
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typedef enum
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{
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ADC_FIFO_EMPTY = 0x01,
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ADC_FIFO_FULL = 0x02,
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ADC_FIFO_ALMOST_FULL = 0x04,
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ADC_CHANNEL_VALID = 0x08,
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ADC_ERR = 0x10,
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}enum_ADC_int_index_t;
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/* ADC convert mode */
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typedef enum
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{
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ADC_SINGLE_MODE,
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ADC_LOOP_MODE,
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}enum_ADC_convert_mode_t;
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/* ADC FIFO mode */
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typedef enum
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{
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ADC_FIFO_DISABLE,
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ADC_FIFO_ENABLE,
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}enum_ADC_FIFO_EN_t;
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/* ADC convert mode */
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typedef enum
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{
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ADC_HARDWARE_TRIGGER,
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ADC_SOFTWARE_TRIGGER,
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}enum_ADC_trigger_mode_t;
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typedef enum
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{
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ADC_REF_IOLDO,
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ADC_REF_1P2V,
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}enum_ADC_reference_t;
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/**
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* @brief hard trigger config definition
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*/
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typedef struct
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{
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uint32_t ADC_Convert_Mode; /*!< Specifies the convert mode, single or loop.
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This parameter can be a value @ref enum_ADC_convert_mode_t */
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uint32_t ADC_Channel_Max; /*!< Specifies the number of Maximum conversion channels.
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This parameter can be a value between 1 ~ 8 */
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}struct_HardTriggerConfig_t;
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/**
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* @brief ADC Initialization Structure definition
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*/
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typedef struct
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{
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uint32_t ADC_Reference; /*!< Specifies the reference source of ADC.
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This parameter can be a value @ref enum_ADC_reference_t */
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uint32_t ADC_TriggerMode; /*!< Specifies the number of ADC Trigger Mode.
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This parameter can be a value @ref enum_ADC_trigger_mode_t */
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struct_HardTriggerConfig_t HardTriggerConfig; /*!< ADC hard trigger config parameters */
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}adc_InitConfig_t;
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/* ################################ Initialization, Config Section END ################################ */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* ADC hard Convert Enable/Disable */
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#define __ADC_CONVERT_ENABLE() (ADC->Control.ADC_ConvertEN = 1)
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#define __ADC_CONVERT_DISABLE() (ADC->Control.ADC_ConvertEN = 0)
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/* ADC State machine Reset */
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#define __ADC_RESET() (ADC->Control.ADC_Reset = 1)
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/* soft trigger convert */
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#define __ADC_SOFT_TRIGGER() (ADC->Control.ADC_SoftTrigger = 1)
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/* set soft trigger channel */
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#define __ADC_SET_SOFT_TRIGGER_CHANNEL(__CHANNEL__) (ADC->Config.ADC_SoftTriggerChannel = __CHANNEL__)
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/* Set max channel */
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#define __ADC_SET_MAX_CHANNEL(__MAXCH__) (ADC->Config.ADC_ChannelMax = __MAXCH__)
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/* Set convert mode */
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#define __ADC_SET_CONVERT_MODE(__MODE__) (ADC->Config.ADC_ConvertMode = __MODE__)
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/* Set trigger mode */
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#define __ADC_SET_TRIGGER_MODE(__MODE__) (ADC->Config.ADC_TriggerMode = __MODE__)
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/* set adc clock div */
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#define __ADC_SET_CLK_DIV(__DIV__) (ADC->Timing.Clock_DIV = __DIV__)
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/* set convert setup/sample/timout cycle */
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#define __ADC_SET_SETUP_CYCLE(__CYCLE__) (ADC->Timing.SetupCycle = __CYCLE__)
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#define __ADC_SET_SAMPLE_CYCLE(__CYCLE__) (ADC->Timing.SampleCycle = __CYCLE__)
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#define __ADC_SET_TIMEOUT_CYCLE(__CYCLE__) (ADC->Timing.TimeoutCycle = __CYCLE__)
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/* Get ADC Channel status */
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#define __ADC_GET_CHANNEL_STATUS() (ADC->Channel_Status)
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/* ADC interrupt enable/disable */
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#define __ADC_INT_ENABLE(__INDEX__) (ADC->ADC_INT_Enble |= __INDEX__)
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#define __ADC_INT_DISABLE(__INDEX__) (ADC->ADC_INT_Enble &= ~(__INDEX__))
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#define __ADC_GET_INT_STATUS() (ADC->ADC_INT_Raws)
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/* Set channel map */
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#define __ADC_SET_CHANNEL_MAP(__CHANNEL__, __MAP__) (ADC->ChannelMap[__CHANNEL__] = __MAP__)
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/* Get channel data */
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#define __ADC_GET_CHANNEL_DATA(__CHANNEL__) (ADC->ChannelData[__CHANNEL__])
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/* Exported functions --------------------------------------------------------*/
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/* adc_init */
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void adc_init(adc_InitConfig_t InitConfig);
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/* adc_convert_start/stop */
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void adc_convert_start(void);
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void adc_convert_start_IT(void);
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void adc_convert_stop(void);
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void adc_channel_valid_int_enable(void);
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void adc_channel_valid_int_dsiable(void);
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/* adc_soft_trigger_convert */
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void adc_soft_trigger_convert(uint8_t fu8_Channel);
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/* adc_get_channel_valid_status */
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bool adc_get_channel_valid_status(uint8_t fu8_Channel);
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/* adc_get_channel_data */
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uint32_t adc_get_channel_data(uint8_t fu8_Channel);
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/* adc_set_channel_maping */
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void adc_set_channel_maping(uint8_t fu8_Channel, enum_ADC_Channel_Map_t fe_Map);
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#endif
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