371 lines
15 KiB
C
371 lines
15 KiB
C
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/*
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******************************************************************************
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* @file driver_i2c.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2021
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* @brief Header file of I2C HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_I2C_H__
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#define __DRIVER_I2C_H__
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#include "fr30xx.h"
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/** @addtogroup I2C_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* I2C control Register */
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typedef struct
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{
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uint32_t MASTER_MODE : 1;
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uint32_t SPEED : 2;
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uint32_t ADDR_SLAVE_10BIT : 1;
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uint32_t rsv_0 : 1;
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uint32_t RESTART_EN : 1;
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uint32_t SLAVE_DISABLE : 1;
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uint32_t STOP_DET_IF_ADDR_ESSED : 1;
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uint32_t TX_EMPTY_CTRL : 1;
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uint32_t RX_FIFO_FULL_HLD_CTRL : 1;
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uint32_t STOP_DET_IF_MASTER_ACTIVE : 1;
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uint32_t BUS_DETEC_FEATURE_CTRL : 1;
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uint32_t rsv_1 : 20;
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}REG_I2C_CTRL_t;
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/* target address Register */
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typedef struct
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{
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uint32_t TAR : 10;
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uint32_t rsv_0 : 1;
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uint32_t SPECIAL : 1;
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uint32_t ADDR_MASTER_10BIT : 1;
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uint32_t DEVICE_ID : 1;
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uint32_t rsv_1 : 18;
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}REG_TAR_t;
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/* DATA CMD Register */
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typedef struct
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{
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uint32_t DAT : 8;
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uint32_t CMD : 1;
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uint32_t STOP : 1;
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uint32_t RESTART : 1;
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uint32_t FIRST_DATA_BYTE : 1;
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uint32_t rsv_0 : 20;
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}REG_DATA_CMD_t;
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/* enable Register */
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typedef struct
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{
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uint32_t ENABLE : 1;
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uint32_t ABORT : 1;
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uint32_t TX_CMD_BLOCK : 1;
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uint32_t SDA_STUCK_RECOVERY : 1;
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uint32_t rsv_0 : 28;
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}REG_ENABLE_t;
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/* Status Register */
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typedef struct
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{
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uint32_t ACTIVITY : 1;
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uint32_t TFNF : 1;
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uint32_t TFE : 1;
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uint32_t RFNE : 1;
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uint32_t RFF : 1;
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uint32_t MST_ACTIVITY : 1;
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uint32_t SLV_ACTIVITY : 1;
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uint32_t MST_HOLD_TX_FIFO_EMPTY : 1;
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uint32_t MST_HOLD_RX_FIFO_FULL : 1;
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uint32_t SLV_HOLD_TX_FIFO_EMPTY : 1;
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uint32_t SLV_HOLD_RX_FIFO_FULL : 1;
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uint32_t SDA_STUCK_NOT_RECOVERED : 1;
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uint32_t rsv_0 : 20;
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}REG_STATUS_t;
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/* SDA hold Register */
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typedef struct
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{
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uint32_t SDA_TX_HOLD : 16;
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uint32_t SDA_RX_HOLD : 8;
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uint32_t rsv_0 : 8;
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}REG_SDA_HOLD_t;
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/* TX ABRT SOURCE Register */
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typedef union
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{
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struct
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{
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uint32_t ABRT_7ADDR_NOACK : 1;
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uint32_t ABRT_10ADDR1_NOACK : 1;
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uint32_t ABRT_10ADDR2_NOACK : 1;
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uint32_t ABRT_TXDATA_NOACK : 1;
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uint32_t rsv_0 : 2;
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uint32_t ABRT_SBYTE_ACKDET : 1;
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uint32_t rsv_1 : 1;
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uint32_t ABRT_HS_NORSTRT : 1;
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uint32_t rsv_2 : 1;
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uint32_t ABRT_10B_RD_NORSTRT : 1;
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uint32_t ABRT_MASTER_DIS : 1;
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uint32_t ARB_LOST : 1;
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uint32_t ABRT_SLVFLUSH_TXFIFO : 1;
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uint32_t ABRT_SLV_ARBLOST : 1;
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uint32_t ABRT_SLVRD_INTX : 1;
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uint32_t ABRT_USER_ABRT : 1;
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uint32_t ABRT_SDA_STUCK_AT_LOW : 1;
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uint32_t rsv_3 : 1;
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uint32_t ABRT_DEVICE_SLVADDR_NOACK : 1;
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uint32_t ABRT_DEVICE_WRITE : 1;
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uint32_t rsv_4 : 2;
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uint32_t TX_FLUSH_CNT : 9;
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}TX_ABRT_SOURCE_BIT;
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uint32_t TX_ABRT_SOURCE_DWORD;
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}REG_TX_ABRT_SOURCE_t;
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/* DMA control Register */
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typedef struct
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{
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uint32_t RDMAE : 1;
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uint32_t TDMAE : 1;
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uint32_t rsv_0 : 30;
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}REG_DMA_CR_t;
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/* -----------------------------------------------*/
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/* I2C Register */
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/* -----------------------------------------------*/
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typedef struct
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{
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volatile REG_I2C_CTRL_t CTRL; /* Offset 0x00 */
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volatile REG_TAR_t TAR; /* Offset 0x04 */
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volatile uint32_t SAR; /* Offset 0x08 */
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volatile uint32_t HS_MADDR; /* Offset 0x0C */
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volatile uint32_t DATA_CMD; /* Offset 0x10 */
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volatile uint32_t rsv_0[2];
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volatile uint32_t FS_SCL_HCNT; /* Offset 0x1C */
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volatile uint32_t FS_SCL_LCNT; /* Offset 0x20 */
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volatile uint32_t rsv_1[2];
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volatile uint32_t INT_STAT; /* Offest 0x2C */
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volatile uint32_t INT_MASK; /* Offest 0x30 */
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volatile uint32_t RAW_INT_STAT; /* Offest 0x34 */
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volatile uint32_t RX_TL; /* Offest 0x38 */
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volatile uint32_t TX_TL; /* Offest 0x3C */
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volatile uint32_t CLR_INTR; /* Offest 0x40 */
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volatile uint32_t CLR_RX_UNDER; /* Offest 0x44 */
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volatile uint32_t CLR_RX_OVER; /* Offest 0x48 */
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volatile uint32_t CLR_TX_OVER; /* Offest 0x4C */
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volatile uint32_t CLR_RD_REQ; /* Offest 0x50 */
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volatile uint32_t CLR_TX_ABRT; /* Offest 0x54 */
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volatile uint32_t CLR_RX_DONE; /* Offest 0x58 */
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volatile uint32_t CLR_ACTIVITY; /* Offest 0x5C */
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volatile uint32_t CLR_STOP_DET; /* Offest 0x60 */
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volatile uint32_t CLR_START_DET; /* Offest 0x64 */
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volatile uint32_t rsv_2;
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volatile REG_ENABLE_t ENABLE; /* Offest 0x6C */
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volatile REG_STATUS_t STATUS; /* Offest 0x70 */
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volatile uint32_t TXFLR; /* Offest 0x74 */
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volatile uint32_t RXFLR; /* Offest 0x78 */
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volatile REG_SDA_HOLD_t SDA_HOLD; /* Offest 0x7C */
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volatile REG_TX_ABRT_SOURCE_t TX_ABRT_SOURCE; /* Offest 0x80 */
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volatile uint32_t SLV_DATA_NACK; /* Offest 0x84 */
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volatile REG_DMA_CR_t DMA_CTRL; /* Offest 0x88 */
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volatile uint32_t DMATDL; /* Offest 0x8C */
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volatile uint32_t DMARDL; /* Offest 0x90 */
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volatile uint32_t SDA_SETUP; /* Offest 0x94 */
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volatile uint32_t rsv_3[2];
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volatile uint32_t FS_SPKLEN; /* Offest 0xA0 */
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volatile uint32_t rsv_4;
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volatile uint32_t CLR_RESTART_DET; /* Offest 0xA8 */
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volatile uint32_t SCL_STUCK_LOW_TIMEOUT; /* Offest 0xAC */
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volatile uint32_t SDA_STUCK_LOW_TIMEOUT; /* Offest 0xB0 */
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volatile uint32_t CLR_SCL_STUCK_DET; /* Offest 0xB4 */
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}struct_I2C_t;
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#define I2C0 ((struct_I2C_t *)I2C0_BASE)
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#define I2C1 ((struct_I2C_t *)I2C1_BASE)
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#define I2C2 ((struct_I2C_t *)I2C2_BASE)
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#define I2C3 ((struct_I2C_t *)I2C3_BASE)
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#define I2C4 ((struct_I2C_t *)I2C4_BASE)
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#define I2C5 ((struct_I2C_t *)I2C5_BASE)
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/* ################################ Register Section END ################################## */
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/**
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* @}
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*/
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/** @addtogroup I2C_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization<6F><6E>Config Section Start ################################ */
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/* interrupt index */
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typedef enum
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{
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INT_RX_UNDER = 0x00000001,
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INT_RX_OVER = 0x00000002,
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INT_RX_FULL = 0x00000004,
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INT_TX_OVER = 0x00000008,
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INT_TX_EMPTY = 0x00000010,
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INT_RD_REQ = 0x00000020,
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INT_TX_ABRT = 0x00000040,
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INT_RX_DONE = 0x00000080,
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INT_ACTIVITY = 0x00000100,
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INT_STOP_DET = 0x00000200,
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INT_START_DET = 0x00000400,
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INT_RESTART_DET = 0x00001000,
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INT_MASTER_ON_HOLD = 0x00002000,
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INT_SCL_STUCK_AT_LOW = 0x00004000,
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}enum_INT_Index_t;
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/* interrupt index */
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typedef enum
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{
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CMD_WRITE = 0x0000,
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CMD_READ = 0x0100,
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CMD_STOP = 0x0200,
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CMD_RESTART = 0x0400,
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}enum_CMD_t;
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/* I2C Mode */
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typedef enum
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{
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I2C_MODE_MASTER_7BIT = 0x01,
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I2C_MODE_MASTER_10BIT = 0x11,
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I2C_MODE_SLAVE_7BIT = 0x00,
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I2C_MODE_SLAVE_10BIT = 0x10,
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I2C_MASK_MASTER = 0x01,
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I2C_MASK_10BIT = 0x10,
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}enum_I2C_MODE_t;
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/*
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* @brief I2C Init Structure definition
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*/
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typedef struct
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{
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uint32_t I2C_Mode; /* This parameter can be a value of @ref enum_I2C_MODE_t */
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uint32_t SCL_HCNT; /* This parameter can be a 16-bit value. The minimum limit is 6 */
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uint32_t SCL_LCNT; /* SCL high/low level hold time. The minimum limit is 8 */
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uint32_t Slave_Address; /* This parameter can be a 7-bit or 10-bit address */
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}struct_I2CInit_t;
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/*
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* @brief I2C handle Structure definition
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*/
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typedef struct
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{
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struct_I2C_t *I2Cx; /*!< I2C registers base address */
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struct_I2CInit_t Init; /*!< I2C communication parameters */
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volatile uint32_t u32_TxSize; /*!< I2C Transmit parameters in interrupt */
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volatile uint32_t u32_TxCount;
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volatile uint8_t *p_TxData;
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volatile bool b_TxBusy;
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volatile uint32_t u32_RxSize; /*!< I2C Receive parameters in interrupt */
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volatile uint32_t u32_RxCount;
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volatile uint8_t *p_RxData;
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volatile bool b_RxBusy;
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}I2C_HandleTypeDef;
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/* ################################ Initialization<6F><6E>Config Section END ################################## */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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#define __I2C_ENABLE(__I2Cx__) (__I2Cx__->ENABLE.ENABLE = 1)
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#define __I2C_DISABLE(__I2Cx__) (__I2Cx__->ENABLE.ENABLE = 0)
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/* master transfe abort */
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#define __I2C_MASTER_TRAN_ABORT(__I2Cx__) (__I2Cx__->ENABLE.ABORT = 1)
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/* master Block/start the transmission */
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#define __I2C_MASTER_BLOCK_TRAN(__I2Cx__) (__I2Cx__->ENABLE.TX_CMD_BLOCK = 1)
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#define __I2C_MASTER_START_TRAN(__I2Cx__) (__I2Cx__->ENABLE.TX_CMD_BLOCK = 0)
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/* get the number of valid data in RxFIFO/TxFIFO */
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#define __I2C_GET_TxFIFO_VALID_NUM(__I2Cx__) (__I2Cx__->TXFLR)
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#define __I2C_GET_RxFIFO_VALID_NUM(__I2Cx__) (__I2Cx__->RXFLR)
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/* Get Tx abort source */
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#define __I2C_GET_TX_ABRT_SOURCE(__I2Cx__) (__I2Cx__->TX_ABRT_SOURCE.TX_ABRT_SOURCE_DWORD)
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#define __I2C_IS_TX_ABRT(__I2Cx__) (__I2Cx__->RAW_INT_STAT & INT_TX_ABRT)
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/* get I2C Status */
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#define __I2C_IS_BUSY(__I2Cx__) (__I2Cx__->STATUS.ACTIVITY)
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#define __I2C_IS_MASTER_BUSY(__I2Cx__) (__I2Cx__->STATUS.MST_ACTIVITY)
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#define __I2C_IS_SLAVE_BUSY(__I2Cx__) (__I2Cx__->STATUS.SLV_ACTIVITY)
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#define __I2C_IS_TxFIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.TFNF == 0)
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#define __I2C_IS_TxFIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.TFE)
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#define __I2C_IS_RxFIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.RFF)
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#define __I2C_IS_RxFIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.RFNE == 0)
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#define __I2C_IS_MST_HOLD_TX_FIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.MST_HOLD_TX_FIFO_EMPTY)
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#define __I2C_IS_MST_HOLD_RX_FIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.MST_HOLD_RX_FIFO_FULL)
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#define __I2C_IS_SLV_HOLD_TX_FIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.SLV_HOLD_TX_FIFO_EMPTY)
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#define __I2C_IS_SLV_HOLD_RX_FIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.SLV_HOLD_RX_FIFO_FULL)
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#define __I2C_IS_SDA_STUCK_NOT_RECOVERED(__I2Cx__) (__I2Cx__->STATUS.SDA_STUCK_NOT_RECOVERED)
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/* RxFIFO/TxFIFO Threshold level */
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#define __I2C_RxFIFO_THRESHOLD_LEVEL(__I2Cx__, __LEVEL__) (__I2Cx__->RX_TL = __LEVEL__)
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#define __I2C_TxFIFO_THRESHOLD_LEVEL(__I2Cx__, __LEVEL__) (__I2Cx__->TX_TL = __LEVEL__)
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/* SCL High/Low count, */
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#define __I2C_SCL_HIGH_COUNT(__I2Cx__, __COUNT__) (__I2Cx__->FS_SCL_HCNT = __COUNT__)
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#define __I2C_SCL_LOW_COUNT(__I2Cx__, __COUNT__) (__I2Cx__->FS_SCL_LCNT = __COUNT__)
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#define __I2C_SDA_HOLD(__I2Cx__, __COUNT__) (__I2Cx__->SDA_HOLD.SDA_TX_HOLD = __COUNT__)
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#define __I2C_SDA_SETUP(__I2Cx__, __COUNT__) (__I2Cx__->SDA_SETUP = __COUNT__)
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/* Slave send ACK/NACK */
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#define __I2C_SLAVE_SEND_NACK(__I2Cx__) (__I2Cx__->SLV_DATA_NACK = 1)
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#define __I2C_SLAVE_SEND_ACK(__I2Cx__) (__I2Cx__->SLV_DATA_NACK = 0)
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/* Exported functions ---------------------------------------------------------*/
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/* i2c_IRQHandler */
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void i2c_IRQHandler(I2C_HandleTypeDef *hi2c);
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/* i2c_init */
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void i2c_init(I2C_HandleTypeDef *hi2c);
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/* Master transmit/receive */
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bool i2c_master_transmit(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
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bool i2c_master_receive(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
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|
|
bool i2c_master_transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
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|
|
bool i2c_master_receive_IT(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
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|
|
bool i2c_slave_transmit(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
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|
|
bool i2c_slave_receive(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
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|
|
bool i2c_slave_transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
bool i2c_slave_receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
|
|||
|
|
/* memory write/read */
|
|||
|
|
bool i2c_memory_write(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint16_t fu16_MemAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
bool i2c_memory_read(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint16_t fu16_MemAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
bool i2c_memory_is_busy(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress);
|
|||
|
|
|
|||
|
|
/* interrupt function */
|
|||
|
|
void i2c_int_enable(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
|||
|
|
void i2c_int_disable(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
|||
|
|
bool i2c_is_int_enable(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
|||
|
|
bool i2c_get_int_status(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
|||
|
|
void i2c_clear_int_status(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
|||
|
|
|
|||
|
|
/* sensor write/read */
|
|||
|
|
bool i2c_sensor_write(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint32_t fu32_RegAddress, uint8_t fu8_AddressLength, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
bool i2c_sensor_read(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint32_t fu32_RegAddress, uint8_t fu8_AddressLength, uint8_t *fp_Data, uint32_t fu32_Size);
|
|||
|
|
#endif
|