A36 PCB1.1 软件工程整理
This commit is contained in:
202
fr3092_mcu/components/drivers/bsp/display/driver_display.c
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202
fr3092_mcu/components/drivers/bsp/display/driver_display.c
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/*
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******************************************************************************
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* @file driver_display.c
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2022
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* @brief display abstract interfase.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#include <stdint.h>
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#include "app_lvgl.h"
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#include "app_config.h"
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#include "driver_display.h"
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#ifdef DISPLAY_TYPE_GC9C01
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#include "driver_gc9c01.h"
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#endif
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#ifdef DISPLAY_TYPE_JD9854
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#include "driver_jd9854.h"
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#endif
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#ifdef DISPLAY_TYPE_SH8601A
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#include "driver_sh8601a.h"
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#endif
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#ifdef DISPLAY_TYPE_ICNA3310
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#include "driver_icna3310.h"
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#endif
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#ifdef DISPLAY_TYPE_SH8601Z
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#include "driver_sh8601z.h"
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#endif
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#ifdef DISPLAY_TYPE_NV3047_RGB
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#include "driver_nv3047_rgb.h"
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#endif
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#ifdef DISPLAY_TYPE_ST7701_RGB
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#include "driver_st7701_rgb.h"
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#endif
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#ifdef DISPLAY_TYPE_NV3041A
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#include "driver_nv3041a.h"
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#endif
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void display_init(void)
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{
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#ifdef DISPLAY_TYPE_GC9C01
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gc9c01_init();
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#endif
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#ifdef DISPLAY_TYPE_JD9854
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jd9854_init();
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#endif
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#ifdef DISPLAY_TYPE_SH8601A
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sh8601a_init();
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#endif
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#ifdef DISPLAY_TYPE_ICNA3310
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icna3310_init();
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#endif
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#ifdef DISPLAY_TYPE_SH8601Z
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sh8601z_init();
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#endif
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#ifdef DISPLAY_TYPE_NV3047_RGB
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extern void* get_display_buffer1(void);
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extern void rgb_display_controller_init(void);
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rgb_display_controller_init();
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rgb_display_init(get_display_buffer1());
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#endif
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#ifdef DISPLAY_TYPE_ST7701_RGB
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extern void* get_display_buffer1(void);
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st7701_init(get_display_buffer1());
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#endif
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#ifdef DISPLAY_TYPE_NV3041A
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nv3041a_init();
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#endif
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}
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void display_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e)
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{
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#ifdef DISPLAY_TYPE_GC9C01
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gc9c01_set_window(x_s, x_e, y_s, y_e);
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#endif
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#ifdef DISPLAY_TYPE_JD9854
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jd9854_set_window(x_s, x_e, y_s, y_e);
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#endif
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#ifdef DISPLAY_TYPE_SH8601A
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sh8601a_set_window(x_s, x_e, y_s, y_e);
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#endif
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#ifdef DISPLAY_TYPE_ICNA3310
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icna3310_set_window(x_s, x_e, y_s, y_e);
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#endif
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#ifdef DISPLAY_TYPE_SH8601Z
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sh8601z_set_window(x_s, x_e, y_s, y_e);
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#endif
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#ifdef DISPLAY_TYPE_NV3041A
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nv3041a_set_window(x_s, x_e, y_s, y_e);
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#endif
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}
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void display_update(uint32_t pixel_count, uint8_t pixel_width, void *data)
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{
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#ifdef DISPLAY_TYPE_GC9C01
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gc9c01_display(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_JD9854
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jd9854_display(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_SH8601A
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sh8601a_display(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_ICNA3310
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icna3310_display(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_SH8601Z
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sh8601z_display(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_NV3041A
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nv3041a_display(pixel_count, pixel_width, data);
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#endif
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}
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void display_update_dma(uint32_t pixel_count, uint8_t pixel_width, void *data)
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{
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#ifdef DISPLAY_TYPE_GC9C01
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gc9c01_display_dma(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_JD9854
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jd9854_display_dma(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_SH8601A
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sh8601a_display_dma(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_ICNA3310
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icna3310_display_dma(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_SH8601Z
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sh8601z_display_dma(pixel_count, pixel_width, data);
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#endif
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#ifdef DISPLAY_TYPE_NV3047_RGB
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#endif
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#ifdef DISPLAY_TYPE_ST7701_RGB
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#endif
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#ifdef DISPLAY_TYPE_NV3041A
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nv3041a_display_dma(pixel_count, pixel_width, data);
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#endif
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}
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void display_power_off(void)
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{
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#ifdef DISPLAY_TYPE_SH8601Z
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sh8601z_power_off();
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#endif
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}
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void display_power_on(void)
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{
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#ifdef DISPLAY_TYPE_SH8601Z
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sh8601z_power_on();
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#endif
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}
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void display_update_dma_isr(void)
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{
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#ifdef DISPLAY_TYPE_GC9C01
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gc9c01_display_dma_isr();
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#endif
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#ifdef DISPLAY_TYPE_JD9854
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jd9854_display_dma_isr();
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#endif
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#ifdef DISPLAY_TYPE_SH8601A
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sh8601a_display_dma_isr();
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#endif
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#ifdef DISPLAY_TYPE_ICNA3310
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icna3310_display_dma_isr();
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#endif
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#ifdef DISPLAY_TYPE_SH8601Z
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sh8601z_display_dma_isr();
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#endif
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#ifdef DISPLAY_TYPE_ST7701_RGB
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st7701_rgb_display_dma_irq();
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#endif
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#ifdef DISPLAY_TYPE_NV3041A
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nv3041a_display_dma_isr();
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#endif
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}
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162
fr3092_mcu/components/drivers/bsp/display/driver_display.h
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162
fr3092_mcu/components/drivers/bsp/display/driver_display.h
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#ifndef __DRIVER_DISPLAY_H__
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#define __DRIVER_DISPLAY_H__
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#include <stdint.h>
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#include "driver_spi.h"
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#include "driver_dma.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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// Macro Variables definitions
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//
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//*****************************************************************************
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#define __DISPLAY_CS_SET() display_cs_set()
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#define __DISPLAY_CS_CLEAR() display_cs_clear()
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#define __DISPLAY_RESET_SET() display_reset_set()
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#define __DISPLAY_RESET_CLEAR() display_reset_clear()
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#define __DISPLAY_VCI_SET() display_vci_set()
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#define __DISPLAY_VCI_CLEAR() display_vci_clear()
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#define __DISPLAY_DELAY_MS(counter) display_delay_ms(counter)
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//*****************************************************************************
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//
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// Global Variables definitions
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//
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//*****************************************************************************
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extern SPI_HandleTypeDef spi_display_handle;
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extern DMA_HandleTypeDef dma_display_handle;
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//*****************************************************************************
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//
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// External function definitions
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//
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//*****************************************************************************
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/************************************************************************************
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* @fn display_cs_set
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*
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* @brief Set display driver CS pin to HIGH, this function should be implemented by user when
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* CS is controlled by software.
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*/
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void display_cs_set(void);
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/************************************************************************************
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* @fn display_cs_release
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*
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* @brief Set display driver CS pin to LOW, this function should be implemented by user when
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* CS is controlled by software.
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*/
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void display_cs_clear(void);
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/************************************************************************************
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* @fn display_reset_set
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*
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* @brief Set display driver RESET pin to HIGH, this function should be implemented by user..
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*/
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void display_reset_set(void);
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/************************************************************************************
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* @fn display_reset_clear
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*
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* @brief Set display driver RESET pin to LOW, this function should be implemented by user.
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*/
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void display_reset_clear(void);
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/************************************************************************************
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* @fn display_vci_set
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*
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* @brief Set display driver VCI pin to HIGH, this function should be implemented by user..
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*/
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void display_vci_set(void);
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/************************************************************************************
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* @fn display_vci_clear
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*
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* @brief Set display driver VCI pin to LOW, this function should be implemented by user.
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*/
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void display_vci_clear(void);
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/************************************************************************************
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* @fn display_delay_ms
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*
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* @brief Used in display driver. co_delay_100us or vTaskDelay can be used for implementation
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* by user.
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*/
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void display_delay_ms(uint32_t counter);
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/************************************************************************************
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* @fn display_init
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*
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* @brief Initial display drivers.
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*/
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void display_init(void);
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/************************************************************************************
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* @fn display_set_window
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*
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* @brief used to define area of frame memory where MCU can access.
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*
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* @param x_s: SC.
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* x_e: EC.
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* y_s: SP.
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* y_e: EP.
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*/
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void display_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e);
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/************************************************************************************
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* @fn display_update
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*
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* @brief transfer data to framebuffer of display controller in block mode.
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*
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* @param pixel_count: total pixels count to be sent.
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* pixel_width: this parameter should be 16, 24.
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* data: pointer to data buffer
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*/
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void display_update(uint32_t pixel_count, uint8_t pixel_width, void *data);
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/************************************************************************************
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* @fn display_update_dma
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*
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* @brief transfer data to framebuffer of display controller in DMA mode.
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*
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* @param pixel_count: total pixels count to be sent.
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* pixel_width: this parameter should be 16, 24.
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* data: pointer to data buffer
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*/
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void display_update_dma(uint32_t pixel_count, uint8_t pixel_width, void *data);
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/************************************************************************************
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* @fn display_update_dma_isr
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*
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* @brief this function will be called in DMA isr handler when dma transfer is done.
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*/
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void display_update_dma_isr(void);
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/************************************************************************************
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* @fn display_power_off
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*
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* @brief used to power off display to save power.
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*/
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void display_power_off(void);
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/************************************************************************************
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* @fn display_power_on
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*
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* @brief turn on display.
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*/
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void display_power_on(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DRIVER_DISPLAY_H__ */
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238
fr3092_mcu/components/drivers/bsp/display/driver_icna3310.c
Normal file
238
fr3092_mcu/components/drivers/bsp/display/driver_icna3310.c
Normal file
@ -0,0 +1,238 @@
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#include "driver_display.h"
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static void reg_write(uint8_t addr, uint8_t *value, uint8_t length)
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{
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uint8_t sdat[length + 4];
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sdat[0] = 0x02;
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sdat[1] = 0x00;
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sdat[2] = addr;
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sdat[3] = 0x00;
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memcpy(&sdat[4], value, length);
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__DISPLAY_CS_CLEAR();
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spi_master_transmit_X1(&spi_display_handle, sdat, sizeof(sdat));
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__DISPLAY_CS_SET();
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}
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static void reg_read(uint8_t addr, uint8_t *value, uint8_t length)
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{
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uint8_t sdat[4];
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sdat[0] = 0x03;
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sdat[1] = 0x00;
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sdat[2] = addr;
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sdat[3] = 0x00;
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__DISPLAY_CS_CLEAR();
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spi_master_transmit_X1(&spi_display_handle, sdat, sizeof(sdat));
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spi_master_receive_X1(&spi_display_handle, value, length);
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__DISPLAY_CS_SET();
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}
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void icna3310_init(void)
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{
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uint8_t buffer[4];
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__DISPLAY_VCI_CLEAR();
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__DISPLAY_RESET_CLEAR();
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__DISPLAY_DELAY_MS(200);
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__DISPLAY_VCI_SET();
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__DISPLAY_DELAY_MS(50);
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__DISPLAY_RESET_SET();
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__DISPLAY_DELAY_MS(5);
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__DISPLAY_RESET_CLEAR();
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__DISPLAY_DELAY_MS(5);
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__DISPLAY_RESET_SET();
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__DISPLAY_DELAY_MS(5);
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// __DISPLAY_VCI_CLEAR();
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// __DISPLAY_RESET_CLEAR();
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// __DISPLAY_DELAY_MS(20);
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// __DISPLAY_RESET_SET();
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// __DISPLAY_DELAY_MS(40);
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// __DISPLAY_VCI_SET();
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// __DISPLAY_DELAY_MS(80);
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buffer[0] = 0x20;
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reg_write(0xFE, &buffer[0], 1);
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buffer[0] = 0x5a;
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reg_write(0xF4, &buffer[0], 1);
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buffer[0] = 0x59;
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reg_write(0xF5, &buffer[0], 1);
|
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buffer[0] = 0x40;
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reg_write(0xFE, &buffer[0], 1);
|
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buffer[0] = 0x0a;
|
||||
reg_write(0x08, &buffer[0], 1);
|
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|
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buffer[0] = 0x00;
|
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reg_write(0xFE, &buffer[0], 1);
|
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buffer[0] = 0x80;
|
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reg_write(0xC4, &buffer[0], 1);//SPI sram write enable
|
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buffer[0] = 0x55;
|
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reg_write(0x3A, &buffer[0], 1);//55 RGB565, 77 RGB888
|
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buffer[0] = 0x00;
|
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reg_write(0x35, &buffer[0], 1);
|
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buffer[0] = 0x20;
|
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reg_write(0x53, &buffer[0], 1);
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buffer[0] = 0xFF;
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reg_write(0x51, &buffer[0], 1);
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buffer[0] = 0xFF;
|
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reg_write(0x63, &buffer[0], 1);
|
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buffer[0] = 0x00;
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buffer[1] = 0x06;
|
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buffer[2] = 0x01;
|
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buffer[3] = 0xD7;
|
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reg_write(0x2A, &buffer[0], 4); // paritial update:466RGB
|
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buffer[0] = 0x00;
|
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buffer[1] = 0x00;
|
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buffer[2] = 0x01;
|
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buffer[3] = 0xD1;
|
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reg_write(0x2B, &buffer[0], 4); // partial update:466line
|
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// buffer[0] = 0x00;
|
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// reg_write(0xFE, &buffer[0], 1);
|
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reg_write(0x11, NULL, 0);
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__DISPLAY_DELAY_MS(120);
|
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// buffer[0] = 0x00;
|
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// reg_write(0xFE, &buffer[0], 1);
|
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reg_write(0x29, NULL, 0);
|
||||
__DISPLAY_DELAY_MS(50);
|
||||
}
|
||||
|
||||
void icna3310_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e)
|
||||
{
|
||||
uint8_t data[4];
|
||||
|
||||
x_s += 6;
|
||||
x_e += 6;
|
||||
|
||||
data[0] = x_s >> 8;
|
||||
data[1] = x_s & 0xff;
|
||||
data[2] = x_e >> 8;
|
||||
data[3] = x_e & 0xff;
|
||||
reg_write(0x2A, &data[0], 4);
|
||||
|
||||
data[0] = y_s >> 8;
|
||||
data[1] = y_s & 0xff;
|
||||
data[2] = y_e >> 8;
|
||||
data[3] = y_e & 0xff;
|
||||
reg_write(0x2B, &data[0], 4);
|
||||
|
||||
// reg_write(0x2C, &data[0], 4);
|
||||
}
|
||||
|
||||
void icna3310_adjust_brightness(uint8_t value) //Value 0x00 - 0xFF
|
||||
{
|
||||
uint8_t buffer[1];
|
||||
|
||||
buffer[0] = 0x00;
|
||||
reg_write(0xFE, &buffer[0], 1);
|
||||
buffer[0] = value;
|
||||
reg_write(0x51, &buffer[0], 1);
|
||||
}
|
||||
|
||||
void icna3310_display(uint32_t pixel_count, uint8_t pixel_width, void *data)
|
||||
{
|
||||
uint8_t frame_size;
|
||||
|
||||
if (pixel_width == 16) {
|
||||
frame_size = SPI_FRAME_SIZE_16BIT;
|
||||
}
|
||||
else if (pixel_width == 32) {
|
||||
frame_size = SPI_FRAME_SIZE_24BIT;
|
||||
}
|
||||
spi_display_handle.Init.Frame_Size = frame_size;
|
||||
spi_display_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_display_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_display_handle.MultWireParam.Instruct = 0x32;
|
||||
spi_display_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_display_handle.MultWireParam.Address = 0x002C00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X2X4X8(&spi_display_handle, data, pixel_count);
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_DATA_FRAME_SIZE(spi_display_handle.SPIx, SPI_FRAME_SIZE_8BIT);
|
||||
}
|
||||
|
||||
void icna3310_display_dma(uint32_t pixel_count, uint8_t pixel_width, void *data)
|
||||
{
|
||||
uint8_t spi_trans_width;
|
||||
uint32_t dma_sample_count;
|
||||
|
||||
switch (dma_display_handle.Init.Source_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
dma_sample_count = pixel_count * pixel_width / 32;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
dma_sample_count = pixel_count * pixel_width / 16;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
dma_sample_count = pixel_count * pixel_width / 8;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
switch (dma_display_handle.Init.Desination_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
spi_trans_width = SPI_FRAME_SIZE_32BIT;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
spi_trans_width = SPI_FRAME_SIZE_16BIT;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
spi_trans_width = SPI_FRAME_SIZE_8BIT;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
if (pixel_width != 32) {
|
||||
spi_display_handle.Init.Frame_Size = spi_trans_width;
|
||||
}
|
||||
else {
|
||||
spi_display_handle.Init.Frame_Size = SPI_FRAME_SIZE_24BIT;
|
||||
}
|
||||
spi_display_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_display_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_display_handle.MultWireParam.Instruct = 0x32;
|
||||
spi_display_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_display_handle.MultWireParam.Address = 0x002C00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
__SPI_ENABLE(spi_display_handle.SPIx);
|
||||
spi_master_transmit_X2X4X8_DMA(&spi_display_handle);
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
if ((spi_trans_width == SPI_FRAME_SIZE_32BIT)
|
||||
&& (pixel_width != 32)) {
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_2143);
|
||||
}
|
||||
else {
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
}
|
||||
__SPI_ENABLE(spi_display_handle.SPIx);
|
||||
|
||||
dma_start_IT(&dma_display_handle, (uint32_t)data, (uint32_t)&spi_display_handle.SPIx->DR, dma_sample_count);
|
||||
}
|
||||
|
||||
void icna3310_display_dma_isr(void)
|
||||
{
|
||||
while(__SPI_IS_BUSY(spi_display_handle.SPIx));
|
||||
|
||||
// CS Release
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
/* Clear Transfer complete status */
|
||||
dma_clear_tfr_Status(&dma_display_handle);
|
||||
/* channel Transfer complete interrupt disable */
|
||||
dma_tfr_interrupt_disable(&dma_display_handle);
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_DATA_FRAME_SIZE(spi_display_handle.SPIx, SPI_FRAME_SIZE_8BIT);
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
}
|
||||
16
fr3092_mcu/components/drivers/bsp/display/driver_icna3310.h
Normal file
16
fr3092_mcu/components/drivers/bsp/display/driver_icna3310.h
Normal file
@ -0,0 +1,16 @@
|
||||
#ifndef __DRIVER_ICNA3310_H
|
||||
#define __DRIVER_ICNA3310_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void icna3310_init(void);
|
||||
|
||||
void icna3310_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e);
|
||||
|
||||
void icna3310_display(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
|
||||
void icna3310_display_dma(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
|
||||
void icna3310_display_dma_isr(void);
|
||||
|
||||
#endif // __DRIVER_ICNA3310_H
|
||||
1141
fr3092_mcu/components/drivers/bsp/display/driver_nv3041a.c
Normal file
1141
fr3092_mcu/components/drivers/bsp/display/driver_nv3041a.c
Normal file
File diff suppressed because it is too large
Load Diff
14
fr3092_mcu/components/drivers/bsp/display/driver_nv3041a.h
Normal file
14
fr3092_mcu/components/drivers/bsp/display/driver_nv3041a.h
Normal file
@ -0,0 +1,14 @@
|
||||
#ifndef __DRIVER_NV3041A_H
|
||||
#define __DRIVER_NV3041A_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void nv3041a_init(void);
|
||||
void nv3041a_display_dma_isr(void);
|
||||
void nv3041a_display_dma(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
void nv3041a_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e);
|
||||
void nv3041a_display(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
|
||||
|
||||
|
||||
#endif // __DRIVER_SH8601A_H
|
||||
201
fr3092_mcu/components/drivers/bsp/display/driver_nv3047_rgb.c
Normal file
201
fr3092_mcu/components/drivers/bsp/display/driver_nv3047_rgb.c
Normal file
@ -0,0 +1,201 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file RGB_demo.c
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief RGB interface module Demo.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "driver_nv3047_rgb.h"
|
||||
|
||||
#if (BOARD_SEL == BOARD_EVB_FR3092E_RGB)
|
||||
|
||||
static GPIO_InitTypeDef GPIO_Handle;
|
||||
PARALLEL_HandTypeDef hparallel;
|
||||
SPI_HandleTypeDef spi_handle;
|
||||
DMA_HandleTypeDef dma_handle;
|
||||
DMA_HandleTypeDef dma1_handle;
|
||||
struct_RGB_TypeDef_t rgb_handle;
|
||||
|
||||
unsigned char *coply = NULL;
|
||||
|
||||
void timer0_irq(void);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn rgb_display_controller_init
|
||||
*
|
||||
* @brief rgb_display_controller_init
|
||||
*
|
||||
|
||||
*/
|
||||
void rgb_display_controller_init(void)
|
||||
{
|
||||
/* init parallel CLOCK */
|
||||
__SYSTEM_PARALLEL_CLK_ENABLE();
|
||||
__SYSTEM_PARALLEL_CLK_SELECT_SPLL();
|
||||
__SYSTEM_GPIOA_CLK_ENABLE();
|
||||
__SYSTEM_GPIOB_CLK_ENABLE();
|
||||
__SYSTEM_GPIOC_CLK_ENABLE();
|
||||
__SYSTEM_GPIOD_CLK_ENABLE();
|
||||
__SYSTEM_DMA0_CLK_ENABLE();
|
||||
__SYSTEM_DMA1_CLK_ENABLE();
|
||||
__SYSTEM_TIMER0_CLK_ENABLE();
|
||||
//__SYSTEM_SPI_MASTER1_X8_CLK_ENABLE();
|
||||
__SYSTEM_SPI_MASTER0_X8_CLK_ENABLE();
|
||||
printf("parallel clock:%d\r\n", system_get_peripheral_clock( PER_CLK_PARALLEL));
|
||||
|
||||
/* RGB io init */
|
||||
/*
|
||||
D0~D15 PC0~15
|
||||
DCLK PB13
|
||||
*/
|
||||
GPIO_Handle.Alternate = GPIO_FUNCTION_8;
|
||||
GPIO_Handle.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_DATA_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_DATA_PORT, &GPIO_Handle);
|
||||
|
||||
GPIO_Handle.Alternate = GPIO_FUNCTION_8;
|
||||
GPIO_Handle.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_DCLK_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_DCLK_PORT, &GPIO_Handle);
|
||||
|
||||
GPIO_Handle.Alternate = GPIO_FUNCTION_8;
|
||||
GPIO_Handle.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_VSYNC_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_VSYNC_PORT, &GPIO_Handle);
|
||||
|
||||
GPIO_Handle.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_HSYNC_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_HSYNC_PORT, &GPIO_Handle);
|
||||
|
||||
GPIO_Handle.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_DE_EN_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_DE_EN_PORT, &GPIO_Handle);
|
||||
|
||||
GPIO_Handle.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_RESET_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_RESET_PORT, &GPIO_Handle);
|
||||
|
||||
GPIO_Handle.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Handle.Pin = GPIO_PIN_13;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(GPIOD, &GPIO_Handle);
|
||||
rgb_lcd_reset_release();
|
||||
|
||||
/* backlight */
|
||||
GPIO_Handle.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_BACKLIGHT_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_BACKLIGHT_PORT, &GPIO_Handle);
|
||||
rgb_lcd_backlight_set();
|
||||
rgb_lcd_disp_set();//Display control / standby mode selection. Internal pull low.DISP = “Low” : Standby.DISP = “High” : Normal display.
|
||||
system_delay_us(1000 * 20);
|
||||
|
||||
#ifdef RGB56_LCD_INIT_CONFIG
|
||||
/* SPI CS */
|
||||
GPIO_Handle.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_SPI_CS_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_SPI_CS_PORT, &GPIO_Handle);
|
||||
|
||||
/* SPI io init */
|
||||
// B0,B2 B3
|
||||
GPIO_Handle.Alternate = GPIO_FUNCTION_7;
|
||||
GPIO_Handle.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_Handle.Pin = RGB565_LCD_SPI_CLK_GPIO|RGB565_LCD_SPI_MOSI_GPIO|RGB565_LCD_SPI_MISO_GPIO;
|
||||
GPIO_Handle.Pull = GPIO_PULLUP;
|
||||
gpio_init(RGB565_LCD_SPI_CLK_PORT, &GPIO_Handle);
|
||||
|
||||
/* SPI init */
|
||||
spi_handle.SPIx = SPIMX8_0;
|
||||
spi_handle.Init.Work_Mode = SPI_WORK_MODE_3;
|
||||
spi_handle.Init.Frame_Size = SPI_FRAME_SIZE_9BIT;
|
||||
spi_handle.Init.BaudRate_Prescaler = 100;
|
||||
spi_handle.Init.TxFIFOEmpty_Threshold = 0;
|
||||
spi_handle.Init.RxFIFOFull_Threshold = 0;
|
||||
spi_master_init(&spi_handle);
|
||||
#endif
|
||||
/* PARALLEL Init */
|
||||
hparallel.PARALLELx = PARALLEL0;
|
||||
hparallel.Init.DataBusSelect = DATA_BUS_16_BIT;
|
||||
hparallel.Init.ParallelMode = MODE_6800;
|
||||
hparallel.PARALLELx->DATA_CFG.DATA_TRANS_SEQ_0 = 0;
|
||||
hparallel.PARALLELx->DATA_CFG.DATA_TRANS_SEQ_1 = 1;
|
||||
hparallel.PARALLELx->DATA_CFG.DATA_TRANS_SEQ_2 = 2;
|
||||
hparallel.PARALLELx->DATA_CFG.DATA_TRANS_SEQ_3 = 3;
|
||||
hparallel.Init.ReadClock = WDCLK_DIV_4;
|
||||
hparallel.Init.WriteClock = WDCLK_DIV_2;
|
||||
parallel_init(&hparallel);
|
||||
hparallel.PARALLELx->CRM.WR_L_LEN = 2;
|
||||
hparallel.PARALLELx->CRM.WR_H_LEN = 2;
|
||||
__PARALLEL_CS_SET(hparallel.PARALLELx);
|
||||
|
||||
/* DMA Init */
|
||||
system_dmac_request_id_config(PARALLEL_INTERFACE,DMA0_REQUEST_ID_3);
|
||||
dma_handle.DMAx = DMA0;
|
||||
dma_handle.Channel = DMA_Channel2;
|
||||
dma_handle.Init.Data_Flow = DMA_M2P_DMAC;
|
||||
dma_handle.Init.Request_ID = DMA0_REQUEST_ID_3;
|
||||
dma_handle.Init.Source_Master_Sel = DMA_AHB_MASTER_3;
|
||||
dma_handle.Init.Desination_Master_Sel = DMA_AHB_MASTER_1;
|
||||
dma_handle.Init.Source_Inc = DMA_ADDR_INC_INC;
|
||||
dma_handle.Init.Desination_Inc = DMA_ADDR_INC_NO_CHANGE;
|
||||
dma_handle.Init.Source_Width = DMA_TRANSFER_WIDTH_32;
|
||||
dma_handle.Init.Desination_Width = DMA_TRANSFER_WIDTH_32;
|
||||
dma_handle.Init.Source_Burst_Len = DMA_BURST_LEN_16;
|
||||
dma_handle.Init.Desination_Burst_Len = DMA_BURST_LEN_16;
|
||||
dma_init(&dma_handle);
|
||||
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* @fn rgb_display_init
|
||||
*
|
||||
* @brief rgb_display_init
|
||||
*
|
||||
|
||||
*/
|
||||
void rgb_display_init(void* buffer)
|
||||
{
|
||||
coply = buffer;
|
||||
|
||||
/* rgb init */
|
||||
rgb_init();
|
||||
|
||||
NVIC_ClearPendingIRQ(TIMER0_IRQn);
|
||||
NVIC_EnableIRQ(TIMER0_IRQn);
|
||||
NVIC_ClearPendingIRQ(DMA0_IRQn);
|
||||
NVIC_EnableIRQ(DMA0_IRQn);
|
||||
|
||||
rgb_display_start(Timer0, &rgb_handle, 2, coply);
|
||||
|
||||
printf("%s:%d\r\n", __func__, __LINE__);
|
||||
}
|
||||
|
||||
void timer0_irq(void)
|
||||
{
|
||||
rgb_timer_IRQHandler(Timer0, &rgb_handle);
|
||||
}
|
||||
|
||||
__RAM_CODE void rgb_display_dma_irq(void)
|
||||
{
|
||||
if (dma_get_tfr_Status(&dma_handle))
|
||||
{
|
||||
rgb_dma_IRQHandler(&rgb_handle);
|
||||
dma_clear_tfr_Status(&dma_handle);
|
||||
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -0,0 +1,91 @@
|
||||
|
||||
#ifndef __DRIVER_NV3047_RGB_H__
|
||||
#define __DRIVER_NV3047_RGB_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
#include "app_config.h"
|
||||
#include "rgb565.h"
|
||||
|
||||
#define RGB_ROW 480
|
||||
#define RGB_COLUMN 272
|
||||
|
||||
#define RGB565_LCD_DCLK_PORT GPIOB
|
||||
#define RGB565_LCD_DCLK_GPIO GPIO_PIN_14
|
||||
|
||||
#define RGB565_LCD_VSYNC_PORT GPIOB
|
||||
#define RGB565_LCD_VSYNC_GPIO GPIO_PIN_13
|
||||
|
||||
#define RGB565_LCD_HSYNC_PORT GPIOB
|
||||
#define RGB565_LCD_HSYNC_GPIO GPIO_PIN_15
|
||||
|
||||
#define RGB565_LCD_DISP_PORT GPIOD
|
||||
#define RGB565_LCD_DISP_GPIO GPIO_PIN_12
|
||||
|
||||
#define RGB565_LCD_DE_EN_PORT GPIOB
|
||||
#define RGB565_LCD_DE_EN_GPIO GPIO_PIN_12
|
||||
|
||||
#define RGB565_LCD_DATA_PORT GPIOC
|
||||
#define RGB565_LCD_DATA_GPIO 0xFFFF //GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7
|
||||
|
||||
#define RGB565_LCD_RESET_PORT GPIOA
|
||||
#define RGB565_LCD_RESET_GPIO GPIO_PIN_4
|
||||
|
||||
#define RGB565_LCD_BACKLIGHT_PORT GPIOA
|
||||
#define RGB565_LCD_BACKLIGHT_GPIO GPIO_PIN_4
|
||||
#define RGB565_LCD_SPI_SEL SPIM0
|
||||
|
||||
#ifdef RGB565_LCD_TE_EN
|
||||
#define RGB565_LCD_TE_PORT GPIO_B
|
||||
#define RGB565_LCD_TE_GPIO GPIO_PIN_7
|
||||
#endif
|
||||
|
||||
//#define RGB56_LCD_INIT_CONFIG
|
||||
|
||||
#ifdef RGB56_LCD_INIT_CONFIG
|
||||
#define RGB565_LCD_SPI_CS_PORT GPIOD
|
||||
#define RGB565_LCD_SPI_CS_GPIO GPIO_PIN_12
|
||||
|
||||
#define RGB565_LCD_SPI_CLK_PORT GPIOB
|
||||
#define RGB565_LCD_SPI_CLK_GPIO GPIO_PIN_0
|
||||
|
||||
#define RGB565_LCD_SPI_MOSI_PORT GPIOB
|
||||
#define RGB565_LCD_SPI_MOSI_GPIO GPIO_PIN_2
|
||||
|
||||
#define RGB565_LCD_SPI_MISO_PORT GPIOB
|
||||
#define RGB565_LCD_SPI_MISO_GPIO GPIO_PIN_3
|
||||
|
||||
#define rgb_spi_cs_set() gpio_write_pin(RGB565_LCD_SPI_CS_PORT,RGB565_LCD_SPI_CS_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_spi_cs_release() gpio_write_pin(RGB565_LCD_SPI_CS_PORT,RGB565_LCD_SPI_CS_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#endif
|
||||
|
||||
/* signal drive*/
|
||||
#define rgb_lcd_enable_set() gpio_write_pin(RGB565_LCD_DE_EN_PORT,RGB565_LCD_DE_EN_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_enable_release() gpio_write_pin(RGB565_LCD_DE_EN_PORT,RGB565_LCD_DE_EN_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_vsync_set() gpio_write_pin(RGB565_LCD_VSYNC_PORT,RGB565_LCD_VSYNC_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_vsync_release() gpio_write_pin(RGB565_LCD_VSYNC_PORT,RGB565_LCD_VSYNC_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_hsync_set() gpio_write_pin(RGB565_LCD_HSYNC_PORT,RGB565_LCD_HSYNC_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_hsync_release() gpio_write_pin(RGB565_LCD_HSYNC_PORT,RGB565_LCD_HSYNC_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_reset_set() gpio_write_pin(RGB565_LCD_RESET_PORT,RGB565_LCD_RESET_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_reset_release() gpio_write_pin(RGB565_LCD_RESET_PORT,RGB565_LCD_RESET_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_disp_set() gpio_write_pin(RGB565_LCD_DISP_PORT,RGB565_LCD_DISP_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_disp_release() gpio_write_pin(RGB565_LCD_DISP_PORT,RGB565_LCD_DISP_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_backlight_set() gpio_write_pin(RGB565_LCD_BACKLIGHT_PORT,RGB565_LCD_BACKLIGHT_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_backlight_release() gpio_write_pin(RGB565_LCD_BACKLIGHT_PORT,RGB565_LCD_BACKLIGHT_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* rgb_demo */
|
||||
void rgb_display_init(void* buffer);
|
||||
void rgb_display_controller_init(void);
|
||||
|
||||
|
||||
__RAM_CODE void rgb_display_dma_irq(void);
|
||||
|
||||
|
||||
#endif
|
||||
526
fr3092_mcu/components/drivers/bsp/display/driver_sh8601a.c
Normal file
526
fr3092_mcu/components/drivers/bsp/display/driver_sh8601a.c
Normal file
@ -0,0 +1,526 @@
|
||||
#include "driver_display.h"
|
||||
#include "driver_sh8601a.h"
|
||||
|
||||
#define SH8601A_MAX_PARA_COUNT (300)
|
||||
|
||||
#define SH8601A_QSPI_INST_CMD_WRITE (0x02)
|
||||
#define SH8601A_QSPI_INST_CMD_READ (0x03)
|
||||
#define SH8601A_QSPI_INST_1WIRE_PIXEL_WRITE (0x02)
|
||||
#define SH8601A_QSPI_INST_4WIRE_PIXEL_WRITE_TYPE1 (0x32)
|
||||
#define SH8601A_QSPI_INST_4WIRE_PIXEL_WRITE_TYPE2 (0x12)
|
||||
#define SH8601A_QSPI_SEQ_FINISH_CODE (0x00)
|
||||
|
||||
typedef struct _SH8601A_CMD_DESC {
|
||||
uint8_t instruction;
|
||||
uint8_t index;
|
||||
uint16_t delay;
|
||||
uint16_t wordcount;
|
||||
uint8_t payload[SH8601A_MAX_PARA_COUNT];
|
||||
} SH8601A_CMD_DESC;
|
||||
|
||||
const SH8601A_CMD_DESC SH8601A_PRE_OTP_POWERON_SEQ_CMD[] = {
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0x5A, 0x5A}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0x5A, 0x5A}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xE4, 1, 1, {0x01}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x90, 1, 6, {0x33, 0x00, 0xC6, 0x01, 0xC6, 0x01}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x91, 1, 20, {0x65, 0x00, 0x00, 0xE2, 0x00, 0x00, 0x00, 0xE2, 0x00, 0xE2, 0x00, 0xE2, 0x00, 0xE2, 0x00, 0x03, 0x00, 0x00, 0xFF, 0x11}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x92, 1, 20, {0x61, 0xE3, 0x00, 0xC5, 0x01, 0x00, 0x00, 0xE2, 0x00, 0xE3, 0x00, 0xE2, 0x00, 0xE2, 0x00, 0x03, 0x00, 0x00, 0xFF, 0x22}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x93, 1, 20, {0x69, 0x00, 0x00, 0xE2, 0x00, 0xE3, 0x00, 0xC5, 0x01, 0xE2, 0x00, 0xE3, 0x00, 0xE2, 0x00, 0x03, 0x00, 0x00, 0xFF, 0x33}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x94, 1, 20, {0x6D, 0xE3, 0x00, 0xC5, 0x01, 0xE3, 0x00, 0xC5, 0x01, 0xE3, 0x00, 0xE3, 0x00, 0xE2, 0x00, 0x03, 0x00, 0x00, 0xFF, 0x33}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x9D, 1, 168, {0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x06, 0x0C, 0x12, 0x18, 0x1E, 0x24, 0x2A, 0x30, 0x36, 0x3C, 0x42, 0x48, 0x4E, 0x54, 0x5A, 0x60, 0x09, 0x0D, 0x12, 0x16, 0x1B, 0x24, 0x2D, 0x36, 0x3F, 0x5A, 0x63, 0x6C, 0x75, 0x7E, 0x87, 0x90, 0x05, 0x0A, 0x0F, 0x14, 0x19, 0x1E, 0x23, 0x28, 0x2D, 0x32, 0x37, 0x3C, 0x41, 0x46, 0x4B, 0x50, 0x0F, 0x1E, 0x2D, 0x3C, 0x4B, 0x5A, 0x69, 0x78, 0x87, 0x96, 0xA5, 0xB4, 0xC3, 0xD2, 0xE1, 0xF5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x80, 0x60, 0x40, 0x20, 0x00, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x9E, 1, 12, {0x3B, 0x00, 0x71, 0x00, 0xA3, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 51, {0x00, 0xC6, 0x01, 0xC6, 0x01, 0x05, 0x00, 0x05, 0x00, 0xA7, 0x00, 0xA7, 0x00, 0x05, 0x00, 0x05, 0x00, 0xA7, 0x00, 0xA7, 0x00, 0x00, 0x52, 0x00, 0x64, 0x00, 0x8A, 0x00, 0xB0, 0x00, 0x52, 0x00, 0x64, 0x00, 0x8A, 0x00, 0xB0, 0x00, 0x00, 0x10, 0x00, 0x00, 0xDF, 0x01, 0x00, 0x00, 0xDF, 0x01, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB2, 1, 68, {0x19, 0x14, 0x19, 0x14, 0x01, 0xEE, 0x02, 0x30, 0x02, 0xE4, 0x02, 0x3F, 0x02, 0x06, 0x76, 0x78, 0xE8, 0x04, 0x06, 0x00, 0x00, 0x31, 0x16, 0x15, 0x3D, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5, 0x10, 0xFF, 0xFF, 0xE0, 0xAA, 0xAA, 0xFF, 0xFF, 0x24, 0x14, 0x04, 0x14, 0x13, 0x14, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB3, 1, 44, {0x00, 0x0D, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x1F, 0x02, 0x00, 0x0B, 0x00, 0x0C, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x00, 0x06, 0x13, 0x04, 0x00, 0x08, 0x15, 0x09, 0x00, 0x07}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB4, 1, 65, {0x09, 0x02, 0x00, 0x00, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x40, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x03, 0x47, 0x8B, 0x30, 0x74, 0xB8, 0x12, 0x56, 0x9A, 0x21, 0x65, 0xA9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x56, 0x9A, 0x21, 0x65, 0xA9, 0x03, 0x47, 0x8B, 0x30, 0x74, 0xB8, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB5, 1, 58, {0x4C, 0x09, 0x09, 0x09, 0x49, 0x40, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x21, 0x00, 0x14, 0x03, 0x21, 0x00, 0x14, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x03, 0x02, 0x52, 0x00, 0x21, 0x00, 0x21, 0x00, 0x14, 0x03, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x14, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB6, 1, 26, {0x00, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x40, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB7, 1, 51, {0x0C, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x21, 0x00, 0x14, 0x03, 0x21, 0x00, 0x14, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x03, 0x02, 0x52, 0x00, 0x21, 0x00, 0x21, 0x00, 0x14, 0x03, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x14, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB8, 1, 95, {0x00, 0x67, 0x31, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x00, 0x22, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x00, 0x22, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xBB, 1, 19, {0x01, 0x02, 0x07, 0x01, 0x46, 0x46, 0x46, 0xD9, 0x00, 0xAA, 0x00, 0x7D, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xBD, 1, 22, {0x01, 0x00, 0x00, 0x64, 0x00, 0x62, 0x00, 0x04, 0x01, 0x15, 0x00, 0x00, 0x00, 0x00, 0x1D, 0x05, 0x00, 0x10, 0x16, 0x16, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xBE, 1, 106, {0x4B, 0x00, 0x69, 0x00, 0x87, 0x00, 0xA5, 0x00, 0xC3, 0x00, 0xE1, 0x00, 0xFF, 0x00, 0x7F, 0x00, 0xFF, 0x00, 0x64, 0x00, 0xAA, 0x00, 0x19, 0x00, 0x32, 0x00, 0x4B, 0x00, 0x4B, 0x00, 0x4B, 0x00, 0x4B, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x01, 0x01, 0x15, 0x00, 0x00, 0x00, 0x00, 0x8A, 0x00, 0x26, 0x01, 0xD0, 0x01, 0xD0, 0x01, 0xD0, 0x01, 0xD0, 0x01, 0xD0, 0x01, 0xD0, 0x01, 0x1C, 0x00, 0x64, 0x00, 0x00, 0x00, 0x89, 0x00, 0xD0, 0x01, 0xD0, 0x01, 0x4B, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xBF, 1, 35, {0x03, 0xF0, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC2, 1, 136, {0x00, 0x00, 0x84, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDD, 0x00, 0x97, 0x00, 0x83, 0x00, 0xEE, 0x00, 0xA8, 0x00, 0x94, 0x00, 0x16, 0x01, 0xCF, 0x00, 0xBC, 0x00, 0x3B, 0x01, 0xF4, 0x00, 0xE1, 0x00, 0x61, 0x01, 0x12, 0x01, 0x08, 0x01, 0x94, 0x01, 0x46, 0x01, 0x41, 0x01, 0xB7, 0x01, 0x6D, 0x01, 0x6B, 0x01, 0xDE, 0x01, 0x93, 0x01, 0x9C, 0x01, 0xF7, 0x01, 0xAF, 0x01, 0xBB, 0x01, 0x27, 0x02, 0xE1, 0x01, 0xFC, 0x01, 0x52, 0x02, 0x0F, 0x02, 0x34, 0x02, 0x77, 0x02, 0x36, 0x02, 0x65, 0x02, 0xBE, 0x02, 0x7C, 0x02, 0xB9, 0x02, 0xFA, 0x02, 0xBA, 0x02, 0x08, 0x03, 0x31, 0x03, 0xF4, 0x02, 0x4F, 0x03, 0x63, 0x03, 0x29, 0x03, 0x8C, 0x03, 0x9E, 0x03, 0x5F, 0x03, 0xD1, 0x03, 0xFD, 0x03, 0xBC, 0x03, 0x4A, 0x04, 0x6E, 0x04, 0x28, 0x04, 0xC4, 0x04, 0xD1, 0x04, 0x91, 0x04, 0x49, 0x05, 0x3D, 0x05, 0xF1, 0x04, 0xC1, 0x05}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC3, 1, 136, {0x00, 0x00, 0xFF, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDD, 0x00, 0x97, 0x00, 0x83, 0x00, 0xEE, 0x00, 0xA8, 0x00, 0x94, 0x00, 0x16, 0x01, 0xCF, 0x00, 0xBC, 0x00, 0x3B, 0x01, 0xF4, 0x00, 0xE1, 0x00, 0x61, 0x01, 0x12, 0x01, 0x08, 0x01, 0x94, 0x01, 0x46, 0x01, 0x41, 0x01, 0xB7, 0x01, 0x6D, 0x01, 0x6B, 0x01, 0xDE, 0x01, 0x93, 0x01, 0x9C, 0x01, 0xF7, 0x01, 0xAF, 0x01, 0xBB, 0x01, 0x27, 0x02, 0xE1, 0x01, 0xFC, 0x01, 0x52, 0x02, 0x0F, 0x02, 0x34, 0x02, 0x77, 0x02, 0x36, 0x02, 0x65, 0x02, 0xBE, 0x02, 0x7C, 0x02, 0xB9, 0x02, 0xFA, 0x02, 0xBA, 0x02, 0x08, 0x03, 0x31, 0x03, 0xF4, 0x02, 0x4F, 0x03, 0x63, 0x03, 0x29, 0x03, 0x8C, 0x03, 0x9E, 0x03, 0x5F, 0x03, 0xD1, 0x03, 0xFD, 0x03, 0xBC, 0x03, 0x4A, 0x04, 0x6E, 0x04, 0x28, 0x04, 0xC4, 0x04, 0xD1, 0x04, 0x91, 0x04, 0x49, 0x05, 0x3D, 0x05, 0xF1, 0x04, 0xC1, 0x05}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC5, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x00, 0x37, 0x00, 0x32, 0x00, 0x24, 0x01, 0xBD, 0x00, 0xAC, 0x00, 0x3D, 0x01, 0xD6, 0x00, 0xC5, 0x00, 0x50, 0x01, 0xE9, 0x00, 0xD8, 0x00, 0x66, 0x01, 0xFF, 0x00, 0xEE, 0x00, 0x95, 0x01, 0x2E, 0x01, 0x1E, 0x01, 0xB8, 0x01, 0x50, 0x01, 0x44, 0x01, 0xDB, 0x01, 0x73, 0x01, 0x68, 0x01, 0xF5, 0x01, 0x8E, 0x01, 0x84, 0x01, 0x21, 0x02, 0xBE, 0x01, 0xBA, 0x01, 0x4B, 0x02, 0xEB, 0x01, 0xEE, 0x01, 0x6B, 0x02, 0x0E, 0x02, 0x18, 0x02, 0xA9, 0x02, 0x51, 0x02, 0x6C, 0x02, 0xE2, 0x02, 0x8B, 0x02, 0xB2, 0x02, 0x0B, 0x03, 0xB7, 0x02, 0xE7, 0x02, 0x34, 0x03, 0xE5, 0x02, 0x1F, 0x03, 0x57, 0x03, 0x0A, 0x03, 0x4B, 0x03, 0xA3, 0x03, 0x52, 0x03, 0xA9, 0x03, 0xEB, 0x03, 0x9A, 0x03, 0x00, 0x04, 0x2F, 0x04, 0xDC, 0x03, 0x5A, 0x04, 0x64, 0x04, 0x14, 0x04, 0x9E, 0x04}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC6, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x4D, 0x00, 0x46, 0x00, 0x28, 0x01, 0xC1, 0x00, 0xB0, 0x00, 0x42, 0x01, 0xDB, 0x00, 0xCA, 0x00, 0x5C, 0x01, 0xF5, 0x00, 0xE4, 0x00, 0x77, 0x01, 0x10, 0x01, 0xFF, 0x00, 0xA9, 0x01, 0x42, 0x01, 0x35, 0x01, 0xCE, 0x01, 0x67, 0x01, 0x5B, 0x01, 0xF1, 0x01, 0x8A, 0x01, 0x80, 0x01, 0x0C, 0x02, 0xA7, 0x01, 0xA0, 0x01, 0x3D, 0x02, 0xDD, 0x01, 0xDD, 0x01, 0x66, 0x02, 0x08, 0x02, 0x11, 0x02, 0x8C, 0x02, 0x33, 0x02, 0x45, 0x02, 0xD0, 0x02, 0x79, 0x02, 0x9D, 0x02, 0x04, 0x03, 0xB0, 0x02, 0xDE, 0x02, 0x33, 0x03, 0xE5, 0x02, 0x1F, 0x03, 0x5D, 0x03, 0x11, 0x03, 0x53, 0x03, 0x89, 0x03, 0x3C, 0x03, 0x8A, 0x03, 0xDE, 0x03, 0x8D, 0x03, 0xF1, 0x03, 0x2F, 0x04, 0xDC, 0x03, 0x59, 0x04, 0x6F, 0x04, 0x20, 0x04, 0xAC, 0x04, 0xB3, 0x04, 0x64, 0x04, 0xFF, 0x04}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC7, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9A, 0x00, 0x63, 0x00, 0x5A, 0x00, 0x2C, 0x01, 0xC5, 0x00, 0xB4, 0x00, 0x48, 0x01, 0xE1, 0x00, 0xD0, 0x00, 0x65, 0x01, 0xFE, 0x00, 0xED, 0x00, 0x87, 0x01, 0x20, 0x01, 0x0F, 0x01, 0xB5, 0x01, 0x4E, 0x01, 0x41, 0x01, 0xE5, 0x01, 0x7D, 0x01, 0x72, 0x01, 0x01, 0x02, 0x9B, 0x01, 0x93, 0x01, 0x1D, 0x02, 0xBA, 0x01, 0xB6, 0x01, 0x55, 0x02, 0xF5, 0x01, 0xFB, 0x01, 0x7C, 0x02, 0x21, 0x02, 0x2F, 0x02, 0xA4, 0x02, 0x4C, 0x02, 0x65, 0x02, 0xF0, 0x02, 0x99, 0x02, 0xC1, 0x02, 0x20, 0x03, 0xCE, 0x02, 0x04, 0x03, 0x51, 0x03, 0x04, 0x03, 0x44, 0x03, 0x83, 0x03, 0x36, 0x03, 0x82, 0x03, 0xB5, 0x03, 0x62, 0x03, 0xBF, 0x03, 0x0F, 0x04, 0xBD, 0x03, 0x2F, 0x04, 0x5C, 0x04, 0x0C, 0x04, 0x94, 0x04, 0xAB, 0x04, 0x5C, 0x04, 0xF5, 0x04, 0xFA, 0x04, 0xA8, 0x04, 0x50, 0x05}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC8, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBC, 0x00, 0x79, 0x00, 0x6E, 0x00, 0x2F, 0x01, 0xC8, 0x00, 0xB7, 0x00, 0x4D, 0x01, 0xE6, 0x00, 0xD5, 0x00, 0x6D, 0x01, 0x06, 0x01, 0xF5, 0x00, 0x8F, 0x01, 0x28, 0x01, 0x18, 0x01, 0xC1, 0x01, 0x5A, 0x01, 0x4E, 0x01, 0xEF, 0x01, 0x87, 0x01, 0x7D, 0x01, 0x0F, 0x02, 0xAB, 0x01, 0xA4, 0x01, 0x2F, 0x02, 0xCD, 0x01, 0xCB, 0x01, 0x63, 0x02, 0x04, 0x02, 0x0D, 0x02, 0x91, 0x02, 0x38, 0x02, 0x4A, 0x02, 0xBC, 0x02, 0x65, 0x02, 0x86, 0x02, 0x01, 0x03, 0xAC, 0x02, 0xD9, 0x02, 0x39, 0x03, 0xEA, 0x02, 0x25, 0x03, 0x6E, 0x03, 0x23, 0x03, 0x69, 0x03, 0xA4, 0x03, 0x53, 0x03, 0xAA, 0x03, 0xD7, 0x03, 0x85, 0x03, 0xE8, 0x03, 0x37, 0x04, 0xE5, 0x03, 0x64, 0x04, 0x8A, 0x04, 0x3C, 0x04, 0xCF, 0x04, 0xE0, 0x04, 0x8F, 0x04, 0x32, 0x05, 0x30, 0x05, 0xDF, 0x04, 0x92, 0x05}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC9, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDE, 0x00, 0x8F, 0x00, 0x82, 0x00, 0x33, 0x01, 0xCC, 0x00, 0xBB, 0x00, 0x52, 0x01, 0xEB, 0x00, 0xDA, 0x00, 0x76, 0x01, 0x0F, 0x01, 0xFE, 0x00, 0x98, 0x01, 0x31, 0x01, 0x22, 0x01, 0xCD, 0x01, 0x65, 0x01, 0x5A, 0x01, 0xF8, 0x01, 0x92, 0x01, 0x89, 0x01, 0x1B, 0x02, 0xB8, 0x01, 0xB2, 0x01, 0x3C, 0x02, 0xDB, 0x01, 0xDC, 0x01, 0x70, 0x02, 0x14, 0x02, 0x1F, 0x02, 0xA1, 0x02, 0x49, 0x02, 0x60, 0x02, 0xCF, 0x02, 0x78, 0x02, 0x9C, 0x02, 0x11, 0x03, 0xBE, 0x02, 0xF0, 0x02, 0x4D, 0x03, 0xFF, 0x02, 0x3E, 0x03, 0x87, 0x03, 0x3A, 0x03, 0x87, 0x03, 0xC1, 0x03, 0x6E, 0x03, 0xCD, 0x03, 0xF7, 0x03, 0xA6, 0x03, 0x10, 0x04, 0x56, 0x04, 0x05, 0x04, 0x8B, 0x04, 0xB2, 0x04, 0x63, 0x04, 0xFD, 0x04, 0x10, 0x05, 0xBE, 0x04, 0x6A, 0x05, 0x64, 0x05, 0x14, 0x05, 0xD2, 0x05}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xCA, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0x00, 0x96, 0x00, 0x36, 0x01, 0xCF, 0x00, 0xBE, 0x00, 0x57, 0x01, 0xF0, 0x00, 0xDF, 0x00, 0x7E, 0x01, 0x17, 0x01, 0x06, 0x01, 0xA0, 0x01, 0x39, 0x01, 0x2B, 0x01, 0xD9, 0x01, 0x71, 0x01, 0x66, 0x01, 0x02, 0x02, 0x9C, 0x01, 0x94, 0x01, 0x26, 0x02, 0xC4, 0x01, 0xC1, 0x01, 0x49, 0x02, 0xE8, 0x01, 0xEB, 0x01, 0x7E, 0x02, 0x23, 0x02, 0x32, 0x02, 0xB1, 0x02, 0x59, 0x02, 0x76, 0x02, 0xDF, 0x02, 0x88, 0x02, 0xAF, 0x02, 0x22, 0x03, 0xD1, 0x02, 0x07, 0x03, 0x60, 0x03, 0x14, 0x03, 0x57, 0x03, 0x9F, 0x03, 0x4E, 0x03, 0xA4, 0x03, 0xDA, 0x03, 0x88, 0x03, 0xEC, 0x03, 0x13, 0x04, 0xC1, 0x03, 0x34, 0x04, 0x74, 0x04, 0x25, 0x04, 0xB3, 0x04, 0xD8, 0x04, 0x87, 0x04, 0x29, 0x05, 0x37, 0x05, 0xE7, 0x04, 0x9B, 0x05, 0x95, 0x05, 0x41, 0x05, 0x0B, 0x06}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xCB, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x01, 0xBB, 0x00, 0xAA, 0x00, 0x3A, 0x01, 0xD3, 0x00, 0xC2, 0x00, 0x5C, 0x01, 0xF5, 0x00, 0xE4, 0x00, 0x87, 0x01, 0x20, 0x01, 0x0F, 0x01, 0xA9, 0x01, 0x42, 0x01, 0x35, 0x01, 0xE5, 0x01, 0x7D, 0x01, 0x72, 0x01, 0x0C, 0x02, 0xA7, 0x01, 0xA0, 0x01, 0x32, 0x02, 0xD1, 0x01, 0xCF, 0x01, 0x55, 0x02, 0xF5, 0x01, 0xFB, 0x01, 0x8C, 0x02, 0x33, 0x02, 0x44, 0x02, 0xC1, 0x02, 0x6A, 0x02, 0x8C, 0x02, 0xF0, 0x02, 0x99, 0x02, 0xC2, 0x02, 0x33, 0x03, 0xE4, 0x02, 0x1E, 0x03, 0x74, 0x03, 0x29, 0x03, 0x70, 0x03, 0xB6, 0x03, 0x63, 0x03, 0xC0, 0x03, 0xF3, 0x03, 0xA2, 0x03, 0x0A, 0x04, 0x2E, 0x04, 0xDB, 0x03, 0x58, 0x04, 0x93, 0x04, 0x45, 0x04, 0xDA, 0x04, 0xFE, 0x04, 0xAC, 0x04, 0x54, 0x05, 0x5F, 0x05, 0x0F, 0x05, 0xCC, 0x05, 0xC5, 0x05, 0x6E, 0x05, 0x43, 0x06}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xCC, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x00, 0x49, 0x00, 0x43, 0x00, 0x27, 0x01, 0xC0, 0x00, 0xAF, 0x00, 0x42, 0x01, 0xDB, 0x00, 0xCA, 0x00, 0x5A, 0x01, 0xF3, 0x00, 0xE2, 0x00, 0x74, 0x01, 0x0D, 0x01, 0xFC, 0x00, 0xA6, 0x01, 0x3F, 0x01, 0x32, 0x01, 0xCA, 0x01, 0x63, 0x01, 0x57, 0x01, 0xEE, 0x01, 0x87, 0x01, 0x7D, 0x01, 0x08, 0x02, 0xA3, 0x01, 0x9C, 0x01, 0x39, 0x02, 0xD9, 0x01, 0xD8, 0x01, 0x62, 0x02, 0x03, 0x02, 0x0C, 0x02, 0x87, 0x02, 0x2D, 0x02, 0x3D, 0x02, 0xCB, 0x02, 0x74, 0x02, 0x97, 0x02, 0x00, 0x03, 0xAB, 0x02, 0xD8, 0x02, 0x2D, 0x03, 0xDD, 0x02, 0x16, 0x03, 0x56, 0x03, 0x09, 0x03, 0x4A, 0x03, 0x82, 0x03, 0x35, 0x03, 0x81, 0x03, 0xD5, 0x03, 0x83, 0x03, 0xE6, 0x03, 0x24, 0x04, 0xD1, 0x03, 0x4B, 0x04, 0x65, 0x04, 0x14, 0x04, 0x9E, 0x04, 0xA7, 0x04, 0x58, 0x04, 0xF1, 0x04}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xCD, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC1, 0x00, 0x7D, 0x00, 0x71, 0x00, 0x30, 0x01, 0xC9, 0x00, 0xB8, 0x00, 0x4E, 0x01, 0xE7, 0x00, 0xD6, 0x00, 0x6F, 0x01, 0x08, 0x01, 0xF7, 0x00, 0x91, 0x01, 0x2A, 0x01, 0x1A, 0x01, 0xC3, 0x01, 0x5C, 0x01, 0x50, 0x01, 0xF0, 0x01, 0x89, 0x01, 0x7F, 0x01, 0x11, 0x02, 0xAD, 0x01, 0xA7, 0x01, 0x32, 0x02, 0xD1, 0x01, 0xCE, 0x01, 0x65, 0x02, 0x07, 0x02, 0x10, 0x02, 0x93, 0x02, 0x3B, 0x02, 0x4E, 0x02, 0xC0, 0x02, 0x69, 0x02, 0x8B, 0x02, 0x03, 0x03, 0xAF, 0x02, 0xDD, 0x02, 0x3C, 0x03, 0xEE, 0x02, 0x2A, 0x03, 0x73, 0x03, 0x28, 0x03, 0x6F, 0x03, 0xA9, 0x03, 0x58, 0x03, 0xB0, 0x03, 0xDD, 0x03, 0x8B, 0x03, 0xEF, 0x03, 0x3C, 0x04, 0xEA, 0x03, 0x6A, 0x04, 0x92, 0x04, 0x44, 0x04, 0xD9, 0x04, 0xE9, 0x04, 0x98, 0x04, 0x3C, 0x05, 0x39, 0x05, 0xE8, 0x04, 0x9D, 0x05}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xCE, 1, 136, {0x00, 0x00, 0x6A, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x01, 0xBB, 0x00, 0xAA, 0x00, 0x3A, 0x01, 0xD3, 0x00, 0xC2, 0x00, 0x5C, 0x01, 0xF5, 0x00, 0xE4, 0x00, 0x87, 0x01, 0x20, 0x01, 0x0F, 0x01, 0xA9, 0x01, 0x42, 0x01, 0x35, 0x01, 0xE5, 0x01, 0x7D, 0x01, 0x72, 0x01, 0x0C, 0x02, 0xA7, 0x01, 0xA0, 0x01, 0x32, 0x02, 0xD1, 0x01, 0xCF, 0x01, 0x55, 0x02, 0xF5, 0x01, 0xFB, 0x01, 0x8C, 0x02, 0x33, 0x02, 0x44, 0x02, 0xC1, 0x02, 0x6A, 0x02, 0x8C, 0x02, 0xF0, 0x02, 0x99, 0x02, 0xC2, 0x02, 0x33, 0x03, 0xE4, 0x02, 0x1E, 0x03, 0x74, 0x03, 0x29, 0x03, 0x70, 0x03, 0xB6, 0x03, 0x63, 0x03, 0xC0, 0x03, 0xF3, 0x03, 0xA2, 0x03, 0x0A, 0x04, 0x2E, 0x04, 0xDB, 0x03, 0x58, 0x04, 0x93, 0x04, 0x45, 0x04, 0xDA, 0x04, 0xFE, 0x04, 0xAC, 0x04, 0x54, 0x05, 0x5F, 0x05, 0x0F, 0x05, 0xCC, 0x05, 0xC5, 0x05, 0x6E, 0x05, 0x43, 0x06}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xD3, 1, 11, {0x11, 0xC6, 0x01, 0xC6, 0x01, 0x08, 0x08, 0x14, 0x14, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xD4, 1, 54, {0x02, 0x00, 0x2c, 0x00, 0x19, 0x00, 0x06, 0x00, 0x6c, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x19, 0x00, 0x2c, 0x00, 0x02, 0x00, 0x3b, 0x00, 0x6c, 0x00, 0x06, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x07, 0x00, 0x03, 0x00, 0x1e, 0x00, 0x7e, 0x00, 0x1e, 0x00, 0x08, 0x00, 0x29, 0x00, 0x08, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xD5, 1, 54, {0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x06, 0x00, 0x6c, 0x00, 0x3b, 0x00, 0x02, 0x00, 0x2c, 0x00, 0x19, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x6c, 0x00, 0x06, 0x00, 0x19, 0x00, 0x2c, 0x00, 0x02, 0x00, 0x08, 0x00, 0x29, 0x00, 0x08, 0x00, 0x1e, 0x00, 0x7e, 0x00, 0x1e, 0x00, 0x03, 0x00, 0x07, 0x00, 0x03, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xD6, 1, 54, {0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x06, 0x00, 0x6c, 0x00, 0x3b, 0x00, 0x02, 0x00, 0x2c, 0x00, 0x19, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x6c, 0x00, 0x06, 0x00, 0x19, 0x00, 0x2c, 0x00, 0x02, 0x00, 0x08, 0x00, 0x29, 0x00, 0x08, 0x00, 0x1e, 0x00, 0x7e, 0x00, 0x1e, 0x00, 0x03, 0x00, 0x07, 0x00, 0x03, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xD7, 1, 54, {0x02, 0x00, 0x2c, 0x00, 0x19, 0x00, 0x06, 0x00, 0x6c, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x19, 0x00, 0x2c, 0x00, 0x02, 0x00, 0x3b, 0x00, 0x6c, 0x00, 0x06, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x07, 0x00, 0x03, 0x00, 0x1e, 0x00, 0x7e, 0x00, 0x1e, 0x00, 0x08, 0x00, 0x29, 0x00, 0x08, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xDF, 1, 19, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xEE, 1, 44, {0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF0, 1, 24, {0x10, 0x79, 0x77, 0x22, 0x4A, 0x25, 0x1C, 0x19, 0x00, 0x10, 0x0F, 0x11, 0x38, 0xAA, 0x20, 0x20, 0x2A, 0x22, 0x2A, 0xCA, 0x88, 0x10, 0x10, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF1, 1, 25, {0x10, 0x09, 0x03, 0x00, 0x4A, 0x25, 0x1C, 0x19, 0x00, 0x10, 0x0F, 0x00, 0x30, 0xAA, 0x20, 0x20, 0x2F, 0x23, 0x2F, 0x22, 0x2E, 0xCF, 0x88, 0x10, 0x10}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF1, 1, 25, {0x10, 0x09, 0x03, 0x00, 0x4A, 0x25, 0x1C, 0x19, 0x00, 0x10, 0x0F, 0x11, 0x30, 0xAA, 0x10, 0x10, 0x26, 0x20, 0x25, 0x12, 0x16, 0xC5, 0x88, 0x10, 0x01}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF2, 1, 34, {0xFF, 0x53, 0x00, 0x11, 0x19, 0x0A, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x00, 0x01, 0x01, 0xFF, 0x53, 0x10, 0x11, 0x19, 0x0A, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x01, 0x01, 0x01}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF3, 1, 36, {0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x08, 0x08, 0x02, 0x03, 0x02, 0x02, 0x03, 0x01, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF4, 1, 21, {0x99, 0x99, 0x99, 0x88, 0x88, 0x77, 0x66, 0x55, 0x55, 0x55, 0x55, 0x55, 0x44, 0x94, 0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF5, 1, 21, {0x66, 0x66, 0x56, 0x55, 0x45, 0x44, 0x33, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x62, 0x02, 0x02, 0x02, 0x00, 0x01, 0x01, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xF8, 1, 16, {0x03, 0x22, 0x22, 0x77, 0x37, 0x00, 0x10, 0x10, 0x26, 0x20, 0x25, 0x12, 0x14, 0x05, 0x66, 0x66}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xD1}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x4A, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x63, 1, 1, {0xFF}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x53, 1, 1, {0x28}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC4, 50, 1, {0x84}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x3A, 1, 1, {0x05}}, // 16bits pixel
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xBA, 1, 1, {0x81}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 1, {0xC0}},
|
||||
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
const SH8601A_CMD_DESC SH8601A_POST_OTP_POWERON_SEQ_CMD[] = {
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xC2}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x4A, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x63, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x53, 1, 1, {0x28}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC4, 25, 1, {0x84}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
// {SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0x5A, 0x5A}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0x5A, 0x5A}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 51, {0xC0, 0xC6, 0x01, 0xC6, 0x01, 0x05, 0x00, 0x05, 0x00, 0x2B, 0x01, 0x2B, 0x01, 0x05, 0x00, 0x05, 0x00, 0x2B, 0x01, 0x2B, 0x01, 0x00, 0x52, 0x00, 0x64, 0x00, 0x8A, 0x00, 0xB0, 0x00, 0x52, 0x00, 0x64, 0x00, 0x8A, 0x00, 0xB0, 0x00, 0x00, 0x10, 0x00, 0x00, 0xDF, 0x01, 0x00, 0x00, 0xDF, 0x01, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB4, 1, 65, {0x09, 0x02, 0x00, 0x00, 0x10, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x2C, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x02, 0x46, 0x8A, 0x13, 0x57, 0x9B, 0x31, 0x75, 0xB9, 0x20, 0x64, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x64, 0xA8, 0x31, 0x75, 0xB9, 0x13, 0x57, 0x9B, 0x02, 0x46, 0x8A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB5, 1, 58, {0x4C, 0x09, 0x09, 0x09, 0x49, 0x40, 0x00, 0x01, 0x2C, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x03, 0x02, 0x6E, 0x00, 0x2C, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB6, 1, 26, {0x00, 0x10, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x2C, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB7, 1, 51, {0x0C, 0x00, 0x01, 0x2C, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x03, 0x02, 0x6E, 0x00, 0x2C, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB8, 1, 95, {0x00, 0x67, 0x31, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x00, 0x22, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x00, 0x22, 0x00, 0x00, 0x00}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xC2}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x4A, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x63, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x53, 1, 1, {0x28}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC4, 25, 1, {0x84}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xBA, 1, 1, {0x80}}, // bist: 0x81, exit bist: 0x80
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 1, {0xC0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0xA5, 0xA5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0xA5, 0xA5}},
|
||||
|
||||
// {SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0x5A, 0x5A}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0x5A, 0x5A}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xC2}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xB0, 1, 1, {0x16}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 9, {0x01, 0x05, 0x00, 0xA2, 0x00, 0xA7, 0x00, 0xA7, 0x00}}, // 0x01=45Hz, 0x00=60Hz
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0x4A, 1, 1, {0xFF}},
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0x63, 1, 1, {0xFF}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x53, 1, 1, {0x28}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC4, 25, 1, {0x84}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0xBA, 1, 1, {0x80}}, // bist: 0x81, exit bist: 0x80
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 1, {0xC0}},
|
||||
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0xA5, 0xA5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0xA5, 0xA5}},
|
||||
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
const SH8601A_CMD_DESC SH8601A_POWEROFF_SEQ_CMD[] = {
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x28, 25, 0, {0}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x10, 50, 0, {0}},
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
const SH8601A_CMD_DESC SH8601A_OTP_WRITE[] = {
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xD0, 1000, 2, {0x01}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xD0, 10, 2, {0x00}},
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
static DMA_LLI_InitTypeDef *Link_Channel = (void *)0x1fffe000;
|
||||
|
||||
static void write_cmd(uint8_t cmd)
|
||||
{
|
||||
uint8_t spi_data[4];
|
||||
|
||||
spi_data[0] = SH8601A_QSPI_INST_CMD_WRITE;
|
||||
spi_data[1] = 0x00;
|
||||
spi_data[2] = cmd;
|
||||
spi_data[3] = 0x00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, (uint16_t *)spi_data, 4);
|
||||
__DISPLAY_CS_SET();
|
||||
}
|
||||
|
||||
static void write_buff(uint8_t *buffer, uint8_t len)
|
||||
{
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, (uint16_t *)buffer, len);
|
||||
__DISPLAY_CS_SET();
|
||||
}
|
||||
|
||||
static void read_reg(uint8_t reg, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
uint8_t spi_data[4];
|
||||
|
||||
spi_data[0] = SH8601A_QSPI_INST_CMD_READ;
|
||||
spi_data[1] = 0x00;
|
||||
spi_data[2] = reg;
|
||||
spi_data[3] = 0x00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, (uint16_t *)spi_data, 4);
|
||||
spi_master_receive_X1(&spi_display_handle, buffer, len);
|
||||
__DISPLAY_CS_SET();
|
||||
}
|
||||
|
||||
static void SH8601A_Reg_Write(const SH8601A_CMD_DESC* cmd)
|
||||
{
|
||||
uint16_t idx = 0;
|
||||
|
||||
while (cmd[idx].instruction != SH8601A_QSPI_SEQ_FINISH_CODE)
|
||||
{
|
||||
uint8_t sdat[cmd[idx].wordcount + 4];
|
||||
|
||||
sdat[0] = cmd[idx].instruction;
|
||||
|
||||
sdat[1] = 0;
|
||||
sdat[2] = cmd[idx].index; // Set in the middle 8 bits ADDR[15:8] of the 24 bits ADDR[23:0]
|
||||
sdat[3] = 0;
|
||||
|
||||
for(uint16_t i=0; i<cmd[idx].wordcount; i++)
|
||||
{
|
||||
sdat[i+4] = cmd[idx].payload[i];
|
||||
}
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, sdat, sizeof(sdat));
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
if (cmd[idx].delay != 0)
|
||||
{
|
||||
__DISPLAY_DELAY_MS(cmd[idx].delay);
|
||||
}
|
||||
|
||||
idx++;
|
||||
}
|
||||
}
|
||||
|
||||
static void SH8601A_Init_Pre_OTP(void)
|
||||
{
|
||||
//pull low RESX
|
||||
//power on VBAT: VBAT = 3.7V
|
||||
//power on VDDI: VDDI = 1.8V
|
||||
//pull high VCI_EN: enable VCI = 3.3V
|
||||
//delay 10ms
|
||||
//pull high RESX: IC reset
|
||||
//delay 10ms
|
||||
SH8601A_Reg_Write(SH8601A_PRE_OTP_POWERON_SEQ_CMD);
|
||||
}
|
||||
|
||||
static void SH8601A_Init_Post_OTP(void)
|
||||
{
|
||||
//pull low RESX
|
||||
//power on VBAT: VBAT = 3.7V
|
||||
//power on VDDI: VDDI = 1.8V
|
||||
//pull high VCI_EN: enable VCI = 3.3V
|
||||
//delay 10ms
|
||||
//pull high RESX: IC reset
|
||||
//delay 10ms
|
||||
SH8601A_Reg_Write(SH8601A_POST_OTP_POWERON_SEQ_CMD);
|
||||
}
|
||||
|
||||
static void SH8601A_Power_Off(void)
|
||||
{
|
||||
SH8601A_Reg_Write(SH8601A_POWEROFF_SEQ_CMD);
|
||||
//delay 100ms
|
||||
//pull low RESX
|
||||
//delay 10ms
|
||||
//pull low VCI_EN: disable VCI
|
||||
//power off VDDI
|
||||
//power off VBAT
|
||||
}
|
||||
|
||||
static void SH8601A_OTP_Write(void)
|
||||
{
|
||||
/*********************************************
|
||||
* Register read:
|
||||
* Index: 0xCF (OTP_STATUS)
|
||||
* Para: 1 Byte read
|
||||
* Check BANK_CHECK_MCS[1:0]:
|
||||
* - 00h: No writen, 3 times writable
|
||||
* - 01h: 1 time written, 2 times writable
|
||||
* - 02h: 2 times written, 1 time writable
|
||||
* - 03h: 3 time written, no longer be written
|
||||
**********************************************/
|
||||
|
||||
//power on VOTP: VOTP = 6V external supply
|
||||
//delay 20ms
|
||||
SH8601A_Reg_Write(SH8601A_OTP_WRITE);
|
||||
//power off VOTP
|
||||
//delay 20ms
|
||||
|
||||
/*********************************************
|
||||
* OTP status verification:
|
||||
* Index: 0xCF (OTP_STATUS)
|
||||
* Para: 3 Bytes read
|
||||
* Check PRG_ERR_1:
|
||||
* - 0: OK
|
||||
* - 1: FAIL
|
||||
OTP rewrite(power off -> power on -> rewrite)
|
||||
* Check PRG_ERR_0:
|
||||
* - 0: OK
|
||||
* - 1: FAIL
|
||||
Not rewrite OTP
|
||||
**********************************************/
|
||||
|
||||
/* Go to power off sequence */
|
||||
}
|
||||
|
||||
static void sh8601a_read_regs(void)
|
||||
{
|
||||
uint8_t buffer[6];
|
||||
|
||||
read_reg(0x90, buffer, 6);
|
||||
read_reg(0x2A, buffer, 4);
|
||||
read_reg(0x2B, buffer, 4);
|
||||
}
|
||||
|
||||
void sh8601a_init(void)
|
||||
{
|
||||
__DISPLAY_VCI_CLEAR();
|
||||
__DISPLAY_RESET_CLEAR();
|
||||
__DISPLAY_DELAY_MS(20);
|
||||
__DISPLAY_VCI_SET();
|
||||
__DISPLAY_DELAY_MS(40);
|
||||
__DISPLAY_RESET_SET();
|
||||
__DISPLAY_DELAY_MS(80);
|
||||
|
||||
SH8601A_Init_Pre_OTP();
|
||||
}
|
||||
|
||||
void sh8601a_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e)
|
||||
{
|
||||
uint8_t data[8];
|
||||
|
||||
data[0] = 0x02;
|
||||
data[1] = 0x00;
|
||||
data[2] = 0x2A;
|
||||
data[3] = 0x00;
|
||||
data[4] = x_s >> 8;
|
||||
data[5] = x_s & 0xff;
|
||||
data[6] = x_e >> 8;
|
||||
data[7] = x_e & 0xff;
|
||||
write_buff(data, 8);
|
||||
|
||||
data[0] = 0x02;
|
||||
data[1] = 0x00;
|
||||
data[2] = 0x2B;
|
||||
data[3] = 0x00;
|
||||
data[4] = y_s >> 8;
|
||||
data[5] = y_s & 0xff;
|
||||
data[6] = y_e >> 8;
|
||||
data[7] = y_e & 0xff;
|
||||
write_buff(data, 8);
|
||||
|
||||
// write_cmd(0x2c);
|
||||
}
|
||||
|
||||
void sh8601a_display(uint32_t pixel_count, uint8_t pixel_width, void *data)
|
||||
{
|
||||
uint8_t frame_size;
|
||||
|
||||
if (pixel_width == 16) {
|
||||
frame_size = SPI_FRAME_SIZE_16BIT;
|
||||
}
|
||||
else if (pixel_width == 32) {
|
||||
frame_size = SPI_FRAME_SIZE_24BIT;
|
||||
}
|
||||
spi_display_handle.Init.Frame_Size = frame_size;
|
||||
spi_display_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_display_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_display_handle.MultWireParam.Instruct = 0x32;
|
||||
spi_display_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_display_handle.MultWireParam.Address = 0x002C00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X2X4X8(&spi_display_handle, data, pixel_count);
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_DATA_FRAME_SIZE(spi_display_handle.SPIx, SPI_FRAME_SIZE_8BIT);
|
||||
}
|
||||
|
||||
void sh8601a_display_dma(uint32_t pixel_count, uint8_t pixel_width, void *data)
|
||||
{
|
||||
//#define USE_DMA_LINK_MODE
|
||||
uint8_t spi_trans_width;
|
||||
uint32_t dma_sample_count;
|
||||
|
||||
#ifdef USE_DMA_LINK_MODE
|
||||
#define DMA_SINGLE_TRANSFER_SIZE 20000
|
||||
uint32_t link_count;
|
||||
uint32_t i;
|
||||
uint32_t link_trans_size;
|
||||
dma_LinkParameter_t LinkParameter;
|
||||
|
||||
|
||||
switch (dma_display_handle.Init.Source_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
dma_sample_count = pixel_count * pixel_width / 32;
|
||||
link_trans_size = 4 * DMA_SINGLE_TRANSFER_SIZE;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
dma_sample_count = pixel_count * pixel_width / 16;
|
||||
link_trans_size = 2 * DMA_SINGLE_TRANSFER_SIZE;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
dma_sample_count = pixel_count * pixel_width / 8;
|
||||
link_trans_size = DMA_SINGLE_TRANSFER_SIZE;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
link_count = dma_sample_count / DMA_SINGLE_TRANSFER_SIZE;
|
||||
if(dma_sample_count % DMA_SINGLE_TRANSFER_SIZE)
|
||||
{
|
||||
link_count++;
|
||||
}
|
||||
|
||||
for (i = 0; i < link_count; i++)
|
||||
{
|
||||
uint8_t all_set = (dma_sample_count <= DMA_SINGLE_TRANSFER_SIZE);
|
||||
|
||||
LinkParameter.SrcAddr = (uint32_t)data + i * link_trans_size;
|
||||
LinkParameter.DstAddr = (uint32_t)&spi_display_handle.SPIx->DR;
|
||||
if(all_set)
|
||||
{
|
||||
LinkParameter.NextLink = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LinkParameter.NextLink = (uint32_t)&Link_Channel[i + 1];
|
||||
}
|
||||
LinkParameter.Data_Flow = dma_display_handle.Init.Data_Flow;
|
||||
LinkParameter.Request_ID = dma_display_handle.Init.Request_ID;
|
||||
LinkParameter.Source_Master_Sel = dma_display_handle.Init.Source_Master_Sel;
|
||||
LinkParameter.Desination_Master_Sel = dma_display_handle.Init.Desination_Master_Sel;
|
||||
LinkParameter.Source_Inc = dma_display_handle.Init.Source_Inc;
|
||||
LinkParameter.Desination_Inc = dma_display_handle.Init.Desination_Inc;
|
||||
LinkParameter.Source_Width = dma_display_handle.Init.Source_Width;
|
||||
LinkParameter.Desination_Width = dma_display_handle.Init.Desination_Width;
|
||||
LinkParameter.Source_Burst_Len = dma_display_handle.Init.Source_Burst_Len;
|
||||
LinkParameter.Desination_Burst_Len = dma_display_handle.Init.Desination_Burst_Len;
|
||||
LinkParameter.Size = all_set ? dma_sample_count : DMA_SINGLE_TRANSFER_SIZE;
|
||||
LinkParameter.gather_enable = 0;
|
||||
LinkParameter.scatter_enable = 0;
|
||||
dma_sample_count -= DMA_SINGLE_TRANSFER_SIZE;
|
||||
|
||||
dma_linked_list_init(&Link_Channel[i], &LinkParameter);
|
||||
}
|
||||
#else
|
||||
switch (dma_display_handle.Init.Source_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
dma_sample_count = pixel_count * pixel_width / 32;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
dma_sample_count = pixel_count * pixel_width / 16;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
dma_sample_count = pixel_count * pixel_width / 8;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
switch (dma_display_handle.Init.Desination_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
spi_trans_width = SPI_FRAME_SIZE_32BIT;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
spi_trans_width = SPI_FRAME_SIZE_16BIT;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
spi_trans_width = SPI_FRAME_SIZE_8BIT;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
spi_display_handle.Init.Frame_Size = spi_trans_width;
|
||||
spi_display_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_display_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_display_handle.MultWireParam.Instruct = 0x32;
|
||||
spi_display_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_display_handle.MultWireParam.Address = 0x002C00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
__SPI_ENABLE(spi_display_handle.SPIx);
|
||||
spi_master_transmit_X2X4X8_DMA(&spi_display_handle);
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
if (spi_trans_width == SPI_FRAME_SIZE_32BIT) {
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_2143);
|
||||
}
|
||||
else {
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
}
|
||||
__SPI_ENABLE(spi_display_handle.SPIx);
|
||||
#ifndef USE_DMA_LINK_MODE
|
||||
dma_start_IT(&dma_display_handle, (uint32_t)data, (uint32_t)&spi_display_handle.SPIx->DR, dma_sample_count);
|
||||
#else
|
||||
dma_linked_list_start_IT(Link_Channel, &LinkParameter, &dma_display_handle);
|
||||
#endif
|
||||
}
|
||||
|
||||
void sh8601a_display_dma_isr(void)
|
||||
{
|
||||
while(__SPI_IS_BUSY(spi_display_handle.SPIx));
|
||||
|
||||
// CS Release
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
/* Clear Transfer complete status */
|
||||
dma_clear_tfr_Status(&dma_display_handle);
|
||||
/* channel Transfer complete interrupt disable */
|
||||
dma_tfr_interrupt_disable(&dma_display_handle);
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_DATA_FRAME_SIZE(spi_display_handle.SPIx, SPI_FRAME_SIZE_8BIT);
|
||||
}
|
||||
16
fr3092_mcu/components/drivers/bsp/display/driver_sh8601a.h
Normal file
16
fr3092_mcu/components/drivers/bsp/display/driver_sh8601a.h
Normal file
@ -0,0 +1,16 @@
|
||||
#ifndef __DRIVER_SH8601A_H
|
||||
#define __DRIVER_SH8601A_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void sh8601a_init(void);
|
||||
|
||||
void sh8601a_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e);
|
||||
|
||||
void sh8601a_display(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
|
||||
void sh8601a_display_dma(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
|
||||
void sh8601a_display_dma_isr(void);
|
||||
|
||||
#endif // __DRIVER_SH8601A_H
|
||||
501
fr3092_mcu/components/drivers/bsp/display/driver_sh8601z.c
Normal file
501
fr3092_mcu/components/drivers/bsp/display/driver_sh8601z.c
Normal file
@ -0,0 +1,501 @@
|
||||
#include "driver_display.h"
|
||||
#include "driver_sh8601z.h"
|
||||
|
||||
#define SH8601A_MAX_PARA_COUNT (300)
|
||||
|
||||
#define SH8601A_QSPI_INST_CMD_WRITE (0x02)
|
||||
#define SH8601A_QSPI_INST_CMD_READ (0x03)
|
||||
#define SH8601A_QSPI_INST_1WIRE_PIXEL_WRITE (0x02)
|
||||
#define SH8601A_QSPI_INST_4WIRE_PIXEL_WRITE_TYPE1 (0x32)
|
||||
#define SH8601A_QSPI_INST_4WIRE_PIXEL_WRITE_TYPE2 (0x12)
|
||||
#define SH8601A_QSPI_SEQ_FINISH_CODE (0x00)
|
||||
|
||||
typedef struct _SH8601A_CMD_DESC {
|
||||
uint8_t instruction;
|
||||
uint8_t index;
|
||||
uint16_t delay;
|
||||
uint16_t wordcount;
|
||||
uint8_t payload[SH8601A_MAX_PARA_COUNT];
|
||||
} SH8601A_CMD_DESC;
|
||||
|
||||
static const SH8601A_CMD_DESC SH8601A_PRE_OTP_POWERON_SEQ_CMD[] = {
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0x6F}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xBF}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xBF}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x3A, 1, 1, {0x05}}, // 16bits pixel
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x53, 25, 1, {0x20}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
static const SH8601A_CMD_DESC SH8601A_POST_OTP_POWERON_SEQ_CMD[] = {
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xC2}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x4A, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x63, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x53, 1, 1, {0x28}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC4, 25, 1, {0x84}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
// {SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0x5A, 0x5A}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0x5A, 0x5A}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 51, {0xC0, 0xC6, 0x01, 0xC6, 0x01, 0x05, 0x00, 0x05, 0x00, 0x2B, 0x01, 0x2B, 0x01, 0x05, 0x00, 0x05, 0x00, 0x2B, 0x01, 0x2B, 0x01, 0x00, 0x52, 0x00, 0x64, 0x00, 0x8A, 0x00, 0xB0, 0x00, 0x52, 0x00, 0x64, 0x00, 0x8A, 0x00, 0xB0, 0x00, 0x00, 0x10, 0x00, 0x00, 0xDF, 0x01, 0x00, 0x00, 0xDF, 0x01, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB4, 1, 65, {0x09, 0x02, 0x00, 0x00, 0x10, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x2C, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x02, 0x46, 0x8A, 0x13, 0x57, 0x9B, 0x31, 0x75, 0xB9, 0x20, 0x64, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x64, 0xA8, 0x31, 0x75, 0xB9, 0x13, 0x57, 0x9B, 0x02, 0x46, 0x8A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB5, 1, 58, {0x4C, 0x09, 0x09, 0x09, 0x49, 0x40, 0x00, 0x01, 0x2C, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x03, 0x02, 0x6E, 0x00, 0x2C, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB6, 1, 26, {0x00, 0x10, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x2C, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x47}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB7, 1, 51, {0x0C, 0x00, 0x01, 0x2C, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x03, 0x02, 0x6E, 0x00, 0x2C, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB8, 1, 95, {0x00, 0x67, 0x31, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x00, 0x22, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x00, 0x22, 0x00, 0x00, 0x00}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xC2}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x4A, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x63, 1, 1, {0xFF}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x53, 1, 1, {0x28}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC4, 25, 1, {0x84}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xBA, 1, 1, {0x80}}, // bist: 0x81, exit bist: 0x80
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 1, {0xC0}},
|
||||
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0xA5, 0xA5}},
|
||||
// {SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0xA5, 0xA5}},
|
||||
|
||||
// {SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0x5A, 0x5A}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0x5A, 0x5A}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x11, 10, 0, {0}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2A, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x2B, 1, 4, {0x00, 0x00, 0x01, 0xC5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x44, 1, 2, {0x01, 0xC2}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x35, 1, 1, {0x00}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xB0, 1, 1, {0x16}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 9, {0x01, 0x05, 0x00, 0xA2, 0x00, 0xA7, 0x00, 0xA7, 0x00}}, // 0x01=45Hz, 0x00=60Hz
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0x51, 1, 1, {0xFF}},
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0x4A, 1, 1, {0xFF}},
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0x63, 1, 1, {0xFF}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x53, 1, 1, {0x28}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC4, 25, 1, {0x84}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x29, 1, 0, {0}},
|
||||
//{SH8601A_QSPI_INST_CMD_WRITE, 0xBA, 1, 1, {0x80}}, // bist: 0x81, exit bist: 0x80
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xB1, 1, 1, {0xC0}},
|
||||
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC0, 1, 2, {0xA5, 0xA5}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xC1, 1, 2, {0xA5, 0xA5}},
|
||||
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
static const SH8601A_CMD_DESC SH8601A_POWEROFF_SEQ_CMD[] = {
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x28, 15, 0, {0}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0x10, 0, 0, {0}},
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
static const SH8601A_CMD_DESC SH8601A_OTP_WRITE[] = {
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xD0, 1000, 2, {0x01}},
|
||||
{SH8601A_QSPI_INST_CMD_WRITE, 0xD0, 10, 2, {0x00}},
|
||||
{SH8601A_QSPI_SEQ_FINISH_CODE, 0, 0, 0, {0}},
|
||||
};
|
||||
|
||||
#ifdef USE_DMA_LINK_MODE
|
||||
static DMA_LLI_InitTypeDef *Link_Channel = (void *)0x1fffe000;
|
||||
#endif
|
||||
|
||||
static void write_cmd(uint8_t cmd)
|
||||
{
|
||||
uint8_t spi_data[4];
|
||||
|
||||
spi_data[0] = SH8601A_QSPI_INST_CMD_WRITE;
|
||||
spi_data[1] = 0x00;
|
||||
spi_data[2] = cmd;
|
||||
spi_data[3] = 0x00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, (uint16_t *)spi_data, 4);
|
||||
__DISPLAY_CS_SET();
|
||||
}
|
||||
|
||||
static void write_buff(uint8_t *buffer, uint8_t len)
|
||||
{
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, (uint16_t *)buffer, len);
|
||||
__DISPLAY_CS_SET();
|
||||
}
|
||||
|
||||
static void read_reg(uint8_t reg, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
uint8_t spi_data[4];
|
||||
|
||||
spi_data[0] = SH8601A_QSPI_INST_CMD_READ;
|
||||
spi_data[1] = 0x00;
|
||||
spi_data[2] = reg;
|
||||
spi_data[3] = 0x00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, (uint16_t *)spi_data, 4);
|
||||
spi_master_receive_X1(&spi_display_handle, buffer, len);
|
||||
__DISPLAY_CS_SET();
|
||||
}
|
||||
|
||||
static void SH8601A_Reg_Write(const SH8601A_CMD_DESC* cmd)
|
||||
{
|
||||
uint16_t idx = 0;
|
||||
|
||||
while (cmd[idx].instruction != SH8601A_QSPI_SEQ_FINISH_CODE)
|
||||
{
|
||||
uint8_t sdat[cmd[idx].wordcount + 4];
|
||||
|
||||
sdat[0] = cmd[idx].instruction;
|
||||
|
||||
sdat[1] = 0;
|
||||
sdat[2] = cmd[idx].index; // Set in the middle 8 bits ADDR[15:8] of the 24 bits ADDR[23:0]
|
||||
sdat[3] = 0;
|
||||
|
||||
for(uint16_t i=0; i<cmd[idx].wordcount; i++)
|
||||
{
|
||||
sdat[i+4] = cmd[idx].payload[i];
|
||||
}
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X1(&spi_display_handle, sdat, sizeof(sdat));
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
if (cmd[idx].delay != 0)
|
||||
{
|
||||
__DISPLAY_DELAY_MS(cmd[idx].delay);
|
||||
}
|
||||
|
||||
idx++;
|
||||
}
|
||||
}
|
||||
|
||||
static void SH8601A_Init_Pre_OTP(void)
|
||||
{
|
||||
//pull low RESX
|
||||
//power on VBAT: VBAT = 3.7V
|
||||
//power on VDDI: VDDI = 1.8V
|
||||
//pull high VCI_EN: enable VCI = 3.3V
|
||||
//delay 10ms
|
||||
//pull high RESX: IC reset
|
||||
//delay 10ms
|
||||
SH8601A_Reg_Write(SH8601A_PRE_OTP_POWERON_SEQ_CMD);
|
||||
}
|
||||
|
||||
static void SH8601A_Init_Post_OTP(void)
|
||||
{
|
||||
//pull low RESX
|
||||
//power on VBAT: VBAT = 3.7V
|
||||
//power on VDDI: VDDI = 1.8V
|
||||
//pull high VCI_EN: enable VCI = 3.3V
|
||||
//delay 10ms
|
||||
//pull high RESX: IC reset
|
||||
//delay 10ms
|
||||
SH8601A_Reg_Write(SH8601A_POST_OTP_POWERON_SEQ_CMD);
|
||||
}
|
||||
|
||||
static void SH8601A_Power_Off(void)
|
||||
{
|
||||
SH8601A_Reg_Write(SH8601A_POWEROFF_SEQ_CMD);
|
||||
//delay 100ms
|
||||
//pull low RESX
|
||||
//delay 10ms
|
||||
//pull low VCI_EN: disable VCI
|
||||
//power off VDDI
|
||||
//power off VBAT
|
||||
}
|
||||
|
||||
static void SH8601A_OTP_Write(void)
|
||||
{
|
||||
/*********************************************
|
||||
* Register read:
|
||||
* Index: 0xCF (OTP_STATUS)
|
||||
* Para: 1 Byte read
|
||||
* Check BANK_CHECK_MCS[1:0]:
|
||||
* - 00h: No writen, 3 times writable
|
||||
* - 01h: 1 time written, 2 times writable
|
||||
* - 02h: 2 times written, 1 time writable
|
||||
* - 03h: 3 time written, no longer be written
|
||||
**********************************************/
|
||||
|
||||
//power on VOTP: VOTP = 6V external supply
|
||||
//delay 20ms
|
||||
SH8601A_Reg_Write(SH8601A_OTP_WRITE);
|
||||
//power off VOTP
|
||||
//delay 20ms
|
||||
|
||||
/*********************************************
|
||||
* OTP status verification:
|
||||
* Index: 0xCF (OTP_STATUS)
|
||||
* Para: 3 Bytes read
|
||||
* Check PRG_ERR_1:
|
||||
* - 0: OK
|
||||
* - 1: FAIL
|
||||
OTP rewrite(power off -> power on -> rewrite)
|
||||
* Check PRG_ERR_0:
|
||||
* - 0: OK
|
||||
* - 1: FAIL
|
||||
Not rewrite OTP
|
||||
**********************************************/
|
||||
|
||||
/* Go to power off sequence */
|
||||
}
|
||||
|
||||
static void sh8601a_read_regs(void)
|
||||
{
|
||||
uint8_t buffer[6];
|
||||
|
||||
read_reg(0x90, buffer, 6);
|
||||
read_reg(0x2A, buffer, 4);
|
||||
read_reg(0x2B, buffer, 4);
|
||||
}
|
||||
|
||||
void sh8601z_init(void)
|
||||
{
|
||||
__DISPLAY_VCI_CLEAR();
|
||||
__DISPLAY_RESET_CLEAR();
|
||||
__DISPLAY_DELAY_MS(10);
|
||||
__DISPLAY_VCI_SET();
|
||||
__DISPLAY_DELAY_MS(10);
|
||||
__DISPLAY_RESET_SET();
|
||||
__DISPLAY_DELAY_MS(10);
|
||||
|
||||
SH8601A_Init_Pre_OTP();
|
||||
}
|
||||
|
||||
void sh8601z_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e)
|
||||
{
|
||||
uint8_t data[8];
|
||||
|
||||
x_s += 16;
|
||||
x_e += 16;
|
||||
|
||||
data[0] = 0x02;
|
||||
data[1] = 0x00;
|
||||
data[2] = 0x2A;
|
||||
data[3] = 0x00;
|
||||
data[4] = x_s >> 8;
|
||||
data[5] = x_s & 0xff;
|
||||
data[6] = x_e >> 8;
|
||||
data[7] = x_e & 0xff;
|
||||
write_buff(data, 8);
|
||||
|
||||
data[0] = 0x02;
|
||||
data[1] = 0x00;
|
||||
data[2] = 0x2B;
|
||||
data[3] = 0x00;
|
||||
data[4] = y_s >> 8;
|
||||
data[5] = y_s & 0xff;
|
||||
data[6] = y_e >> 8;
|
||||
data[7] = y_e & 0xff;
|
||||
write_buff(data, 8);
|
||||
|
||||
// write_cmd(0x2c);
|
||||
}
|
||||
|
||||
void sh8601z_display(uint32_t pixel_count, uint8_t pixel_width, void *data)
|
||||
{
|
||||
uint8_t frame_size;
|
||||
|
||||
if (pixel_width == 16) {
|
||||
frame_size = SPI_FRAME_SIZE_16BIT;
|
||||
}
|
||||
else if (pixel_width == 32) {
|
||||
frame_size = SPI_FRAME_SIZE_24BIT;
|
||||
}
|
||||
spi_display_handle.Init.Frame_Size = frame_size;
|
||||
spi_display_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_display_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_display_handle.MultWireParam.Instruct = 0x32;
|
||||
spi_display_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_display_handle.MultWireParam.Address = 0x002C00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
spi_master_transmit_X2X4X8(&spi_display_handle, data, pixel_count);
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_DATA_FRAME_SIZE(spi_display_handle.SPIx, SPI_FRAME_SIZE_8BIT);
|
||||
}
|
||||
|
||||
void sh8601z_display_dma(uint32_t pixel_count, uint8_t pixel_width, void *data)
|
||||
{
|
||||
//#define USE_DMA_LINK_MODE
|
||||
uint8_t spi_trans_width;
|
||||
uint32_t dma_sample_count;
|
||||
|
||||
#ifdef USE_DMA_LINK_MODE
|
||||
#define DMA_SINGLE_TRANSFER_SIZE 20000
|
||||
uint32_t link_count;
|
||||
uint32_t i;
|
||||
uint32_t link_trans_size;
|
||||
dma_LinkParameter_t LinkParameter;
|
||||
|
||||
|
||||
switch (dma_display_handle.Init.Source_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
dma_sample_count = pixel_count * pixel_width / 32;
|
||||
link_trans_size = 4 * DMA_SINGLE_TRANSFER_SIZE;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
dma_sample_count = pixel_count * pixel_width / 16;
|
||||
link_trans_size = 2 * DMA_SINGLE_TRANSFER_SIZE;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
dma_sample_count = pixel_count * pixel_width / 8;
|
||||
link_trans_size = DMA_SINGLE_TRANSFER_SIZE;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
link_count = dma_sample_count / DMA_SINGLE_TRANSFER_SIZE;
|
||||
if(dma_sample_count % DMA_SINGLE_TRANSFER_SIZE)
|
||||
{
|
||||
link_count++;
|
||||
}
|
||||
|
||||
for (i = 0; i < link_count; i++)
|
||||
{
|
||||
uint8_t all_set = (dma_sample_count <= DMA_SINGLE_TRANSFER_SIZE);
|
||||
|
||||
LinkParameter.SrcAddr = (uint32_t)data + i * link_trans_size;
|
||||
LinkParameter.DstAddr = (uint32_t)&spi_display_handle.SPIx->DR;
|
||||
if(all_set)
|
||||
{
|
||||
LinkParameter.NextLink = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LinkParameter.NextLink = (uint32_t)&Link_Channel[i + 1];
|
||||
}
|
||||
LinkParameter.Data_Flow = dma_display_handle.Init.Data_Flow;
|
||||
LinkParameter.Request_ID = dma_display_handle.Init.Request_ID;
|
||||
LinkParameter.Source_Master_Sel = dma_display_handle.Init.Source_Master_Sel;
|
||||
LinkParameter.Desination_Master_Sel = dma_display_handle.Init.Desination_Master_Sel;
|
||||
LinkParameter.Source_Inc = dma_display_handle.Init.Source_Inc;
|
||||
LinkParameter.Desination_Inc = dma_display_handle.Init.Desination_Inc;
|
||||
LinkParameter.Source_Width = dma_display_handle.Init.Source_Width;
|
||||
LinkParameter.Desination_Width = dma_display_handle.Init.Desination_Width;
|
||||
LinkParameter.Source_Burst_Len = dma_display_handle.Init.Source_Burst_Len;
|
||||
LinkParameter.Desination_Burst_Len = dma_display_handle.Init.Desination_Burst_Len;
|
||||
LinkParameter.Size = all_set ? dma_sample_count : DMA_SINGLE_TRANSFER_SIZE;
|
||||
LinkParameter.gather_enable = 0;
|
||||
LinkParameter.scatter_enable = 0;
|
||||
dma_sample_count -= DMA_SINGLE_TRANSFER_SIZE;
|
||||
|
||||
dma_linked_list_init(&Link_Channel[i], &LinkParameter);
|
||||
}
|
||||
#else
|
||||
switch (dma_display_handle.Init.Source_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
dma_sample_count = pixel_count * pixel_width / 32;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
dma_sample_count = pixel_count * pixel_width / 16;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
dma_sample_count = pixel_count * pixel_width / 8;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
switch (dma_display_handle.Init.Desination_Width) {
|
||||
case DMA_TRANSFER_WIDTH_32:
|
||||
spi_trans_width = SPI_FRAME_SIZE_32BIT;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_16:
|
||||
spi_trans_width = SPI_FRAME_SIZE_16BIT;
|
||||
break;
|
||||
case DMA_TRANSFER_WIDTH_8:
|
||||
spi_trans_width = SPI_FRAME_SIZE_8BIT;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
spi_display_handle.Init.Frame_Size = spi_trans_width;
|
||||
spi_display_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_display_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_display_handle.MultWireParam.Instruct = 0x32;
|
||||
spi_display_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_display_handle.MultWireParam.Address = 0x002C00;
|
||||
|
||||
__DISPLAY_CS_CLEAR();
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
__SPI_ENABLE(spi_display_handle.SPIx);
|
||||
spi_master_transmit_X2X4X8_DMA(&spi_display_handle);
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
if (spi_trans_width == SPI_FRAME_SIZE_32BIT) {
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_2143);
|
||||
}
|
||||
else {
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
}
|
||||
__SPI_ENABLE(spi_display_handle.SPIx);
|
||||
#ifndef USE_DMA_LINK_MODE
|
||||
dma_start_IT(&dma_display_handle, (uint32_t)data, (uint32_t)&spi_display_handle.SPIx->DR, dma_sample_count);
|
||||
#else
|
||||
dma_linked_list_start_IT(Link_Channel, &LinkParameter, &dma_display_handle);
|
||||
#endif
|
||||
}
|
||||
|
||||
void sh8601z_power_off(void)
|
||||
{
|
||||
SH8601A_Power_Off();
|
||||
|
||||
__DISPLAY_DELAY_MS(100);
|
||||
__DISPLAY_RESET_CLEAR();
|
||||
__DISPLAY_DELAY_MS(10);
|
||||
__DISPLAY_VCI_CLEAR();
|
||||
}
|
||||
|
||||
void sh8601z_power_on(void)
|
||||
{
|
||||
__DISPLAY_VCI_CLEAR();
|
||||
__DISPLAY_RESET_CLEAR();
|
||||
__DISPLAY_DELAY_MS(10);
|
||||
__DISPLAY_VCI_SET();
|
||||
__DISPLAY_DELAY_MS(10);
|
||||
__DISPLAY_RESET_SET();
|
||||
__DISPLAY_DELAY_MS(10);
|
||||
|
||||
SH8601A_Init_Pre_OTP();
|
||||
}
|
||||
|
||||
void sh8601z_display_dma_isr(void)
|
||||
{
|
||||
while(__SPI_IS_BUSY(spi_display_handle.SPIx));
|
||||
|
||||
// CS Release
|
||||
__DISPLAY_CS_SET();
|
||||
|
||||
/* Clear Transfer complete status */
|
||||
dma_clear_tfr_Status(&dma_display_handle);
|
||||
/* channel Transfer complete interrupt disable */
|
||||
dma_tfr_interrupt_disable(&dma_display_handle);
|
||||
|
||||
__SPI_DISABLE(spi_display_handle.SPIx);
|
||||
__SPI_TX_ENDIAN_SET(spi_display_handle.SPIx, TX_RX_Endian_4321);
|
||||
__SPI_DATA_FRAME_SIZE(spi_display_handle.SPIx, SPI_FRAME_SIZE_8BIT);
|
||||
}
|
||||
20
fr3092_mcu/components/drivers/bsp/display/driver_sh8601z.h
Normal file
20
fr3092_mcu/components/drivers/bsp/display/driver_sh8601z.h
Normal file
@ -0,0 +1,20 @@
|
||||
#ifndef __DRIVER_SH8601A_H
|
||||
#define __DRIVER_SH8601A_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void sh8601z_init(void);
|
||||
|
||||
void sh8601z_set_window(uint16_t x_s, uint16_t x_e, uint16_t y_s, uint16_t y_e);
|
||||
|
||||
void sh8601z_display(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
|
||||
void sh8601z_display_dma(uint32_t pixel_count, uint8_t pixel_width, void *data);
|
||||
|
||||
void sh8601z_power_off(void);
|
||||
|
||||
void sh8601z_power_on(void);
|
||||
|
||||
void sh8601z_display_dma_isr(void);
|
||||
|
||||
#endif // __DRIVER_SH8601A_H
|
||||
1032
fr3092_mcu/components/drivers/bsp/display/driver_st7701_rgb.c
Normal file
1032
fr3092_mcu/components/drivers/bsp/display/driver_st7701_rgb.c
Normal file
File diff suppressed because it is too large
Load Diff
139
fr3092_mcu/components/drivers/bsp/display/driver_st7701_rgb.h
Normal file
139
fr3092_mcu/components/drivers/bsp/display/driver_st7701_rgb.h
Normal file
@ -0,0 +1,139 @@
|
||||
|
||||
#ifndef __DRIVER_ST7701_RGB_H__
|
||||
#define __DRIVER_ST7701_RGB_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
#include "app_config.h"
|
||||
|
||||
#define RGB_ROW 480
|
||||
#define RGB_COLUMN 480
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t VerticalSignalCount;
|
||||
|
||||
unsigned char *rgb_TxData;
|
||||
|
||||
}struct_RGB_TypeDef_t;
|
||||
|
||||
#define RGB565_LCD_DCLK_PORT GPIOB
|
||||
#define RGB565_LCD_DCLK_GPIO GPIO_PIN_13
|
||||
|
||||
#define RGB565_LCD_VSYNC_PORT GPIOB
|
||||
#define RGB565_LCD_VSYNC_GPIO GPIO_PIN_14
|
||||
|
||||
#define RGB565_LCD_HSYNC_PORT GPIOB
|
||||
#define RGB565_LCD_HSYNC_GPIO GPIO_PIN_15
|
||||
|
||||
#define RGB565_LCD_DISP_PORT GPIOA
|
||||
#define RGB565_LCD_DISP_GPIO GPIO_PIN_6
|
||||
|
||||
#define RGB565_LCD_DE_EN_PORT GPIOB
|
||||
#define RGB565_LCD_DE_EN_GPIO GPIO_PIN_12
|
||||
|
||||
#define RGB565_LCD_DATA_PORT GPIOC
|
||||
#define RGB565_LCD_DATA_GPIO 0xFFFF //GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7
|
||||
|
||||
#define RGB565_LCD_RESET_PORT GPIOD
|
||||
#define RGB565_LCD_RESET_GPIO GPIO_PIN_13
|
||||
|
||||
#define RGB565_LCD_BACKLIGHT_PORT GPIOA
|
||||
#define RGB565_LCD_BACKLIGHT_GPIO GPIO_PIN_6
|
||||
|
||||
|
||||
#ifdef RGB565_LCD_TE_EN
|
||||
#define RGB565_LCD_TE_PORT GPIO_B
|
||||
#define RGB565_LCD_TE_GPIO GPIO_PIN_7
|
||||
#endif
|
||||
|
||||
#define RGB56_LCD_INIT_CONFIG
|
||||
|
||||
#ifdef RGB56_LCD_INIT_CONFIG
|
||||
#define RGB565_LCD_SPI_CS_PORT GPIOD
|
||||
#define RGB565_LCD_SPI_CS_GPIO GPIO_PIN_12
|
||||
|
||||
#define RGB565_LCD_SPI_CLK_PORT GPIOB
|
||||
#define RGB565_LCD_SPI_CLK_GPIO GPIO_PIN_0
|
||||
|
||||
#define RGB565_LCD_SPI_MOSI_PORT GPIOB
|
||||
#define RGB565_LCD_SPI_MOSI_GPIO GPIO_PIN_2
|
||||
|
||||
#define RGB565_LCD_SPI_MISO_PORT GPIOB
|
||||
#define RGB565_LCD_SPI_MISO_GPIO GPIO_PIN_3
|
||||
|
||||
#define RGB565_LCD_SPI_SEL SPIM0
|
||||
|
||||
#define rgb_spi_cs_set() gpio_write_pin(RGB565_LCD_SPI_CS_PORT,RGB565_LCD_SPI_CS_GPIO,GPIO_PIN_CLEAR)
|
||||
#define rgb_spi_cs_release() gpio_write_pin(RGB565_LCD_SPI_CS_PORT,RGB565_LCD_SPI_CS_GPIO,GPIO_PIN_SET)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/* signal drive*/
|
||||
#define rgb_lcd_enable_set() gpio_write_pin(RGB565_LCD_DE_EN_PORT,RGB565_LCD_DE_EN_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_enable_release() gpio_write_pin(RGB565_LCD_DE_EN_PORT,RGB565_LCD_DE_EN_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_vsync_set() gpio_write_pin(RGB565_LCD_VSYNC_PORT,RGB565_LCD_VSYNC_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_vsync_release() gpio_write_pin(RGB565_LCD_VSYNC_PORT,RGB565_LCD_VSYNC_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_hsync_set() gpio_write_pin(RGB565_LCD_HSYNC_PORT,RGB565_LCD_HSYNC_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_hsync_release() gpio_write_pin(RGB565_LCD_HSYNC_PORT,RGB565_LCD_HSYNC_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_reset_set() gpio_write_pin(RGB565_LCD_RESET_PORT,RGB565_LCD_RESET_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_reset_release() gpio_write_pin(RGB565_LCD_RESET_PORT,RGB565_LCD_RESET_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_disp_set() gpio_write_pin(RGB565_LCD_DISP_PORT,RGB565_LCD_DISP_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_disp_release() gpio_write_pin(RGB565_LCD_DISP_PORT,RGB565_LCD_DISP_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
#define rgb_lcd_backlight_set() gpio_write_pin(RGB565_LCD_BACKLIGHT_PORT,RGB565_LCD_BACKLIGHT_GPIO,GPIO_PIN_SET)
|
||||
#define rgb_lcd_backlight_release() gpio_write_pin(RGB565_LCD_BACKLIGHT_PORT,RGB565_LCD_BACKLIGHT_GPIO,GPIO_PIN_CLEAR)
|
||||
|
||||
|
||||
#define __RGB_LCD_DENABLE_SET rgb_lcd_enable_release
|
||||
#define __RGB_LCD_DENABLE_RELEASE rgb_lcd_enable_set
|
||||
|
||||
#define __RGB_LCD_VSYNC_SET rgb_lcd_vsync_set
|
||||
#define __RGB_LCD_VSYNC__RELEASE rgb_lcd_vsync_release
|
||||
|
||||
#define __RGB_LCD_HSYNC_SET rgb_lcd_hsync_set
|
||||
#define __RGB_LCD_HSYNC__RELEASE rgb_lcd_hsync_release
|
||||
|
||||
#define __RGB_LCD_RESET_SET rgb_lcd_reset_set
|
||||
#define __RGB_LCD_RESET_RELEASE rgb_lcd_reset_release
|
||||
|
||||
#define __RGB_SPI_CS_RELEASE rgb_spi_cs_release
|
||||
#define __RGB_SPI_CS_SET rgb_spi_cs_set
|
||||
|
||||
#define __8080_DATA_WR_LEN(__LEVEL__) __PARALLEL_SET_WR_LEN(hparallel.PARALLELx,__LEVEL__)
|
||||
#define __8080_TXFIFO_EMPTY() __PARALLEL_INT_STATUS(hparallel.PARALLELx)&INT_TXFIFO_EMPTY
|
||||
#define __8080_WRITE_BLANK() hparallel.PARALLELx->TX_FIFO = 0
|
||||
|
||||
#define __TIMER_CLEAR_IQR(__TIMERx__) timer_int_clear(__TIMERx__)
|
||||
#define __TIMER_INIT(__TIMERx__, __LoadCount__) timer_init(__TIMERx__, (24000 * __LoadCount__))
|
||||
#define __TIMER_INT_ENABLE(__TIMERx__) timer_int_enable(__TIMERx__)
|
||||
#define __TIMER_START(__TIMERx__) timer_start(__TIMERx__)
|
||||
|
||||
#define __DMA_GET_TFR_STATUS() dma_get_tfr_Status(&dma_handle)
|
||||
#define __DMA_CLEAR_TFR_STATUS() dma_clear_tfr_Status(&dma_handle)
|
||||
#define __DMA_TO_8080_START_IT(__BUFFER__,__SIZE__) dma_start_IT(&dma_handle, (uint32_t)__BUFFER__, (uint32_t)&hparallel.PARALLELx->TX_FIFO, __SIZE__)
|
||||
|
||||
#define __SPI_WRITE_DATA(__BUFFER__, __SIZE__) spi_master_transmit_X1(&spi_handle, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* rgb_display_start */
|
||||
/* rgb_timer_IRQHandler */
|
||||
/* rgb_dma_IRQHandler */
|
||||
void rgb_display_start(struct_Timer_t *TIMERx, struct_RGB_TypeDef_t *hrgb, uint32_t fps, unsigned char *Imagedata);
|
||||
void rgb_timer_IRQHandler(struct_Timer_t *TIMERx, struct_RGB_TypeDef_t *hrgb);
|
||||
void rgb_dma_IRQHandler(struct_RGB_TypeDef_t *hrgb);
|
||||
|
||||
void st7701_init(void* buffer);
|
||||
void st7701_rgb_display_dma_irq(void);
|
||||
|
||||
__RAM_CODE void rgb_display_dma_irq(void);
|
||||
|
||||
|
||||
#endif
|
||||
350
fr3092_mcu/components/drivers/bsp/psram/driver_psram.c
Normal file
350
fr3092_mcu/components/drivers/bsp/psram/driver_psram.c
Normal file
@ -0,0 +1,350 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_flash.c
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Internal XIP Flash module driver.
|
||||
* This file provides firmware functions to manage the internal
|
||||
* stacked xip flash
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "fr30xx.h"
|
||||
|
||||
#include "driver_psram.h"
|
||||
|
||||
#include "co_util.h"
|
||||
|
||||
#define PSRAM_ENABLE_Q_MODE 1
|
||||
|
||||
#define PSRAM_LATENCY_CFG 3
|
||||
#define PSRAM_HIGH_SPEED 1
|
||||
#define PSRAM_OSPI_IF OSPI
|
||||
|
||||
#define PSRAM_READ_IDENTIFICATION 0x9F
|
||||
|
||||
#define PSRAM_READ_OPCODE 0x03
|
||||
#define PSRAM_FAST_READ_OPCODE 0x0B
|
||||
#define PSRAM_FAST_QUAL_READ_OPCODE 0xEB
|
||||
|
||||
#define PSRAM_PAGE_PROGRAM_OPCODE 0x02
|
||||
#define PSRAM_PAGE_QUAL_PROGRAM_OPCODE 0x38
|
||||
|
||||
#define PSRAM_ENTER_QUAD_MODE_OPCODE 0x35
|
||||
#define PSRAM_EXIT_QUAD_MODE_OPCODE 0xF5
|
||||
|
||||
#define PSRAM_RESET_ENABLE_OPCODE 0x66
|
||||
#define PSRAM_RESET_OPCODE 0x99
|
||||
|
||||
static const struct qspi_stig_reg_t psram_read_ctrl_cmd = {
|
||||
.enable_bank = 0,
|
||||
.dummy_cycles = PSRAM_LATENCY_CFG-1,
|
||||
.write_bytes = 0,
|
||||
.enable_write = 0,
|
||||
.addr_bytes = QSPI_STIG_ADDR_BYTES_4,
|
||||
.enable_mode = 0,
|
||||
.enable_cmd_addr = 1,
|
||||
.read_bytes = 2,
|
||||
.enable_read = 1,
|
||||
.opcode = 0x40,
|
||||
};
|
||||
|
||||
static const struct qspi_stig_reg_t psram_write_ctrl_cmd = {
|
||||
.enable_bank = 0,
|
||||
.dummy_cycles = 0,
|
||||
.write_bytes = 2,
|
||||
.enable_write = 1,
|
||||
.addr_bytes = QSPI_STIG_ADDR_BYTES_4,
|
||||
.enable_mode = 0,
|
||||
.enable_cmd_addr = 1,
|
||||
.read_bytes = 0,
|
||||
.enable_read = 0,
|
||||
.opcode = 0xC0,
|
||||
};
|
||||
|
||||
static const struct qspi_stig_reg_t psram_read_id_cmd = {
|
||||
.enable_bank = 0,
|
||||
.dummy_cycles = 0,
|
||||
.write_bytes = 0,
|
||||
.enable_write = 0,
|
||||
.addr_bytes = 0,
|
||||
.enable_mode = 0,
|
||||
.enable_cmd_addr = 0,
|
||||
.read_bytes = 3,
|
||||
.enable_read = 1,
|
||||
.opcode = PSRAM_READ_IDENTIFICATION,
|
||||
};
|
||||
|
||||
static const struct qspi_stig_reg_t enter_quad_mode_cmd = {
|
||||
.enable_bank = 0,
|
||||
.dummy_cycles = 0,
|
||||
.write_bytes = 0,
|
||||
.enable_write = 0,
|
||||
.addr_bytes = 0,
|
||||
.enable_mode = 0,
|
||||
.enable_cmd_addr = 0,
|
||||
.read_bytes = 0,
|
||||
.enable_read = 0,
|
||||
.opcode = PSRAM_ENTER_QUAD_MODE_OPCODE,
|
||||
};
|
||||
|
||||
static const struct qspi_stig_reg_t reset_enable_cmd = {
|
||||
.enable_bank = 0,
|
||||
.dummy_cycles = 0,
|
||||
.write_bytes = 0,
|
||||
.enable_write = 0,
|
||||
.addr_bytes = 0,
|
||||
.enable_mode = 0,
|
||||
.enable_cmd_addr = 0,
|
||||
.read_bytes = 0,
|
||||
.enable_read = 0,
|
||||
.opcode = PSRAM_RESET_ENABLE_OPCODE,
|
||||
};
|
||||
|
||||
static const struct qspi_stig_reg_t reset_cmd = {
|
||||
.enable_bank = 0,
|
||||
.dummy_cycles = 0,
|
||||
.write_bytes = 0,
|
||||
.enable_write = 0,
|
||||
.addr_bytes = 0,
|
||||
.enable_mode = 0,
|
||||
.enable_cmd_addr = 0,
|
||||
.read_bytes = 0,
|
||||
.enable_read = 0,
|
||||
.opcode = PSRAM_RESET_OPCODE,
|
||||
};
|
||||
|
||||
static uint8_t psram_read_mode(uint8_t mode)
|
||||
{
|
||||
uint8_t result[2];
|
||||
|
||||
__QSPI_CMD_ADDRESS_SET(PSRAM_OSPI_IF, mode);
|
||||
qspi_stig_cmd(PSRAM_OSPI_IF, psram_read_ctrl_cmd, QSPI_STIG_CMD_READ, 2, result);
|
||||
|
||||
return result[0];
|
||||
}
|
||||
|
||||
static void psram_write_mode(uint8_t mode, uint8_t data)
|
||||
{
|
||||
uint8_t buffer[2];
|
||||
|
||||
buffer[0] = data;
|
||||
buffer[1] = data;
|
||||
__QSPI_CMD_ADDRESS_SET(PSRAM_OSPI_IF, mode);
|
||||
qspi_stig_cmd(PSRAM_OSPI_IF, psram_write_ctrl_cmd, QSPI_STIG_CMD_WRITE, 2, buffer);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void psram_controller_init(uint16_t page_boundary)
|
||||
{
|
||||
while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
|
||||
|
||||
__QSPI_READ_OPCODE_SET(PSRAM_OSPI_IF, 0x20);
|
||||
__QSPI_READ_INSTRUCTION_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_OIO);
|
||||
__QSPI_READ_ADDRESS_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_OIO);
|
||||
__QSPI_READ_DATA_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_OIO);
|
||||
__QSPI_READ_DUMMY_CYCLES_SET(PSRAM_OSPI_IF, (PSRAM_LATENCY_CFG<<1)-1);
|
||||
__QSPI_READ_MODE_ENABLE_SET(PSRAM_OSPI_IF, 0);
|
||||
__QSPI_MODE_BIT_SET(PSRAM_OSPI_IF, 0);
|
||||
|
||||
__QSPI_WRITE_OPCODE_SET(PSRAM_OSPI_IF, 0xA0);
|
||||
__QSPI_WRITE_ADDRESS_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_OIO);
|
||||
__QSPI_WRITE_DATA_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_OIO);
|
||||
__QSPI_WRITE_DUMMY_CYCLES_SET(PSRAM_OSPI_IF, PSRAM_LATENCY_CFG-1);
|
||||
__QSPI_WRITE_WEL_DISABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_POLL_DISABLE(PSRAM_OSPI_IF);
|
||||
|
||||
//init configuration register
|
||||
__QSPI_CFG_CPOL_SET(PSRAM_OSPI_IF, 0);
|
||||
__QSPI_CFG_CPHA_SET(PSRAM_OSPI_IF, 0);
|
||||
__QSPI_CFG_DAC_ENABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CFG_LEGACY_DISABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CFG_REMAP_ENABLE(PSRAM_OSPI_IF);
|
||||
#if PSRAM_HIGH_SPEED
|
||||
__QSPI_CFG_BAUDRATE_SET(PSRAM_OSPI_IF, QSPI_BAUDRATE_DIV_6);
|
||||
__QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, 0);
|
||||
#else
|
||||
__QSPI_CFG_BAUDRATE_SET(PSRAM_OSPI_IF, QSPI_BAUDRATE_DIV_16);
|
||||
__QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, 0);
|
||||
#endif
|
||||
|
||||
// __QSPI_CFG_AHB_DECODER_ENABLE(PSRAM_OSPI_IF);
|
||||
|
||||
__QSPI_READ_CAPTURE_LP_CLK_EN(PSRAM_OSPI_IF);
|
||||
__QSPI_DELAY_CS_START_SET(PSRAM_OSPI_IF, 2);
|
||||
__QSPI_DELAY_CS_END_SET(PSRAM_OSPI_IF, 2);
|
||||
__QSPI_DELAY_CS_DESSERT_SET(PSRAM_OSPI_IF, 2);
|
||||
|
||||
__QSPI_DEVICE_PAGE_SIZE_SET(PSRAM_OSPI_IF, page_boundary);
|
||||
// __QSPI_DEVICE_CS0_SIZE_SET(PSRAM_OSPI_IF, 3); // 4Gb space
|
||||
|
||||
__QSPI_CS_CTRL_RD_BRK_ENABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CS_CTRL_DIS_CS_AFT_FIRST_BYTE_SET(PSRAM_OSPI_IF);
|
||||
__QSPI_CS_PAGE_BOUNDARY_SET(PSRAM_OSPI_IF, page_boundary);
|
||||
__QSPI_CS_PAGE_BOUNDARY_PROTECT_ENABLE(PSRAM_OSPI_IF);
|
||||
|
||||
// __QSPI_REMAP_ADDRESS_SET(PSRAM_OSPI_IF, PSRAM_DAC_BASE);
|
||||
|
||||
__QSPI_DEVICE_ADDR_BYTES_SET(PSRAM_OSPI_IF, QSPI_DEVICE_ADDR_BYTES_4);
|
||||
__QSPI_CFG_DTR_ENABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CFG_OCTAL_XCCELA_ENABLE(PSRAM_OSPI_IF);
|
||||
|
||||
__QSPI_ENABLE(PSRAM_OSPI_IF);
|
||||
}
|
||||
|
||||
void psram_init(void)
|
||||
{
|
||||
// uint8_t mode[7];
|
||||
uint8_t value;
|
||||
|
||||
#if PSRAM_HIGH_SPEED
|
||||
psram_controller_init(0x0040);
|
||||
#else
|
||||
psram_controller_init(0x0008);
|
||||
#endif
|
||||
|
||||
value = (1<<5) | ((PSRAM_LATENCY_CFG-3)<<2) | (0<<0);
|
||||
psram_write_mode(0x00, value);
|
||||
#if PSRAM_LATENCY_CFG == 3
|
||||
value = (0<<5);
|
||||
#elif PSRAM_LATENCY_CFG == 4
|
||||
value = (4<<5);
|
||||
#elif PSRAM_LATENCY_CFG == 5
|
||||
value = (2<<5);
|
||||
#elif PSRAM_LATENCY_CFG == 6
|
||||
value = (6<<5);
|
||||
#elif PSRAM_LATENCY_CFG == 7
|
||||
value = (1<<5);
|
||||
#else
|
||||
#error "UNACCEPTABLE configure"
|
||||
#endif
|
||||
|
||||
printf("write 0x%02x to mode reg4.\r\n", value);
|
||||
psram_write_mode(0x04, value);
|
||||
co_delay_100us(1);
|
||||
|
||||
// mode[0] = psram_read_mode(0x00);
|
||||
// printf("mode 0: 0x%02x\r\n", mode[0]);
|
||||
// mode[1] = psram_read_mode(0x01);
|
||||
// printf("mode 1: 0x%02x\r\n", mode[1]);
|
||||
// mode[2] = psram_read_mode(0x02);
|
||||
// printf("mode 2: 0x%02x\r\n", mode[2]);
|
||||
// mode[3] = psram_read_mode(0x03);
|
||||
// printf("mode 3: 0x%02x\r\n", mode[3]);
|
||||
// mode[4] = psram_read_mode(0x04);
|
||||
// printf("mode 4: 0x%02x\r\n", mode[4]);
|
||||
// mode[5] = psram_read_mode(0x06);
|
||||
// printf("mode 6: 0x%02x\r\n", mode[5]);
|
||||
// mode[6] = psram_read_mode(0x08);
|
||||
// printf("mode 8: 0x%02x\r\n", mode[6]);
|
||||
}
|
||||
#else
|
||||
static void psram_enter_quad(void)
|
||||
{
|
||||
qspi_stig_cmd(PSRAM_OSPI_IF, enter_quad_mode_cmd, QSPI_STIG_CMD_EXE, 0, NULL);
|
||||
}
|
||||
|
||||
static void psram_controller_init(uint16_t page_boundary)
|
||||
{
|
||||
while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
|
||||
|
||||
#if PSRAM_ENABLE_Q_MODE == 1
|
||||
__QSPI_READ_OPCODE_SET(PSRAM_OSPI_IF, PSRAM_FAST_READ_OPCODE);
|
||||
__QSPI_READ_INSTRUCTION_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_READ_ADDRESS_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_READ_DATA_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_READ_DUMMY_CYCLES_SET(PSRAM_OSPI_IF, 4);
|
||||
__QSPI_READ_MODE_ENABLE_SET(PSRAM_OSPI_IF, 0);
|
||||
__QSPI_MODE_BIT_SET(PSRAM_OSPI_IF, 0);
|
||||
|
||||
__QSPI_WRITE_OPCODE_SET(PSRAM_OSPI_IF, PSRAM_PAGE_QUAL_PROGRAM_OPCODE);
|
||||
__QSPI_WRITE_ADDRESS_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_WRITE_DATA_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_WRITE_DUMMY_CYCLES_SET(PSRAM_OSPI_IF, 0);
|
||||
#else
|
||||
__QSPI_READ_OPCODE_SET(PSRAM_OSPI_IF, PSRAM_FAST_QUAL_READ_OPCODE);
|
||||
__QSPI_READ_INSTRUCTION_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_STAND);
|
||||
__QSPI_READ_ADDRESS_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_READ_DATA_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_READ_DUMMY_CYCLES_SET(PSRAM_OSPI_IF, 6);
|
||||
__QSPI_READ_MODE_ENABLE_SET(PSRAM_OSPI_IF, 0);
|
||||
__QSPI_MODE_BIT_SET(PSRAM_OSPI_IF, 0);
|
||||
|
||||
__QSPI_WRITE_OPCODE_SET(PSRAM_OSPI_IF, PSRAM_PAGE_QUAL_PROGRAM_OPCODE);
|
||||
__QSPI_WRITE_ADDRESS_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_WRITE_DATA_TYPE_SET(PSRAM_OSPI_IF, QSPI_WIRE_TYPE_QIO);
|
||||
__QSPI_WRITE_DUMMY_CYCLES_SET(PSRAM_OSPI_IF, 0);
|
||||
#endif
|
||||
|
||||
//init configuration register
|
||||
__QSPI_CFG_CPOL_SET(PSRAM_OSPI_IF, 0);
|
||||
__QSPI_CFG_CPHA_SET(PSRAM_OSPI_IF, 0);
|
||||
__QSPI_CFG_DAC_ENABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CFG_LEGACY_DISABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CFG_REMAP_ENABLE(PSRAM_OSPI_IF);
|
||||
#if PSRAM_HIGH_SPEED
|
||||
__QSPI_CFG_BAUDRATE_SET(PSRAM_OSPI_IF, QSPI_BAUDRATE_DIV_2);
|
||||
__QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, 4);
|
||||
#else
|
||||
__QSPI_CFG_BAUDRATE_SET(PSRAM_OSPI_IF, QSPI_BAUDRATE_DIV_8);
|
||||
__QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, 0);
|
||||
#endif
|
||||
|
||||
// __QSPI_CFG_AHB_DECODER_ENABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_WRITE_WEL_DISABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_POLL_DISABLE(PSRAM_OSPI_IF);
|
||||
|
||||
__QSPI_READ_CAPTURE_LP_CLK_EN(PSRAM_OSPI_IF);
|
||||
__QSPI_DELAY_CS_START_SET(PSRAM_OSPI_IF, 2);
|
||||
__QSPI_DELAY_CS_END_SET(PSRAM_OSPI_IF, 2);
|
||||
__QSPI_DELAY_CS_DESSERT_SET(PSRAM_OSPI_IF, 2);
|
||||
|
||||
__QSPI_DEVICE_PAGE_SIZE_SET(PSRAM_OSPI_IF, page_boundary);
|
||||
// __QSPI_DEVICE_CS0_SIZE_SET(PSRAM_OSPI_IF, 3); // 4Gb space
|
||||
|
||||
__QSPI_CS_CTRL_RD_BRK_ENABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CS_CTRL_DIS_CS_AFT_FIRST_BYTE_SET(PSRAM_OSPI_IF);
|
||||
__QSPI_CS_PAGE_BOUNDARY_SET(PSRAM_OSPI_IF, page_boundary);
|
||||
__QSPI_CS_PAGE_BOUNDARY_PROTECT_ENABLE(PSRAM_OSPI_IF);
|
||||
|
||||
__QSPI_REMAP_ADDRESS_SET(PSRAM_OSPI_IF, PSRAM_DAC_BASE);
|
||||
|
||||
__QSPI_CFG_OCTAL_OPI_DISABLE(PSRAM_OSPI_IF);
|
||||
__QSPI_CFG_OCTAL_XCCELA_DISABLE(PSRAM_OSPI_IF);
|
||||
|
||||
__QSPI_ENABLE(PSRAM_OSPI_IF);
|
||||
}
|
||||
|
||||
void psram_init(bool reset)
|
||||
{
|
||||
if (reset) {
|
||||
qspi_stig_cmd(PSRAM_OSPI_IF, reset_enable_cmd, QSPI_STIG_CMD_EXE, 0, NULL);
|
||||
// co_delay_10us(1000);
|
||||
qspi_stig_cmd(PSRAM_OSPI_IF, reset_cmd, QSPI_STIG_CMD_EXE, 0, NULL);
|
||||
// co_delay_10us(1000);
|
||||
#if PSRAM_ENABLE_Q_MODE == 1
|
||||
psram_enter_quad();
|
||||
// co_delay_10us(1000);
|
||||
#endif // PSRAM_ENABLE_Q_MODE == 1
|
||||
}
|
||||
|
||||
#if PSRAM_HIGH_SPEED
|
||||
psram_controller_init(0x0040);
|
||||
#else
|
||||
psram_controller_init(0x0010);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t psram_read_id(void)
|
||||
{
|
||||
uint32_t psram_id;
|
||||
qspi_stig_cmd(PSRAM_OSPI_IF, psram_read_id_cmd, QSPI_STIG_CMD_READ, 3, (uint8_t *)&psram_id);
|
||||
return (psram_id&0xffffff);
|
||||
}
|
||||
#endif
|
||||
|
||||
40
fr3092_mcu/components/drivers/bsp/psram/driver_psram.h
Normal file
40
fr3092_mcu/components/drivers/bsp/psram/driver_psram.h
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_psram.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of PSRAM module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_PSRAM_H__
|
||||
#define __DRIVER_PSRAM_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/*
|
||||
* @brief PSRAM Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Reserve; /*!< reserve */
|
||||
} PSRAM_InitTypeDef;
|
||||
|
||||
/* ################################ Initialization、Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void psram_init(bool reset);
|
||||
|
||||
uint32_t psram_read_id(void);
|
||||
|
||||
#endif // __DRIVER_PSRAM_H__
|
||||
463
fr3092_mcu/components/drivers/bsp/rgb_565/rgb565.c
Normal file
463
fr3092_mcu/components/drivers/bsp/rgb_565/rgb565.c
Normal file
@ -0,0 +1,463 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file rgb565.c
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief rgb565 IC driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the 8080 SPI Timer and DMA norflash driver for rgb565.
|
||||
* @ Initialization and de-initialization functions
|
||||
* @ IO operation functions
|
||||
* @ Peripheral Control functions
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "rgb565.h"
|
||||
#include "app_config.h"
|
||||
|
||||
#if BOARD_SEL == BOARD_EVB_FR3092E_RGB
|
||||
|
||||
#ifdef RGB56_LCD_INIT_CONFIG
|
||||
static void rgb_reg_writer(uint16_t *fp_data, uint32_t size)
|
||||
{
|
||||
__RGB_SPI_CS_SET();
|
||||
/* fp_Data[0] stores command, while others store data
|
||||
Bit8 set to 1 as data, otherwise it is a command
|
||||
*/
|
||||
for(int i = 1; i < size; i++)
|
||||
{
|
||||
fp_data[i] = fp_data[i] + 0x100;
|
||||
}
|
||||
|
||||
__SPI_WRITE_DATA(fp_data,size);
|
||||
|
||||
__RGB_SPI_CS_RELEASE();
|
||||
}
|
||||
#endif
|
||||
static void rgb_idle_clock(uint32_t count)
|
||||
{
|
||||
/* 8080 hits idle Clocks */
|
||||
__8080_DATA_WR_LEN(count);
|
||||
for(int i = 0; i < count/2; i++)
|
||||
__8080_WRITE_BLANK();
|
||||
}
|
||||
|
||||
static void Line_porch_set(uint32_t count)
|
||||
{
|
||||
for(int i = 0; i < count; i++)
|
||||
{
|
||||
__RGB_LCD_HSYNC__RELEASE();
|
||||
//__RGB_LCD_DENABLE_RELEASE();
|
||||
__RGB_LCD_DENABLE_SET();
|
||||
rgb_idle_clock(4);
|
||||
|
||||
__RGB_LCD_HSYNC_SET();
|
||||
rgb_idle_clock(RGB_ROW);
|
||||
}
|
||||
}
|
||||
|
||||
static void Vertical_back_porch_set(void)
|
||||
{
|
||||
__RGB_LCD_HSYNC__RELEASE();
|
||||
__RGB_LCD_DENABLE_SET();
|
||||
rgb_idle_clock(4);
|
||||
|
||||
__RGB_LCD_HSYNC_SET();
|
||||
|
||||
rgb_idle_clock(4);
|
||||
|
||||
while(!(__8080_TXFIFO_EMPTY()));
|
||||
}
|
||||
|
||||
static void Vertical_front_porch_set(void)
|
||||
{
|
||||
__RGB_LCD_HSYNC_SET();
|
||||
__RGB_LCD_DENABLE_SET();
|
||||
|
||||
rgb_idle_clock(4);
|
||||
|
||||
while(!(__8080_TXFIFO_EMPTY()));
|
||||
}
|
||||
|
||||
void rgb_init(void)
|
||||
{
|
||||
uint16_t WBuffer[20];
|
||||
|
||||
__RGB_LCD_RESET_RELEASE();
|
||||
system_delay_us(50 * 1000);
|
||||
__RGB_LCD_RESET_SET();
|
||||
system_delay_us(1000 * 120);
|
||||
|
||||
#ifdef RGB56_LCD_INIT_CONFIG
|
||||
WBuffer[0] = 0xFF;
|
||||
WBuffer[1] = 0x77;
|
||||
WBuffer[2] = 0x01;
|
||||
WBuffer[3] = 0x00;
|
||||
WBuffer[4] = 0x00;
|
||||
WBuffer[5] = 0x10;
|
||||
rgb_reg_writer(WBuffer, 6);
|
||||
|
||||
WBuffer[0] = 0xC0;
|
||||
WBuffer[1] = 0x3B;
|
||||
WBuffer[2] = 0x00;
|
||||
rgb_reg_writer(WBuffer, 3);
|
||||
|
||||
WBuffer[0] = 0xC1;
|
||||
WBuffer[1] = 0x10;
|
||||
WBuffer[2] = 0x0C;
|
||||
rgb_reg_writer(WBuffer, 3);
|
||||
|
||||
WBuffer[0] = 0xC2;
|
||||
WBuffer[1] = 0x21;
|
||||
WBuffer[2] = 0x0A;
|
||||
rgb_reg_writer(WBuffer, 3);
|
||||
|
||||
WBuffer[0] = 0xB0;
|
||||
WBuffer[1] = 0x40;
|
||||
WBuffer[2] = 0x09;
|
||||
WBuffer[3] = 0x4F;
|
||||
WBuffer[4] = 0x0B;
|
||||
WBuffer[5] = 0x10;
|
||||
WBuffer[6] = 0x07;
|
||||
WBuffer[7] = 0x00;
|
||||
WBuffer[8] = 0x08;
|
||||
WBuffer[9] = 0x06;
|
||||
WBuffer[10] = 0x20;
|
||||
WBuffer[11] = 0x02;
|
||||
WBuffer[12] = 0x12;
|
||||
WBuffer[13] = 0x0F;
|
||||
WBuffer[14] = 0x67;
|
||||
WBuffer[15] = 0x2E;
|
||||
WBuffer[16] = 0xDF;
|
||||
rgb_reg_writer(WBuffer, 17);
|
||||
|
||||
WBuffer[0] = 0xB1;
|
||||
WBuffer[1] = 0x4F;
|
||||
WBuffer[2] = 0x18;
|
||||
WBuffer[3] = 0x60;
|
||||
WBuffer[4] = 0x0E;
|
||||
WBuffer[5] = 0x10;
|
||||
WBuffer[6] = 0x04;
|
||||
WBuffer[7] = 0x0C;
|
||||
WBuffer[8] = 0x08;
|
||||
WBuffer[9] = 0x09;
|
||||
WBuffer[10] = 0x26;
|
||||
WBuffer[11] = 0x07;
|
||||
WBuffer[12] = 0x13;
|
||||
WBuffer[13] = 0x11;
|
||||
WBuffer[14] = 0x71;
|
||||
WBuffer[15] = 0x39;
|
||||
WBuffer[16] = 0xDF;
|
||||
rgb_reg_writer(WBuffer, 17);
|
||||
|
||||
WBuffer[0] = 0xFF;
|
||||
WBuffer[1] = 0x77;
|
||||
WBuffer[2] = 0x01;
|
||||
WBuffer[3] = 0x00;
|
||||
WBuffer[4] = 0x00;
|
||||
WBuffer[5] = 0x11;
|
||||
rgb_reg_writer(WBuffer, 6);
|
||||
|
||||
WBuffer[0] = 0xB0;
|
||||
WBuffer[1] = 0x4D;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xB1;
|
||||
WBuffer[1] = 0x41;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xB2;
|
||||
WBuffer[1] = 0x87;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xB3;
|
||||
WBuffer[1] = 0x80;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xB5;
|
||||
WBuffer[1] = 0x49;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xB7;
|
||||
WBuffer[1] = 0x87;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xB8;
|
||||
WBuffer[1] = 0x23;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xC0;
|
||||
WBuffer[1] = 0x07;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xC1;
|
||||
WBuffer[1] = 0x78;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xC2;
|
||||
WBuffer[1] = 0x78;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0xD0;
|
||||
WBuffer[1] = 0x88;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
system_delay_us(100 * 1000);
|
||||
|
||||
WBuffer[0] = 0xE0;
|
||||
WBuffer[1] = 0x00;
|
||||
WBuffer[2] = 0x00;
|
||||
WBuffer[3] = 0x00;
|
||||
WBuffer[4] = 0x00;
|
||||
rgb_reg_writer(WBuffer, 5);
|
||||
|
||||
WBuffer[0] = 0xE1;
|
||||
WBuffer[1] = 0x04;
|
||||
WBuffer[2] = 0xA0;
|
||||
WBuffer[3] = 0x06;
|
||||
WBuffer[4] = 0xA0;
|
||||
WBuffer[5] = 0x05;
|
||||
WBuffer[6] = 0xA0;
|
||||
WBuffer[7] = 0x07;
|
||||
WBuffer[8] = 0xA0;
|
||||
WBuffer[9] = 0x00;
|
||||
WBuffer[10] = 0x44;
|
||||
WBuffer[11] = 0x44;
|
||||
rgb_reg_writer(WBuffer, 12);
|
||||
|
||||
WBuffer[0] = 0xE2;
|
||||
WBuffer[1] = 0x11;
|
||||
WBuffer[2] = 0x11;
|
||||
WBuffer[3] = 0x44;
|
||||
WBuffer[4] = 0x44;
|
||||
WBuffer[5] = 0xE9;
|
||||
WBuffer[6] = 0xA0;
|
||||
WBuffer[7] = 0xEB;
|
||||
WBuffer[8] = 0xA0;
|
||||
WBuffer[9] = 0xEA;
|
||||
WBuffer[10] = 0xA0;
|
||||
WBuffer[11] = 0xEC;
|
||||
WBuffer[12] = 0xA0;
|
||||
WBuffer[13] = 0x00;
|
||||
rgb_reg_writer(WBuffer, 14);
|
||||
|
||||
WBuffer[0] = 0xE3;
|
||||
WBuffer[1] = 0x00;
|
||||
WBuffer[2] = 0x00;
|
||||
WBuffer[3] = 0x11;
|
||||
WBuffer[4] = 0x11;
|
||||
rgb_reg_writer(WBuffer, 5);
|
||||
|
||||
WBuffer[0] = 0xE4;
|
||||
WBuffer[1] = 0x44;
|
||||
WBuffer[2] = 0x44;
|
||||
rgb_reg_writer(WBuffer, 3);
|
||||
|
||||
WBuffer[0] = 0xE5;
|
||||
WBuffer[1] = 0x06;
|
||||
WBuffer[2] = 0xEA;
|
||||
WBuffer[3] = 0xA0;
|
||||
WBuffer[4] = 0xA0;
|
||||
WBuffer[5] = 0x08;
|
||||
WBuffer[6] = 0xEC;
|
||||
WBuffer[7] = 0xA0;
|
||||
WBuffer[8] = 0xA0;
|
||||
WBuffer[9] = 0x0A;
|
||||
WBuffer[10] = 0xEE;
|
||||
WBuffer[11] = 0xA0;
|
||||
WBuffer[12] = 0xA0;
|
||||
WBuffer[13] = 0x0C;
|
||||
WBuffer[14] = 0xF0;
|
||||
WBuffer[15] = 0xA0;
|
||||
WBuffer[16] = 0xA0;
|
||||
rgb_reg_writer(WBuffer, 17);
|
||||
|
||||
WBuffer[0] = 0xE6;
|
||||
WBuffer[1] = 0x00;
|
||||
WBuffer[2] = 0x00;
|
||||
WBuffer[3] = 0x11;
|
||||
WBuffer[4] = 0x11;
|
||||
rgb_reg_writer(WBuffer, 5);
|
||||
|
||||
WBuffer[0] = 0xE7;
|
||||
WBuffer[1] = 0x44;
|
||||
WBuffer[2] = 0x44;
|
||||
rgb_reg_writer(WBuffer, 3);
|
||||
|
||||
WBuffer[0] = 0xE8;
|
||||
WBuffer[1] = 0x07;
|
||||
WBuffer[2] = 0xEB;
|
||||
WBuffer[3] = 0xA0;
|
||||
WBuffer[4] = 0xA0;
|
||||
WBuffer[5] = 0x09;
|
||||
WBuffer[6] = 0xED;
|
||||
WBuffer[7] = 0xA0;
|
||||
WBuffer[8] = 0xA0;
|
||||
WBuffer[9] = 0x0B;
|
||||
WBuffer[10] = 0xEF;
|
||||
WBuffer[11] = 0xA0;
|
||||
WBuffer[12] = 0xA0;
|
||||
WBuffer[13] = 0x0D;
|
||||
WBuffer[14] = 0xF1;
|
||||
WBuffer[15] = 0xA0;
|
||||
WBuffer[16] = 0xA0;
|
||||
rgb_reg_writer(WBuffer, 17);
|
||||
|
||||
WBuffer[0] = 0xE9;
|
||||
WBuffer[1] = 0x36;
|
||||
WBuffer[2] = 0x00;
|
||||
rgb_reg_writer(WBuffer, 3);
|
||||
|
||||
WBuffer[0] = 0xEB;
|
||||
WBuffer[1] = 0x00;
|
||||
WBuffer[2] = 0x00;
|
||||
WBuffer[3] = 0x4E;
|
||||
WBuffer[4] = 0x4E;
|
||||
WBuffer[5] = 0xEE;
|
||||
WBuffer[6] = 0x44;
|
||||
WBuffer[7] = 0x40;
|
||||
rgb_reg_writer(WBuffer, 8);
|
||||
|
||||
WBuffer[0] = 0xED;
|
||||
WBuffer[1] = 0xFF;
|
||||
WBuffer[2] = 0xFF;
|
||||
WBuffer[3] = 0x76;
|
||||
WBuffer[4] = 0x54;
|
||||
WBuffer[5] = 0xC1;
|
||||
WBuffer[6] = 0x0F;
|
||||
WBuffer[7] = 0xB2;
|
||||
WBuffer[8] = 0x3F;
|
||||
WBuffer[9] = 0x32;
|
||||
WBuffer[10] = 0xBF;
|
||||
WBuffer[11] = 0x01;
|
||||
WBuffer[12] = 0xC4;
|
||||
WBuffer[13] = 0x56;
|
||||
WBuffer[14] = 0x7F;
|
||||
WBuffer[15] = 0xFF;
|
||||
WBuffer[16] = 0xFF;
|
||||
rgb_reg_writer(WBuffer, 17);
|
||||
|
||||
WBuffer[0] = 0xFF;
|
||||
WBuffer[1] = 0x77;
|
||||
WBuffer[2] = 0x01;
|
||||
WBuffer[3] = 0x00;
|
||||
WBuffer[4] = 0x00;
|
||||
WBuffer[5] = 0x00;
|
||||
rgb_reg_writer(WBuffer, 6);
|
||||
|
||||
WBuffer[0] = 0x35;
|
||||
WBuffer[1] = 0x00;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0x36;
|
||||
WBuffer[1] = 0x00;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0x3A;
|
||||
WBuffer[1] = 0x66;
|
||||
rgb_reg_writer(WBuffer, 2);
|
||||
|
||||
WBuffer[0] = 0x11;
|
||||
rgb_reg_writer(WBuffer,1);
|
||||
|
||||
system_delay_us(200 * 1000);
|
||||
|
||||
WBuffer[0] = 0x29;
|
||||
rgb_reg_writer(WBuffer,1);
|
||||
#endif
|
||||
|
||||
system_delay_us(50 * 1000);
|
||||
}
|
||||
|
||||
void rgb_display_start(struct_Timer_t *TIMERx, struct_RGB_TypeDef_t *hrgb, uint32_t fps, unsigned char *Imagedata)
|
||||
{
|
||||
__TIMER_INIT(TIMERx, fps);
|
||||
__TIMER_INT_ENABLE(TIMERx);
|
||||
|
||||
hrgb->rgb_TxData = Imagedata;
|
||||
hrgb->VerticalSignalCount = 0;
|
||||
|
||||
__TIMER_START(TIMERx);
|
||||
}
|
||||
|
||||
volatile uint32_t time_cnt1=0;
|
||||
volatile uint32_t time_cnt2=0;
|
||||
extern uint32_t get_system_dwt_value();
|
||||
|
||||
void rgb_timer_IRQHandler(struct_Timer_t *TIMERx, struct_RGB_TypeDef_t *hrgb)
|
||||
{
|
||||
__TIMER_CLEAR_IQR(TIMERx);
|
||||
|
||||
/* If the previous frame is not completed ,return */
|
||||
if(hrgb->VerticalSignalCount != 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
//printf("t:%d\r\n",(get_system_dwt_value()-time_cnt1)/192);
|
||||
/* Vertical signal Start*/
|
||||
__RGB_LCD_VSYNC__RELEASE();
|
||||
Line_porch_set(4);
|
||||
__RGB_LCD_VSYNC_SET();
|
||||
Line_porch_set(8);
|
||||
|
||||
/* set Vertical back porch signal */
|
||||
Vertical_back_porch_set();
|
||||
|
||||
/* send First Row */
|
||||
__RGB_LCD_DENABLE_RELEASE();
|
||||
__8080_DATA_WR_LEN(RGB_ROW);
|
||||
|
||||
__DMA_TO_8080_START_IT(&hrgb->rgb_TxData[0], RGB_ROW / 2);
|
||||
time_cnt1 = get_system_dwt_value();
|
||||
|
||||
}
|
||||
|
||||
volatile uint8_t te_sign;
|
||||
|
||||
|
||||
void rgb_dma_IRQHandler(struct_RGB_TypeDef_t *hrgb)
|
||||
{
|
||||
if (__DMA_GET_TFR_STATUS())
|
||||
{
|
||||
__DMA_CLEAR_TFR_STATUS();
|
||||
|
||||
hrgb->VerticalSignalCount++;
|
||||
}
|
||||
|
||||
while(!(__8080_TXFIFO_EMPTY()));
|
||||
|
||||
/* Row *Column End of one frame transmission */
|
||||
if(hrgb->VerticalSignalCount == RGB_COLUMN) //12ms
|
||||
{
|
||||
te_sign = 0;
|
||||
hrgb->VerticalSignalCount = 0;
|
||||
|
||||
__RGB_LCD_VSYNC_SET();
|
||||
|
||||
Line_porch_set(8);
|
||||
|
||||
return;
|
||||
}
|
||||
// else if(hrgb->VerticalSignalCount == 360)
|
||||
else if(hrgb->VerticalSignalCount == 180)
|
||||
{
|
||||
te_sign = 1;
|
||||
}
|
||||
|
||||
/* set Vertical back porch signal and back porch signal */
|
||||
Vertical_front_porch_set();
|
||||
Vertical_back_porch_set();
|
||||
|
||||
/* send next Row */
|
||||
__RGB_LCD_DENABLE_RELEASE();
|
||||
__8080_DATA_WR_LEN(RGB_ROW);
|
||||
__DMA_TO_8080_START_IT(&hrgb->rgb_TxData[RGB_ROW * hrgb->VerticalSignalCount * 2], RGB_ROW / 2);
|
||||
}
|
||||
|
||||
#endif
|
||||
76
fr3092_mcu/components/drivers/bsp/rgb_565/rgb565.h
Normal file
76
fr3092_mcu/components/drivers/bsp/rgb_565/rgb565.h
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file rgb565.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief rgb565 Config header file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __RGB565_H__
|
||||
#define __RGB565_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
#include "driver_nv3047_rgb.h"
|
||||
|
||||
extern SPI_HandleTypeDef spi_handle;
|
||||
extern DMA_HandleTypeDef dma_handle;
|
||||
extern PARALLEL_HandTypeDef hparallel;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t VerticalSignalCount;
|
||||
|
||||
unsigned char *rgb_TxData;
|
||||
|
||||
}struct_RGB_TypeDef_t;
|
||||
|
||||
|
||||
|
||||
#define __RGB_LCD_DENABLE_SET rgb_lcd_enable_release
|
||||
#define __RGB_LCD_DENABLE_RELEASE rgb_lcd_enable_set
|
||||
|
||||
#define __RGB_LCD_VSYNC_SET rgb_lcd_vsync_set
|
||||
#define __RGB_LCD_VSYNC__RELEASE rgb_lcd_vsync_release
|
||||
|
||||
#define __RGB_LCD_HSYNC_SET rgb_lcd_hsync_set
|
||||
#define __RGB_LCD_HSYNC__RELEASE rgb_lcd_hsync_release
|
||||
|
||||
#define __RGB_LCD_RESET_SET rgb_lcd_reset_set
|
||||
#define __RGB_LCD_RESET_RELEASE rgb_lcd_reset_release
|
||||
|
||||
#define __RGB_SPI_CS_RELEASE rgb_spi_cs_release
|
||||
#define __RGB_SPI_CS_SET rgb_spi_cs_set
|
||||
|
||||
#define __8080_DATA_WR_LEN(__LEVEL__) __PARALLEL_SET_WR_LEN(hparallel.PARALLELx,__LEVEL__)
|
||||
#define __8080_TXFIFO_EMPTY() __PARALLEL_INT_STATUS(hparallel.PARALLELx)&INT_TXFIFO_EMPTY
|
||||
#define __8080_WRITE_BLANK() hparallel.PARALLELx->TX_FIFO = 0
|
||||
|
||||
#define __TIMER_CLEAR_IQR(__TIMERx__) timer_int_clear(__TIMERx__)
|
||||
#define __TIMER_INIT(__TIMERx__, __LoadCount__) timer_init(__TIMERx__, (24000 * __LoadCount__))
|
||||
#define __TIMER_INT_ENABLE(__TIMERx__) timer_int_enable(__TIMERx__)
|
||||
#define __TIMER_START(__TIMERx__) timer_start(__TIMERx__)
|
||||
|
||||
#define __DMA_GET_TFR_STATUS() dma_get_tfr_Status(&dma_handle)
|
||||
#define __DMA_CLEAR_TFR_STATUS() dma_clear_tfr_Status(&dma_handle)
|
||||
#define __DMA_TO_8080_START_IT(__BUFFER__,__SIZE__) dma_start_IT(&dma_handle, (uint32_t)__BUFFER__, (uint32_t)&hparallel.PARALLELx->TX_FIFO, __SIZE__)
|
||||
|
||||
#define __SPI_WRITE_DATA(__BUFFER__, __SIZE__) spi_master_transmit_X1(&spi_handle, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* rgb_display_start */
|
||||
/* rgb_timer_IRQHandler */
|
||||
/* rgb_dma_IRQHandler */
|
||||
void rgb_init(void);
|
||||
void rgb_display_start(struct_Timer_t *TIMERx, struct_RGB_TypeDef_t *hrgb, uint32_t fps, unsigned char *Imagedata);
|
||||
void rgb_timer_IRQHandler(struct_Timer_t *TIMERx, struct_RGB_TypeDef_t *hrgb);
|
||||
void rgb_dma_IRQHandler(struct_RGB_TypeDef_t *hrgb);
|
||||
|
||||
#endif
|
||||
746
fr3092_mcu/components/drivers/bsp/spi_flash/IC_W25Qxx.c
Normal file
746
fr3092_mcu/components/drivers/bsp/spi_flash/IC_W25Qxx.c
Normal file
@ -0,0 +1,746 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file IC_W25Qxx.c
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief W25Qxx IC driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the spi norflash driver for W25Qxx.
|
||||
* @ Initialization and de-initialization functions
|
||||
* @ IO operation functions
|
||||
* @ Peripheral Control functions
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "IC_W25Qxx.h"
|
||||
|
||||
static void (*read_callback)(void) = NULL;
|
||||
|
||||
/*********************************************************************************
|
||||
* function : Read_IT_callback
|
||||
* Description : callback function used in read data with interrupt mode
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Owen Data : 2022
|
||||
**********************************************************************************/
|
||||
static void Read_IT_callback(SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__SPI_CS_Release();
|
||||
|
||||
if (read_callback)
|
||||
{
|
||||
read_callback();
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_WriteEnable
|
||||
* Description : Write Enable
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_WriteEnable(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = WRITE_ENABLE;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_WriteDisable
|
||||
* Description : Write Disable
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_WriteDisable(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = WRITE_DISABLE;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_WriteRegister
|
||||
* Description : Write status register
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_WriteRegister(uint8_t fu8_Register_S7_S0, uint8_t fu8_Register_S15_S08)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[3];
|
||||
|
||||
lu8_DataBuffer[0] = WRITE_STATUS_REGISTER;
|
||||
lu8_DataBuffer[1] = fu8_Register_S7_S0;
|
||||
lu8_DataBuffer[2] = fu8_Register_S15_S08;
|
||||
|
||||
/* Write Enable */
|
||||
IC_W25Qxx_WriteEnable();
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 3);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
/* Wait Write register End */
|
||||
IC_W25Qxx_WaitBusy();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_WriteHRegister
|
||||
* Description : Write high status register separately
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_WriteHRegister(uint8_t fu8_Register_S15_S08)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[2];
|
||||
|
||||
lu8_DataBuffer[0] = WRITE_STATUS_H_REGISTER;
|
||||
lu8_DataBuffer[1] = fu8_Register_S15_S08;
|
||||
|
||||
/* Write Enable */
|
||||
IC_W25Qxx_WriteEnable();
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 2);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
/* Wait Write register End */
|
||||
IC_W25Qxx_WaitBusy();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_ID
|
||||
* Description : Read Manufacture ID and Device ID
|
||||
* Input :
|
||||
* Output : Manufacture ID and Device ID
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
uint32_t IC_W25Qxx_Read_ID(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[4];
|
||||
|
||||
lu8_DataBuffer[0] = READ_ID;
|
||||
lu8_DataBuffer[1] = 0;
|
||||
lu8_DataBuffer[2] = 0;
|
||||
lu8_DataBuffer[3] = 0;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* Recieve Manufacture ID and Device ID */
|
||||
__SPI_Read_Data(lu8_DataBuffer, 3);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
return ((uint32_t)lu8_DataBuffer[0] << 16
|
||||
| (uint32_t)lu8_DataBuffer[1] << 8
|
||||
| (uint32_t)lu8_DataBuffer[2]);
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_RegisterS07_S00
|
||||
* Description : Read Status Register S07 ~ S00
|
||||
* Input :
|
||||
* Output : Status Register S07 ~ S00
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
uint8_t IC_W25Qxx_Read_RegisterS07_S00(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = READ_STATUS_REGISTER_S07_S00;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* Recieve Status Register S07 ~ S00 */
|
||||
__SPI_Read_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
return lu8_DataBuffer[0];
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_RegisterS15_S08
|
||||
* Description : Read Status Register S15 ~ S08
|
||||
* Input :
|
||||
* Output : Status Register S15 ~ S08
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
uint8_t IC_W25Qxx_Read_RegisterS15_S08(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = READ_STATUS_REGISTER_S15_S08;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* Recieve Status Register S15 ~ S08 */
|
||||
__SPI_Read_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
return lu8_DataBuffer[0];
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Data
|
||||
* Description : Read Data
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Data(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[4];
|
||||
|
||||
lu8_DataBuffer[0] = READ_DATA;
|
||||
lu8_DataBuffer[1] = (uint8_t)(fu32_DataAddress >> 16 & 0xFF);
|
||||
lu8_DataBuffer[2] = (uint8_t)(fu32_DataAddress >> 8 & 0xFF);
|
||||
lu8_DataBuffer[3] = (uint8_t)(fu32_DataAddress >> 0 & 0xFF);
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command and Recieve Data */
|
||||
__SPI_Read_flash_X1(lu8_DataBuffer, 4, pu8_Buffer, fu32_Length);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Data_IT
|
||||
* Description : Read Data
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Data_IT(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[4];
|
||||
|
||||
lu8_DataBuffer[0] = READ_DATA;
|
||||
lu8_DataBuffer[1] = (uint8_t)(fu32_DataAddress >> 16 & 0xFF);
|
||||
lu8_DataBuffer[2] = (uint8_t)(fu32_DataAddress >> 8 & 0xFF);
|
||||
lu8_DataBuffer[3] = (uint8_t)(fu32_DataAddress >> 0 & 0xFF);
|
||||
|
||||
spi_flash_handle.RxCpltCallback = Read_IT_callback;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command and Recieve Data */
|
||||
__SPI_Read_flash_X1_IT(lu8_DataBuffer, 4, pu8_Buffer, fu32_Length);
|
||||
// /* CS Realse */
|
||||
// __SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Data_DMA
|
||||
* Description : Read Data
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Data_DMA(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[4];
|
||||
|
||||
lu8_DataBuffer[0] = READ_DATA;
|
||||
lu8_DataBuffer[1] = (uint8_t)(fu32_DataAddress >> 16 & 0xFF);
|
||||
lu8_DataBuffer[2] = (uint8_t)(fu32_DataAddress >> 8 & 0xFF);
|
||||
lu8_DataBuffer[3] = (uint8_t)(fu32_DataAddress >> 0 & 0xFF);
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command and Recieve Data */
|
||||
__SPI_Read_flash_X1_DMA(lu8_DataBuffer, 4, fu32_Length);
|
||||
dma_start_IT(&dma_flash_handle, (uint32_t)&spi_flash_handle.SPIx->DR, (uint32_t)pu8_Buffer, fu32_Length);
|
||||
// /* CS Realse */
|
||||
// __SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Dual_Output
|
||||
* Description : Dual Output Fast Read
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Dual_Output(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X2;
|
||||
spi_flash_handle.MultWireParam.ReceiveWaitCycles = 8;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = DUAL_OUTPUT_FAST_READ;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send Data */
|
||||
__SPI_Read_Data_X2X4X8(pu8_Buffer, fu32_Length);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Dual_Output_IT
|
||||
* Description : Dual Output Fast Read with interrupt mode
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Dual_Output_IT(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X2;
|
||||
spi_flash_handle.MultWireParam.ReceiveWaitCycles = 8;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = DUAL_OUTPUT_FAST_READ;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
spi_flash_handle.RxCpltCallback = Read_IT_callback;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send Data */
|
||||
__SPI_Read_Data_X2X4X8_IT(pu8_Buffer, fu32_Length);
|
||||
// /* CS Realse */
|
||||
// __SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Dual_Output_DMA
|
||||
* Description : Dual Output Fast Read with DMA mode
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Dual_Output_DMA(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X2;
|
||||
spi_flash_handle.MultWireParam.ReceiveWaitCycles = 8;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = DUAL_OUTPUT_FAST_READ;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send Data */
|
||||
__SPI_Read_Data_X2X4X8_DMA(fu32_Length);
|
||||
dma_start_IT(&dma_flash_handle, (uint32_t)&spi_flash_handle.SPIx->DR, (uint32_t)pu8_Buffer, fu32_Length);
|
||||
// /* CS Realse */
|
||||
// __SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Quad_Output
|
||||
* Description : Quad Output Fast Read
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Quad_Output(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_flash_handle.MultWireParam.ReceiveWaitCycles = 8;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = QUAD_OUTPUT_FAST_READ;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send Data */
|
||||
__SPI_Read_Data_X2X4X8(pu8_Buffer, fu32_Length);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Quad_Output_IT
|
||||
* Description : Quad Output Fast Read
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Quad_Output_IT(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_flash_handle.MultWireParam.ReceiveWaitCycles = 8;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = QUAD_OUTPUT_FAST_READ;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
spi_flash_handle.RxCpltCallback = Read_IT_callback;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send Data */
|
||||
__SPI_Read_Data_X2X4X8_IT(pu8_Buffer, fu32_Length);
|
||||
// /* CS Realse */
|
||||
// __SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Read_Quad_Output_DMA
|
||||
* Description : Quad Output Fast Read
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Read_Quad_Output_DMA(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_flash_handle.MultWireParam.ReceiveWaitCycles = 8;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = QUAD_OUTPUT_FAST_READ;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send Data */
|
||||
__SPI_Read_Data_X2X4X8_DMA(fu32_Length);
|
||||
dma_start_IT(&dma_flash_handle, (uint32_t)&spi_flash_handle.SPIx->DR, (uint32_t)pu8_Buffer, fu32_Length);
|
||||
// /* CS Realse */
|
||||
// __SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_PageProgram
|
||||
* Description : Page Program
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_PageProgram(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[4];
|
||||
|
||||
lu8_DataBuffer[0] = PAGE_PROGARM;
|
||||
lu8_DataBuffer[1] = (uint8_t)(fu32_DataAddress >> 16 & 0xFF);
|
||||
lu8_DataBuffer[2] = (uint8_t)(fu32_DataAddress >> 8 & 0xFF);
|
||||
lu8_DataBuffer[3] = (uint8_t)(fu32_DataAddress >> 0 & 0xFF);
|
||||
|
||||
/* Write Enable */
|
||||
IC_W25Qxx_WriteEnable();
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 4);
|
||||
/* Send Data */
|
||||
__SPI_Write_Data(pu8_Buffer, fu32_Length);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
/* Wait Erase End */
|
||||
IC_W25Qxx_WaitBusy();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_PageProgram_Quad
|
||||
* Description : Quad Page Program
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_PageProgram_Quad(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X4;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = QUAD_PAGE_PROGRAM;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
/* Write Enable */
|
||||
IC_W25Qxx_WriteEnable();
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send Data */
|
||||
__SPI_Write_Data_X2X4X8(pu8_Buffer, fu32_Length);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
/* Wait Erase End */
|
||||
IC_W25Qxx_WaitBusy();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_EraseSector
|
||||
* Description : Erease The specific Sector
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_EraseSector(uint32_t fu32_DataAddress)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[4];
|
||||
|
||||
lu8_DataBuffer[0] = SECTOR_ERASE;
|
||||
lu8_DataBuffer[1] = (uint8_t)(fu32_DataAddress >> 16 & 0xFF);
|
||||
lu8_DataBuffer[2] = (uint8_t)(fu32_DataAddress >> 8 & 0xFF);
|
||||
lu8_DataBuffer[3] = (uint8_t)(fu32_DataAddress >> 0 & 0xFF);
|
||||
|
||||
/* Write Enable */
|
||||
IC_W25Qxx_WriteEnable();
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 4);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
/* Wait Erase End */
|
||||
IC_W25Qxx_WaitBusy();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_EraseChip
|
||||
* Description : Erease The Whole Chip
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_EraseChip(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = CHIP_ERASE;
|
||||
|
||||
/* Write Enable */
|
||||
IC_W25Qxx_WriteEnable();
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
/* Wait Erase End */
|
||||
IC_W25Qxx_WaitBusy();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_QuadConfig
|
||||
* Description : Quad Function Config
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_QuadConfig(bool fb_Config)
|
||||
{
|
||||
uint8_t lu8_CurrentState;
|
||||
|
||||
lu8_CurrentState = IC_W25Qxx_Read_RegisterS15_S08();
|
||||
|
||||
if (fb_Config == true)
|
||||
{
|
||||
/* Set W25Qxx Quad Enable */
|
||||
if ((lu8_CurrentState & REGISTER_S15_S08_QE) == 0)
|
||||
{
|
||||
// IC_W25Qxx_WriteRegister(REGISTER_NULL, REGISTER_S15_S08_QE);
|
||||
IC_W25Qxx_WriteHRegister(REGISTER_S15_S08_QE);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set W25Qxx Quad Disable */
|
||||
if (lu8_CurrentState & REGISTER_S15_S08_QE)
|
||||
{
|
||||
IC_W25Qxx_WriteRegister(REGISTER_NULL, REGISTER_NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_WaitBusy
|
||||
* Description : Wait IC Not Busy
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_WaitBusy(void)
|
||||
{
|
||||
/* Wait IC Not Busy */
|
||||
while(IC_W25Qxx_Read_RegisterS07_S00() & REGISTER_S07_S00_WIP);
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_PowerDown
|
||||
* Description :
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_PowerDown(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = DEEP_POWER_DOWN;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Wakeup
|
||||
* Description :
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Wakeup(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = RELEASE_FORM_DEEP_POWER_DOWN;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Reset
|
||||
* Description : W25Qxx Reset
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Reset(void)
|
||||
{
|
||||
uint8_t lu8_DataBuffer[1];
|
||||
|
||||
lu8_DataBuffer[0] = ENABLE_RESET;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
lu8_DataBuffer[0] = RESET;
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
/* Send command */
|
||||
__SPI_Write_Data(lu8_DataBuffer, 1);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Set_Read_Callback
|
||||
* Description : used to set read callback when unblock mode (IT, DMA) is used
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : owen Data : 2022
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Set_Read_Callback(void (*cb)(void))
|
||||
{
|
||||
read_callback = cb;
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_Spi_Interrupt
|
||||
* Description : SPI interrupt handler
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_Spi_Interrupt(void)
|
||||
{
|
||||
spi_master_IRQHandler(&spi_flash_handle);
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* function : IC_W25Qxx_DMA_Interrupt
|
||||
* Description : DMA interrupt handler
|
||||
* Input :
|
||||
* Output :
|
||||
* Author : Chris_Kyle Data : 2020
|
||||
**********************************************************************************/
|
||||
void IC_W25Qxx_DMA_Interrupt(void)
|
||||
{
|
||||
if (dma_get_tfr_Status(&dma_flash_handle)) {
|
||||
dma_clear_tfr_Status(&dma_flash_handle);
|
||||
|
||||
Read_IT_callback(NULL);
|
||||
}
|
||||
|
||||
if (dma_get_error_Status(&dma_flash_handle)) {
|
||||
dma_clear_error_Status(&dma_flash_handle);
|
||||
}
|
||||
}
|
||||
|
||||
void IC_W25Qxx_PageProgram_Dual(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length)
|
||||
{
|
||||
spi_flash_handle.MultWireParam.Wire_X2X4X8 = Wire_X2;
|
||||
spi_flash_handle.MultWireParam.InstructLength = INST_8BIT;
|
||||
spi_flash_handle.MultWireParam.Instruct = 0xA2;
|
||||
spi_flash_handle.MultWireParam.AddressLength = ADDR_24BIT;
|
||||
spi_flash_handle.MultWireParam.Address = fu32_DataAddress;
|
||||
|
||||
/* Write Enable */
|
||||
IC_W25Qxx_WriteEnable();
|
||||
|
||||
/* CS Select */
|
||||
__SPI_CS_Select();
|
||||
|
||||
/* Send Data */
|
||||
__SPI_Write_Data_X2X4X8(pu8_Buffer, fu32_Length);
|
||||
/* CS Realse */
|
||||
__SPI_CS_Release();
|
||||
|
||||
/* Wait Erase End */
|
||||
IC_W25Qxx_WaitBusy();
|
||||
}
|
||||
224
fr3092_mcu/components/drivers/bsp/spi_flash/IC_W25Qxx.h
Normal file
224
fr3092_mcu/components/drivers/bsp/spi_flash/IC_W25Qxx.h
Normal file
@ -0,0 +1,224 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file IC_W25Qxx.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief IC_W25Qxx Config header file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __IC_W25QXX_H__
|
||||
#define __IC_W25QXX_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "driver_spi.h"
|
||||
#include "driver_dma.h"
|
||||
|
||||
extern SPI_HandleTypeDef spi_flash_handle;
|
||||
extern DMA_HandleTypeDef dma_flash_handle;
|
||||
extern void spi_flash_cs_set(void);
|
||||
extern void spi_flash_cs_clear(void);
|
||||
|
||||
#define __SPI_CS_Release() spi_flash_cs_set()
|
||||
|
||||
#define __SPI_CS_Select() spi_flash_cs_clear()
|
||||
|
||||
#define __SPI_Read_Data(__BUFFER__, __SIZE__) spi_master_receive_X1(&spi_flash_handle, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
#define __SPI_Write_Data(__BUFFER__, __SIZE__) spi_master_transmit_X1(&spi_flash_handle, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
#define __SPI_Read_flash_X1(__CMD__, __CSIZE__, __BUFFER__, __SIZE__) spi_master_readflash_X1(&spi_flash_handle, (uint16_t *)__CMD__, __CSIZE__, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
#define __SPI_Read_flash_X1_IT(__CMD__, __CSIZE__, __BUFFER__, __SIZE__) spi_master_readflash_X1_IT(&spi_flash_handle, (uint8_t *)__CMD__, __CSIZE__, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
#define __SPI_Read_flash_X1_DMA(__CMD__, __CSIZE__, __SIZE__) spi_master_readflash_X1_DMA(&spi_flash_handle, (uint8_t *)__CMD__, __CSIZE__, __SIZE__)
|
||||
|
||||
#define __SPI_Write_Data_X2X4X8(__BUFFER__, __SIZE__) spi_master_transmit_X2X4X8(&spi_flash_handle, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
#define __SPI_Read_Data_X2X4X8(__BUFFER__, __SIZE__) spi_master_receive_X2X4X8(&spi_flash_handle, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
#define __SPI_Read_Data_X2X4X8_IT(__BUFFER__, __SIZE__) spi_master_receive_X2X4X8_IT(&spi_flash_handle, (void *)__BUFFER__, __SIZE__)
|
||||
|
||||
#define __SPI_Read_Data_X2X4X8_DMA(__SIZE__) spi_master_receive_X2X4X8_DMA(&spi_flash_handle, __SIZE__)
|
||||
|
||||
/*********************************************************************************
|
||||
One Block have 32K
|
||||
|
||||
Block Setor Address Range
|
||||
|
||||
17 0x011000 ~ 0x011FFF
|
||||
16 0x010000 ~ 0x010FFF
|
||||
15 0x00F000 ~ 0x00FFFF
|
||||
14 0x00E000 ~ 0x00EFFF
|
||||
1 13 0x00D000 ~ 0x00DFFF
|
||||
12 0x00C000 ~ 0x00CFFF
|
||||
11 0x00B000 ~ 0x00BFFF
|
||||
10 0x00A000 ~ 0x00AFFF
|
||||
9 0x009000 ~ 0x009FFF
|
||||
|
||||
8 0x008000 ~ 0x008FFF
|
||||
7 0x007000 ~ 0x007FFF
|
||||
6 0x006000 ~ 0x006FFF
|
||||
5 0x005000 ~ 0x005FFF
|
||||
0 4 0x004000 ~ 0x004FFF
|
||||
3 0x003000 ~ 0x003FFF
|
||||
2 0x002000 ~ 0x002FFF
|
||||
1 0x001000 ~ 0x001FFF
|
||||
0 0x000000 ~ 0x000FFF
|
||||
**********************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief W25Qxx Size
|
||||
*/
|
||||
#define W25QXX_PAGE_SIZE (256U) // Each Page has 256 Bytes
|
||||
#define W25QXX_SECTOR_SIZE (4096U) // Each Sector has 4k
|
||||
|
||||
/**
|
||||
* @brief W25Qxx Command Descriptions
|
||||
*/
|
||||
#define WRITE_ENABLE (0x06)
|
||||
#define WRITE_DISABLE (0x04)
|
||||
#define READ_STATUS_REGISTER_S07_S00 (0x05)
|
||||
#define READ_STATUS_REGISTER_S15_S08 (0x35)
|
||||
#define WRITE_STATUS_REGISTER (0x01)
|
||||
#define WRITE_STATUS_H_REGISTER (0x31)
|
||||
#define WRITE_ENABLE_VOLATILE_STATUS_REGISTER (0x50)
|
||||
#define READ_DATA (0x03)
|
||||
#define READ_DATA_FAST (0x0B)
|
||||
#define DUAL_OUTPUT_FAST_READ (0x3B)
|
||||
#define QUAD_OUTPUT_FAST_READ (0x6B)
|
||||
#define DUAL_IO_FAST_READ (0xBB)
|
||||
#define QUAD_IO_FAST_READ (0xEB)
|
||||
#define SET_BURST_WITH_WRAP (0x77)
|
||||
#define PAGE_PROGARM (0x02)
|
||||
#define QUAD_PAGE_PROGRAM (0x32)
|
||||
#define SECTOR_ERASE (0x20)
|
||||
#define BLOCK_ERASE_32K (0x52)
|
||||
#define BLOCK_ERASE_64K (0x52)
|
||||
#define CHIP_ERASE (0xC7)
|
||||
#define READ_DEVICE_ID (0x90)
|
||||
#define READ_ID (0x9F)
|
||||
#define READ_UNIQUE_ID (0x4B)
|
||||
#define ERASE_SECURITY_REGISTER (0x44)
|
||||
#define PROGRAM_SECURITY_REGISTER (0x42)
|
||||
#define READ_SECURITY_REGISTER (0x48)
|
||||
#define ENABLE_RESET (0x66)
|
||||
#define RESET (0x99)
|
||||
#define PROGRAM_ERASE_SUSPEND (0x75)
|
||||
#define PROGRAM_ERASE_RESUME (0x7A)
|
||||
#define DEEP_POWER_DOWN (0xB9)
|
||||
#define RELEASE_FORM_DEEP_POWER_DOWN (0xAB)
|
||||
#define READ_DATA_COMPATIBILITY (0x5A)
|
||||
|
||||
/**
|
||||
* @brief W25Qxx Stauts Register
|
||||
*/
|
||||
#define REGISTER_NULL (0)
|
||||
|
||||
#define REGISTER_S07_S00_SRP0 (1 << 7)
|
||||
#define REGISTER_S07_S00_BP4 (1 << 6)
|
||||
#define REGISTER_S07_S00_BP3 (1 << 5)
|
||||
#define REGISTER_S07_S00_BP2 (1 << 4)
|
||||
#define REGISTER_S07_S00_BP1 (1 << 3)
|
||||
#define REGISTER_S07_S00_BP0 (1 << 2)
|
||||
#define REGISTER_S07_S00_WEL (1 << 1)
|
||||
#define REGISTER_S07_S00_WIP (1 << 0)
|
||||
|
||||
#define REGISTER_S15_S08_SUS (1 << 7)
|
||||
#define REGISTER_S15_S08_CMP (1 << 6)
|
||||
#define REGISTER_S15_S08_NULL (1 << 5)
|
||||
#define REGISTER_S15_S08_DC (1 << 4)
|
||||
#define REGISTER_S15_S08_LB1 (1 << 3)
|
||||
#define REGISTER_S15_S08_LB0 (1 << 2)
|
||||
#define REGISTER_S15_S08_QE (1 << 1) // Quad Enable
|
||||
#define REGISTER_S15_S08_SRP1 (1 << 0)
|
||||
|
||||
/* Function : IC_W25Qxx_WriteEnable */
|
||||
void IC_W25Qxx_WriteEnable(void);
|
||||
|
||||
/* Function : IC_W25Qxx_WriteDisable */
|
||||
void IC_W25Qxx_WriteDisable(void);
|
||||
|
||||
/* Function : IC_W25Qxx_WriteRegister */
|
||||
void IC_W25Qxx_WriteRegister(uint8_t fu8_Register_S7_S0, uint8_t fu8_Register_S15_S08);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_ID */
|
||||
uint32_t IC_W25Qxx_Read_ID(void);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_RegisterS07_S00 */
|
||||
uint8_t IC_W25Qxx_Read_RegisterS07_S00(void);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_RegisterS15_S08 */
|
||||
uint8_t IC_W25Qxx_Read_RegisterS15_S08(void);
|
||||
|
||||
/* Function : IC_W25Qxx_Read */
|
||||
void IC_W25Qxx_Read_Data(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read with interrupt mode */
|
||||
void IC_W25Qxx_Read_Data_IT(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read with DMA mode */
|
||||
void IC_W25Qxx_Read_Data_DMA(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_Dual_Output */
|
||||
void IC_W25Qxx_Read_Dual_Output(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_Dual_Output_IT with interrupt mode */
|
||||
void IC_W25Qxx_Read_Dual_Output_IT(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_Dual_Output_DMA with DMA mode */
|
||||
void IC_W25Qxx_Read_Dual_Output_DMA(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_Quad_Output */
|
||||
void IC_W25Qxx_Read_Quad_Output(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_Quad_Output with interrupt mode */
|
||||
void IC_W25Qxx_Read_Quad_Output_IT(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_Quad_Output with DMA mode */
|
||||
void IC_W25Qxx_Read_Quad_Output_DMA(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_PageProgram */
|
||||
void IC_W25Qxx_PageProgram(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_PageProgram_Quad */
|
||||
void IC_W25Qxx_PageProgram_Quad(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
|
||||
/* Function : IC_W25Qxx_EraseSector */
|
||||
void IC_W25Qxx_EraseSector(uint32_t fu32_DataAddress);
|
||||
|
||||
/* Function : IC_W25Qxx_EraseChip */
|
||||
void IC_W25Qxx_EraseChip(void);
|
||||
|
||||
/* Function : IC_W25Qxx_QuadConfig */
|
||||
void IC_W25Qxx_QuadConfig(bool fb_Config);
|
||||
|
||||
/* Function : IC_W25Qxx_WaitBusy */
|
||||
void IC_W25Qxx_WaitBusy(void);
|
||||
|
||||
/* Function : IC_W25Qxx_Reset */
|
||||
void IC_W25Qxx_Reset(void);
|
||||
|
||||
/* Function : IC_W25Qxx_PowerDown */
|
||||
void IC_W25Qxx_PowerDown(void);
|
||||
|
||||
/* Function : IC_W25Qxx_Wakeup */
|
||||
void IC_W25Qxx_Wakeup(void);
|
||||
|
||||
/* Function : IC_W25Qxx_Read_Set_Callback */
|
||||
void IC_W25Qxx_Set_Read_Callback(void (*cb)(void));
|
||||
|
||||
/* Function : IC_W25Qxx_Spi_Interrupt */
|
||||
void IC_W25Qxx_Spi_Interrupt(void);
|
||||
|
||||
/* Function : IC_W25Qxx_DMA_Interrupt */
|
||||
void IC_W25Qxx_DMA_Interrupt(void);
|
||||
void IC_W25Qxx_PageProgram_Dual(uint8_t *pu8_Buffer, uint32_t fu32_DataAddress, uint32_t fu32_Length);
|
||||
#endif
|
||||
132
fr3092_mcu/components/drivers/bsp/spi_flash/ext_flash.c
Normal file
132
fr3092_mcu/components/drivers/bsp/spi_flash/ext_flash.c
Normal file
@ -0,0 +1,132 @@
|
||||
|
||||
#include "ext_flash.h"
|
||||
#include "driver_gpio.h"
|
||||
#include "driver_spi.h"
|
||||
#include "driver_dma.h"
|
||||
#include "IC_W25Qxx.h"
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern SPI_HandleTypeDef spi_flash_handle;
|
||||
extern DMA_HandleTypeDef dma_flash_handle;
|
||||
|
||||
|
||||
void ext_flash_gpio_init(void)
|
||||
{
|
||||
/* ========================================================== */
|
||||
/* ========= External Flash interface configuration ======== */
|
||||
/* ========================================================== */
|
||||
GPIO_InitTypeDef gpio_config;
|
||||
|
||||
/* config GPIO for external flash */
|
||||
gpio_config.Pin = GPIO_PIN_8 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
|
||||
gpio_config.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_config.Pull = GPIO_PULLUP;
|
||||
gpio_config.Alternate = GPIO_FUNCTION_7;
|
||||
gpio_init(GPIOC, &gpio_config);
|
||||
|
||||
/* CS of external flash is controllerd by software */
|
||||
__SYSTEM_GPIOC_CLK_ENABLE();
|
||||
gpio_config.Pin = GPIO_PIN_9;
|
||||
gpio_config.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
gpio_config.Pull = GPIO_PULLUP;
|
||||
gpio_config.Alternate = GPIO_FUNCTION_0;
|
||||
gpio_init(GPIOC, &gpio_config);
|
||||
}
|
||||
|
||||
void ext_flash_dma_init(void)
|
||||
{
|
||||
/* config DMA0 for external flash */
|
||||
__SYSTEM_DMA0_CLK_ENABLE();
|
||||
dma_flash_handle.DMAx = DMA0;
|
||||
dma_flash_handle.Channel = DMA_Channel0;
|
||||
dma_flash_handle.Init.Data_Flow = DMA_P2M_DMAC;
|
||||
dma_flash_handle.Init.Request_ID = 2;
|
||||
system_dmac_request_id_config(SPIMX8_1_RX, DMA0_REQUEST_ID_2);
|
||||
dma_flash_handle.Init.Source_Master_Sel = DMA_AHB_MASTER_1;
|
||||
dma_flash_handle.Init.Desination_Master_Sel = DMA_AHB_MASTER_4;
|
||||
dma_flash_handle.Init.Source_Inc = DMA_ADDR_INC_NO_CHANGE;
|
||||
dma_flash_handle.Init.Desination_Inc = DMA_ADDR_INC_INC;
|
||||
dma_flash_handle.Init.Source_Width = DMA_TRANSFER_WIDTH_32;
|
||||
dma_flash_handle.Init.Desination_Width = DMA_TRANSFER_WIDTH_32;
|
||||
dma_flash_handle.Init.Source_Burst_Len = DMA_BURST_LEN_4;
|
||||
dma_flash_handle.Init.Desination_Burst_Len = DMA_BURST_LEN_4;
|
||||
dma_init(&dma_flash_handle);
|
||||
}
|
||||
|
||||
void ext_flash_controler_init(void)
|
||||
{
|
||||
/* Initial SPIx8_1 for extern flash */
|
||||
__SYSTEM_SPI_MASTER1_X8_CLK_ENABLE();
|
||||
spi_flash_handle.SPIx = SPIMX8_1;
|
||||
spi_flash_handle.Init.Work_Mode = SPI_WORK_MODE_3;
|
||||
spi_flash_handle.Init.Frame_Size = SPI_FRAME_SIZE_8BIT;
|
||||
spi_flash_handle.Init.BaudRate_Prescaler = 2;
|
||||
spi_flash_handle.Init.TxFIFOEmpty_Threshold = 20;
|
||||
spi_flash_handle.Init.RxFIFOFull_Threshold = 0;
|
||||
spi_master_init(&spi_flash_handle);
|
||||
// __SPI_RX_SAMPLE_DLY(spi_flash_handle.SPIx, 2);
|
||||
spi_flash_cs_set();
|
||||
|
||||
IC_W25Qxx_QuadConfig(true);
|
||||
|
||||
NVIC_EnableIRQ(DMA0_IRQn);
|
||||
NVIC_EnableIRQ(SPIMX8_1_IRQn);
|
||||
}
|
||||
|
||||
void ext_flash_device_init(void)
|
||||
{
|
||||
ext_flash_gpio_init();
|
||||
ext_flash_dma_init();
|
||||
ext_flash_controler_init();
|
||||
}
|
||||
|
||||
uint32_t ext_flash_get_id(void)
|
||||
{
|
||||
return IC_W25Qxx_Read_ID();
|
||||
}
|
||||
|
||||
// void spi_flash_cs_set(void)
|
||||
// {
|
||||
// gpio_write_pin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET);
|
||||
// }
|
||||
|
||||
// void spi_flash_cs_clear(void)
|
||||
// {
|
||||
// gpio_write_pin(GPIOC, GPIO_PIN_9, GPIO_PIN_CLEAR);
|
||||
// }
|
||||
|
||||
void ext_flash_erase(uint32_t addr, uint32_t len)
|
||||
{
|
||||
for (int i = 0; i < len; i += 4096)
|
||||
{
|
||||
IC_W25Qxx_EraseSector(addr + i);
|
||||
}
|
||||
}
|
||||
|
||||
void ext_flash_chip_erase(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void ext_flash_protect_enable(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void ext_flash_protect_disable(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
uint8_t ext_flash_read(uint32_t addr, int len,uint8_t* buffer)
|
||||
{
|
||||
IC_W25Qxx_Read_Data(buffer, addr, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t ext_flash_write(uint32_t addr, int len,uint8_t* buffer)
|
||||
{
|
||||
IC_W25Qxx_PageProgram(buffer, addr, len);
|
||||
return 0;
|
||||
}
|
||||
27
fr3092_mcu/components/drivers/bsp/spi_flash/ext_flash.h
Normal file
27
fr3092_mcu/components/drivers/bsp/spi_flash/ext_flash.h
Normal file
@ -0,0 +1,27 @@
|
||||
#ifndef __EXT_FLASH__
|
||||
#define __EXT_FLASH__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void ext_flash_device_init(void);
|
||||
uint32_t ext_flash_get_id(void);
|
||||
void spi_flash_cs_set(void);
|
||||
void spi_flash_cs_clear(void);
|
||||
|
||||
void ext_flash_erase(uint32_t addr, uint32_t len);
|
||||
void ext_flash_chip_erase(void);
|
||||
void ext_flash_protect_enable(void);
|
||||
void ext_flash_protect_disable(void);
|
||||
uint8_t ext_flash_read(uint32_t addr, int len,uint8_t* buffer);
|
||||
uint8_t ext_flash_write(uint32_t addr, int len,uint8_t* buffer);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EXT_FLASH__ */
|
||||
2243
fr3092_mcu/components/drivers/bsp/touchpad/chsc5816_ctp.h
Normal file
2243
fr3092_mcu/components/drivers/bsp/touchpad/chsc5816_ctp.h
Normal file
File diff suppressed because it is too large
Load Diff
1064
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_comp.c
Normal file
1064
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_comp.c
Normal file
File diff suppressed because it is too large
Load Diff
41
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_comp.h
Normal file
41
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_comp.h
Normal file
@ -0,0 +1,41 @@
|
||||
#ifndef __CHSC6X_COMP_H__
|
||||
#define __CHSC6X_COMP_H__
|
||||
|
||||
struct ts_fw_infos {
|
||||
unsigned short chsc6x_cfg_version; //customer read
|
||||
unsigned short chsc6x_boot_version; //customer read
|
||||
unsigned short chsc6x_vendor_id; //customer read
|
||||
unsigned short chsc6x_project_id; //customer read
|
||||
unsigned short chsc6x_chip_id; //customer read
|
||||
unsigned short chsc6x_chip_type; //customer read
|
||||
unsigned short chsc6x_rpt_lcd_x; //customer read must after chsc6x_get_chip_info
|
||||
unsigned short chsc6x_rpt_lcd_y; //customer read must after chsc6x_get_chip_info
|
||||
unsigned short chsc6x_max_pt_num; //customer read must after chsc6x_get_chip_info
|
||||
};
|
||||
|
||||
|
||||
/* FUNC In your systerm init process,Must call this interface function to detec if the TP IC is Chipsemi corp'.
|
||||
* PARM pfw_infos: to get top 5 fw info in struct ts_fw_infos.
|
||||
* PARM update_ret_flag: point value=1 update succeed; point value=0 update failed, If opend CHSC6X_AUTO_UPGRADE macro.
|
||||
* RETURN 1:is chsc chip, 0:is not chsc chip
|
||||
*/
|
||||
extern int chsc6x_tp_dect(struct ts_fw_infos *pfw_infos, unsigned char *update_ret_flag);
|
||||
|
||||
|
||||
/* FUNC You can call this interfacce function to realize upgrade TP Firmware by OTA.
|
||||
* PARM pfw_infos: to get top 6 fw infos in struct ts_fw_infos, after ota upgrade.
|
||||
* PARM p_fw_upd: array address of the upgrade firmware array
|
||||
* PARM fw_len: total size of the upgrade firmware array
|
||||
* RETURN NULL
|
||||
*/
|
||||
extern void chsc6x_ota_upgrade_tp_fw(struct ts_fw_infos *pfw_infos, unsigned char* p_fw_upd, unsigned int fw_len);
|
||||
|
||||
|
||||
/* FUNC: get fw info in struct ts_fw_infos you can call this func anytime.
|
||||
* PARM pfw_infos: can get all fw infos in struct ts_fw_infos, after call this interface.
|
||||
* RETURN NULL
|
||||
*/
|
||||
extern void chsc6x_get_chip_info(struct ts_fw_infos *infos);
|
||||
|
||||
|
||||
#endif
|
||||
895
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_flash_boot.h
Normal file
895
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_flash_boot.h
Normal file
@ -0,0 +1,895 @@
|
||||
#ifndef __CHSC6X_FLASH_BOOT_H__
|
||||
#define __CHSC6X_FLASH_BOOT_H__
|
||||
|
||||
const unsigned char chsc_boot[] = {
|
||||
0x43,0x48,0x53,0x43,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
|
||||
0xCC,0x00,0x00,0x00,0x8C,0x36,0x00,0x00,0x01,0xC6,0x0E,0x00,0x01,0xC6,0x0E,0x08,
|
||||
0x01,0x3C,0x02,0x93,0x1B,0x02,0x02,0x00,0x00,0x01,0x0F,0x01,0x13,0x0F,0x43,0x0A,
|
||||
0x0A,0x16,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0D,0x10,0x0C,0x00,0x00,0x00,
|
||||
0x00,0x0B,0x08,0x03,0x01,0x04,0x05,0x09,0x02,0x06,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x07,0x0A,0x0F,0x0E,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x18,0x45,0x91,0x02,0x38,0x00,0x72,0x01,0x72,0x01,0x50,0x00,0xF0,0x00,
|
||||
0x90,0x01,0x00,0x02,0x84,0x03,0x20,0x10,0x78,0x78,0x78,0x78,0x64,0x40,0x08,0x84,
|
||||
0x08,0x1E,0x26,0x23,0x28,0x26,0x5C,0x0B,0x90,0x08,0x46,0x46,0x23,0x23,0x65,0xBD,
|
||||
0x1B,0x06,0x11,0x20,0x03,0x19,0x84,0xAF,0x9E,0x40,0x91,0x01,0xC8,0x60,0x2C,0x2D,
|
||||
0x25,0x11,0x32,0x6A,0x80,0x32,0x21,0x46,0xC8,0x28,0xDA,0x6B,0x59,0x05,0x84,0xA2,
|
||||
0x26,0x06,0x33,0x08,0x22,0x06,0x2B,0x08,0xF7,0x05,0x07,0x08,0x3E,0x06,0x95,0x08,
|
||||
0x00,0x00,0x34,0x2D,0x34,0x2D,0x00,0x00,0x00,0x00,0xD6,0x02,0x0E,0x00,0x08,0x08,
|
||||
0x28,0x10,0x32,0x03,0x51,0x32,0x01,0x21,0x19,0x19,0x11,0x12,0x13,0x13,0x11,0x19,
|
||||
0x1A,0x1A,0x1D,0x1B,0x1A,0x19,0x19,0x82,0x08,0x80,0x36,0x35,0x2D,0x02,0x88,0x36,
|
||||
0xBD,0x4E,0x4C,0x54,0x40,0x00,0x88,0x00,0x4A,0x80,0xC0,0x46,0x00,0xA0,0x20,0x09,
|
||||
0x20,0x0A,0x08,0x50,0x04,0xB1,0x91,0x02,0xFB,0xCB,0x13,0x08,0xC0,0x6B,0x14,0x08,
|
||||
0x85,0x06,0x12,0x08,0xC0,0x6B,0x13,0x08,0x85,0x06,0x1B,0x08,0x1B,0x09,0x10,0x0A,
|
||||
0x08,0x50,0x04,0xB1,0x91,0x02,0xFB,0xCB,0x10,0x09,0x11,0x0A,0x00,0xA0,0x08,0x50,
|
||||
0x04,0xB1,0x91,0x02,0xFB,0xCD,0x0C,0x09,0x04,0xA0,0x08,0x40,0x05,0xA0,0x48,0x40,
|
||||
0x0C,0x09,0x0D,0x0A,0x0D,0x0B,0x08,0x58,0x10,0x50,0x04,0xB1,0x04,0xB2,0x9A,0x02,
|
||||
0xF9,0xCB,0x01,0x90,0x19,0x9C,0xC0,0x46,0x12,0x00,0x00,0x00,0x13,0x00,0x00,0x00,
|
||||
0xFC,0x9D,0x80,0x00,0xFC,0x9C,0x80,0x00,0x0C,0x06,0x80,0x00,0x00,0x84,0x80,0x00,
|
||||
0x00,0x85,0x80,0x00,0x10,0x36,0x00,0x00,0x04,0x8D,0x80,0x00,0x7C,0x8D,0x80,0x00,
|
||||
0x00,0x84,0x80,0x00,0x00,0xA0,0x80,0x00,0xCE,0xFA,0xAD,0xDE,0xE0,0x93,0x80,0x00,
|
||||
0x00,0x65,0x0F,0x64,0xD8,0x6B,0x01,0x64,0xF0,0x64,0x4F,0x06,0x56,0x06,0x5D,0x06,
|
||||
0x64,0x06,0xF0,0x64,0x44,0x06,0x10,0x64,0x00,0x90,0x10,0x99,0x10,0x6C,0xA0,0x06,
|
||||
0xF0,0x6C,0xB9,0x06,0xB2,0x06,0xAB,0x06,0xA4,0x06,0xF0,0x6C,0x01,0x6C,0xD0,0x6B,
|
||||
0x0F,0x6C,0x00,0x69,0x00,0x00,0x00,0x00,0x03,0xA2,0x05,0x80,0x01,0xA2,0x03,0x80,
|
||||
0x02,0xA2,0x01,0x80,0x00,0xA2,0xFF,0x87,0xCB,0x6B,0x18,0x64,0x80,0xA4,0x23,0x03,
|
||||
0xC3,0x6B,0x09,0x0B,0x18,0x50,0x04,0xB3,0x19,0x50,0x08,0xBB,0x1A,0x40,0x18,0x48,
|
||||
0x00,0xA8,0xFC,0xC1,0x01,0xAA,0x02,0xC9,0x08,0xB3,0x18,0x58,0x01,0x80,0x04,0xB3,
|
||||
0x18,0x58,0x18,0x6C,0xC3,0x6B,0x70,0x07,0x64,0x06,0x80,0x00,0x60,0x06,0x80,0x00,
|
||||
0x68,0x06,0x80,0x00,0xC0,0x46,0xC0,0x46,0x01,0x08,0x08,0x01,0x01,0x08,0x08,0x01,
|
||||
0x00,0xFA,0xAA,0x00,0x00,0xFA,0xB4,0x00,0x01,0x08,0x08,0x01,0x01,0x08,0x08,0x01,
|
||||
0x00,0xFA,0xAA,0x00,0x00,0xFA,0xB4,0x00,0x01,0x08,0x08,0x01,0x01,0x08,0x08,0x01,
|
||||
0x00,0xFA,0xAA,0x00,0x00,0xFA,0xB4,0x00,0x01,0x08,0x08,0x01,0x01,0x08,0x08,0x01,
|
||||
0x00,0xFA,0xAA,0x00,0x00,0xFA,0xB4,0x00,0x70,0x65,0x00,0x90,0x67,0x99,0x24,0x0B,
|
||||
0x00,0xA2,0x1A,0x40,0x23,0x0A,0xB9,0xA1,0x11,0x40,0x1A,0x48,0x00,0xAA,0xFC,0xC1,
|
||||
0x1F,0x0B,0x01,0xA2,0x1A,0x40,0x20,0x0C,0x20,0x0E,0x81,0xA5,0x06,0xA1,0x06,0xA0,
|
||||
0x00,0x90,0x5A,0x98,0x0B,0xA0,0x01,0xA1,0x00,0x90,0x56,0x98,0x25,0x40,0x20,0xA3,
|
||||
0xC0,0x06,0x01,0xBB,0x00,0xAB,0xFB,0xC1,0x66,0xA2,0x32,0x40,0x18,0x09,0x4A,0x4E,
|
||||
0x01,0xAA,0x09,0xC1,0x17,0x09,0x0B,0x40,0x03,0xB1,0x0B,0x40,0x16,0x0B,0x02,0xA1,
|
||||
0x19,0x40,0x09,0xBB,0x1A,0x40,0x07,0x80,0x4B,0x4E,0x00,0xAB,0x04,0xC0,0x06,0xA0,
|
||||
0x00,0x90,0x24,0x98,0x04,0xA8,0xD9,0xC0,0x09,0x0B,0x00,0xA2,0x1A,0x40,0x09,0x0A,
|
||||
0xAB,0xA1,0x11,0x40,0x1A,0x48,0x00,0xAA,0xFC,0xC1,0x05,0x0B,0x01,0xA2,0x1A,0x40,
|
||||
0x20,0xA3,0xC0,0x06,0x01,0xBB,0x00,0xAB,0xFB,0xC1,0x00,0x90,0x5F,0x99,0x70,0x6D,
|
||||
0x0D,0x00,0x80,0x00,0x0C,0x00,0x80,0x00,0x67,0x00,0x80,0x00,0x0F,0x04,0x80,0x00,
|
||||
0x2C,0x8F,0x80,0x00,0x06,0x04,0x80,0x00,0x09,0x02,0x80,0x00,0x00,0xF6,0x80,0xA3,
|
||||
0xDB,0xF3,0x00,0xFE,0xC0,0xE8,0x05,0x0B,0x05,0x0A,0x18,0x50,0x01,0xA3,0x11,0x48,
|
||||
0x0B,0x02,0xFC,0xC1,0x03,0x0B,0x18,0x48,0x70,0x07,0xC0,0x46,0xB8,0x00,0x80,0x00,
|
||||
0xBA,0x00,0x80,0x00,0xB9,0x00,0x80,0x00,0x00,0xF6,0xC0,0xA3,0xDB,0xF3,0x00,0xFE,
|
||||
0x09,0xF6,0xC0,0xE8,0x09,0xFC,0x04,0x0B,0x40,0xE8,0x04,0x0A,0x18,0x50,0x01,0xA3,
|
||||
0x11,0x48,0x0B,0x02,0xFC,0xC1,0x70,0x07,0xB8,0x00,0x80,0x00,0xBA,0x00,0x80,0x00,
|
||||
0x70,0x65,0x0B,0x0A,0x0B,0x0B,0x28,0xB2,0x15,0x48,0x40,0xB3,0x80,0xA2,0x0A,0x09,
|
||||
0xED,0xE8,0x0A,0x0C,0x12,0xF1,0x07,0x80,0x1E,0x48,0xB6,0xF0,0x36,0x19,0x96,0xEB,
|
||||
0x46,0x03,0x01,0xB3,0x0E,0x20,0x02,0xB1,0xAB,0x02,0xF5,0xC1,0x70,0x6D,0xC0,0x46,
|
||||
0x6C,0x90,0x80,0x00,0x00,0x8E,0x80,0x00,0xFC,0x90,0x80,0x00,0x80,0x8D,0x80,0x00,
|
||||
0x07,0x0A,0x00,0xA3,0x53,0x45,0x93,0x45,0x06,0x0A,0x13,0x40,0x03,0xB2,0x13,0x40,
|
||||
0x05,0x0B,0x02,0xA2,0x1A,0x40,0x01,0xA2,0x09,0xBB,0x1A,0x40,0x70,0x07,0xC0,0x46,
|
||||
0x2C,0x8F,0x80,0x00,0x06,0x04,0x80,0x00,0x09,0x02,0x80,0x00,0x00,0x65,0x05,0x0B,
|
||||
0x1A,0x58,0x08,0xBB,0x1B,0x58,0x13,0x00,0x5A,0xF4,0x01,0xC5,0x00,0x90,0x6C,0x98,
|
||||
0x00,0x6D,0xC0,0x46,0x48,0x06,0x80,0x00,0xF0,0x65,0x02,0xEC,0x00,0xA4,0x00,0xA3,
|
||||
0x40,0xA0,0x07,0x0E,0x09,0x80,0x15,0x28,0xA5,0x02,0x04,0xC9,0xF7,0x1C,0x00,0xAF,
|
||||
0x01,0xC1,0x2C,0xEC,0x18,0xEC,0x01,0xB3,0x02,0xB2,0x8B,0x02,0xF3,0xCB,0xF0,0x6D,
|
||||
0x80,0x92,0x80,0x00,0x80,0xEA,0xC9,0xEA,0x02,0xEC,0x0B,0xEC,0x50,0x03,0x59,0x03,
|
||||
0x08,0xE8,0x70,0x07,0x30,0x65,0x05,0xEC,0x1C,0xEC,0xAA,0x02,0x0A,0xC0,0x03,0x38,
|
||||
0x59,0xEA,0x80,0xEA,0x48,0x03,0x51,0xEB,0xFF,0x97,0xC8,0x9E,0x01,0xE9,0x00,0xA9,
|
||||
0x00,0xCC,0x01,0xA1,0x09,0xF4,0x08,0xE4,0x30,0x6D,0x10,0x65,0x00,0xA4,0x03,0x1F,
|
||||
0x01,0xA0,0x93,0x02,0x04,0xCB,0x89,0xEA,0xD8,0xE7,0xCA,0xFF,0x8B,0x02,0x50,0x01,
|
||||
0x10,0x6D,0x10,0x65,0x04,0x58,0x03,0xEC,0x94,0x02,0x01,0xCA,0x02,0x50,0x04,0x80,
|
||||
0x89,0xEA,0x00,0xA0,0x8C,0x02,0x01,0xCB,0x19,0x50,0x01,0xA0,0x10,0x6D,0x92,0xF8,
|
||||
0x00,0xA3,0x01,0x80,0x02,0xD0,0x01,0xB3,0x93,0x02,0xFB,0xC3,0x70,0x07,0x10,0x65,
|
||||
0x00,0xA3,0x02,0x80,0x10,0xD9,0x10,0xD0,0x01,0xB3,0x93,0x02,0xFA,0xC3,0x10,0x6D,
|
||||
0x04,0x0B,0x1B,0x58,0x18,0xEA,0x4B,0xF0,0x59,0xE8,0xC9,0xF0,0x81,0x02,0x80,0x01,
|
||||
0x40,0x02,0x70,0x07,0x34,0x06,0x80,0x00,0x10,0x65,0x12,0x0B,0x03,0xA2,0x1A,0x40,
|
||||
0x11,0x0C,0x63,0x4E,0x00,0xAB,0x0E,0xC1,0x02,0xA0,0x00,0x90,0x81,0x9B,0xA3,0x4D,
|
||||
0x0E,0xAB,0x0B,0xC8,0x0D,0x0B,0x01,0xA2,0x1A,0x40,0xA3,0x4D,0x01,0xB3,0x1B,0xF6,
|
||||
0x1B,0xFE,0xA3,0x45,0x04,0x80,0x04,0xA0,0xFF,0x97,0x3A,0x9F,0x01,0xA3,0x63,0x45,
|
||||
0x05,0x0B,0x5B,0x4D,0x01,0xAB,0x03,0xC1,0x05,0x0A,0x13,0x40,0x03,0xB2,0x13,0x40,
|
||||
0x10,0x6D,0xC0,0x46,0x09,0x02,0x80,0x00,0x2C,0x8F,0x80,0x00,0x00,0x02,0x80,0x00,
|
||||
0x06,0x04,0x80,0x00,0x04,0x0A,0x80,0xA3,0x10,0x58,0x11,0x58,0x5B,0xF4,0x19,0x03,
|
||||
0x18,0x00,0x11,0x50,0x70,0x07,0xC0,0x46,0x40,0x06,0x80,0x00,0x10,0x65,0x04,0xEC,
|
||||
0x00,0x90,0x88,0x9B,0x03,0xA1,0x02,0xA0,0xFF,0x97,0xFE,0x9E,0x17,0x0A,0x18,0x0B,
|
||||
0x00,0xA1,0x1A,0x20,0x14,0xA0,0xFF,0x97,0xF7,0x9E,0x06,0xA1,0x11,0xA0,0xFF,0x97,
|
||||
0xF3,0x9E,0x01,0xA1,0x05,0xA0,0xFF,0x97,0xEF,0x9E,0x21,0xF6,0x09,0xFE,0x08,0xA0,
|
||||
0xFF,0x97,0xEA,0x9E,0x21,0xF4,0x09,0xFE,0x24,0xF2,0x09,0xA0,0xFF,0x97,0xE4,0x9E,
|
||||
0x21,0xFE,0x0A,0xA0,0xFF,0x97,0xE0,0x9E,0x0A,0x0A,0x01,0xA3,0x13,0x40,0x03,0xB2,
|
||||
0x13,0x40,0x09,0x0B,0x66,0xA2,0x1A,0x40,0x01,0xA1,0x01,0xA0,0xFF,0x97,0xD4,0x9E,
|
||||
0x6C,0xA1,0x00,0xA0,0xFF,0x97,0xD0,0x9E,0x10,0x6D,0xC0,0x46,0x01,0x01,0x00,0x00,
|
||||
0x6C,0x00,0x80,0x00,0x06,0x04,0x80,0x00,0x0F,0x04,0x80,0x00,0x10,0x65,0x64,0xA1,
|
||||
0x00,0xA0,0xFF,0x97,0xC1,0x9E,0x00,0xA1,0x14,0xA0,0xFF,0x97,0xBD,0x9E,0x04,0xA1,
|
||||
0x06,0xA0,0xFF,0x97,0xB9,0x9E,0x03,0xA1,0x01,0xA0,0xFF,0x97,0xB5,0x9E,0x16,0x0B,
|
||||
0x00,0xA4,0x1C,0x40,0x03,0xB3,0x1C,0x40,0xFF,0x97,0x9C,0x9F,0x06,0xA0,0xFF,0x97,
|
||||
0x95,0x9E,0x83,0xF7,0x0B,0xC5,0x11,0x0B,0xDC,0x45,0x11,0x0B,0x1B,0x58,0x7A,0xB3,
|
||||
0x1B,0x48,0x0F,0xA2,0x1A,0x00,0x0F,0x0B,0x01,0xBA,0x2C,0xB3,0x1A,0x40,0x0B,0x0B,
|
||||
0x5A,0x4E,0x02,0xAA,0x04,0xC1,0x01,0xA2,0x5A,0x45,0x32,0xA2,0x1A,0x46,0x06,0x80,
|
||||
0x5A,0x4E,0x00,0xAA,0x01,0xC1,0x01,0xA2,0x00,0x80,0x00,0xA2,0x5A,0x45,0x03,0x0B,
|
||||
0x00,0xA2,0x9A,0x45,0x10,0x6D,0xC0,0x46,0x06,0x04,0x80,0x00,0x2C,0x8F,0x80,0x00,
|
||||
0x7C,0x93,0x80,0x00,0x6C,0x90,0x80,0x00,0x00,0x65,0x19,0x0B,0x19,0x28,0x19,0x0B,
|
||||
0x28,0xB3,0x1B,0x48,0x9A,0xF0,0xD3,0xE8,0xDA,0xE0,0x17,0x0B,0x91,0x02,0x0A,0xCD,
|
||||
0x1A,0x48,0x01,0xB2,0x12,0xF6,0x12,0xFE,0x1A,0x40,0x08,0xAA,0x05,0xC9,0x13,0x09,
|
||||
0x00,0xA2,0x0A,0x40,0x00,0x80,0x00,0xA2,0x1A,0x40,0x10,0x0B,0x1A,0x48,0x03,0xAA,
|
||||
0x15,0xC8,0x0F,0x0A,0x11,0x28,0x01,0xB1,0x09,0xF4,0x09,0xFC,0x11,0x20,0x1A,0x48,
|
||||
0x01,0xB2,0x12,0xF6,0x12,0xFE,0x1A,0x40,0x00,0xA2,0xDA,0x45,0x5A,0x46,0x05,0x0B,
|
||||
0x28,0xB3,0x1A,0x48,0x07,0x08,0x52,0xF0,0x07,0x09,0x02,0x90,0xCA,0x9D,0x00,0x6D,
|
||||
0x7C,0x92,0x80,0x00,0x6C,0x90,0x80,0x00,0x7C,0x8D,0x80,0x00,0x2C,0x8F,0x80,0x00,
|
||||
0xB8,0x93,0x80,0x00,0x9C,0x90,0x80,0x00,0xFC,0x90,0x80,0x00,0x10,0x65,0x17,0x0B,
|
||||
0x1A,0xEC,0x80,0xB2,0x14,0x48,0x16,0x0A,0x81,0xB3,0x19,0x48,0x53,0xEC,0xD8,0x4F,
|
||||
0x93,0xEC,0xDB,0x4F,0x09,0xF2,0x1B,0xF2,0x21,0x03,0x03,0x03,0x99,0x02,0x1C,0xC2,
|
||||
0x13,0xEC,0x2B,0xB3,0x19,0x48,0x0F,0x0B,0x1B,0x28,0x01,0xB1,0x99,0x02,0x14,0xCB,
|
||||
0x28,0xB2,0x10,0x48,0x0C,0x0B,0x40,0xF0,0x0C,0x09,0xC0,0xE8,0x0B,0x80,0x1A,0x28,
|
||||
0x12,0xF4,0x12,0xE4,0x00,0xAA,0x04,0xCA,0x0C,0x28,0x52,0x02,0xD2,0xE0,0xA2,0xEA,
|
||||
0x0A,0x20,0x02,0xB3,0x02,0xB1,0x83,0x02,0xF1,0xC1,0x10,0x6D,0xA4,0x8F,0x80,0x00,
|
||||
0x6C,0x90,0x80,0x00,0x7C,0x92,0x80,0x00,0x1C,0x92,0x80,0x00,0x9C,0x90,0x80,0x00,
|
||||
0xF0,0x65,0x3E,0x0C,0x23,0x48,0x05,0xF4,0x2D,0xFC,0x03,0xAB,0x75,0xC9,0xFF,0x97,
|
||||
0xBD,0x9F,0x63,0x4B,0x18,0xEE,0x02,0xC0,0x00,0xA2,0x39,0x0B,0x6C,0x80,0x39,0x0A,
|
||||
0x13,0xEC,0x80,0xB3,0x81,0xB2,0x19,0x48,0x13,0x48,0x1B,0xF2,0x0B,0x03,0x36,0x09,
|
||||
0x4A,0xEC,0xD6,0x4F,0x8A,0xEC,0xD2,0x4F,0x12,0xF2,0x32,0x03,0x93,0x02,0x02,0xC9,
|
||||
0x2F,0x0A,0x50,0x40,0x59,0x80,0x28,0xAB,0x22,0xC9,0x62,0x49,0x10,0xEE,0x1F,0xC1,
|
||||
0x2B,0x0B,0x5A,0x48,0x01,0xB2,0x12,0xF6,0x12,0xFE,0x5A,0x40,0x0F,0xAA,0x4C,0xC9,
|
||||
0x58,0x40,0x28,0xB1,0x0C,0x48,0x29,0x0B,0x64,0xF0,0x29,0x0A,0xE4,0xE8,0x0C,0x80,
|
||||
0x19,0x28,0x09,0xF4,0x08,0xE4,0x00,0xA8,0x05,0xCD,0xA8,0x02,0x03,0xCA,0x10,0x28,
|
||||
0x89,0xE4,0x09,0xE8,0x11,0x20,0x02,0xB3,0x02,0xB2,0xA3,0x02,0xF0,0xC1,0x34,0x80,
|
||||
0x1A,0x0A,0x51,0x49,0x00,0xA9,0x04,0xC0,0x52,0x49,0x01,0xAA,0x29,0xC1,0x13,0xAB,
|
||||
0x27,0xC8,0x17,0x0B,0x9A,0x48,0x01,0xB2,0x12,0xF6,0x12,0xFE,0x9A,0x40,0x0F,0xAA,
|
||||
0x23,0xC9,0x00,0xA2,0x9A,0x40,0x14,0x0B,0x1A,0xEC,0x28,0xB2,0x29,0xB3,0x17,0x48,
|
||||
0x1E,0x48,0x12,0x09,0x12,0x0A,0x00,0xA3,0x10,0x80,0x08,0x28,0x04,0xF4,0x24,0xE4,
|
||||
0x00,0xAC,0x08,0xCD,0xB3,0x02,0x01,0xC3,0xAC,0x02,0x04,0xCA,0x14,0x28,0x00,0xF4,
|
||||
0x80,0xE4,0x00,0xE9,0x10,0x20,0x01,0xB3,0x02,0xB1,0x02,0xB2,0xBB,0x02,0xEC,0xC3,
|
||||
0x03,0x80,0x03,0x0B,0x00,0xA2,0x9A,0x40,0x5A,0x40,0xF0,0x6D,0x2C,0x8F,0x80,0x00,
|
||||
0x7C,0x8D,0x80,0x00,0xA4,0x8F,0x80,0x00,0x6C,0x90,0x80,0x00,0x1C,0x92,0x80,0x00,
|
||||
0x9C,0x90,0x80,0x00,0x02,0x0B,0x00,0xF6,0x00,0xFE,0x18,0x40,0x70,0x07,0xC0,0x46,
|
||||
0x01,0x00,0x80,0x00,0x02,0x0B,0x00,0xF6,0x00,0xFE,0x18,0x40,0x70,0x07,0xC0,0x46,
|
||||
0x09,0x00,0x80,0x00,0x02,0x0B,0x00,0xF6,0x00,0xFE,0x18,0x40,0x70,0x07,0xC0,0x46,
|
||||
0x0A,0x00,0x80,0x00,0x02,0x0B,0x00,0xF6,0x00,0xFE,0x18,0x40,0x70,0x07,0xC0,0x46,
|
||||
0x0B,0x00,0x80,0x00,0xF0,0x65,0x3C,0x0B,0x1B,0x48,0x09,0xF6,0x81,0x60,0x04,0xEC,
|
||||
0x09,0xFE,0x05,0xAB,0x52,0xC1,0x39,0x0B,0x1B,0x4E,0x00,0xAB,0x4E,0xC1,0xB4,0xA0,
|
||||
0x00,0xA9,0x40,0xC0,0x01,0xA9,0x3A,0xC1,0x35,0x0B,0x08,0xA2,0x1A,0x40,0x35,0x09,
|
||||
0x0B,0x58,0x00,0x33,0x34,0x0B,0x14,0xA2,0x1A,0x40,0xA2,0xF0,0x12,0xE9,0x10,0xF1,
|
||||
0x82,0xEA,0x32,0x0E,0x92,0xF0,0x40,0xA5,0x9C,0x06,0x0F,0x58,0x00,0x3B,0xFB,0xEA,
|
||||
0x93,0x02,0x09,0xC2,0x37,0x58,0x3D,0x02,0xF7,0xC0,0x60,0x06,0x07,0x48,0xF8,0xF6,
|
||||
0xF3,0xC5,0x2B,0x09,0x08,0xA0,0x08,0x40,0x2A,0x09,0xD3,0xEA,0x8B,0x02,0x0B,0xCD,
|
||||
0xD8,0xF0,0xC0,0xE8,0x28,0x0B,0x22,0x0A,0x40,0xF0,0x00,0xA1,0xC0,0xE8,0x11,0x40,
|
||||
0xC0,0xE2,0xFF,0x97,0xA9,0x9C,0x2C,0x80,0x96,0xA1,0x49,0xF0,0x8B,0x02,0x25,0xCD,
|
||||
0x1C,0x0B,0x18,0x58,0x00,0x39,0x41,0xEA,0x91,0x02,0xFA,0xC3,0x1E,0x80,0x02,0xA9,
|
||||
0x28,0xC1,0xDF,0xA0,0x40,0xF0,0xFF,0x97,0x97,0x9C,0xA1,0xF0,0x0C,0xE9,0x1B,0x0B,
|
||||
0x21,0xF1,0x1A,0x58,0x0C,0xEB,0x64,0xF1,0x14,0xEB,0x1A,0x80,0x10,0x0B,0x08,0xA2,
|
||||
0x1A,0x40,0x10,0x0B,0x1A,0x58,0x00,0x32,0xA2,0xF0,0x12,0xE9,0x11,0xF1,0x8A,0xEA,
|
||||
0x92,0xF0,0x18,0x58,0x00,0x39,0x41,0xEA,0x91,0x02,0xFA,0xC3,0x08,0x0B,0x00,0xA2,
|
||||
0x1A,0x40,0xA2,0xF0,0x14,0xE9,0x22,0xF1,0x00,0x3B,0x14,0xEB,0x64,0xF1,0xE4,0xE8,
|
||||
0x04,0x0B,0x1C,0x50,0x01,0x60,0xF0,0x6D,0x03,0x00,0x80,0x00,0x2C,0x8F,0x80,0x00,
|
||||
0x68,0x00,0x80,0x00,0x34,0x06,0x80,0x00,0x22,0x00,0x80,0x00,0x48,0x06,0x80,0x00,
|
||||
0x83,0x00,0x80,0x00,0x0E,0x10,0x00,0x00,0x08,0xE7,0xFE,0xFF,0x68,0x90,0x80,0x00,
|
||||
0x10,0x65,0x24,0x0B,0x66,0xA2,0x1A,0x40,0x02,0xA1,0x02,0xA0,0xFF,0x97,0xC4,0x9C,
|
||||
0x21,0x0B,0xAA,0xA2,0x21,0x0C,0x1A,0x40,0xFF,0xA3,0x23,0x40,0x00,0x90,0x42,0x99,
|
||||
0x1F,0x0A,0x00,0xA3,0x13,0x50,0x11,0x58,0x08,0xB2,0x11,0x50,0x28,0xBA,0x23,0x40,
|
||||
0x13,0x40,0x10,0xB2,0x13,0x50,0x1B,0x0A,0x08,0xA1,0x11,0x40,0x1A,0x09,0x04,0xBA,
|
||||
0x11,0x20,0x1A,0x09,0x5C,0xA2,0x0A,0x40,0x08,0xB1,0x0A,0x40,0x01,0xB1,0x0A,0x40,
|
||||
0x01,0xB1,0x0A,0x40,0x16,0x0A,0x05,0xA1,0x11,0x40,0x16,0x09,0x25,0xB2,0x11,0x20,
|
||||
0x40,0xB2,0x13,0x40,0x14,0x0B,0x7F,0xA2,0x1A,0x40,0xE0,0xA3,0x1B,0xF2,0x1C,0x48,
|
||||
0x12,0x0B,0x1B,0x48,0x63,0x00,0xFF,0xAB,0x09,0xC1,0x23,0xEC,0x50,0xBB,0x1B,0xF6,
|
||||
0x1B,0xFE,0xA8,0xAB,0x03,0xC8,0x03,0xA0,0x21,0xEC,0xFF,0x97,0x85,0x9C,0x0C,0x0B,
|
||||
0x1C,0x21,0x10,0x6D,0x0F,0x04,0x80,0x00,0x10,0x04,0x80,0x00,0x61,0x00,0x80,0x00,
|
||||
0x40,0x06,0x80,0x00,0x86,0x00,0x80,0x00,0x07,0x08,0x00,0x00,0x01,0x00,0x80,0x00,
|
||||
0x03,0x00,0x80,0x00,0x00,0x9F,0xFF,0xFF,0x64,0x00,0x80,0x00,0x01,0xE0,0x00,0x00,
|
||||
0xB8,0x93,0x80,0x00,0x00,0x65,0x22,0x0A,0x22,0x0B,0x10,0xA0,0x1A,0x50,0x03,0xA1,
|
||||
0xFF,0x97,0x62,0x9C,0x64,0xA1,0x00,0xA0,0xFF,0x97,0x5E,0x9C,0x06,0xA0,0xFF,0x97,
|
||||
0x45,0x9C,0x01,0xEC,0x06,0xA0,0xFF,0x97,0x57,0x9C,0x1B,0x0B,0xF0,0xA2,0x1A,0x40,
|
||||
0x1A,0x09,0x00,0xA2,0x06,0xB3,0x1A,0x40,0x03,0xB3,0x1A,0x40,0x0A,0x20,0x18,0x0A,
|
||||
0x00,0xA3,0x13,0x40,0x17,0x0A,0x13,0xA1,0x11,0x40,0x17,0x08,0x01,0xBA,0x13,0x40,
|
||||
0x02,0xA2,0x02,0x40,0x01,0xB0,0x01,0x40,0x14,0x09,0x0B,0x40,0x07,0xB1,0x0A,0x40,
|
||||
0x13,0x0A,0x13,0x40,0x13,0x0A,0x13,0x40,0x01,0xA3,0x01,0xB2,0x13,0x40,0x12,0x0A,
|
||||
0x13,0x40,0x12,0x0A,0x12,0x0B,0x12,0xF4,0x12,0xFC,0x1A,0x20,0x11,0x08,0xF0,0xA2,
|
||||
0x00,0xA1,0xFF,0x97,0xCC,0x9C,0x10,0x0B,0x82,0xA2,0x1A,0x40,0x00,0x6D,0xC0,0x46,
|
||||
0x00,0x9E,0x80,0x00,0x7C,0x93,0x80,0x00,0x00,0x04,0x80,0x00,0x0A,0x04,0x80,0x00,
|
||||
0x0E,0x04,0x80,0x00,0x0C,0x02,0x80,0x00,0x0D,0x02,0x80,0x00,0x01,0x02,0x80,0x00,
|
||||
0x12,0x02,0x80,0x00,0x15,0x04,0x80,0x00,0x17,0x02,0x80,0x00,0x80,0x8D,0x80,0x00,
|
||||
0x14,0x02,0x80,0x00,0x00,0xE0,0x80,0x00,0x6B,0x00,0x80,0x00,0x18,0x0B,0x1B,0x58,
|
||||
0x9A,0x49,0x07,0xA1,0x11,0x00,0x17,0x0A,0x20,0xB1,0x11,0x40,0x19,0x29,0x16,0x0A,
|
||||
0x89,0xF5,0x89,0xFF,0x11,0x40,0x19,0x4A,0x0A,0xB2,0x11,0x20,0x99,0x28,0x0E,0xBA,
|
||||
0x11,0x20,0x59,0x29,0x02,0xB2,0x11,0x20,0x19,0x4B,0x0F,0xB2,0x11,0x40,0x9A,0x29,
|
||||
0x18,0xEC,0x0E,0x0B,0x12,0xFA,0x1A,0x40,0xF6,0xB3,0xFF,0xB3,0xFF,0xA2,0x0C,0x09,
|
||||
0x1A,0x40,0x16,0xB0,0x00,0xA3,0xC2,0x1C,0x00,0xAA,0x02,0xC0,0x8A,0xE8,0x3F,0xB2,
|
||||
0x13,0x40,0x01,0xB3,0x30,0xAB,0xF6,0xC1,0x06,0x0B,0x02,0xA2,0x1A,0x40,0x70,0x07,
|
||||
0x7C,0x93,0x80,0x00,0x0D,0x04,0x80,0x00,0x06,0x02,0x80,0x00,0x17,0x02,0x80,0x00,
|
||||
0x00,0x8E,0x80,0x00,0x09,0x02,0x80,0x00,0x00,0x65,0x06,0x0A,0x06,0x0B,0x1A,0x50,
|
||||
0xFF,0x97,0xB0,0x9C,0x05,0x0A,0x80,0xA3,0x11,0x58,0xDB,0xF1,0x0B,0x03,0x13,0x50,
|
||||
0x00,0x6D,0xC0,0x46,0x09,0xF0,0x00,0x00,0x20,0x06,0x80,0x00,0x40,0x06,0x80,0x00,
|
||||
0xF0,0x65,0x17,0x0B,0x9C,0x4D,0x17,0x0A,0x17,0x0B,0x18,0x09,0x00,0xAC,0x07,0xC0,
|
||||
0x28,0xB1,0x0D,0x48,0x40,0xB3,0x80,0xA1,0xED,0xE8,0x15,0x0C,0x09,0xF1,0x1C,0x80,
|
||||
0x28,0xB1,0x0D,0x48,0x40,0xB3,0x80,0xA1,0xED,0xE8,0x11,0x0C,0x09,0xF1,0x07,0x80,
|
||||
0x1E,0x48,0xB6,0xF0,0x36,0x19,0x8E,0xEB,0xC6,0x00,0x16,0x20,0x01,0xB3,0x02,0xB2,
|
||||
0xAB,0x02,0xF5,0xC1,0x0B,0x80,0x1E,0x48,0xB6,0xF0,0x36,0x19,0x17,0x28,0x8E,0xEB,
|
||||
0xC6,0x00,0xF6,0xE9,0x16,0x20,0x01,0xB3,0x02,0xB2,0xAB,0x02,0xF3,0xC1,0xF0,0x6D,
|
||||
0x2C,0x8F,0x80,0x00,0xFC,0x90,0x80,0x00,0x00,0x8E,0x80,0x00,0x6C,0x90,0x80,0x00,
|
||||
0x80,0x8D,0x80,0x00,0x04,0x0A,0x05,0x0B,0x10,0x58,0x11,0x58,0x0B,0x00,0x13,0x50,
|
||||
0x80,0xA3,0x5B,0xF4,0x18,0x00,0x70,0x07,0x40,0x06,0x80,0x00,0xFF,0xFF,0xFF,0xFE,
|
||||
0x70,0x65,0x2B,0x0B,0x00,0xA6,0x1E,0x40,0x2A,0x0D,0x2B,0x58,0x9B,0x49,0x35,0xAB,
|
||||
0x4D,0xC1,0xFA,0xA0,0x80,0xF0,0x02,0x90,0xA5,0x9A,0x27,0x0C,0x29,0x58,0x20,0xEC,
|
||||
0x0C,0xA2,0x02,0x90,0xE2,0x9A,0x20,0xEC,0x08,0xA1,0x02,0x90,0xF9,0x9A,0x23,0x48,
|
||||
0x00,0xA8,0x35,0xC1,0x62,0x48,0xD2,0xE8,0xFF,0xAA,0x31,0xC1,0x42,0xAB,0x0B,0xC1,
|
||||
0x1E,0x0B,0x1A,0x58,0x05,0xA1,0x51,0x40,0x22,0x49,0xC1,0xAA,0x28,0xC1,0x1C,0x0A,
|
||||
0x01,0xA1,0x11,0x40,0x1B,0x58,0x11,0x80,0x98,0xAB,0x21,0xC1,0x17,0x0B,0x1A,0x58,
|
||||
0x05,0xA3,0x53,0x40,0xE1,0x48,0xA3,0x48,0x09,0xF2,0x19,0x03,0x15,0x0B,0x99,0x02,
|
||||
0x16,0xC1,0x23,0x49,0x55,0xAB,0x03,0xC1,0x56,0x40,0x13,0x0B,0x5E,0x40,0x0F,0x80,
|
||||
0xAA,0xAB,0x0D,0xC1,0x11,0x08,0xCC,0xA1,0x02,0x90,0xB8,0x9A,0x00,0xA8,0x03,0xC1,
|
||||
0x00,0x90,0x44,0x9D,0xFF,0x97,0x1A,0x9F,0x08,0x0B,0x1B,0x58,0x00,0xA2,0x5A,0x40,
|
||||
0x03,0x0B,0x08,0xA2,0x1A,0x40,0x03,0x0B,0x1B,0x58,0x30,0xA2,0x9A,0x41,0x70,0x6D,
|
||||
0x83,0x00,0x80,0x00,0x24,0x8F,0x80,0x00,0x0C,0x8F,0x80,0x00,0x28,0x8F,0x80,0x00,
|
||||
0x03,0x00,0x80,0x00,0x36,0x35,0x00,0x00,0x2C,0x8F,0x80,0x00,0x00,0x9E,0x80,0x00,
|
||||
0x30,0x65,0x04,0x3C,0x80,0xF0,0x24,0xE8,0x20,0x58,0x03,0x3D,0x00,0xA8,0x05,0xC0,
|
||||
0x00,0xA9,0x03,0xC0,0x00,0xA3,0x23,0x50,0x01,0xA0,0x10,0x80,0x0B,0xAD,0x08,0xC8,
|
||||
0x19,0xF1,0xCB,0xEA,0x93,0x02,0x09,0xC2,0x28,0xAA,0x07,0xC9,0x01,0xA3,0x23,0x50,
|
||||
0x04,0x80,0x00,0xA0,0x64,0xAD,0x02,0xC9,0x20,0x50,0x00,0x80,0x00,0xA0,0x30,0x6D,
|
||||
0xF0,0x65,0x92,0x60,0x11,0x33,0x7D,0x0B,0x1B,0x58,0x7C,0xB3,0x1B,0x28,0x0C,0x33,
|
||||
0x03,0x28,0x14,0xEC,0x1A,0xF4,0x05,0xEC,0x0E,0xEC,0x79,0x0F,0x00,0xAA,0x00,0xCC,
|
||||
0x89,0x83,0x39,0x1D,0x77,0x0A,0x00,0xA9,0x00,0xC1,0xF9,0x82,0x76,0x08,0x67,0xF1,
|
||||
0x38,0xE8,0x03,0x30,0x12,0x1D,0x0A,0x32,0x00,0xA2,0x08,0xA9,0x00,0xC1,0x0A,0x3A,
|
||||
0xE7,0xF0,0xBA,0xE8,0x71,0x08,0x52,0xF0,0x10,0x1A,0x0F,0x30,0x70,0x08,0x10,0x1A,
|
||||
0x0A,0x3A,0x10,0x30,0x07,0xB2,0x07,0xA0,0x10,0x00,0x1B,0xF4,0x84,0x06,0x1B,0xE4,
|
||||
0x07,0x33,0x67,0x04,0x69,0x0A,0x7F,0xF0,0xBA,0x1A,0x9B,0xEA,0x0D,0x32,0x00,0xA2,
|
||||
0xB0,0x1E,0x05,0x33,0x09,0x30,0x66,0x0B,0xFF,0x1A,0x0E,0x37,0xC7,0xEB,0x05,0x38,
|
||||
0xC2,0xE7,0x83,0xE8,0x53,0x00,0x1B,0xF4,0xF8,0xE7,0x1B,0xFC,0x04,0x33,0x3B,0xE8,
|
||||
0x43,0x00,0x60,0x0A,0x1B,0xF4,0x1B,0xFC,0x0B,0x37,0x03,0x38,0x06,0x33,0x03,0x32,
|
||||
0x00,0xA7,0x00,0xA2,0x8C,0x06,0x08,0x34,0x16,0x80,0x10,0xD8,0x01,0xA1,0x3B,0xEC,
|
||||
0x21,0x02,0x0F,0xC0,0xE3,0xF3,0x57,0x09,0x03,0x3C,0x1B,0xFC,0x8C,0x02,0x02,0xC0,
|
||||
0x9C,0x02,0x03,0xC3,0x03,0x80,0x1F,0xEC,0x03,0x33,0x00,0x80,0x03,0x33,0x9F,0x02,
|
||||
0x00,0xC8,0x3B,0xEC,0x01,0xB2,0x1F,0xEC,0x62,0x05,0xE6,0xC3,0x03,0x3A,0xD0,0xEB,
|
||||
0x00,0xF4,0x08,0x3C,0x00,0xFC,0x64,0xAF,0x07,0xC9,0x4A,0x0B,0x11,0xEC,0x79,0x03,
|
||||
0x58,0x03,0xFF,0x97,0xB3,0x99,0x00,0xF4,0x00,0xFC,0x04,0x39,0x00,0xA3,0x08,0x33,
|
||||
0x02,0xA9,0x1E,0xC9,0x2B,0xA3,0x63,0x03,0x43,0x0A,0xD3,0xE8,0x02,0xB3,0xDB,0x4F,
|
||||
0x05,0xAB,0x16,0xC0,0x0D,0x3A,0x0F,0x39,0x53,0xEA,0x05,0x3A,0x53,0x03,0x06,0x39,
|
||||
0xDB,0xFF,0x08,0x33,0x0B,0xEC,0x04,0x39,0x5B,0xE8,0x1E,0xAB,0x09,0xCD,0x13,0xA8,
|
||||
0x07,0xC8,0x8F,0xA2,0x00,0xA3,0xBA,0x02,0x5B,0x01,0x08,0x3A,0x5B,0x02,0x1A,0x00,
|
||||
0x08,0x32,0x06,0x3F,0x00,0xA3,0x05,0x33,0x02,0xAF,0x1D,0xC9,0x2B,0xA3,0x63,0x03,
|
||||
0x31,0x0A,0xD3,0xE8,0x02,0xB3,0xDB,0x4F,0x05,0xAB,0x15,0xC0,0x0E,0x39,0x10,0x3A,
|
||||
0x0B,0x3F,0x8B,0xEA,0x7B,0x03,0xDB,0xFF,0x05,0x33,0x13,0xA8,0x0C,0xC8,0x06,0x38,
|
||||
0x03,0xEC,0x04,0x38,0x1B,0xE8,0x1E,0xAB,0x06,0xCD,0x03,0x39,0x05,0x3A,0x45,0xA3,
|
||||
0x8B,0x02,0x9B,0x01,0x1A,0x00,0x05,0x32,0x0C,0x3B,0x1B,0xFA,0x0B,0x33,0x07,0x3A,
|
||||
0x09,0x3B,0x0D,0x38,0x0E,0x39,0xFF,0x97,0x85,0x9A,0x0B,0x3F,0x1F,0x0A,0xA3,0xF0,
|
||||
0xB8,0x02,0x05,0xC2,0xD1,0x18,0x1D,0xA9,0x4F,0xC8,0x01,0xB1,0xD1,0x10,0x4C,0x80,
|
||||
0x00,0xA1,0xD1,0x10,0x0B,0x39,0x4A,0xF0,0x90,0x02,0x46,0xC2,0x18,0x0A,0xD2,0x18,
|
||||
0x04,0xAA,0x42,0xCC,0x17,0x09,0x2A,0x28,0xCB,0x18,0x11,0xF4,0x09,0xE4,0xC9,0xEA,
|
||||
0x01,0xA9,0x01,0xCD,0x9A,0xEC,0x02,0x80,0x01,0xB1,0x02,0xCA,0x9A,0xEE,0x12,0xF4,
|
||||
0x12,0xFC,0x2A,0x20,0x10,0x0A,0x33,0x28,0xA1,0xF0,0x8A,0x18,0x19,0xF4,0x09,0xE4,
|
||||
0x89,0xEA,0x01,0xA9,0x1A,0xCD,0x93,0xEC,0x1B,0x80,0xC0,0x46,0x7C,0x93,0x80,0x00,
|
||||
0xCC,0x8E,0x80,0x00,0xF8,0x8E,0x80,0x00,0xAC,0x8E,0x80,0x00,0x98,0x8E,0x80,0x00,
|
||||
0xD8,0x8E,0x80,0x00,0x10,0x27,0x00,0x00,0x4C,0x8F,0x80,0x00,0x00,0x8F,0x80,0x00,
|
||||
0xF4,0x8E,0x80,0x00,0xA8,0x8E,0x80,0x00,0xF0,0x8E,0x80,0x00,0x01,0xB1,0x02,0xCA,
|
||||
0x93,0xEE,0x1B,0xF4,0x1B,0xFC,0x33,0x20,0xCC,0x09,0x00,0xA7,0xE8,0x1F,0xA2,0xF0,
|
||||
0x50,0x10,0x1B,0xF4,0xCA,0x09,0x1B,0xE4,0x53,0x10,0xCA,0x0B,0xA7,0xF0,0xFB,0x18,
|
||||
0x03,0x33,0x1A,0xF4,0xC8,0x0B,0xFB,0x18,0x04,0x33,0x19,0xF4,0xC7,0x0B,0xDB,0x1B,
|
||||
0x06,0x33,0xC7,0x0B,0xDB,0x1B,0x07,0x33,0x2B,0xA3,0x18,0xEC,0x60,0x03,0xC5,0x0B,
|
||||
0x18,0xE8,0x09,0x30,0x03,0xEC,0x02,0xB3,0xDB,0x4F,0x12,0xFC,0x09,0xFC,0x05,0xAB,
|
||||
0x00,0xC0,0x8E,0x80,0xC0,0x08,0x03,0x1D,0x02,0xAB,0x00,0xC8,0x4D,0x81,0x08,0x3B,
|
||||
0x05,0x38,0x03,0x02,0x00,0xC0,0x48,0x81,0x12,0xF4,0x09,0xF4,0x12,0xE4,0x09,0xE4,
|
||||
0x03,0x32,0x04,0x31,0x07,0x3A,0x06,0x39,0x08,0xF4,0x11,0xF4,0x00,0xE4,0x09,0xE4,
|
||||
0x03,0x3A,0x04,0x3B,0xFF,0x97,0xF6,0x99,0x64,0xA8,0x20,0xC9,0xB3,0x0B,0xFB,0x18,
|
||||
0x03,0xAB,0x1C,0xC8,0xB0,0x0B,0x1A,0x1D,0x03,0xAA,0x18,0xC9,0x09,0x3B,0x03,0xB3,
|
||||
0xDB,0x4F,0x02,0xAB,0x13,0xC1,0xAE,0x0B,0x1B,0x1D,0x00,0xAB,0x0F,0xC0,0x00,0xA3,
|
||||
0x04,0xAA,0x03,0xC0,0x0A,0x3B,0x07,0xA2,0x04,0xB3,0x13,0x00,0xE2,0xF0,0xD3,0xE8,
|
||||
0xA8,0x0A,0x5B,0xF0,0x9A,0x1A,0x06,0x32,0xA7,0x0A,0x9A,0x1A,0x07,0x32,0x06,0x38,
|
||||
0x03,0x3A,0x07,0xF4,0x03,0x39,0x3F,0xE4,0x79,0xEA,0x07,0x38,0xD7,0xEB,0xFB,0xF0,
|
||||
0xDF,0xE9,0x04,0x3A,0x09,0x31,0x03,0xF4,0x04,0x39,0x1B,0xE4,0x59,0xEA,0xD3,0xEA,
|
||||
0xDA,0xF0,0xD3,0xE8,0x5B,0xF0,0x06,0x33,0x12,0xA3,0x0C,0x31,0x07,0x33,0x7F,0xF0,
|
||||
0xFB,0xE7,0x1B,0xFF,0x06,0x39,0xDB,0xE9,0x03,0x38,0x1B,0xE1,0xC0,0xE8,0xCB,0xE7,
|
||||
0x1B,0xFF,0x5B,0xE8,0x04,0x3A,0x1B,0xE1,0xD2,0xE8,0x08,0x30,0xB8,0xA3,0x05,0x32,
|
||||
0x00,0x33,0x01,0x33,0xB9,0xA0,0xB9,0xA1,0x08,0x3A,0x05,0x3B,0x02,0x90,0x86,0x98,
|
||||
0x00,0xA8,0x0B,0xC0,0x06,0x3A,0x07,0x38,0x13,0xEC,0x0C,0x3A,0x09,0x39,0x01,0xB8,
|
||||
0x9B,0xE8,0x07,0x30,0x7F,0xE8,0x06,0x33,0x00,0xA8,0xD9,0xC1,0x08,0x3F,0x00,0xAF,
|
||||
0x01,0xCC,0x01,0xA0,0x08,0x30,0x05,0x39,0x00,0xA9,0x01,0xCC,0x01,0xA2,0x05,0x32,
|
||||
0x20,0xA7,0x6B,0x06,0xFB,0x1A,0x14,0xA0,0x6F,0x06,0xC7,0x1B,0x2B,0x20,0x37,0x20,
|
||||
0xC3,0x80,0x07,0xAB,0x00,0xC0,0xC0,0x80,0x12,0xF4,0x12,0xE4,0x94,0x06,0x07,0x3A,
|
||||
0x09,0xF4,0x10,0xF4,0x09,0xE4,0x00,0xE4,0x40,0xEA,0x06,0x3F,0xC3,0xE7,0xC0,0xE8,
|
||||
0x3A,0xF4,0x58,0x00,0x12,0xE4,0x63,0x06,0xD2,0xEA,0xD7,0xE7,0xD2,0xE9,0x7A,0x00,
|
||||
0x82,0xE8,0x00,0xA0,0x33,0x1E,0x59,0xEA,0x00,0xA0,0x2F,0x1E,0x05,0x33,0xCB,0xE7,
|
||||
0xC8,0xE8,0x61,0x06,0x58,0x00,0x7B,0xEA,0xD9,0xE7,0x5B,0xE8,0x4B,0x00,0xC1,0xE8,
|
||||
0x65,0x0B,0x1B,0x1D,0x9C,0x06,0x01,0xA3,0x23,0xA9,0x00,0xCC,0x00,0xA3,0x1B,0xF6,
|
||||
0x00,0xAB,0x03,0xC0,0x01,0xA0,0x23,0xA3,0x84,0x05,0x1E,0xC0,0x01,0xA3,0x05,0xAA,
|
||||
0x00,0xCC,0x00,0xA3,0x1B,0xF6,0x00,0xAB,0x12,0xC0,0x07,0xA3,0x9C,0x05,0x0F,0xC8,
|
||||
0x53,0xF0,0x99,0x02,0x0C,0xCD,0x48,0xE0,0x84,0x06,0x94,0x05,0x03,0xCC,0xD0,0xEC,
|
||||
0x84,0x06,0x8C,0x05,0x08,0xCB,0x96,0xAB,0x07,0xCD,0x1B,0xE1,0x96,0xB3,0x04,0x80,
|
||||
0x96,0xA3,0x96,0xA9,0x01,0xCC,0x70,0x80,0x03,0xEC,0x03,0x38,0x03,0x39,0xC9,0xEB,
|
||||
0x3F,0xEA,0x08,0x37,0x0C,0x31,0x08,0x39,0x3F,0xF1,0x7F,0xEA,0x04,0x38,0x05,0x39,
|
||||
0x40,0xEA,0x0F,0x30,0x04,0x38,0x08,0xEA,0x05,0x30,0x05,0x39,0x00,0xF1,0x02,0x32,
|
||||
0x40,0xEA,0x9C,0x06,0x0F,0xA1,0xFB,0xE7,0x1B,0xFF,0xDB,0xE9,0x1B,0xE1,0x09,0x33,
|
||||
0xC3,0xE7,0x1B,0xFF,0x1B,0xE8,0x1B,0xE1,0x06,0x33,0x04,0x3B,0x1A,0xEC,0x06,0x3B,
|
||||
0xD2,0xE8,0x06,0x3B,0x07,0x32,0xDA,0xE7,0x9B,0xE8,0x53,0x00,0x10,0x33,0x09,0x3B,
|
||||
0x1A,0xEC,0x03,0x3B,0xD2,0xE8,0x09,0x3B,0x06,0x32,0xDA,0xE7,0x9B,0xE8,0x53,0x00,
|
||||
0x09,0x33,0x10,0x3B,0x1A,0xEC,0x09,0x3B,0xD2,0xE8,0x09,0x32,0x0F,0x3A,0x0C,0x3B,
|
||||
0x80,0xE8,0x09,0x3A,0xFF,0xE8,0x01,0xB9,0x01,0xA3,0x62,0x05,0x00,0xCC,0x00,0xA3,
|
||||
0x1B,0xF6,0x00,0xAB,0x01,0xC0,0x00,0xA9,0xCD,0xCC,0x02,0x3A,0x09,0x3B,0x93,0x02,
|
||||
0x14,0xCC,0x08,0x3F,0x02,0xB1,0x3B,0xEC,0x4B,0x03,0xDA,0xE7,0x12,0xFF,0xD3,0xE8,
|
||||
0x05,0x3A,0x51,0x03,0x03,0x38,0x1B,0xE1,0x1B,0xE8,0x2B,0x20,0xCB,0xE7,0x1B,0xFF,
|
||||
0x59,0xE8,0x04,0x3B,0x09,0xE1,0xC9,0xE8,0x31,0x20,0x07,0x80,0x18,0xA0,0x6F,0x06,
|
||||
0xC7,0x1B,0x1C,0xA1,0x68,0x06,0x08,0x1A,0x2F,0x20,0x30,0x20,0x13,0x0A,0x06,0x39,
|
||||
0xA3,0xF0,0x99,0x10,0x07,0x3F,0x12,0x0A,0x9F,0x10,0x12,0x0A,0xA3,0xF0,0x99,0x18,
|
||||
0x12,0x0A,0x99,0x10,0x10,0x0A,0x99,0x18,0x11,0x0A,0x99,0x10,0x00,0xA0,0x2A,0x1E,
|
||||
0x00,0xA1,0x73,0x1E,0x0D,0x38,0x0E,0x39,0xFF,0x97,0xAC,0x98,0x0B,0x3A,0x90,0x02,
|
||||
0x00,0xC2,0x77,0x80,0x0C,0x0B,0x1F,0x1D,0x00,0xAF,0x4B,0xC0,0x0C,0x0B,0x1B,0x1D,
|
||||
0x00,0xAB,0x1B,0xC0,0x00,0xA3,0x03,0xAF,0x1C,0xC9,0x43,0x80,0x04,0x8F,0x80,0x00,
|
||||
0x08,0x8F,0x80,0x00,0xA8,0x8E,0x80,0x00,0xF0,0x8E,0x80,0x00,0xD4,0x8E,0x80,0x00,
|
||||
0xEC,0x8E,0x80,0x00,0x4C,0x8F,0x80,0x00,0xCC,0x8E,0x80,0x00,0x00,0x8F,0x80,0x00,
|
||||
0x78,0x93,0x80,0x00,0x98,0x8E,0x80,0x00,0xD8,0x8E,0x80,0x00,0x00,0xA3,0x08,0xAF,
|
||||
0x00,0xC1,0x0A,0x3B,0xE1,0xF0,0xCB,0xE8,0x73,0x09,0x5B,0xF0,0x00,0xA0,0x2A,0x1E,
|
||||
0x59,0x1E,0x51,0xEA,0xCA,0xE7,0x89,0xE8,0x70,0x08,0x51,0x00,0x1B,0x1A,0x32,0x28,
|
||||
0x00,0xA9,0x0E,0xC0,0x18,0xF4,0x12,0xF4,0x12,0xE4,0x00,0xE4,0x10,0xEA,0xC3,0xE7,
|
||||
0xC0,0xE8,0x58,0x00,0x64,0xA3,0x58,0x03,0xFE,0x97,0x40,0x9F,0x00,0xF4,0x00,0xFC,
|
||||
0x00,0x80,0x67,0x08,0x0A,0x39,0xE2,0xF0,0x52,0xE8,0x40,0xF0,0x65,0x0B,0x92,0xF0,
|
||||
0x01,0xB0,0xD0,0x10,0x0A,0x3A,0xE3,0xF0,0x29,0x28,0x9B,0xE8,0x5E,0x0A,0x5B,0xF0,
|
||||
0x99,0x12,0x5E,0x0A,0x31,0x28,0x99,0x12,0x0A,0x3B,0x07,0xA2,0x01,0xB3,0x1A,0x00,
|
||||
0x5D,0x0B,0x1A,0x15,0x07,0xAF,0x15,0xC8,0x5C,0x0B,0x01,0xB7,0x1F,0x15,0x11,0x80,
|
||||
0x55,0x08,0x21,0xF1,0x0B,0x12,0x55,0x0B,0x30,0x28,0xC8,0x12,0x01,0xA3,0x13,0x15,
|
||||
0x3B,0x15,0x57,0x0A,0x00,0xA7,0xE9,0x1F,0xA3,0xF0,0x99,0x10,0x00,0xA0,0x31,0x1E,
|
||||
0x54,0x0A,0x99,0x10,0xE3,0xF0,0x54,0x0A,0x1B,0xE9,0x5B,0xF0,0x99,0x1C,0xD3,0xE8,
|
||||
0x5A,0x48,0x12,0xF2,0x0A,0x03,0x03,0x32,0xD9,0x48,0x9A,0x48,0x09,0xF2,0x11,0x03,
|
||||
0x0A,0x31,0x5A,0x49,0x19,0x49,0x12,0xF2,0x0A,0x03,0x63,0xF0,0x04,0x32,0x1B,0xE9,
|
||||
0x4A,0x0A,0x5B,0xF0,0xD3,0xE8,0x5B,0x49,0x00,0xAB,0x50,0xC0,0x48,0x09,0xA7,0xF0,
|
||||
0x79,0x18,0x48,0x0A,0x8C,0x06,0xB9,0x18,0x00,0xA3,0xEA,0x1E,0x00,0xA0,0x33,0x1E,
|
||||
0x60,0x06,0xFF,0x97,0x07,0x98,0x11,0x39,0x8A,0xF0,0x52,0xE8,0x91,0xF0,0x42,0x0B,
|
||||
0x52,0xE8,0x42,0x09,0xF8,0x10,0x8A,0xE8,0x10,0x4A,0x04,0x39,0x84,0x06,0x50,0x4A,
|
||||
0x0A,0xF4,0x52,0xE4,0x00,0xF2,0x61,0x06,0x12,0xF4,0x01,0x03,0x12,0xFC,0x91,0x02,
|
||||
0x2D,0xC2,0x0A,0x38,0x02,0xF4,0x12,0xE4,0x04,0x32,0x04,0x38,0x00,0xA2,0xB1,0x1E,
|
||||
0x41,0xEA,0x18,0xB1,0x30,0xA9,0x22,0xC8,0x03,0x3A,0x11,0xF4,0x00,0xA2,0xA8,0x1E,
|
||||
0x09,0xE4,0x08,0xEA,0x1D,0xB0,0x3A,0xA8,0x19,0xC8,0x2D,0x08,0x38,0x18,0x84,0x06,
|
||||
0x8C,0x05,0x14,0xC1,0x2B,0x0A,0x04,0x38,0xB9,0x18,0x81,0x02,0x0F,0xC1,0x28,0xA2,
|
||||
0x69,0x06,0x51,0x1A,0x0C,0xA0,0x6A,0x06,0x82,0x1A,0x31,0x20,0x2A,0x20,0x1F,0x0A,
|
||||
0x12,0x1D,0x01,0xAA,0x01,0xC8,0x00,0xA2,0x00,0x80,0x01,0xA2,0xFA,0x10,0x24,0x0B,
|
||||
0x1B,0x58,0x76,0xB3,0x1B,0x28,0x0F,0xA2,0x13,0x00,0x28,0xEC,0x31,0xEC,0xB9,0xA2,
|
||||
0x00,0x90,0x26,0x99,0x15,0x80,0x13,0x0B,0x60,0xF1,0xC0,0xE8,0x00,0xA1,0x08,0xA2,
|
||||
0xFE,0x97,0xE5,0x9F,0x10,0x0A,0x00,0xA3,0x13,0x15,0x1A,0x0A,0x03,0xA1,0x11,0x15,
|
||||
0x19,0x09,0xA2,0xF0,0x53,0x10,0x19,0x09,0x3B,0x15,0x53,0x10,0x12,0x0B,0xFF,0xA1,
|
||||
0xD1,0x10,0x00,0xA3,0xEA,0x1E,0x0E,0x0B,0xA4,0xF0,0xE2,0x10,0x00,0xA7,0xF2,0x1F,
|
||||
0x0C,0x0B,0x12,0x60,0xE2,0x10,0xF0,0x6D,0x98,0x8E,0x80,0x00,0xD8,0x8E,0x80,0x00,
|
||||
0x90,0xE2,0x00,0x00,0xAC,0x8E,0x80,0x00,0xF8,0x8E,0x80,0x00,0xCC,0x8E,0x80,0x00,
|
||||
0xD4,0x8E,0x80,0x00,0xEC,0x8E,0x80,0x00,0x64,0x93,0x80,0x00,0xE8,0x93,0x80,0x00,
|
||||
0xA8,0x8E,0x80,0x00,0xF0,0x8E,0x80,0x00,0xF4,0x8E,0x80,0x00,0x48,0x93,0x80,0x00,
|
||||
0x7C,0x93,0x80,0x00,0xE8,0x8E,0x80,0x00,0xFC,0x8E,0x80,0x00,0xD0,0x8E,0x80,0x00,
|
||||
0xF0,0x65,0x51,0x0B,0x88,0x60,0x06,0x31,0x1B,0x58,0x05,0x30,0x06,0x28,0x06,0x38,
|
||||
0x76,0xB3,0x19,0x28,0x00,0x28,0x14,0xEC,0x49,0xF9,0x02,0x30,0x00,0xAE,0x01,0xC0,
|
||||
0x00,0xA9,0x03,0xC1,0x49,0x0B,0xA2,0xF0,0x00,0xA0,0xD0,0x10,0x47,0x0A,0xA3,0xF0,
|
||||
0x94,0x06,0x98,0x18,0x02,0x3A,0x12,0xF4,0x37,0xF4,0x45,0x0D,0x04,0x32,0x00,0xA8,
|
||||
0x05,0xC1,0x3F,0xE4,0x60,0x06,0x12,0xE4,0x1F,0x10,0xEA,0x10,0x7A,0x80,0x00,0xF4,
|
||||
0x02,0xFC,0xED,0x1A,0x3F,0xE4,0x03,0xE4,0x07,0x32,0x04,0x3A,0xFB,0xEA,0xD8,0xE7,
|
||||
0x12,0xE4,0x1B,0xE8,0x04,0x32,0x43,0x00,0x2A,0xF4,0x04,0x38,0x12,0xE4,0x82,0xEA,
|
||||
0xD0,0xE7,0x12,0xE8,0x03,0x35,0x42,0x00,0x8B,0x02,0x02,0xC9,0x14,0xA5,0x8A,0x02,
|
||||
0x39,0xC8,0xD3,0xE8,0x1A,0xF1,0xD3,0xEA,0x58,0xF0,0xFE,0x97,0x0B,0x9E,0x85,0xEE,
|
||||
0x05,0xA8,0x03,0xC8,0x00,0xA5,0x02,0xA8,0x00,0xC9,0x45,0xEE,0xB4,0xA3,0x00,0x33,
|
||||
0xA7,0xA3,0x01,0x33,0xB9,0xA0,0xB9,0xA1,0x3A,0xEC,0x04,0x3B,0x01,0x90,0xFE,0x9D,
|
||||
0x00,0xF6,0x00,0xFE,0x01,0xA8,0x04,0xC1,0x26,0x0B,0xA2,0xF0,0xD3,0x18,0x9B,0xF8,
|
||||
0x15,0x80,0x02,0xA8,0x04,0xC1,0x23,0x0B,0xA2,0xF0,0xD3,0x18,0xDB,0xF8,0x0E,0x80,
|
||||
0x2B,0xA3,0x63,0x03,0x20,0x0A,0xD3,0xE8,0x05,0xB3,0xDB,0x4F,0x01,0xAB,0x07,0xC9,
|
||||
0x1C,0x0B,0xA2,0xF0,0xD3,0x18,0x07,0xA2,0x9A,0x02,0x9B,0x01,0x5B,0x02,0xED,0xE8,
|
||||
0x14,0xAD,0x00,0xC9,0x14,0xA5,0x1F,0xA2,0x02,0x38,0x6B,0xEC,0x55,0xEB,0x07,0x3A,
|
||||
0x36,0xF4,0x11,0xF4,0x02,0xF4,0x03,0x38,0x12,0xE4,0x36,0xE4,0x09,0xE4,0x5E,0x03,
|
||||
0x69,0x03,0x53,0x03,0x02,0xF4,0x12,0xE4,0x55,0x03,0x71,0xE8,0x10,0xB1,0x05,0x3A,
|
||||
0xC9,0xF2,0x5B,0xE9,0x09,0xFC,0x10,0xB3,0x11,0x20,0xDB,0xF2,0x07,0x0A,0x06,0x38,
|
||||
0x09,0xF4,0x1B,0xFC,0xA4,0xF0,0x09,0xE4,0x03,0x20,0xA1,0x10,0x1B,0xF4,0x04,0x0A,
|
||||
0x1B,0xE4,0xA3,0x10,0x08,0x60,0xF0,0x6D,0x7C,0x93,0x80,0x00,0x04,0x8F,0x80,0x00,
|
||||
0x08,0x8F,0x80,0x00,0x00,0x8F,0x80,0x00,0x4C,0x8F,0x80,0x00,0x30,0x65,0x02,0xEC,
|
||||
0x00,0xA3,0x01,0x80,0x52,0xE0,0x01,0xB3,0x1F,0xAA,0xFB,0xCC,0x11,0xEC,0x99,0x00,
|
||||
0x41,0xEA,0x09,0xAB,0x03,0xCD,0x18,0xEC,0x0A,0xB8,0x01,0x01,0x02,0x80,0x0A,0xA0,
|
||||
0xC0,0xEA,0x81,0x00,0x08,0xEC,0x0C,0x0C,0x51,0xF0,0x01,0xB2,0x52,0xF0,0x09,0x1F,
|
||||
0x12,0x1F,0x52,0xEA,0x42,0x03,0x92,0xE2,0x52,0xE8,0xD9,0xF7,0x05,0xC5,0x07,0x09,
|
||||
0x4A,0x03,0x80,0xA5,0xED,0xF1,0x52,0xE9,0xD2,0xE3,0x58,0xE0,0x80,0xA1,0x82,0x00,
|
||||
0x09,0xF1,0x50,0xE8,0x00,0xE3,0x30,0x6D,0x04,0x8D,0x80,0x00,0x05,0xB5,0x00,0x00,
|
||||
0xF0,0x65,0x82,0x60,0x01,0x30,0x15,0xF4,0x18,0xF4,0x01,0x3B,0x2C,0xE4,0x00,0xE4,
|
||||
0x2D,0xFC,0x1F,0x28,0x28,0xEA,0x00,0xF4,0x00,0xE4,0x0E,0xEC,0x3F,0xF4,0x00,0xA3,
|
||||
0xC9,0x1E,0x02,0xEC,0x3F,0xE4,0x09,0xEB,0x50,0x03,0x3A,0xEB,0x00,0x32,0x0A,0xEC,
|
||||
0x51,0x03,0x00,0x3A,0x13,0xEC,0x53,0x03,0xC9,0xE8,0x81,0x02,0x23,0xCB,0x80,0xF3,
|
||||
0xFE,0x97,0x4C,0x9D,0xFF,0x97,0xAA,0x9F,0xA7,0x02,0x06,0xCA,0xE7,0xEB,0x47,0x03,
|
||||
0x01,0x3B,0xFF,0xF9,0xEF,0xEB,0x1F,0x20,0x06,0x80,0x00,0x3A,0x13,0xEC,0x43,0x03,
|
||||
0x01,0x3A,0xDB,0xF9,0xEB,0xE8,0x13,0x20,0x33,0x28,0x1B,0xF4,0x1B,0xE4,0xA3,0x02,
|
||||
0x04,0xCA,0xE4,0xEA,0x60,0x03,0xC0,0xF9,0x2D,0xEA,0x03,0x80,0x1C,0xEB,0x60,0x03,
|
||||
0xC0,0xF9,0x2D,0xE8,0x35,0x20,0x02,0x60,0xF0,0x6D,0xC0,0x46,0xF0,0x65,0x58,0x0B,
|
||||
0x08,0xA2,0x1A,0x40,0x57,0x0B,0x1D,0x58,0x2B,0xEC,0x08,0xB3,0xDA,0x2F,0x56,0x0B,
|
||||
0x10,0xF7,0x99,0xED,0xC0,0xFF,0xC8,0x47,0x96,0xFA,0x22,0xB1,0x0E,0x40,0x91,0xF5,
|
||||
0x89,0xFE,0x09,0xF6,0x0C,0xFE,0x29,0xA7,0xFC,0x14,0x07,0xA7,0x17,0x00,0xDA,0xED,
|
||||
0xD7,0x47,0x4E,0x0A,0x34,0xEB,0xD4,0x47,0x2A,0xEC,0x4C,0xB2,0x17,0x28,0x3A,0xFA,
|
||||
0x5A,0x42,0x1F,0x42,0x2A,0xEC,0x4E,0xB2,0x14,0x28,0x83,0x60,0x01,0x34,0x12,0x48,
|
||||
0x9A,0x42,0x22,0xFA,0xDA,0x42,0x2A,0xEC,0x48,0xB2,0x14,0x48,0x9C,0x44,0x52,0x48,
|
||||
0xDA,0x44,0x2A,0xEC,0x4A,0xB2,0x14,0x48,0x1C,0x44,0x52,0x48,0x1C,0xEC,0x5A,0x44,
|
||||
0x2A,0xB4,0x4A,0xFE,0x22,0x40,0x2B,0xB3,0x00,0xA8,0x02,0xC0,0x89,0xFE,0x19,0x40,
|
||||
0x00,0x80,0x1A,0x40,0x38,0x0C,0x72,0xA3,0x01,0xA0,0x23,0x43,0xA3,0x43,0x60,0x43,
|
||||
0xE0,0x43,0x2B,0xEC,0x64,0xB3,0x1B,0x48,0x3F,0xA2,0x1A,0x00,0x63,0xED,0xDA,0x47,
|
||||
0x00,0xA6,0x1E,0xA3,0xE6,0x45,0xA3,0x45,0x2B,0xEC,0x8E,0xB3,0x18,0x28,0x82,0xF9,
|
||||
0xFF,0xA3,0x11,0xEC,0x19,0x00,0x18,0x00,0x12,0xFA,0x00,0x31,0x21,0x47,0x62,0x47,
|
||||
0x02,0x30,0xA0,0x46,0x00,0xA0,0xE0,0x46,0x28,0xEC,0x8A,0xB0,0x00,0x28,0x80,0xF9,
|
||||
0x01,0xEC,0x19,0x00,0x00,0xFA,0xA1,0x47,0xE0,0x47,0x28,0xEC,0x8C,0xB0,0x00,0x28,
|
||||
0x03,0x00,0x60,0xEC,0xC3,0x47,0xA3,0xEC,0x00,0xA0,0xD8,0x47,0x6B,0x06,0x1B,0x48,
|
||||
0x62,0x45,0x23,0x45,0x68,0x06,0x08,0xA1,0x08,0x1C,0x00,0xA1,0x20,0x46,0x61,0x46,
|
||||
0x01,0x3A,0xB9,0xA1,0x50,0xF3,0x49,0xF0,0xB9,0xB0,0xFE,0x97,0x9F,0x9C,0x03,0xFA,
|
||||
0x20,0x41,0x63,0x41,0x7F,0xF3,0x03,0xFC,0x00,0xFE,0xE0,0x41,0xB9,0xA1,0x38,0xEC,
|
||||
0xA3,0x41,0x49,0xF0,0xB9,0xB0,0xFE,0x97,0x91,0x9C,0x03,0xFA,0x63,0x40,0x03,0xFC,
|
||||
0x20,0x40,0xA3,0x40,0x00,0xFE,0xE3,0xEC,0x20,0xA2,0xE0,0x40,0xDA,0x47,0x23,0xED,
|
||||
0x03,0xA2,0xDA,0x47,0x7A,0xB5,0x2B,0x48,0x0F,0xA2,0x13,0x00,0x2C,0xB4,0x23,0x40,
|
||||
0x07,0x0B,0x01,0xA4,0x03,0x60,0x5C,0x40,0x1E,0x40,0xDE,0x45,0x5E,0x46,0xF0,0x6D,
|
||||
0x83,0x00,0x80,0x00,0x7C,0x93,0x80,0x00,0x6C,0x90,0x80,0x00,0x74,0x90,0x80,0x00,
|
||||
0x2C,0x8F,0x80,0x00,0x10,0x65,0x0E,0x0C,0x0E,0x09,0x20,0x58,0xFE,0x97,0xD0,0x9D,
|
||||
0x00,0xA8,0x14,0xC0,0x0C,0x0B,0x5A,0x48,0x00,0xAA,0x06,0xC0,0x1A,0x48,0x00,0xAA,
|
||||
0x03,0xC0,0x9B,0x2B,0xA2,0x28,0x9A,0x02,0x09,0xC0,0x08,0x0B,0x66,0xA2,0x1A,0x40,
|
||||
0x05,0x0B,0x9A,0x2B,0x02,0x0B,0x9A,0x20,0x05,0x0A,0x12,0x58,0x1A,0x50,0x10,0x6D,
|
||||
0x70,0x8E,0x80,0x00,0x40,0x42,0x0F,0x00,0x2C,0x8F,0x80,0x00,0x0F,0x04,0x80,0x00,
|
||||
0x34,0x06,0x80,0x00,0x10,0x65,0xFF,0x97,0x2B,0x98,0xFF,0x97,0x8B,0x98,0x01,0x90,
|
||||
0xAB,0x9C,0x0C,0x0C,0x80,0xA1,0x20,0xEC,0x09,0xF2,0xCC,0xA2,0x01,0x90,0x69,0x9C,
|
||||
0x20,0xEC,0xCC,0xA1,0x01,0x90,0x7A,0x9C,0x00,0xA8,0x04,0xC1,0xFF,0x97,0x06,0x9F,
|
||||
0xFF,0x97,0xDC,0x98,0x02,0x80,0x00,0xA3,0x23,0x20,0x63,0x20,0xFF,0x97,0x14,0x99,
|
||||
0x10,0x6D,0xC0,0x46,0x00,0x9E,0x80,0x00,0x10,0x65,0xFF,0x97,0xDB,0x9F,0x06,0x0C,
|
||||
0x03,0x80,0xFF,0x97,0xAF,0x9F,0xFF,0x97,0x63,0x99,0x63,0x48,0x00,0xAB,0xF8,0xC0,
|
||||
0x00,0x90,0x24,0x98,0x10,0x6D,0xC0,0x46,0x2C,0x8F,0x80,0x00,0x10,0x65,0x0A,0x0B,
|
||||
0x1B,0x48,0x05,0xAB,0x02,0xC1,0x09,0x0B,0xFF,0xA2,0x1A,0x40,0x08,0x0B,0x1A,0x58,
|
||||
0x08,0x0B,0x09,0x0C,0x1A,0x50,0x00,0xA3,0x23,0x40,0x64,0xA0,0x01,0xA1,0xFE,0x97,
|
||||
0x59,0x9F,0x08,0xA3,0x23,0x40,0x10,0x6D,0x03,0x00,0x80,0x00,0x80,0x9F,0x80,0x00,
|
||||
0x34,0x06,0x80,0x00,0x68,0x90,0x80,0x00,0x83,0x00,0x80,0x00,0xF0,0x65,0xFE,0x97,
|
||||
0xD7,0x9C,0x87,0x0B,0x00,0xA2,0x1A,0x41,0xDA,0x46,0x64,0xA2,0x1A,0x46,0x84,0x0B,
|
||||
0x5B,0x4D,0x00,0xAB,0xFB,0xC0,0x83,0x0B,0x1B,0x58,0xDB,0x28,0x1B,0xFB,0x9C,0x06,
|
||||
0x81,0x0B,0x00,0xA2,0x1A,0x20,0x81,0x0B,0x28,0xB3,0x1A,0x48,0x00,0xA1,0x57,0xF0,
|
||||
0x00,0xA3,0x7F,0x08,0x1E,0x80,0x7F,0x0C,0x7F,0x0E,0xE5,0x1A,0xF4,0x1A,0x2D,0xEB,
|
||||
0x2D,0xF4,0x2D,0xFC,0x7D,0x0E,0x2C,0xF4,0x24,0xE4,0xF5,0x12,0x00,0xAC,0x0D,0xCD,
|
||||
0x26,0xEC,0x64,0x06,0x74,0x03,0xE4,0xE0,0x2C,0xE9,0x24,0xF4,0x24,0xFC,0xC4,0x12,
|
||||
0xB4,0xAC,0x06,0xC9,0x01,0xB1,0x09,0xF4,0x09,0xFC,0x02,0x80,0xC4,0xE8,0x00,0xA5,
|
||||
0x25,0x20,0x02,0xB3,0xBB,0x02,0xDE,0xC1,0x6B,0x0B,0x19,0x20,0x68,0x0B,0x09,0xF6,
|
||||
0x09,0xFE,0x19,0x45,0x6E,0x0B,0x1B,0x48,0x01,0xAB,0x04,0xC1,0x52,0xF0,0x6D,0x08,
|
||||
0x67,0x09,0x01,0x90,0xD6,0x9B,0x62,0x0B,0x1A,0x4D,0x00,0xAA,0x0B,0xC1,0xD9,0x4D,
|
||||
0xA8,0xA9,0x02,0xC9,0x01,0xA2,0x5A,0x46,0x1F,0x80,0xD9,0x4D,0x01,0xB1,0x09,0xF6,
|
||||
0x09,0xFE,0xD9,0x45,0x01,0x80,0x00,0xA2,0xDA,0x45,0x5A,0x46,0xFE,0x97,0x78,0x9C,
|
||||
0x01,0x90,0xC4,0x9C,0x00,0x90,0xEC,0x99,0x00,0x90,0x7E,0x9C,0x00,0x90,0x84,0x9F,
|
||||
0x54,0x0B,0x1B,0x58,0x72,0xB3,0x1B,0x28,0xD8,0xF6,0x02,0xC5,0x5A,0x08,0x00,0x90,
|
||||
0xC7,0x98,0x00,0x90,0xD4,0x98,0x01,0x90,0x01,0x9C,0x4D,0x0B,0x5A,0x4D,0x00,0xAA,
|
||||
0xFC,0xC0,0xDB,0x4E,0x00,0xAB,0x08,0xC0,0x54,0x0B,0x55,0x09,0x18,0x58,0xFE,0x97,
|
||||
0xD7,0x9C,0x00,0xA8,0x01,0xC0,0xFF,0x97,0x59,0x9F,0x45,0x0B,0x5A,0x4E,0x01,0xAA,
|
||||
0x1C,0xC1,0x4B,0x0B,0x1B,0x48,0x05,0xAB,0x08,0xC1,0x4E,0x08,0xFE,0x97,0xA4,0x9B,
|
||||
0x4A,0x0B,0x4D,0x09,0x1A,0x58,0x52,0xE8,0x1A,0x50,0x43,0x80,0x4B,0x08,0x00,0xA1,
|
||||
0xFE,0x97,0xB0,0x9E,0xFE,0x97,0x3C,0x9C,0x3A,0x0B,0x1B,0x58,0x7A,0xB3,0x1B,0x48,
|
||||
0x0F,0xA2,0x1A,0x00,0x39,0x0B,0x01,0xBA,0x2C,0xB3,0x2B,0x80,0x5A,0x4E,0x00,0xAA,
|
||||
0x2A,0xC1,0xD9,0x48,0x00,0xA9,0x0C,0xC0,0xD9,0x48,0x01,0xB9,0x09,0xF6,0x09,0xFE,
|
||||
0xD9,0x40,0x01,0xA1,0x19,0x41,0x3E,0x0B,0x1A,0x40,0x3E,0x0B,0x1A,0x58,0x37,0x0B,
|
||||
0x1A,0x50,0x2B,0x0B,0x1A,0x49,0x01,0xAA,0x02,0xC1,0x52,0xA0,0x01,0xA1,0x07,0x80,
|
||||
0x1B,0x4D,0x00,0xAB,0x02,0xC0,0x52,0xA0,0x00,0xA1,0x01,0x80,0xB6,0xA0,0x02,0xA1,
|
||||
0xFE,0x97,0x80,0x9E,0x22,0x0B,0x1A,0x49,0x01,0xAA,0x0B,0xC1,0x00,0xA2,0x1A,0x41,
|
||||
0x2F,0x0B,0x08,0xA2,0x1A,0x40,0x05,0x80,0x5B,0x4E,0x02,0xAB,0x02,0xC1,0x2E,0x08,
|
||||
0xFE,0x97,0x5A,0x9B,0x1A,0x0B,0x19,0x4F,0x5A,0x4F,0x12,0xF2,0x0A,0x03,0x01,0xB2,
|
||||
0xFF,0xA0,0x11,0xF4,0x02,0x00,0x18,0x4F,0x1A,0x47,0x0A,0xFE,0x59,0x4F,0x5A,0x47,
|
||||
0x1A,0x4E,0x00,0xAA,0x04,0xC0,0x1A,0x4E,0x01,0xBA,0x12,0xF6,0x12,0xFE,0x1A,0x46,
|
||||
0x0F,0x0B,0xDA,0x4B,0x5A,0x43,0xFE,0x97,0x2F,0x9D,0x20,0x0B,0x66,0xA2,0x1A,0x40,
|
||||
0x13,0x0B,0x1A,0x48,0x01,0xAA,0x06,0xC1,0x01,0x90,0xE2,0x9C,0x01,0x90,0x1C,0x9D,
|
||||
0x01,0x90,0x50,0x9C,0x07,0x80,0x1B,0x48,0xFF,0xAB,0x04,0xC1,0x01,0x90,0xD8,0x9C,
|
||||
0x01,0x90,0x12,0x9D,0xF0,0x6D,0x64,0xA0,0xFE,0x97,0x92,0x9D,0xF7,0x86,0xC0,0x46,
|
||||
0x2C,0x8F,0x80,0x00,0x7C,0x93,0x80,0x00,0x7C,0x92,0x80,0x00,0x6C,0x90,0x80,0x00,
|
||||
0x5C,0x91,0x80,0x00,0xFC,0x90,0x80,0x00,0x9C,0x90,0x80,0x00,0x1C,0x92,0x80,0x00,
|
||||
0x03,0x00,0x80,0x00,0xBC,0x91,0x80,0x00,0xE0,0x93,0x80,0x00,0x68,0x90,0x80,0x00,
|
||||
0xC0,0xFB,0x39,0x00,0x14,0x05,0x00,0x00,0x80,0xB0,0xED,0xFF,0xF3,0x01,0x00,0x00,
|
||||
0x83,0x00,0x80,0x00,0x34,0x06,0x80,0x00,0x89,0xA9,0x03,0x00,0x0F,0x04,0x80,0x00,
|
||||
0x70,0x65,0x06,0x49,0x84,0xEC,0x05,0xEC,0x32,0xEC,0x21,0xEC,0xFF,0x97,0x60,0x9C,
|
||||
0x28,0xEC,0x32,0xEC,0x21,0xEC,0x00,0xA3,0xFF,0x97,0x7A,0x98,0x70,0x6D,0xF0,0x65,
|
||||
0x2E,0x0B,0x1B,0x58,0x76,0xB3,0x1B,0x48,0x1B,0xF6,0x1A,0xFF,0x1B,0xF1,0x84,0x60,
|
||||
0x1B,0xFF,0x00,0x32,0x00,0xA6,0x01,0x33,0x49,0x80,0x77,0xF0,0x28,0x0B,0xBF,0xE9,
|
||||
0x7F,0xF0,0xDD,0xE9,0x27,0x0C,0x6A,0x48,0xF9,0x1C,0x12,0xF2,0x63,0x48,0x0A,0x03,
|
||||
0x21,0x48,0x1B,0xF2,0x0B,0x03,0xA1,0x48,0x09,0xF4,0x0B,0x03,0xE1,0x48,0x12,0xF4,
|
||||
0x09,0xF6,0x12,0xE4,0x0B,0x03,0x53,0x03,0x1F,0x0A,0x9B,0xE8,0x5B,0xFB,0x03,0x33,
|
||||
0xEA,0x48,0xA9,0x48,0x63,0x49,0x12,0xF2,0x0A,0x03,0x21,0x49,0x1B,0xF2,0x0B,0x03,
|
||||
0xA1,0x49,0x09,0xF4,0x0B,0x03,0xE1,0x49,0x12,0xF4,0x09,0xF6,0x12,0xE4,0x0B,0x03,
|
||||
0x53,0x03,0x15,0x0A,0x9B,0xE8,0x5B,0xFB,0x02,0x33,0xE1,0x4A,0xA3,0x4A,0x09,0xF2,
|
||||
0x19,0x03,0x00,0x3A,0x02,0x78,0xFE,0x97,0xAC,0x9B,0x61,0x4A,0x23,0x4A,0x09,0xF2,
|
||||
0x19,0x03,0x01,0x3A,0x03,0x78,0xFE,0x97,0xA4,0x9B,0x03,0x3B,0x08,0x0A,0xD3,0x15,
|
||||
0x1B,0xFA,0x6B,0x40,0x02,0x3B,0xAB,0x40,0x1B,0xFA,0xEB,0x40,0x01,0xB6,0x07,0x0A,
|
||||
0xD3,0x4B,0x9E,0x02,0xB1,0xCB,0x04,0x60,0xF0,0x6D,0xC0,0x46,0x7C,0x93,0x80,0x00,
|
||||
0xE0,0x93,0x80,0x00,0x6C,0x90,0x80,0x00,0xFF,0x0F,0x00,0x00,0x2C,0x8F,0x80,0x00,
|
||||
0xF0,0x65,0x4E,0x0A,0x55,0x28,0x16,0x28,0x2B,0xF1,0x5B,0xEB,0x9B,0xE9,0x9E,0x60,
|
||||
0x9B,0xE0,0x09,0x33,0x33,0xF1,0x9B,0xEB,0x5B,0xE9,0x9B,0xE0,0x0A,0x33,0x90,0x2A,
|
||||
0x94,0x28,0x03,0xF1,0x1B,0xEA,0x1B,0xE9,0x9B,0xE0,0x0B,0x33,0x23,0xF1,0x1B,0xEB,
|
||||
0x1B,0xE8,0x9B,0xE0,0x0C,0x33,0x93,0x2B,0x91,0x29,0x03,0x33,0x03,0x3F,0x1B,0xF1,
|
||||
0xDB,0xEB,0x5B,0xE8,0x9B,0xE0,0x0D,0x33,0x0B,0xF1,0x5B,0xEA,0xDB,0xE9,0x9B,0xE0,
|
||||
0x0E,0x33,0xD3,0x2B,0x04,0x33,0x17,0x2C,0x3B,0xF1,0x05,0x37,0xDB,0xEB,0x04,0x3F,
|
||||
0xDB,0xE9,0x9B,0xE0,0x0F,0x33,0x3B,0xF1,0xDB,0xEB,0x05,0x3F,0xDB,0xE9,0x9B,0xE0,
|
||||
0x10,0x33,0x00,0xA3,0x07,0x33,0x4A,0x80,0x00,0xAB,0x01,0xC0,0x04,0xAB,0x03,0xC1,
|
||||
0x04,0xAA,0x37,0xC0,0x00,0xAA,0x35,0xC0,0x91,0xEE,0x08,0xEC,0x41,0x02,0x41,0x01,
|
||||
0x00,0xA9,0x06,0xC0,0x00,0xAB,0x04,0xC1,0x09,0x3F,0xAE,0x02,0x2B,0xC8,0x0A,0x3F,
|
||||
0x29,0x80,0x00,0xAA,0x08,0xC1,0x08,0x3F,0x00,0xAF,0x05,0xC0,0x02,0x38,0x0B,0x3F,
|
||||
0x84,0x02,0x20,0xC8,0x0C,0x3F,0x1E,0x80,0x04,0xAA,0x09,0xC1,0x08,0x3F,0x00,0xAF,
|
||||
0x06,0xC0,0x01,0x38,0x03,0x39,0x0D,0x3F,0x88,0x02,0x14,0xC8,0x0E,0x3F,0x12,0x80,
|
||||
0x00,0xA9,0x08,0xC0,0x04,0xAB,0x06,0xC1,0x04,0x38,0x05,0x39,0x0F,0x3F,0x88,0x02,
|
||||
0x09,0xC8,0x10,0x3F,0x07,0x80,0x07,0x38,0x14,0x09,0x47,0xF0,0x01,0xB0,0x7F,0x1A,
|
||||
0x07,0x30,0x00,0x80,0x00,0xA7,0x06,0x38,0x01,0xB2,0x07,0x20,0x02,0xB0,0x06,0x30,
|
||||
0x05,0xAA,0xB9,0xC1,0x01,0xB3,0x02,0x38,0x01,0x39,0x05,0xAB,0x0F,0xC0,0x9A,0xF0,
|
||||
0xD2,0xE8,0x52,0xF0,0x11,0x7F,0xBF,0xE8,0x06,0x37,0x00,0xA2,0x9F,0xEE,0x00,0x32,
|
||||
0x7A,0x02,0x7A,0x01,0x08,0x32,0x02,0x30,0x01,0x31,0x00,0xA2,0xA4,0x87,0x11,0x79,
|
||||
0x02,0x08,0x32,0xA2,0x01,0x90,0xD5,0x99,0x1E,0x60,0xF0,0x6D,0x5C,0x91,0x80,0x00,
|
||||
0xF0,0x65,0xB4,0x0E,0xB4,0x0C,0x00,0xA3,0x8A,0x60,0x33,0x40,0x20,0xEC,0x19,0xA1,
|
||||
0xFE,0x97,0xA2,0x9A,0x18,0xA8,0x00,0xCD,0x59,0x81,0x40,0xF0,0x03,0x1B,0xBD,0xAB,
|
||||
0x00,0xC8,0x54,0x81,0xFF,0x97,0x4C,0x9F,0x20,0xEC,0x19,0xA1,0xFE,0x97,0x94,0x9A,
|
||||
0x05,0xEC,0x18,0xA8,0x00,0xCD,0x4A,0x81,0x43,0xF0,0x1B,0x1B,0xBD,0xAB,0x00,0xC8,
|
||||
0x45,0x81,0xA6,0x0A,0x11,0xEC,0x80,0xB1,0x0B,0x40,0x81,0xB2,0x1B,0xFA,0x13,0x40,
|
||||
0x01,0xA3,0x33,0x40,0xA2,0x0B,0x05,0xA1,0x18,0x50,0xFE,0x97,0x6F,0x99,0x00,0xF6,
|
||||
0x00,0xFE,0x83,0xF1,0x9F,0x0E,0x1B,0xEA,0x9B,0xF0,0x9F,0x0C,0x30,0x40,0x18,0xEA,
|
||||
0x9E,0x0B,0x40,0xE9,0x18,0x40,0x19,0xA2,0x20,0xEC,0x00,0xA1,0xFE,0x97,0xB7,0x9A,
|
||||
0x63,0xE9,0x1A,0x48,0x01,0xA7,0x38,0xEC,0x02,0x03,0x1A,0x40,0x33,0x48,0x00,0xAB,
|
||||
0x06,0xC0,0x6A,0xEF,0xA2,0xE8,0x11,0x48,0x0F,0x03,0x17,0x40,0x03,0xAB,0x05,0xC8,
|
||||
0x6B,0xED,0xE3,0xE8,0x19,0x48,0x01,0xA2,0x0A,0x03,0x1A,0x40,0x8F,0x0B,0x1B,0x48,
|
||||
0x00,0xAB,0x07,0xC0,0x6A,0xEE,0xA2,0xE8,0x10,0x48,0x01,0xA1,0x01,0x03,0x11,0x40,
|
||||
0x03,0xAB,0x05,0xC8,0x01,0xB5,0x65,0xE9,0x2A,0x48,0x01,0xA3,0x13,0x03,0x2B,0x40,
|
||||
0x84,0x0B,0x1A,0x48,0x85,0x0B,0x19,0x48,0x93,0xF0,0x9B,0xE8,0x5B,0xE8,0x1D,0xEF,
|
||||
0x9E,0xEF,0x58,0xEF,0x01,0x35,0x40,0xF0,0x02,0x36,0x5E,0xEE,0x03,0x36,0x08,0x30,
|
||||
0x1E,0xED,0x01,0x38,0x5D,0xEC,0x04,0x36,0x5E,0xED,0x05,0x36,0x6D,0xF0,0x76,0x0E,
|
||||
0x40,0xF0,0x06,0xB3,0x07,0x35,0x09,0x30,0x06,0x33,0xB4,0x06,0x00,0xA3,0x00,0xAB,
|
||||
0x11,0xC1,0x04,0xA9,0x01,0xC1,0x01,0xA3,0x11,0x80,0x00,0xAA,0x01,0xC1,0x01,0xA3,
|
||||
0x0B,0x80,0x07,0x3D,0x66,0x06,0xAD,0x1B,0x08,0x38,0x00,0x35,0x87,0x1B,0x09,0x38,
|
||||
0x85,0x1B,0x01,0x38,0x33,0x80,0x01,0xAB,0x0E,0xC1,0x00,0xA9,0x10,0xC0,0x00,0xAA,
|
||||
0x01,0xC1,0x02,0xA3,0x0A,0x80,0x03,0x3E,0x63,0x08,0x75,0xF0,0x2D,0x1A,0x00,0x35,
|
||||
0x08,0x3D,0x02,0x3E,0x2F,0x1A,0x1F,0x80,0x02,0xAB,0x11,0xC1,0x00,0xA9,0x01,0xC1,
|
||||
0x03,0xA3,0x0F,0x80,0x04,0xAA,0x01,0xC1,0x03,0xA3,0x09,0x80,0x03,0x3E,0x5A,0x08,
|
||||
0x75,0xF0,0x2D,0x1A,0x05,0x3E,0x00,0x35,0x75,0xF0,0x2F,0x1A,0x04,0x3E,0x0B,0x80,
|
||||
0x04,0xA9,0x19,0xC0,0x04,0xAA,0x17,0xC0,0x53,0x08,0x07,0x3D,0x2D,0x1A,0x05,0x3E,
|
||||
0x00,0x35,0x75,0xF0,0x2F,0x1A,0x06,0x3E,0x75,0xF0,0x2D,0x1A,0x30,0xEC,0x00,0x3E,
|
||||
0xBF,0xE9,0xBD,0x02,0x08,0xCC,0x00,0xA8,0x06,0xCB,0x4F,0x0D,0x40,0xE9,0x05,0x48,
|
||||
0x00,0xAD,0x01,0xC1,0x01,0xA5,0x05,0x40,0x01,0xB3,0x04,0xAB,0xA7,0xC1,0x02,0xBA,
|
||||
0x1B,0xC4,0x90,0xF0,0x4B,0xEE,0x82,0xE8,0xD2,0xE8,0x43,0x0D,0xA0,0xE8,0x52,0xF0,
|
||||
0x52,0xE9,0x01,0xB1,0x01,0xA5,0x00,0xAB,0x09,0xCB,0x04,0xAB,0x0D,0xCC,0x06,0x48,
|
||||
0x00,0xAE,0x04,0xC1,0x17,0x28,0x56,0x29,0xB7,0x02,0x00,0xC2,0x05,0x40,0x01,0xB0,
|
||||
0x02,0xB2,0x8B,0x02,0x01,0xC0,0x01,0xB3,0xED,0x87,0x3C,0x0B,0x18,0x48,0x39,0x0B,
|
||||
0x1A,0x48,0x02,0xB2,0x04,0xAA,0x1C,0xCC,0x91,0xF0,0x43,0xEE,0x8A,0xE8,0xD2,0xE8,
|
||||
0x31,0x0D,0xA1,0xE8,0x05,0xBA,0x52,0xF0,0x52,0xE9,0x01,0xB0,0x01,0xA5,0x00,0xAB,
|
||||
0x09,0xCB,0x04,0xAB,0x0D,0xCC,0x0E,0x48,0x00,0xAE,0x04,0xC1,0x57,0x29,0x16,0x28,
|
||||
0xB7,0x02,0x00,0xC2,0x0D,0x40,0x01,0xB1,0x02,0xB2,0x83,0x02,0x01,0xC0,0x01,0xB3,
|
||||
0xED,0x87,0x2A,0x0B,0x1A,0x48,0x02,0xBA,0x1D,0xC4,0x26,0x0B,0x18,0x48,0x43,0xEE,
|
||||
0x99,0xF0,0xC9,0xE8,0x8A,0xE8,0x20,0x0D,0xA1,0xE8,0x52,0xF0,0x52,0xE9,0x01,0xB0,
|
||||
0x01,0xA5,0x5E,0xEC,0x09,0xC0,0x04,0xAB,0x0D,0xCC,0x0E,0x48,0x00,0xAE,0x04,0xC1,
|
||||
0x17,0x28,0x56,0x28,0xB7,0x02,0x00,0xC2,0x0D,0x40,0x05,0xB1,0x0A,0xB2,0x83,0x02,
|
||||
0x01,0xC0,0x01,0xB3,0xED,0x87,0x19,0x0B,0x18,0x48,0x02,0xB0,0x04,0xA8,0x1E,0xCC,
|
||||
0x14,0x0B,0x19,0x48,0x4B,0xEE,0x9A,0xF0,0xD2,0xE8,0x12,0xE8,0x0E,0x08,0xA4,0xE8,
|
||||
0x52,0xF0,0x12,0xE8,0x01,0xB1,0x01,0xA0,0x5D,0xEC,0x0A,0xC0,0x04,0xAB,0x0E,0xCC,
|
||||
0x25,0x48,0x00,0xAD,0x05,0xC1,0x95,0xEE,0x16,0x28,0x2D,0x28,0xAE,0x02,0x00,0xC2,
|
||||
0x20,0x40,0x05,0xB4,0x0A,0xB2,0x8B,0x02,0x01,0xC0,0x01,0xB3,0xEC,0x87,0x0A,0x60,
|
||||
0xF0,0x6D,0xC0,0x46,0x41,0x93,0x80,0x00,0x5C,0x91,0x80,0x00,0xA4,0x8F,0x80,0x00,
|
||||
0x44,0x93,0x80,0x00,0x40,0x93,0x80,0x00,0x80,0x92,0x80,0x00,0x42,0x93,0x80,0x00,
|
||||
0x10,0x65,0x09,0xF6,0x14,0xF4,0x09,0xFE,0x24,0xFC,0x04,0xA9,0x11,0xC0,0x03,0xA9,
|
||||
0x0A,0xC8,0x02,0xA9,0x04,0xC0,0x01,0xA9,0x0B,0xC1,0x40,0xF2,0xFF,0x97,0x76,0x9A,
|
||||
0x40,0xF2,0xFF,0x97,0x73,0x9A,0x04,0x80,0x08,0xA9,0x02,0xC1,0x03,0xEC,0x58,0x03,
|
||||
0x40,0xFA,0x60,0x03,0x64,0xA1,0xFE,0x97,0x0D,0x98,0x80,0xA3,0x9B,0xF0,0xC0,0xE8,
|
||||
0x10,0x6D,0xF0,0x65,0x8D,0x60,0x06,0x31,0x06,0x3A,0x07,0x28,0x13,0x28,0x75,0x09,
|
||||
0x7F,0xE8,0x5B,0xE8,0x3F,0xF4,0x1B,0xF4,0x1B,0xFC,0x3F,0xFC,0x1D,0xF4,0x3C,0xF4,
|
||||
0x24,0xE4,0x2D,0xE4,0x05,0x30,0x00,0x33,0x01,0x33,0x28,0xEC,0x68,0x03,0x23,0xEC,
|
||||
0x63,0x03,0xC0,0xE8,0xFF,0x97,0x4A,0x9A,0x6B,0x0B,0x3E,0xEC,0x02,0x30,0x98,0x02,
|
||||
0x00,0xC8,0xCD,0x80,0x00,0xAD,0x13,0xCA,0x00,0xAC,0x06,0xCA,0x7E,0x02,0xFF,0xA3,
|
||||
0x36,0xF4,0x03,0x33,0x36,0xFC,0x02,0xA3,0x02,0x80,0x01,0xA1,0x03,0x31,0x01,0xA3,
|
||||
0x00,0x39,0x4A,0x02,0x12,0xF4,0x12,0xFC,0x01,0x32,0xFF,0xA2,0x04,0x32,0xB0,0x80,
|
||||
0x00,0xAC,0x00,0xCD,0xA9,0x80,0x7E,0x02,0x01,0xA3,0x36,0xF4,0xFF,0xA1,0x04,0x33,
|
||||
0x36,0xFC,0x03,0x31,0x03,0xA3,0xA4,0x80,0x1C,0x48,0x0C,0x78,0x84,0x14,0x1C,0x49,
|
||||
0x0B,0x78,0x84,0x14,0x1C,0x4A,0x09,0x78,0x44,0x12,0x1C,0x4B,0x07,0x78,0x01,0xB2,
|
||||
0x44,0x12,0x01,0xB3,0x02,0xB1,0x04,0xAA,0xEE,0xC1,0x01,0x3A,0x37,0xF4,0x13,0xF4,
|
||||
0x1B,0xE4,0x3F,0xE4,0x00,0x33,0x9F,0x02,0x19,0xCA,0x78,0xF2,0x19,0xEC,0xFD,0x97,
|
||||
0xA9,0x9F,0x01,0xA5,0x04,0xEC,0xFF,0xA8,0x2D,0xC8,0x00,0xAE,0x0B,0xC0,0x00,0x3B,
|
||||
0x39,0xEC,0x58,0xF2,0xFD,0x97,0x9E,0x9F,0xA0,0xA3,0x5B,0xF1,0x04,0xEC,0x00,0xA5,
|
||||
0x98,0x02,0x1F,0xC8,0x01,0x80,0xA0,0xA4,0x64,0xF1,0x00,0xA5,0x1B,0x80,0x00,0x39,
|
||||
0x48,0xF2,0x39,0xEC,0xFD,0x97,0x8E,0x9F,0x02,0xA5,0x04,0xEC,0xFF,0xA8,0x12,0xC8,
|
||||
0x01,0x3A,0x00,0xAA,0x0A,0xC0,0x78,0xF2,0x00,0x39,0xFD,0x97,0x83,0x9F,0xA0,0xA3,
|
||||
0x5B,0xF1,0x04,0xEC,0x03,0xA5,0x98,0x02,0x04,0xC8,0x01,0x80,0xA0,0xA4,0x64,0xF1,
|
||||
0x03,0xA5,0x00,0x80,0x1C,0xEC,0x0C,0x7B,0x59,0x1D,0x6F,0xF0,0x09,0x7B,0xFA,0x1A,
|
||||
0x20,0xEC,0xFF,0x97,0x45,0x9F,0x00,0x30,0x0B,0x7B,0x59,0x1D,0x07,0x7B,0xFA,0x1A,
|
||||
0x20,0xEC,0xFF,0x97,0x3D,0x9F,0x02,0x3B,0x1D,0xEC,0x28,0x0B,0x00,0x39,0xED,0xE8,
|
||||
0x0B,0xEC,0x6B,0x03,0x26,0x0A,0x36,0xF4,0x9B,0xE8,0x36,0xE4,0x07,0xEC,0x02,0x39,
|
||||
0x30,0xEC,0x58,0x03,0xFD,0x97,0x56,0x9F,0x7D,0x03,0x01,0x39,0x20,0x0B,0xC4,0xF1,
|
||||
0x08,0xF4,0xED,0xE8,0x00,0xE4,0x68,0x03,0x02,0x39,0xFD,0x97,0x4B,0x9F,0xB9,0xA3,
|
||||
0x24,0xFC,0xC0,0xF1,0xDB,0xF0,0x00,0xFC,0x22,0xEC,0x9C,0x02,0x00,0xC9,0x1A,0xEC,
|
||||
0x03,0x39,0x0B,0xF6,0x1B,0xE6,0x11,0xEC,0x1A,0xEC,0x4A,0x03,0xB9,0xA3,0xDB,0xF0,
|
||||
0xD2,0xE8,0x05,0x39,0xB9,0xA3,0xDB,0xF0,0x0A,0x20,0x02,0xEC,0x98,0x02,0x00,0xC9,
|
||||
0x1A,0xEC,0x04,0x39,0x0B,0xF6,0x1B,0xE6,0x11,0xEC,0x1A,0xEC,0x4A,0x03,0xB9,0xA3,
|
||||
0xDB,0xF0,0x06,0x39,0xD2,0xE8,0x0A,0x20,0x0A,0x80,0x01,0xA2,0x04,0x32,0x03,0x32,
|
||||
0x04,0xA3,0x08,0x0A,0x01,0xBB,0x1B,0xF1,0xD3,0xE8,0x00,0xA1,0x00,0xA2,0x53,0x87,
|
||||
0x0D,0x60,0xF0,0x6D,0x38,0xFA,0xFF,0xFF,0x56,0x04,0x00,0x00,0xAA,0xFB,0xFF,0xFF,
|
||||
0x00,0xAC,0x08,0x00,0x30,0x01,0x00,0x00,0xF0,0x65,0xCD,0x0B,0x18,0x29,0x94,0x60,
|
||||
0x00,0x30,0x9E,0x2A,0xCB,0x0B,0x00,0xA2,0xDA,0x43,0xCB,0x08,0x00,0xA1,0x19,0xA2,
|
||||
0xFE,0x97,0x55,0x98,0xC9,0x0B,0x1B,0x48,0x00,0xAB,0x00,0xC1,0x85,0x81,0xC8,0x0D,
|
||||
0x2C,0xEC,0x28,0xEC,0x00,0xA1,0x0C,0xA2,0x0C,0xB4,0xFE,0x97,0x48,0x98,0x20,0xEC,
|
||||
0x00,0xA1,0x0C,0xA2,0xFE,0x97,0x43,0x98,0x00,0xA3,0x15,0x80,0x03,0x48,0x01,0xA7,
|
||||
0x1F,0x02,0x06,0xC0,0x0F,0x28,0x13,0x28,0xFB,0xE8,0x13,0x20,0x23,0x28,0xFF,0xE8,
|
||||
0x27,0x20,0xBC,0x0B,0x02,0xB2,0x01,0xB0,0x02,0xB1,0x9A,0x02,0xEE,0xC1,0x63,0x06,
|
||||
0x05,0xB3,0x02,0xB4,0x19,0xAB,0x07,0xC0,0xB7,0x0F,0xD8,0xE9,0xB7,0x0F,0x59,0xF0,
|
||||
0x2A,0xEC,0xC9,0xE9,0x9C,0x06,0xE1,0x87,0xB3,0x08,0x00,0xA1,0x19,0xA2,0xFE,0x97,
|
||||
0x1E,0x98,0x00,0x38,0x00,0x3A,0x40,0xE0,0x71,0xE0,0xB1,0x0B,0xB1,0x0C,0x76,0xEA,
|
||||
0x12,0xEA,0x00,0xA7,0x08,0x30,0x09,0x31,0x0C,0x36,0x0B,0x32,0x0A,0x33,0x0D,0x34,
|
||||
0x06,0x37,0x00,0xA5,0x38,0x81,0x00,0xA0,0x10,0x7B,0x0D,0x3A,0x58,0x50,0x06,0x3B,
|
||||
0x02,0xDA,0x10,0x30,0x18,0xEC,0xA2,0x0B,0x0E,0x31,0xC0,0xE8,0x05,0xA1,0x0D,0x32,
|
||||
0xFD,0x97,0xB2,0x9F,0x9A,0x0F,0x01,0x30,0x02,0xB8,0x43,0xF0,0xFF,0xE8,0x01,0x3C,
|
||||
0x6B,0xF0,0x5B,0xE9,0x5B,0xF0,0x03,0xB4,0xC2,0xE8,0x02,0x30,0x98,0x09,0x07,0x34,
|
||||
0x04,0xEC,0x01,0x38,0x52,0xF0,0x00,0xA6,0x8A,0xE8,0x05,0x33,0x1B,0xE8,0x04,0x32,
|
||||
0x00,0x36,0x03,0x33,0x33,0x80,0x04,0xAC,0x2C,0xC8,0x02,0x39,0x8C,0x02,0x04,0xC0,
|
||||
0x04,0x38,0x03,0x28,0x94,0x02,0x1F,0xC1,0x0C,0x80,0x05,0x38,0x03,0x3A,0x8C,0x0B,
|
||||
0x01,0xE9,0x01,0xBA,0x49,0xF0,0x52,0xF0,0xD2,0x1A,0xC8,0x1A,0x03,0x39,0x50,0x03,
|
||||
0x4A,0xF0,0x07,0x80,0x03,0x39,0x86,0x0A,0x01,0xB1,0x49,0xF0,0x88,0x1A,0x03,0x39,
|
||||
0x58,0x03,0x4B,0xF0,0x99,0x1A,0xFD,0x97,0x69,0x9E,0x3B,0x28,0x43,0x03,0x00,0x3A,
|
||||
0x12,0xE8,0xF6,0xE8,0x00,0x32,0x05,0x80,0x3A,0x28,0x5A,0x03,0x00,0x38,0xC0,0xE8,
|
||||
0x00,0x30,0xB6,0xE8,0x04,0x39,0x02,0xB1,0x04,0x31,0x01,0xB4,0x02,0xB7,0x01,0x3A,
|
||||
0x07,0x3B,0x02,0xB2,0x9C,0x02,0xC6,0xC1,0x06,0x3C,0x20,0xEC,0x7A,0x0C,0x05,0xA1,
|
||||
0x00,0xE9,0x10,0x36,0xFD,0x97,0x58,0x9F,0x10,0x7B,0x01,0x30,0x6C,0x0A,0x02,0xB8,
|
||||
0x5F,0x58,0x43,0xF0,0xD3,0xE8,0x03,0x33,0x6B,0xF0,0x5B,0xE9,0x5B,0xF0,0xC2,0xE8,
|
||||
0x02,0x30,0x01,0x39,0x01,0x38,0x52,0xF0,0xA4,0xE8,0x03,0xB0,0x07,0x33,0x5B,0xE8,
|
||||
0x05,0x34,0x0F,0x30,0x02,0x3C,0x00,0xA6,0x04,0x33,0x39,0x80,0x04,0xAC,0x30,0xC8,
|
||||
0x02,0x3B,0x9C,0x02,0x04,0xC0,0x05,0x38,0x03,0x28,0x94,0x02,0x24,0xC1,0x10,0x80,
|
||||
0x07,0x38,0x04,0x3A,0x5E,0x0B,0x01,0xE9,0x01,0xBA,0x52,0xF0,0x49,0xF0,0x59,0xE8,
|
||||
0x9A,0xE8,0x92,0x29,0x88,0x29,0x04,0x39,0x50,0x03,0x4A,0xF0,0x9B,0xE8,0x99,0x29,
|
||||
0x0A,0x80,0x04,0x39,0x56,0x0A,0x01,0xB1,0x49,0xF0,0x51,0xE8,0x88,0x29,0x04,0x39,
|
||||
0x58,0x03,0x4B,0xF0,0xD2,0xE8,0x91,0x29,0xFD,0x97,0x08,0x9E,0x03,0x3A,0x13,0x28,
|
||||
0x43,0x03,0x36,0xE8,0xFF,0xE8,0x04,0x80,0x03,0x38,0x02,0x28,0x5A,0x03,0xF6,0xE8,
|
||||
0xBF,0xE8,0x03,0x39,0x05,0x3A,0x02,0xB1,0x02,0xB2,0x03,0x31,0x05,0x32,0x01,0xB4,
|
||||
0x01,0x3A,0x0F,0x3B,0x02,0xB2,0x9C,0x02,0xC0,0xC1,0x10,0x38,0x00,0x39,0xFD,0x97,
|
||||
0xED,0x9D,0x04,0xEC,0x29,0xBC,0x38,0xEC,0xFF,0xBC,0x31,0xEC,0x10,0x34,0xFD,0x97,
|
||||
0xE5,0x9D,0x08,0x3F,0x29,0xB8,0xFF,0xB8,0x11,0x30,0xBC,0x02,0x06,0xCA,0x3B,0xEB,
|
||||
0x9A,0xF0,0xD3,0xE8,0x9B,0xF0,0xDB,0xE1,0xE4,0xEA,0x08,0x80,0x0B,0x39,0x8C,0x02,
|
||||
0x06,0xCD,0x63,0xEA,0x9A,0xF0,0xD3,0xE8,0x9B,0xF0,0xDB,0xE1,0x1C,0xE9,0x10,0x34,
|
||||
0x09,0x3A,0x90,0x02,0x06,0xCA,0x13,0xEA,0x9A,0xF0,0xD3,0xE8,0x9B,0xF0,0xDB,0xE1,
|
||||
0xC0,0xEA,0x08,0x80,0x0C,0x3B,0x98,0x02,0x06,0xCD,0xC3,0xEA,0x9A,0xF0,0xD3,0xE8,
|
||||
0x9B,0xF0,0xDB,0xE1,0x18,0xE8,0x11,0x30,0x10,0x3B,0x10,0x7C,0xA3,0x50,0x63,0x58,
|
||||
0x12,0x78,0xE3,0x50,0x13,0x79,0xFF,0x97,0xAC,0x9D,0xA3,0x58,0x07,0xAB,0x01,0xCC,
|
||||
0x08,0xA3,0xA3,0x50,0x10,0x7B,0xDA,0x58,0x07,0xAA,0x01,0xCC,0x08,0xA2,0xDA,0x50,
|
||||
0x10,0x7B,0x99,0x58,0xDA,0x58,0xC9,0xE0,0xD2,0xE0,0x99,0x50,0xDA,0x50,0xAB,0xF0,
|
||||
0x5B,0xE9,0x0E,0x3F,0x98,0xF0,0x1B,0xE8,0x17,0x08,0x7C,0xF0,0x1B,0x0F,0xC3,0xE8,
|
||||
0xE7,0x1D,0x18,0xEC,0x08,0xB0,0x87,0x40,0x18,0x0F,0xE4,0xE9,0x64,0x48,0xC4,0x40,
|
||||
0x00,0x3C,0x36,0xE9,0x1E,0x42,0x36,0xFA,0x46,0x40,0x18,0xED,0x19,0x41,0x82,0x40,
|
||||
0x09,0xFA,0x12,0xFA,0x41,0x40,0xC2,0x40,0x0A,0x3F,0x3D,0x40,0x06,0x38,0x19,0xB7,
|
||||
0x0C,0xB0,0x0A,0x37,0x06,0x30,0x01,0xB5,0x08,0x09,0x0B,0x48,0x9D,0x02,0x00,0xCA,
|
||||
0xC1,0x86,0x2D,0xF6,0x03,0x0B,0x2D,0xFE,0xDD,0x43,0x14,0x60,0xF0,0x6D,0xC0,0x46,
|
||||
0x48,0x8D,0x80,0x00,0x2C,0x8F,0x80,0x00,0x48,0x93,0x80,0x00,0x41,0x93,0x80,0x00,
|
||||
0xF0,0x93,0x80,0x00,0xFA,0x93,0x80,0x00,0x80,0x92,0x80,0x00,0x5C,0x91,0x80,0x00,
|
||||
0x5C,0x93,0x80,0x00,0x44,0x93,0x80,0x00,0xFC,0x93,0x80,0x00,0x70,0x07,0x70,0x65,
|
||||
0x00,0xA2,0x02,0xA8,0x30,0xCD,0x2B,0xA4,0x61,0x03,0xC2,0xEE,0x17,0x0B,0x52,0xF0,
|
||||
0x52,0xE8,0xD6,0x1C,0x9A,0xE8,0x55,0x48,0x82,0xEE,0x52,0xF0,0x01,0xB8,0x52,0xE8,
|
||||
0x2D,0xF2,0x40,0xF0,0x41,0xE8,0x35,0x03,0xD6,0x1C,0x9A,0xE8,0x54,0x48,0xCA,0x1C,
|
||||
0x59,0xE8,0x4B,0x48,0x1B,0xF2,0x13,0x03,0x24,0xF2,0x1A,0xEC,0x34,0x03,0x19,0xBA,
|
||||
0x12,0xEB,0x10,0xF4,0x05,0xC4,0x21,0xEC,0x14,0xB9,0x49,0xEB,0x01,0xA2,0x08,0xF4,
|
||||
0x0A,0xC5,0x22,0xEC,0x19,0xBA,0xD3,0xEA,0x19,0xF4,0x04,0xC4,0x14,0xBD,0x2C,0xEB,
|
||||
0x02,0xA2,0x23,0xF4,0x00,0xC5,0x00,0xA2,0x10,0xEC,0x70,0x6D,0x4C,0x8F,0x80,0x00,
|
||||
0xF0,0x65,0x16,0xF6,0x36,0xFE,0x2B,0xA3,0x32,0xEC,0x5A,0x03,0x84,0x60,0x49,0x0C,
|
||||
0x00,0x32,0xA5,0xE8,0xEA,0x48,0xAB,0x48,0x12,0xF2,0xAF,0x4C,0x1A,0x03,0xEB,0x4C,
|
||||
0x01,0xB5,0xED,0x4F,0x01,0xBD,0x2D,0xF6,0x2D,0xFE,0x1B,0xF2,0x03,0x35,0x3B,0x03,
|
||||
0x6F,0xF0,0x00,0x3D,0x7F,0xE9,0x3D,0x1D,0xE7,0xE9,0x7F,0x48,0x2E,0xEC,0x3F,0xF2,
|
||||
0x3E,0x03,0x03,0x3F,0x00,0x3D,0x08,0xB7,0x7F,0xF0,0x7F,0xE9,0x3D,0x1D,0xE7,0xE9,
|
||||
0x7F,0x48,0x3F,0xF2,0x2F,0x03,0x35,0xF4,0x2D,0xE4,0xAE,0xEA,0xF5,0xE7,0x76,0xE9,
|
||||
0x3F,0xF4,0x6E,0x00,0x3F,0xE4,0x75,0xEC,0xFE,0xEA,0xF7,0xE7,0xF6,0xE9,0x7E,0x00,
|
||||
0x01,0xB6,0x02,0x50,0x02,0x36,0x0B,0x50,0x31,0xAA,0x03,0xCC,0x01,0xA2,0xB5,0x02,
|
||||
0x12,0xCC,0x54,0x80,0x2C,0x0F,0x2C,0x0E,0x7F,0x4B,0x36,0x4B,0x3F,0xF2,0x37,0x03,
|
||||
0x31,0xA6,0xBC,0x06,0x76,0x02,0xB4,0x04,0x01,0x37,0x94,0x05,0x06,0xCC,0x02,0x3F,
|
||||
0xBD,0x02,0x44,0xCD,0x01,0x3A,0x01,0xBA,0x02,0x50,0x3F,0x80,0x22,0x0E,0xB6,0x4B,
|
||||
0xB4,0x06,0x21,0x0E,0xF7,0x4B,0x66,0x06,0x3F,0xF2,0x3E,0x03,0xB4,0x06,0x40,0xA6,
|
||||
0x76,0x02,0x37,0xEC,0x67,0x04,0x9F,0x02,0x07,0xCD,0x00,0xA7,0x00,0x3C,0xBC,0x06,
|
||||
0x01,0x34,0x02,0xA7,0x64,0x06,0x94,0x06,0x1C,0x80,0x02,0x3E,0xB5,0x02,0x26,0xCA,
|
||||
0x01,0xA7,0x7F,0x02,0x3B,0xEC,0x02,0x50,0x63,0x04,0x1F,0x80,0x26,0xEC,0x01,0x3A,
|
||||
0x09,0xB6,0x76,0xF0,0xB6,0xE8,0x0F,0x0A,0xB2,0x1C,0x00,0x32,0x0D,0x0A,0xB6,0xE8,
|
||||
0x76,0x48,0x00,0x3A,0x36,0xF2,0x32,0x03,0x93,0x02,0x00,0xCD,0x13,0xEC,0x01,0xB7,
|
||||
0x3F,0xF6,0x3F,0xFE,0x03,0x3E,0x01,0xB4,0xB7,0x02,0xE7,0xC3,0x62,0x06,0x4A,0xAB,
|
||||
0x05,0xCC,0x02,0x3F,0xBD,0x02,0x02,0xCA,0x02,0x50,0x01,0xA3,0x0B,0x50,0x04,0x60,
|
||||
0xF0,0x6D,0xC0,0x46,0x4C,0x8F,0x80,0x00,0x6C,0x90,0x80,0x00,0xF0,0x65,0x12,0xF6,
|
||||
0x2B,0xA3,0x12,0xFE,0x5A,0x03,0x3A,0x0F,0x87,0x60,0x04,0x30,0x05,0x31,0xBB,0xE8,
|
||||
0x01,0xB3,0xDB,0x4F,0x37,0x0C,0x00,0xA0,0x01,0x33,0x00,0xA3,0x02,0x33,0x25,0xEC,
|
||||
0x03,0x30,0x00,0xA6,0x06,0x32,0x84,0x06,0x37,0x80,0x06,0x38,0x30,0x09,0x5A,0xF0,
|
||||
0x12,0xE8,0x50,0x1C,0x52,0xE8,0x51,0x48,0x09,0xF2,0x01,0x03,0x18,0xEC,0x06,0x3A,
|
||||
0x08,0xB0,0x2B,0x0F,0x40,0xF0,0x80,0xE8,0xC2,0x1D,0xC0,0xE9,0x40,0x48,0x00,0xF2,
|
||||
0x02,0x03,0x08,0xEC,0xB1,0x02,0x00,0xC2,0x30,0xEC,0x06,0xF4,0x36,0xFC,0x08,0xEC,
|
||||
0xA9,0x02,0x00,0xC9,0x28,0xEC,0x03,0x3F,0x05,0xF4,0x68,0x06,0x2D,0xFC,0x02,0x20,
|
||||
0xBA,0x02,0x02,0xC2,0x0C,0xA7,0x3F,0x1A,0x07,0x20,0x6F,0x06,0x3F,0x28,0x38,0xF4,
|
||||
0x00,0xFC,0x03,0x30,0x10,0xEC,0xA2,0x02,0x00,0xC9,0x20,0xEC,0x04,0xF4,0x02,0x38,
|
||||
0x80,0xE8,0x02,0x30,0x24,0xFC,0x8C,0x04,0x01,0xB3,0x1A,0xF6,0x01,0x39,0x12,0xFE,
|
||||
0x8A,0x02,0xC2,0xC3,0x60,0x06,0x02,0xA9,0x14,0xC9,0x0F,0xEC,0x02,0xBF,0x3F,0xF6,
|
||||
0x3F,0xFE,0x80,0xEB,0x39,0xEC,0x40,0xEB,0xFD,0x97,0x20,0x9C,0x04,0x3A,0x02,0x3B,
|
||||
0x03,0x39,0x10,0x50,0x58,0xEA,0x00,0xEB,0x39,0xEC,0xFD,0x97,0x17,0x9C,0x05,0x3A,
|
||||
0x10,0x50,0x0A,0x80,0x01,0x39,0xFD,0x97,0x11,0x9C,0x04,0x3B,0x01,0x39,0x18,0x50,
|
||||
0x02,0x38,0xFD,0x97,0x0B,0x9C,0x05,0x3F,0x38,0x50,0x07,0x60,0xF0,0x6D,0xC0,0x46,
|
||||
0x4C,0x8F,0x80,0x00,0xFF,0xFF,0x00,0x00,0xF0,0x65,0xC7,0x0B,0xDB,0x4B,0x8E,0x60,
|
||||
0x06,0xA2,0xC6,0x08,0x00,0xA1,0x05,0x33,0xFD,0x97,0x51,0x9D,0xC4,0x0B,0x1A,0xEC,
|
||||
0x81,0xB3,0x80,0xB2,0x1B,0x48,0x12,0x48,0x1B,0xF2,0x13,0x03,0x63,0xAB,0x08,0xC8,
|
||||
0xC0,0x0B,0x1B,0x58,0x7A,0xB3,0x1B,0x48,0x0F,0xA2,0x1A,0x00,0xBE,0x0B,0x2C,0xB3,
|
||||
0x1A,0x40,0xBD,0x0B,0x2C,0xB3,0x1B,0x48,0x00,0xA0,0x07,0x33,0x04,0x30,0x00,0xA5,
|
||||
0xCE,0x82,0x00,0xA1,0x0D,0x31,0x0C,0x31,0xA9,0xF0,0x49,0xE9,0x8B,0xF0,0xB7,0x0A,
|
||||
0xC9,0xE8,0x89,0xE8,0x0C,0x4D,0x2B,0xA2,0x62,0x03,0xB5,0x0B,0xD2,0xE8,0x53,0xEC,
|
||||
0xDE,0x4F,0x0B,0xEC,0x08,0xB3,0x58,0x48,0x09,0x4A,0x00,0xF2,0x08,0x03,0x02,0x30,
|
||||
0x99,0x48,0xDB,0x48,0x1B,0xF2,0x0B,0x03,0x08,0x33,0x03,0xB2,0xD3,0x4F,0x00,0xAB,
|
||||
0x09,0xC0,0xA5,0x0F,0xFA,0x4C,0x01,0xA3,0x22,0x01,0x13,0x02,0x03,0xC0,0xFA,0x4C,
|
||||
0xA3,0x00,0x9A,0x03,0xFA,0x44,0x2B,0xA3,0x63,0x03,0xA5,0x0A,0xD3,0xE8,0xDA,0xEC,
|
||||
0x00,0xA0,0xD0,0x47,0x02,0xB3,0xDB,0x4F,0x00,0xAB,0x02,0xC1,0xA1,0x0B,0x01,0xA2,
|
||||
0x1A,0x15,0xA0,0x0B,0x1B,0x1D,0x00,0xAB,0x4E,0xC0,0x9C,0x09,0x07,0x3A,0x8C,0x06,
|
||||
0x9B,0x0F,0xA9,0xF0,0xB2,0x02,0x25,0xC9,0x2B,0xA3,0x18,0xEC,0x60,0x03,0x72,0xF0,
|
||||
0x49,0xE9,0x03,0x30,0x12,0xE8,0x88,0xF0,0x09,0xE8,0x61,0x04,0x08,0xED,0x09,0x49,
|
||||
0x8C,0x06,0x41,0x48,0x63,0x06,0x09,0xF2,0x19,0x03,0xB9,0x14,0x09,0xFA,0xBA,0xE8,
|
||||
0x51,0x40,0x32,0xEC,0x03,0x39,0x08,0xB2,0x52,0xF0,0x53,0xE8,0xC1,0x48,0x82,0x48,
|
||||
0x09,0xF2,0x0A,0x03,0x01,0xB6,0xFA,0x14,0x36,0xF6,0x12,0xFA,0xFB,0xE8,0x5A,0x40,
|
||||
0x36,0xFE,0x21,0x80,0x2B,0xA3,0x18,0xEC,0x60,0x03,0x72,0xEE,0x49,0xE9,0x52,0xF0,
|
||||
0x03,0x30,0x12,0xE8,0x88,0xF0,0x09,0xE8,0x61,0x04,0x08,0xED,0x09,0x49,0x8C,0x06,
|
||||
0x41,0x48,0x63,0x06,0x09,0xF2,0x19,0x03,0xB9,0x14,0x09,0xFA,0xBA,0xE8,0x51,0x40,
|
||||
0x03,0x39,0xF2,0xED,0x52,0xF0,0x53,0xE8,0xC1,0x48,0x82,0x48,0x09,0xF2,0x0A,0x03,
|
||||
0xFA,0x14,0x12,0xFA,0xFB,0xE8,0x5A,0x40,0x02,0xAE,0x76,0xC9,0x2B,0xA1,0x61,0x03,
|
||||
0x73,0x0A,0x73,0xEE,0x88,0xE8,0x10,0xB1,0x5B,0xF0,0x89,0xE8,0xC9,0xE8,0xC0,0xE8,
|
||||
0xE3,0xF0,0x71,0x0A,0x1B,0xE9,0x06,0x31,0x03,0x30,0x5B,0xF0,0xD3,0xE8,0x5A,0x29,
|
||||
0x09,0x32,0x9F,0x29,0x0A,0x37,0x1B,0x2A,0x0B,0x33,0x66,0x0B,0x1B,0x58,0x8A,0xB3,
|
||||
0x1B,0x28,0x00,0xA1,0x42,0x1E,0x06,0x38,0x3F,0xA7,0x1F,0x00,0x00,0xA1,0x43,0x1E,
|
||||
0xA5,0xA1,0x00,0x31,0x01,0x31,0xB9,0xA0,0xB9,0xA1,0x00,0x90,0x2F,0x9B,0x00,0xA8,
|
||||
0x02,0xC0,0x05,0xBF,0x3F,0xF4,0x3F,0xFC,0x60,0x0B,0x02,0x3A,0x9A,0x02,0x39,0xCC,
|
||||
0x09,0x38,0x03,0xEC,0x7B,0x03,0x9B,0xF2,0x1B,0xFC,0x9A,0x02,0x12,0xCB,0x06,0xBF,
|
||||
0x3F,0xF4,0x0A,0x39,0x3F,0xFC,0x0B,0xEC,0x7B,0x03,0x9B,0xF2,0x1B,0xFC,0x9A,0x02,
|
||||
0x08,0xCB,0x0B,0x38,0x47,0x03,0x08,0x3A,0xBF,0xF2,0x13,0xF4,0x1B,0xE4,0x3F,0xFC,
|
||||
0xBB,0x02,0x1F,0xCA,0xE3,0xF0,0x50,0x0A,0x1B,0xE9,0x5B,0xF0,0xD3,0xE8,0x03,0x39,
|
||||
0xDA,0x28,0x0A,0x20,0xA8,0xF0,0x19,0x29,0x06,0x3B,0x40,0xE9,0x19,0x20,0x83,0xF0,
|
||||
0xC0,0xE8,0x46,0x0B,0x18,0xE8,0x03,0xED,0x02,0x41,0x12,0xFA,0x99,0x40,0x09,0xFA,
|
||||
0x5A,0x40,0xD9,0x40,0x3C,0x0B,0x01,0xA1,0xDA,0x4C,0xA1,0x00,0x0A,0x03,0x12,0xF6,
|
||||
0x12,0xFE,0xDA,0x44,0x38,0x0B,0xDB,0x4C,0x23,0x01,0xDF,0xF7,0x05,0xC5,0x05,0x3B,
|
||||
0x01,0xBB,0x1B,0xF6,0x1B,0xFE,0x05,0x33,0xC7,0x81,0x2B,0xA3,0x18,0xEC,0x60,0x03,
|
||||
0x37,0x0A,0x13,0xE8,0x59,0xEC,0xCE,0x47,0x03,0x30,0x99,0xEC,0xC8,0x4F,0x01,0xA8,
|
||||
0x6E,0xC8,0x24,0xB3,0x1A,0x49,0xD9,0x48,0x12,0xF2,0x0A,0x03,0x59,0x49,0x09,0xF4,
|
||||
0x0A,0x03,0x99,0x49,0x09,0xF6,0x0A,0x03,0x02,0x39,0x8A,0x02,0x07,0xCA,0xD9,0x40,
|
||||
0x02,0x38,0x02,0xFA,0x1A,0x41,0x00,0xA2,0x5A,0x41,0x02,0xFE,0x9A,0x41,0x30,0xEC,
|
||||
0x21,0xEC,0xFF,0x97,0x5C,0x9D,0x00,0xA8,0x0C,0xC0,0x22,0xEC,0x0D,0x78,0x0C,0x79,
|
||||
0xFF,0x97,0x8E,0x9D,0x2B,0xA3,0x63,0x03,0x21,0x0A,0xD3,0xE8,0x02,0xB3,0x02,0xA2,
|
||||
0xDA,0x47,0x23,0x80,0x07,0x39,0x1E,0x0F,0xB1,0x02,0x19,0xC8,0x0C,0x79,0x22,0xEC,
|
||||
0x0D,0x78,0xFF,0x97,0x1B,0x9E,0xAB,0xF0,0x5B,0xE9,0x9A,0xF0,0x9B,0xE8,0x17,0x0A,
|
||||
0xD3,0xE8,0x2B,0xA2,0x62,0x03,0xBF,0xE8,0x3A,0xEC,0x24,0xB2,0xD1,0x48,0x12,0x49,
|
||||
0x12,0xF2,0x11,0x03,0x19,0x42,0x09,0xFA,0x59,0x42,0x02,0xB7,0x07,0xA3,0x04,0x80,
|
||||
0x2B,0xA3,0x63,0x03,0xFF,0xE8,0x02,0xB7,0x01,0xA3,0xFB,0x47,0xE3,0xF0,0x0E,0x0A,
|
||||
0x1B,0xE9,0x0D,0x39,0x5B,0xF0,0x99,0x12,0xD3,0xE8,0x0C,0x3A,0x08,0xA6,0x5A,0x20,
|
||||
0x6A,0x06,0xB2,0x1A,0x9A,0x20,0x4A,0x81,0x2C,0x8F,0x80,0x00,0xE0,0x93,0x80,0x00,
|
||||
0xA4,0x8F,0x80,0x00,0x7C,0x93,0x80,0x00,0x6C,0x90,0x80,0x00,0x48,0x93,0x80,0x00,
|
||||
0x4C,0x8F,0x80,0x00,0x90,0x8E,0x80,0x00,0x64,0x93,0x80,0x00,0xCF,0x07,0x00,0x00,
|
||||
0x02,0xA8,0x45,0xC1,0xAF,0xF0,0x7F,0xE9,0xB8,0xF0,0x3F,0xE8,0xD6,0x08,0xC7,0xE9,
|
||||
0x38,0xED,0x08,0x30,0x3F,0x49,0x02,0x37,0x47,0x48,0x02,0x38,0x3F,0xF2,0x38,0x03,
|
||||
0x07,0xF4,0x3F,0xE4,0x02,0x37,0x48,0x48,0x9F,0x48,0x00,0xF2,0x07,0x03,0xBC,0x06,
|
||||
0x02,0x3F,0xBC,0x04,0x60,0x06,0x40,0xE0,0x02,0x30,0x0D,0x30,0x08,0x3F,0xBF,0x48,
|
||||
0xBC,0x06,0x08,0x3F,0xF8,0x48,0x67,0x06,0x00,0xF2,0x38,0x03,0x9F,0x4C,0xDB,0x4C,
|
||||
0x00,0xF4,0x1B,0xF2,0x3B,0x03,0x00,0xE4,0x03,0x3F,0xC0,0xE8,0x73,0xEE,0x5B,0xF0,
|
||||
0xFF,0xE8,0xBC,0x06,0x6B,0x06,0x08,0xA7,0xFB,0x1C,0x40,0xE0,0x67,0x06,0x0C,0x30,
|
||||
0xD3,0x15,0x02,0x3B,0x1F,0xFA,0x13,0xEC,0x63,0x04,0x5F,0x40,0x03,0x3F,0x07,0xB6,
|
||||
0x76,0xF0,0xF6,0xE9,0x90,0x15,0x00,0xFA,0x96,0xE9,0x70,0x40,0x03,0xA3,0x46,0x80,
|
||||
0x03,0xA8,0x46,0xC1,0xAF,0xF0,0x7F,0xE9,0xB8,0xF0,0x3F,0xE8,0xB2,0x08,0xC7,0xE9,
|
||||
0x38,0xED,0x08,0x30,0x3F,0x49,0x02,0x37,0x47,0x48,0x02,0x38,0x3F,0xF2,0x38,0x03,
|
||||
0x07,0xF4,0x3F,0xE4,0x02,0x37,0x48,0x48,0x9F,0x48,0x00,0xF2,0x07,0x03,0xBC,0x06,
|
||||
0x02,0x3F,0xBC,0x04,0x60,0x06,0x40,0xE0,0x02,0x30,0x0D,0x30,0x08,0x3F,0xBF,0x48,
|
||||
0xBC,0x06,0x08,0x3F,0xF8,0x48,0x67,0x06,0x00,0xF2,0x38,0x03,0x9F,0x4C,0xDB,0x4C,
|
||||
0x00,0xF4,0x1B,0xF2,0x3B,0x03,0x00,0xE4,0x03,0x3F,0xC0,0xE8,0x73,0xEE,0x5B,0xF0,
|
||||
0xFF,0xE8,0xBC,0x06,0x6B,0x06,0x08,0xA7,0xFB,0x1C,0x40,0xE0,0x67,0x06,0x0C,0x30,
|
||||
0xD3,0x15,0x02,0x3B,0x1F,0xFA,0x13,0xEC,0x63,0x04,0x5F,0x40,0x03,0x3F,0x07,0xB6,
|
||||
0x76,0xF0,0xF6,0xE9,0x90,0x15,0x00,0xFA,0x96,0xE9,0x70,0x40,0x07,0xA3,0xCB,0x47,
|
||||
0xA5,0x80,0x04,0xA8,0x02,0xC1,0x00,0xA0,0xC8,0x47,0xA0,0x80,0x07,0xA2,0xCA,0x47,
|
||||
0xA9,0xF0,0x49,0xE9,0x8A,0xF0,0x89,0xE8,0x8B,0x0A,0x51,0xE8,0x0A,0xED,0x56,0x48,
|
||||
0x09,0x49,0x36,0xF2,0x0E,0x03,0x36,0xF4,0x36,0xE4,0x0D,0x36,0xD7,0x48,0x91,0x48,
|
||||
0x3F,0xF2,0x0F,0x03,0x85,0x0A,0x3F,0xF4,0x3F,0xE4,0x12,0x58,0x0C,0x37,0x72,0xB2,
|
||||
0x12,0x28,0x91,0xF6,0x00,0xC4,0x82,0x80,0x05,0xB3,0x02,0x33,0xDB,0x4F,0x02,0xAB,
|
||||
0x7D,0xC8,0xE3,0xF0,0x7E,0x0A,0x1B,0xE9,0x5B,0xF0,0x98,0x1A,0x03,0x30,0xD3,0xE8,
|
||||
0x5B,0x28,0x06,0x33,0xA5,0xA3,0x32,0xEC,0x00,0x33,0x01,0x33,0xB9,0xA1,0x3B,0xEC,
|
||||
0xB9,0xA0,0x00,0x90,0x9B,0x99,0x03,0xEC,0x5A,0xEE,0x93,0x01,0x5B,0x02,0x14,0xA1,
|
||||
0x19,0x00,0x03,0x3B,0xF2,0xEA,0x12,0xF4,0x12,0xE4,0x09,0x31,0xD1,0xE7,0x50,0xE8,
|
||||
0x06,0x3A,0xBB,0xEA,0x1B,0xF4,0x48,0x00,0x1B,0xE4,0x08,0x30,0xD8,0xE7,0x1B,0xE8,
|
||||
0x08,0x3A,0x43,0x00,0x99,0xE8,0x09,0xF4,0x09,0xE4,0x50,0xA9,0x03,0xCD,0x02,0x38,
|
||||
0x03,0xA3,0xC3,0x47,0x38,0x80,0x32,0xA9,0x03,0xCD,0x02,0x39,0x02,0xA3,0xCB,0x47,
|
||||
0x32,0x80,0x09,0x3A,0x91,0x02,0x2F,0xCD,0x02,0x38,0xC0,0x4F,0x00,0xA2,0x84,0x06,
|
||||
0x94,0x05,0x29,0xC1,0x03,0x38,0x06,0x3A,0x00,0xF4,0x00,0xE4,0x12,0xF4,0x84,0x06,
|
||||
0x12,0xE4,0x66,0x04,0x94,0x06,0x02,0x3A,0x01,0xA0,0xD0,0x47,0x09,0x3A,0x67,0x04,
|
||||
0x76,0xE0,0x7F,0xE0,0x00,0xAA,0x17,0xC0,0x1E,0xA9,0x00,0xCC,0x00,0xA0,0x00,0xF6,
|
||||
0x00,0xA8,0x11,0xC0,0x59,0xF0,0x08,0x38,0xC9,0xE8,0x88,0x02,0x03,0xCD,0xA2,0xF0,
|
||||
0x01,0xA1,0x50,0x0B,0x07,0x80,0x08,0x3A,0x51,0xF0,0x8A,0xE8,0x93,0x02,0x03,0xCD,
|
||||
0x4D,0x0B,0xA2,0xF0,0x01,0xA1,0xD1,0x10,0x2B,0xA3,0x63,0x03,0x4B,0x0A,0xD3,0xE8,
|
||||
0x05,0xB3,0xDB,0x4F,0x00,0xAB,0x08,0xC1,0x03,0x3E,0x06,0x3F,0x33,0xF4,0x1B,0xE4,
|
||||
0x0D,0x33,0x3B,0xF4,0x1B,0xE4,0x0C,0x33,0x01,0x80,0x0D,0x36,0x0C,0x37,0x0D,0x3A,
|
||||
0x00,0xAA,0x12,0xC0,0x04,0x3B,0x59,0xF0,0x41,0x08,0xC9,0xE8,0x0C,0x3E,0x49,0xF0,
|
||||
0x43,0xE8,0x9E,0x40,0x36,0xFA,0xDE,0x40,0x42,0x14,0x12,0xFA,0x5A,0x40,0x1C,0x41,
|
||||
0x04,0x3B,0x01,0xB3,0x1B,0xF6,0x1B,0xFE,0x04,0x33,0x01,0xB5,0x2D,0xF4,0x2D,0xFC,
|
||||
0x38,0x0C,0xE3,0x4B,0x9D,0x02,0x00,0xC2,0x2B,0x85,0x05,0x3E,0x00,0xAE,0x00,0xC0,
|
||||
0xA1,0x80,0x0C,0x36,0x0D,0x36,0x2C,0x0B,0x1D,0x4D,0x2B,0xA1,0x69,0x03,0x2F,0x0B,
|
||||
0x58,0xE8,0x42,0xEC,0x14,0xA4,0x6F,0x06,0xD6,0x4F,0xE7,0x1D,0x2E,0x0A,0x57,0x15,
|
||||
0x84,0xEC,0xE2,0x4F,0x01,0xAA,0x08,0xC1,0x02,0xAE,0x6D,0xC9,0x0D,0x78,0x0C,0x79,
|
||||
0x2A,0xEC,0xFF,0x97,0x6B,0x9C,0x07,0xA3,0x14,0x80,0x02,0xAA,0x14,0xC1,0x76,0xF8,
|
||||
0x72,0xF0,0x52,0xE8,0xD0,0x1C,0x9A,0xE8,0x52,0x48,0x12,0xF2,0x02,0x03,0x08,0xB6,
|
||||
0x0D,0x32,0x76,0xF0,0x71,0xE8,0xCA,0x1C,0x59,0xE8,0x4B,0x48,0x1B,0xF2,0x13,0x03,
|
||||
0x0C,0x33,0x03,0xA3,0xE3,0x47,0x58,0x80,0x03,0xAA,0x13,0xC1,0x72,0xEE,0x52,0xF0,
|
||||
0x52,0xE8,0xD0,0x1C,0x9A,0xE8,0x52,0x48,0x12,0xF2,0x02,0x03,0x07,0xB6,0x0D,0x32,
|
||||
0x76,0xF0,0x71,0xE8,0xCA,0x1C,0x59,0xE8,0x4B,0x48,0x1B,0xF2,0x13,0x03,0x0C,0x33,
|
||||
0x04,0xA3,0xE7,0x87,0x07,0xAA,0x21,0xC1,0xEB,0xF0,0x09,0x0A,0x5B,0xE9,0x5B,0xF0,
|
||||
0xD3,0xE8,0x06,0xA1,0x5A,0x1E,0x0D,0x32,0x08,0xA2,0x9B,0x1E,0x0C,0x33,0x05,0xA3,
|
||||
0xE3,0x47,0x03,0xB0,0x24,0x80,0xC0,0x46,0x48,0x93,0x80,0x00,0x7C,0x93,0x80,0x00,
|
||||
0x64,0x93,0x80,0x00,0xFC,0x8E,0x80,0x00,0xD0,0x8E,0x80,0x00,0x4C,0x8F,0x80,0x00,
|
||||
0xE0,0x93,0x80,0x00,0x2C,0x8F,0x80,0x00,0x90,0x8E,0x80,0x00,0x05,0xAA,0x18,0xC1,
|
||||
0x03,0xB0,0xC3,0x4F,0x01,0xAB,0x0F,0xC8,0xEB,0xF0,0x40,0x09,0x5B,0xE9,0x5B,0xF0,
|
||||
0xCB,0xE8,0x06,0xA6,0x99,0x1F,0x0D,0x31,0x08,0xA7,0xDB,0x1F,0xE2,0x47,0x0C,0x33,
|
||||
0xC3,0x4F,0x01,0xB3,0xC3,0x47,0x08,0x80,0x68,0x06,0x14,0xA1,0x08,0x1C,0xE0,0x47,
|
||||
0x03,0x80,0x69,0x06,0x14,0xA2,0x51,0x1C,0xE1,0x47,0x0C,0x3A,0x00,0xAA,0x12,0xC0,
|
||||
0x04,0x3B,0x59,0xF0,0x32,0x08,0xC9,0xE8,0x49,0xF0,0x43,0xE8,0x9A,0x40,0x12,0xFA,
|
||||
0xDA,0x40,0x0D,0x3A,0x42,0x14,0x12,0xFA,0x5A,0x40,0x1D,0x41,0x04,0x3B,0x01,0xB3,
|
||||
0x1B,0xF6,0x1B,0xFE,0x04,0x33,0x6C,0x06,0x10,0xA6,0x2A,0x0B,0x34,0x1D,0x2A,0x0A,
|
||||
0xDC,0x43,0x27,0x0B,0x19,0x49,0x93,0xEC,0xDB,0x4F,0x00,0xAB,0x17,0xC1,0x50,0xEC,
|
||||
0xC3,0x47,0x10,0xED,0xC3,0x47,0x50,0xED,0xC3,0x47,0xD0,0xED,0xC3,0x47,0x90,0xED,
|
||||
0xC3,0x47,0x02,0xB0,0xC3,0x47,0x20,0xB0,0x03,0x40,0x2A,0xB2,0x01,0xB0,0x03,0x40,
|
||||
0x13,0x40,0x1E,0x0B,0x01,0xA0,0x5A,0x1C,0x88,0x00,0x82,0x03,0x5A,0x14,0x18,0x0B,
|
||||
0x5D,0x48,0x1C,0x48,0x2D,0xF2,0x15,0x0A,0xC8,0xF0,0x2C,0x03,0x09,0xC0,0x40,0xE8,
|
||||
0x40,0xF0,0x12,0xE8,0xD4,0x20,0x98,0x48,0xDB,0x48,0x1B,0xF2,0x03,0x03,0x13,0x21,
|
||||
0x07,0x80,0x43,0xE8,0x5B,0xF0,0xD3,0xE8,0x11,0x0A,0x90,0x28,0xD8,0x20,0xD2,0x28,
|
||||
0x1A,0x21,0xCB,0xF0,0x59,0xE8,0x09,0x0B,0x49,0xF0,0x59,0xE8,0x08,0xEC,0x08,0xB0,
|
||||
0x42,0x28,0x8A,0x21,0x0A,0x0A,0x14,0x29,0x0B,0xEC,0x44,0x20,0x0C,0xB3,0x58,0x28,
|
||||
0x08,0x22,0x52,0x29,0x0E,0x60,0x5A,0x20,0xF0,0x6D,0xC0,0x46,0x64,0x93,0x80,0x00,
|
||||
0xE0,0x93,0x80,0x00,0x2C,0x8F,0x80,0x00,0x4C,0x8F,0x80,0x00,0x78,0x93,0x80,0x00,
|
||||
0x48,0x93,0x80,0x00,0x04,0x0B,0x42,0xF0,0x10,0xE8,0x19,0x58,0xC0,0xF0,0x1A,0x58,
|
||||
0x52,0xEA,0x82,0x02,0xFB,0xC3,0x70,0x07,0x34,0x06,0x80,0x00,0x30,0x65,0x03,0x3D,
|
||||
0x80,0xEA,0xC9,0xEA,0x02,0xEC,0x0B,0xEC,0x50,0x03,0x59,0x03,0x2A,0xEC,0x55,0x03,
|
||||
0x09,0xE8,0x04,0x3C,0x01,0xA0,0xA9,0x02,0x05,0xCC,0x23,0xEC,0x5C,0x03,0x00,0xA0,
|
||||
0xA1,0x02,0x00,0xCD,0x02,0xA0,0x30,0x6D,0x13,0xF4,0x02,0x28,0x12,0xF4,0x09,0xF4,
|
||||
0x1B,0xE4,0x12,0xE4,0x09,0xE4,0x9A,0x02,0x02,0xCB,0xCB,0xEA,0x9A,0x02,0x00,0xCB,
|
||||
0x03,0x20,0x70,0x07,0x00,0xA3,0x01,0x80,0xC1,0x14,0x01,0xB3,0x93,0x02,0xFB,0xC3,
|
||||
0x70,0x07,0x30,0x65,0x52,0xE0,0x00,0xA3,0x00,0xA4,0x03,0x80,0xCD,0x1A,0x01,0xB4,
|
||||
0xC5,0x12,0x02,0xB3,0x94,0x02,0xF9,0xCB,0x30,0x6D,0x10,0x65,0x00,0xA3,0x02,0x80,
|
||||
0xCC,0x1C,0xC4,0x14,0x01,0xB3,0x93,0x02,0xFA,0xC3,0x10,0x6D,0x10,0x65,0x09,0xF4,
|
||||
0x02,0xEC,0x49,0xFC,0x00,0xA3,0x00,0xA0,0x07,0x80,0x14,0x28,0x01,0xB3,0x00,0xE9,
|
||||
0x00,0xF4,0x1B,0xF4,0x00,0xFC,0x1B,0xFC,0x02,0xB2,0x8B,0x02,0xF5,0xC3,0x10,0x6D,
|
||||
0x10,0x65,0x09,0xF4,0x02,0xEC,0x09,0xFC,0x00,0xA0,0x00,0xA3,0x07,0x80,0x14,0x48,
|
||||
0x01,0xB3,0x00,0xE9,0x00,0xF6,0x1B,0xF4,0x00,0xFE,0x1B,0xFC,0x01,0xB2,0x8B,0x02,
|
||||
0xF5,0xC3,0x10,0x6D,0x70,0x07,0x00,0x00,0x00,0x65,0x07,0x0A,0x07,0x0B,0x08,0x08,
|
||||
0x1A,0x50,0x08,0x0B,0x18,0x50,0x08,0x0B,0x01,0xA2,0x1A,0x40,0xFF,0xA1,0x0A,0xA2,
|
||||
0xFF,0x97,0xB0,0x9F,0x00,0x6D,0xC0,0x46,0x80,0x9F,0x80,0x00,0x28,0x8F,0x80,0x00,
|
||||
0x00,0x9F,0x80,0x00,0x24,0x8F,0x80,0x00,0xF8,0x9F,0x80,0x00,0xF0,0x65,0x52,0x0B,
|
||||
0x52,0x0D,0x00,0xA2,0x85,0x60,0x1A,0x44,0x6A,0x41,0x2C,0x80,0x56,0xF0,0xB6,0xE8,
|
||||
0x4F,0x09,0x76,0xF0,0x88,0xE9,0x04,0x49,0xA9,0xE9,0x0C,0x41,0x61,0xF0,0x09,0xE9,
|
||||
0x49,0xF0,0x8C,0x06,0x29,0xEC,0x61,0x04,0x01,0xA7,0x4F,0x41,0x1F,0x4C,0x00,0x37,
|
||||
0x01,0xA7,0xA7,0x00,0x3C,0xEC,0x00,0x3F,0x3C,0x03,0x24,0xF6,0x24,0xFE,0x1C,0x44,
|
||||
0x43,0x0C,0xA6,0x1D,0x44,0x48,0x24,0xF2,0x34,0x03,0x66,0x06,0xAC,0x15,0x24,0xFA,
|
||||
0x4C,0x40,0x84,0x48,0xC0,0x48,0x00,0xF2,0x20,0x03,0x88,0x40,0x01,0xB2,0x00,0xFA,
|
||||
0x12,0xF6,0xC8,0x40,0x12,0xFE,0xD9,0x4B,0x8A,0x02,0xCF,0xC3,0xD9,0x4C,0x1A,0x4C,
|
||||
0x0A,0x00,0xDA,0x44,0xDA,0x4B,0x00,0xAA,0x01,0xC0,0x02,0xA2,0xDA,0x40,0x32,0x0D,
|
||||
0xEB,0x48,0x00,0xAB,0x5B,0xC0,0x01,0x7C,0x20,0xEC,0xFF,0xA1,0x08,0xA2,0xFD,0x97,
|
||||
0x86,0x98,0x2B,0x4C,0x6A,0x4C,0xEE,0x4B,0x5A,0x00,0x26,0x40,0x2B,0x0B,0x94,0x06,
|
||||
0x1A,0x49,0x57,0xF0,0xBF,0xE8,0x7F,0xF0,0xF9,0x1C,0xDF,0xE9,0x78,0x48,0xBB,0x48,
|
||||
0xFF,0x48,0x00,0xF2,0x3F,0xF2,0x08,0x03,0x3B,0x03,0xED,0x4B,0x00,0xF4,0x1B,0xF4,
|
||||
0x67,0x06,0x01,0xE4,0x1B,0xE4,0x17,0x01,0x00,0xAD,0x0F,0xC1,0x01,0xA5,0x3D,0x02,
|
||||
0x2C,0xC0,0x10,0xA7,0xBC,0x06,0x67,0x06,0x3E,0x03,0x92,0xF0,0x16,0x03,0x26,0x40,
|
||||
0x61,0x40,0xA3,0x40,0x00,0xE6,0xFF,0xA9,0x1A,0xCC,0x0D,0x80,0x01,0xA5,0x3D,0x00,
|
||||
0x6F,0x02,0x6F,0x01,0x92,0xF0,0x00,0x37,0x16,0x03,0x7F,0xF1,0x3E,0x03,0x26,0x40,
|
||||
0x61,0x40,0xA3,0x40,0xFF,0xA9,0x09,0xCC,0xFF,0xAB,0x0F,0xCD,0x01,0xA2,0x1B,0xE2,
|
||||
0x13,0x03,0x22,0x48,0xDB,0xF1,0x13,0x03,0x23,0x40,0x07,0x80,0x00,0xE6,0x01,0xA5,
|
||||
0x22,0x48,0x05,0x03,0xAD,0xF1,0x15,0x03,0x25,0x40,0xED,0x87,0x09,0x0B,0x1B,0x48,
|
||||
0x01,0xAB,0x04,0xC0,0x08,0x08,0x01,0x79,0x02,0xA2,0xFD,0x97,0x38,0x98,0x02,0x0B,
|
||||
0x1A,0x4C,0x05,0x60,0x5A,0x44,0xF0,0x6D,0x2C,0x8F,0x80,0x00,0xE8,0x93,0x80,0x00,
|
||||
0xE0,0x93,0x80,0x00,0x03,0x00,0x80,0x00,0x80,0x9F,0x80,0x00,0x00,0x65,0xFE,0x97,
|
||||
0x59,0x9A,0x0F,0x0B,0x1B,0x58,0x9B,0x49,0x35,0xAB,0x01,0xC1,0xFD,0x97,0x08,0x9C,
|
||||
0x0C,0x0B,0x1A,0x48,0xA5,0xAA,0x12,0xC1,0x5A,0x48,0x03,0xAA,0x03,0xC1,0x0A,0x0A,
|
||||
0x02,0xA1,0x51,0x46,0x08,0x80,0x5A,0xAA,0x09,0xC1,0x07,0x0A,0x01,0xA1,0xD1,0x46,
|
||||
0x06,0x0A,0x11,0x58,0x06,0x0A,0x11,0x50,0x00,0xA2,0x1A,0x40,0x5A,0x40,0x00,0x6D,
|
||||
0x24,0x8F,0x80,0x00,0x00,0x9F,0x80,0x00,0x2C,0x8F,0x80,0x00,0x34,0x06,0x80,0x00,
|
||||
0x68,0x90,0x80,0x00,0xF0,0x65,0x39,0x0B,0x5B,0x4A,0x00,0xAB,0x03,0xC1,0x38,0x0B,
|
||||
0x1B,0x48,0x00,0xAB,0x68,0xC0,0x37,0x0A,0x37,0x0B,0x12,0x28,0x7F,0xA0,0x10,0x00,
|
||||
0x1B,0x28,0x36,0x0A,0x93,0x02,0x16,0xC9,0x30,0x0A,0x51,0x4A,0x00,0xA9,0x08,0xC1,
|
||||
0x3D,0xA8,0x06,0xC1,0x32,0x0C,0x01,0xA1,0x51,0x42,0xA3,0x02,0x01,0xC1,0x51,0x41,
|
||||
0x0F,0x80,0x30,0x0A,0x93,0x02,0x0C,0xC1,0x28,0x09,0x00,0xA2,0x4A,0x42,0x4A,0x41,
|
||||
0x29,0x09,0x0A,0x20,0x05,0x80,0x80,0xA2,0x12,0xF4,0x9D,0xE8,0x2A,0x0A,0x93,0x02,
|
||||
0x04,0xC9,0x03,0xA2,0x13,0x00,0x29,0x0A,0x9B,0xF0,0x9D,0x18,0x28,0x0B,0x28,0xB3,
|
||||
0x1B,0x48,0x98,0x02,0x02,0xC9,0x27,0x0A,0x95,0x02,0x00,0xC1,0x03,0xEC,0x23,0x0A,
|
||||
0x00,0xA1,0x14,0x59,0x00,0xA2,0x07,0x80,0x2E,0x28,0x89,0xE9,0x09,0xF4,0x26,0x20,
|
||||
0x09,0xFC,0x01,0xB2,0x02,0xB5,0x02,0xB4,0x9A,0x02,0xF5,0xC3,0x1B,0x0A,0x14,0x59,
|
||||
0x5A,0xF0,0xA4,0xE8,0x25,0xEC,0x1A,0xEC,0x1B,0x0E,0x0B,0x80,0x1D,0xAA,0x02,0xC8,
|
||||
0x7F,0xF0,0xBF,0x1B,0x2F,0x20,0x27,0x28,0x79,0xE8,0x09,0xF4,0x09,0xFC,0x01,0xB2,
|
||||
0x02,0xB4,0x02,0xB5,0xD7,0xEA,0x82,0x02,0xF0,0xC3,0x10,0x0B,0x1B,0x59,0x52,0xF0,
|
||||
0x9A,0xE8,0x11,0x20,0x05,0x0B,0x5B,0x4A,0x01,0xAB,0x02,0xC1,0x0F,0x0B,0x08,0xA2,
|
||||
0x1A,0x40,0x03,0x0B,0x00,0xA2,0x1A,0x20,0xF0,0x6D,0xC0,0x46,0x2C,0x8F,0x80,0x00,
|
||||
0x24,0x9F,0x80,0x00,0x20,0x9F,0x80,0x00,0x22,0x9F,0x80,0x00,0xFF,0xFE,0x00,0x00,
|
||||
0xF1,0xFF,0x00,0x00,0xFF,0xFF,0x00,0x00,0xFF,0xEF,0x00,0x00,0x64,0x8D,0x80,0x00,
|
||||
0x6C,0x90,0x80,0x00,0xD8,0x9E,0x80,0x00,0xB8,0x93,0x80,0x00,0x83,0x00,0x80,0x00,
|
||||
0xF0,0x65,0x19,0x0C,0x81,0x60,0x22,0xEC,0x18,0x09,0x00,0xA3,0x18,0x08,0x16,0x80,
|
||||
0x5D,0xF0,0xED,0xE8,0x17,0x0E,0x6D,0xF0,0xAE,0x1D,0x16,0x0F,0x00,0x36,0xED,0xE9,
|
||||
0x6E,0x48,0x00,0x3F,0x36,0xF2,0x37,0x03,0x97,0x20,0xAF,0x48,0xED,0x48,0x2D,0xF2,
|
||||
0x3D,0x03,0xD5,0x20,0x0D,0x48,0x01,0xB3,0x55,0x42,0x06,0xB1,0x06,0xB2,0xC5,0x4B,
|
||||
0xAB,0x02,0xE5,0xCB,0xC3,0x4B,0x23,0x40,0x63,0x48,0x01,0xB3,0x63,0x40,0x90,0xA7,
|
||||
0x03,0x4C,0xBF,0xF1,0xDB,0xE9,0x63,0x20,0x20,0xEC,0x1C,0xA1,0xFF,0x97,0x26,0x9E,
|
||||
0x01,0x60,0x40,0x02,0xA0,0x23,0xF0,0x6D,0xD8,0x9E,0x80,0x00,0xE4,0x93,0x80,0x00,
|
||||
0x2C,0x8F,0x80,0x00,0xE0,0x93,0x80,0x00,0xF0,0x65,0x2C,0x0B,0x2C,0x08,0x5B,0x59,
|
||||
0x00,0xA2,0x1A,0x20,0x82,0x60,0x9A,0x20,0x2A,0x09,0x04,0xEC,0x2C,0x80,0x0D,0x48,
|
||||
0x01,0x35,0x55,0xF0,0xAD,0xE8,0x28,0x0E,0x6D,0xF0,0xAE,0x1D,0x26,0x0F,0x00,0x36,
|
||||
0xED,0xE9,0x6E,0x48,0x00,0x3F,0x36,0xF2,0x37,0x03,0x00,0x37,0xAE,0x48,0xED,0x48,
|
||||
0x6F,0x06,0x3F,0x28,0x2D,0xF2,0x35,0x03,0x1F,0x20,0x5D,0x20,0x01,0x3D,0x01,0xAD,
|
||||
0x05,0xC1,0x1D,0x28,0x1D,0x0E,0x35,0x03,0x2D,0xF4,0x2D,0xFC,0x1D,0x20,0x25,0x4C,
|
||||
0x67,0x4C,0x7D,0x00,0x03,0xAD,0x04,0xC1,0xE5,0x4B,0x01,0xAD,0x01,0xC1,0x00,0xA5,
|
||||
0x1D,0x20,0x01,0xB2,0x04,0xB3,0x06,0xB1,0xC5,0x4B,0xAA,0x02,0xCF,0xCB,0x14,0x0B,
|
||||
0x1A,0x48,0x01,0xB2,0x12,0xF6,0x12,0xFE,0x1A,0x40,0x43,0x49,0x00,0xAB,0x0A,0xC0,
|
||||
0x10,0x0B,0x9B,0x49,0xC0,0xAB,0x06,0xC1,0x08,0x0B,0x59,0x59,0x80,0xA3,0x08,0x28,
|
||||
0xDB,0xF1,0x03,0x03,0x0B,0x20,0x05,0x0B,0x05,0x09,0x5B,0x59,0xC9,0x4B,0x19,0x21,
|
||||
0x19,0x29,0x12,0xF2,0x0A,0x03,0x02,0x60,0x1A,0x21,0xF0,0x6D,0x64,0x8D,0x80,0x00,
|
||||
0x2C,0x8F,0x80,0x00,0xE4,0x93,0x80,0x00,0xE0,0x93,0x80,0x00,0x00,0x80,0xFF,0xFF,
|
||||
0x94,0x8E,0x80,0x00,0x88,0x93,0x80,0x00,0x00,0x00,0x00,0x10,0xA0,0x16,0xB6,0x1B,
|
||||
0x00,0x20,0xC6,0x23,0x31,0x27,0x54,0x2A,0x41,0x2D,0x00,0x30,0x98,0x32,0x10,0x35,
|
||||
0x6C,0x37,0xB0,0x39,0xDD,0x3B,0xF7,0x3D,0x00,0x40,0xF8,0x41,0xE1,0x43,0xBE,0x45,
|
||||
0x8D,0x47,0x52,0x49,0x0B,0x4B,0xBB,0x4C,0x62,0x4E,0x00,0x50,0x95,0x51,0x23,0x53,
|
||||
0xA9,0x54,0x29,0x56,0xA2,0x57,0x15,0x59,0x82,0x5A,0x00,0x00,0x50,0x02,0xA0,0x04,
|
||||
0xF0,0x06,0x40,0x09,0x90,0x0B,0xE0,0x0D,0x50,0x02,0xA0,0x04,0xF0,0x06,0x40,0x09,
|
||||
0x90,0x0B,0xE0,0x0D,0x00,0x9F,0x80,0x00,0xFC,0x90,0x80,0x00,0xBC,0x91,0x80,0x00,
|
||||
0xD8,0x9E,0x80,0x00,0x9C,0x90,0x80,0x00,0x26,0x9F,0x80,0x00,0x96,0x9F,0x80,0x00,
|
||||
0x02,0x9E,0xD8,0x2D,
|
||||
};
|
||||
|
||||
#endif
|
||||
186
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_main.c
Normal file
186
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_main.c
Normal file
@ -0,0 +1,186 @@
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "chsc6x_comp.h"
|
||||
#include "chsc6x_platform.h"
|
||||
|
||||
struct ts_event {
|
||||
unsigned short x; /*x coordinate */
|
||||
unsigned short y; /*y coordinate */
|
||||
int flag; /* touch event flag: 0 -- down; 1-- up; 2 -- contact */
|
||||
int id; /*touch ID */
|
||||
};
|
||||
|
||||
bool chsc6x_read_touch_info(uint16_t *x, uint16_t *y)
|
||||
{
|
||||
int ret;
|
||||
int rd_len = 0;
|
||||
unsigned char point_num;
|
||||
unsigned char read_buf[6];
|
||||
struct ts_event events[CHSC6X_MAX_POINTS_NUM];
|
||||
|
||||
if(1 == CHSC6X_MAX_POINTS_NUM) {
|
||||
rd_len = 3;
|
||||
} else if(2 == CHSC6X_MAX_POINTS_NUM) {
|
||||
if ((CHSC6X_RES_MAX_X < 255) && (CHSC6X_RES_MAX_Y < 255) ) {
|
||||
rd_len = 5;
|
||||
} else {
|
||||
rd_len = 6;
|
||||
}
|
||||
} else {
|
||||
chsc6x_err("CHSC641X_MAX_POINTS_NUM more than two");
|
||||
return false;
|
||||
}
|
||||
|
||||
ret = chsc6x_i2c_read(CHSC6X_I2C_ID, read_buf, rd_len);
|
||||
if(rd_len == ret) {
|
||||
point_num = read_buf[0] & 0x03;
|
||||
|
||||
if(1 == CHSC6X_MAX_POINTS_NUM) {
|
||||
events[0].x = (unsigned short)(((read_buf[0] & 0x40) >> 6) << 8) | (unsigned short)read_buf[1];
|
||||
events[0].y = (unsigned short)(((read_buf[0] & 0x80) >> 7) << 8) | (unsigned short)read_buf[2];
|
||||
|
||||
events[0].flag= (read_buf[0] >> 4) & 0x03;
|
||||
events[0].id = (read_buf[0] >>2) & 0x01;
|
||||
chsc6x_info("chsc6x: 000 X:%d, Y:%d, point_num:%d,flag:%d, id:%d \r\n", \
|
||||
events[0].x, events[0].y, point_num, events[0].flag, events[0].id);
|
||||
|
||||
} else if(2 == CHSC6X_MAX_POINTS_NUM) {
|
||||
if ((CHSC6X_RES_MAX_X > 255) || (CHSC6X_RES_MAX_Y > 255) ) {
|
||||
events[0].x = (unsigned short)((read_buf[5] & 0x01) << 8) | (unsigned short)read_buf[1];
|
||||
events[0].y = (unsigned short)((read_buf[5] & 0x02) << 7) | (unsigned short)read_buf[2];
|
||||
|
||||
events[0].flag = (read_buf[0] >> 4) & 0x03;
|
||||
events[0].id = (read_buf[0] >>2) & 0x01;
|
||||
chsc6x_info("chsc6x: 111 X:%d, Y:%d, point_num:%d,flag:%d, id:%d \r\n", \
|
||||
events[0].x, events[0].y, point_num, events[0].flag, events[0].id);
|
||||
|
||||
events[1].x = (unsigned short)((read_buf[5] & 0x04) << 6) | (unsigned short)read_buf[3];
|
||||
events[1].y = (unsigned short)((read_buf[5] & 0x08) << 5) | (unsigned short)read_buf[4];
|
||||
|
||||
events[1].flag = (read_buf[0] >> 6) & 0x03;
|
||||
events[1].id = (read_buf[0] >>3) & 0x01;
|
||||
chsc6x_info("chsc6x: 222 X:%d, Y:%d, point_num:%d,flag:%d, id:%d \r\n", \
|
||||
events[1].x, events[1].y, point_num, events[1].flag, events[1].id);
|
||||
} else {
|
||||
events[0].x = read_buf[1];
|
||||
events[0].y = read_buf[2];
|
||||
|
||||
events[0].flag = (read_buf[0] >> 4) & 0x03;
|
||||
events[0].id = (read_buf[0] >>2) & 0x01;
|
||||
chsc6x_info("chsc6x: 333 X:%d, Y:%d, point_num:%d,flag:%d, id:%d \r\n", \
|
||||
events[0].x, events[0].y, point_num, events[0].flag, events[0].id);
|
||||
|
||||
events[1].x = read_buf[3];
|
||||
events[1].y = read_buf[4];
|
||||
|
||||
events[1].flag = (read_buf[0] >> 6) & 0x03;
|
||||
events[1].id = (read_buf[0] >>3) & 0x01;
|
||||
chsc6x_info("chsc6x: 444 X:%d, Y:%d, point_num:%d,flag:%d, id:%d \r\n", \
|
||||
events[1].x, events[1].y, point_num, events[1].flag, events[1].id);
|
||||
}
|
||||
}
|
||||
static uint16_t last_x = 0xffff, last_y = 0xffff;
|
||||
static uint8_t same_counter = 0;
|
||||
*x = events[0].x;
|
||||
*y = events[0].y;
|
||||
if ((last_x == events[0].x) && (last_y == events[0].y)) {
|
||||
if (same_counter < 10) {
|
||||
same_counter++;
|
||||
}
|
||||
}
|
||||
else {
|
||||
last_x = events[0].x;
|
||||
last_y = events[0].y;
|
||||
same_counter = 0;
|
||||
}
|
||||
if ((point_num != 0)
|
||||
&& ((events[0].flag == 0) || (events[0].flag == 2))
|
||||
&& (same_counter < 10)) {
|
||||
return true;
|
||||
}
|
||||
else {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
else{
|
||||
chsc6x_err("chsc6x: chsc6x_read_touch_info iic err! rd_len=%d, ret=%d \r\n", rd_len, ret);
|
||||
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
void chsc6x_resume(void)
|
||||
{
|
||||
chsc6x_info("touch_resume");
|
||||
chsc6x_tp_reset();
|
||||
}
|
||||
|
||||
void chsc6x_suspend(void)
|
||||
{
|
||||
unsigned char buft[1] = {0};
|
||||
int ret = -1;
|
||||
chsc6x_tp_reset();
|
||||
ret = chsc6x_write_bytes_u16addr_sub(CHSC6X_I2C_ID, 0xa503, buft, 0);
|
||||
if(ret == 0) {
|
||||
chsc6x_info("touch_suspend OK \r\n");
|
||||
}else{
|
||||
chsc6x_info("touch_suspend failed \r\n");
|
||||
}
|
||||
}
|
||||
|
||||
void chsc6x_dbcheck(void)
|
||||
{
|
||||
unsigned char buft[1] = {0};
|
||||
int ret = -1;
|
||||
chsc6x_tp_reset();
|
||||
ret = chsc6x_write_bytes_u16addr_sub(CHSC6X_I2C_ID, 0xd001, buft, 0); //0xd001 close
|
||||
if(ret == 0) {
|
||||
chsc6x_info("Enable dbcheck OK \r\n");
|
||||
}else{
|
||||
chsc6x_info("Enable dbcheck failed \r\n");
|
||||
}
|
||||
}
|
||||
|
||||
void chsc6x_palmcheck(void)
|
||||
{
|
||||
unsigned char buft[1] = {0};
|
||||
int ret = -1;
|
||||
chsc6x_tp_reset();
|
||||
ret = chsc6x_write_bytes_u16addr_sub(CHSC6X_I2C_ID, 0xd101, buft, 0); //0xd100 close
|
||||
if(ret == 0) {
|
||||
chsc6x_info("Enable palmcheck OK \r\n");
|
||||
}else{
|
||||
chsc6x_info("Enable palmcheck failed \r\n");
|
||||
}
|
||||
}
|
||||
|
||||
void chsc6x_init(void)
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
unsigned char fw_update_ret_flag = 0; //1:update OK, !0 fail
|
||||
struct ts_fw_infos fw_infos;
|
||||
|
||||
chsc6x_tp_reset_active();
|
||||
|
||||
for(i = 0; i < 3; i++) {
|
||||
ret = chsc6x_tp_dect(&fw_infos, &fw_update_ret_flag);
|
||||
if(1 == ret) {
|
||||
#if CHSC6X_AUTO_UPGRADE /* If need update FW */
|
||||
chsc6x_info("chsc6x_tp_dect succeed!\r\n");
|
||||
if(1 == fw_update_ret_flag) {
|
||||
chsc6x_err("update fw succeed! \r\n");
|
||||
break;
|
||||
} else {
|
||||
chsc6x_err("update fw failed! \r\n");
|
||||
}
|
||||
#else
|
||||
break;
|
||||
#endif
|
||||
}else {
|
||||
chsc6x_err("chsc6x_tp_dect failed! i = %d \r\n", i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
339
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_platform.c
Normal file
339
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_platform.c
Normal file
@ -0,0 +1,339 @@
|
||||
#include "chsc6x_platform.h"
|
||||
#include "fr30xx.h"
|
||||
|
||||
void touchpad_reset_set(void);
|
||||
void touchpad_reset_clear(void);
|
||||
void touchpad_delay_ms(uint32_t counter);
|
||||
|
||||
extern I2C_HandleTypeDef i2c_touchpad_handle;
|
||||
|
||||
/************************************************************************************
|
||||
* @fn i2c_memory_read
|
||||
*
|
||||
* @brief i2c memory read.
|
||||
*/
|
||||
bool i2c_memory_chsc6x_read_only(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size)
|
||||
{
|
||||
uint32_t lu32_RxCount = fu32_Size;
|
||||
|
||||
if (fu32_Size == 0)
|
||||
goto _exit_i2c_read;
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->TAR.TAR = fu16_DevAddress >> 1;
|
||||
|
||||
__I2C_ENABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->DATA_CMD = (0 >> 8) & 0xFF;
|
||||
hi2c->I2Cx->DATA_CMD = 0 & 0xFF;
|
||||
|
||||
while (!__I2C_IS_TxFIFO_EMPTY(hi2c->I2Cx));
|
||||
|
||||
/* DevAddress NACK */
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
goto _exit_i2c_read;
|
||||
}
|
||||
|
||||
if (fu32_Size > 1)
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_RESTART | CMD_READ;
|
||||
|
||||
while (fu32_Size - 2)
|
||||
{
|
||||
if (!__I2C_IS_TxFIFO_FULL(hi2c->I2Cx))
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_READ;
|
||||
|
||||
fu32_Size--;
|
||||
}
|
||||
|
||||
while (!__I2C_IS_RxFIFO_EMPTY(hi2c->I2Cx))
|
||||
{
|
||||
*fp_Data++ = hi2c->I2Cx->DATA_CMD & 0xFF;
|
||||
|
||||
lu32_RxCount--;
|
||||
}
|
||||
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
goto _exit_i2c_read;
|
||||
}
|
||||
}
|
||||
|
||||
/* Last byte with stop */
|
||||
while (__I2C_IS_TxFIFO_FULL(hi2c->I2Cx));
|
||||
hi2c->I2Cx->DATA_CMD = CMD_READ | CMD_STOP;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_RESTART | CMD_READ | CMD_STOP;
|
||||
}
|
||||
|
||||
uint8_t to_counter = 100;
|
||||
while (lu32_RxCount)
|
||||
{
|
||||
if (!__I2C_IS_RxFIFO_EMPTY(hi2c->I2Cx))
|
||||
{
|
||||
*fp_Data++ = hi2c->I2Cx->DATA_CMD & 0xFF;
|
||||
|
||||
lu32_RxCount--;
|
||||
}
|
||||
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
goto _exit_i2c_read;
|
||||
}
|
||||
|
||||
system_delay_us(10);
|
||||
to_counter--;
|
||||
if (to_counter == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
while(__I2C_IS_BUSY(hi2c->I2Cx));
|
||||
|
||||
if (lu32_RxCount == 0) {
|
||||
return true;
|
||||
}
|
||||
else {
|
||||
return false;
|
||||
}
|
||||
|
||||
_exit_i2c_read:
|
||||
|
||||
__NOP();
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* @fn i2c_memory_read
|
||||
*
|
||||
* @brief i2c memory read.
|
||||
*/
|
||||
bool i2c_memory_chsc6x_read(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint16_t fu16_MemAddress, uint8_t *fp_Data, uint32_t fu32_Size)
|
||||
{
|
||||
uint32_t lu32_RxCount = fu32_Size;
|
||||
|
||||
if (fu32_Size == 0)
|
||||
goto _exit_i2c_read;
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->TAR.TAR = fu16_DevAddress >> 1;
|
||||
|
||||
__I2C_ENABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->DATA_CMD = (fu16_MemAddress >> 8) & 0xFF;
|
||||
hi2c->I2Cx->DATA_CMD = fu16_MemAddress & 0xFF;
|
||||
|
||||
while (!__I2C_IS_TxFIFO_EMPTY(hi2c->I2Cx));
|
||||
|
||||
/* DevAddress NACK */
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
goto _exit_i2c_read;
|
||||
}
|
||||
|
||||
if (fu32_Size > 1)
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_RESTART | CMD_READ;
|
||||
|
||||
while (fu32_Size - 2)
|
||||
{
|
||||
if (!__I2C_IS_TxFIFO_FULL(hi2c->I2Cx))
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_READ;
|
||||
|
||||
fu32_Size--;
|
||||
}
|
||||
|
||||
while (!__I2C_IS_RxFIFO_EMPTY(hi2c->I2Cx))
|
||||
{
|
||||
*fp_Data++ = hi2c->I2Cx->DATA_CMD & 0xFF;
|
||||
|
||||
lu32_RxCount--;
|
||||
}
|
||||
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
goto _exit_i2c_read;
|
||||
}
|
||||
}
|
||||
|
||||
/* Last byte with stop */
|
||||
while (__I2C_IS_TxFIFO_FULL(hi2c->I2Cx));
|
||||
hi2c->I2Cx->DATA_CMD = CMD_READ | CMD_STOP;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_RESTART | CMD_READ | CMD_STOP;
|
||||
}
|
||||
|
||||
while (lu32_RxCount)
|
||||
{
|
||||
if (!__I2C_IS_RxFIFO_EMPTY(hi2c->I2Cx))
|
||||
{
|
||||
*fp_Data++ = hi2c->I2Cx->DATA_CMD & 0xFF;
|
||||
|
||||
lu32_RxCount--;
|
||||
}
|
||||
}
|
||||
|
||||
while(__I2C_IS_BUSY(hi2c->I2Cx));
|
||||
|
||||
return true;
|
||||
|
||||
_exit_i2c_read:
|
||||
|
||||
__NOP();
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* @fn i2c_memory_write
|
||||
*
|
||||
* @brief i2c memory write.
|
||||
*/
|
||||
bool i2c_memory_chsc6x_write(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint16_t fu16_MemAddress, uint8_t *fp_Data, uint32_t fu32_Size)
|
||||
{
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->TAR.TAR = fu16_DevAddress >> 1;
|
||||
|
||||
__I2C_ENABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->DATA_CMD = (fu16_MemAddress >> 8) & 0xFF;
|
||||
hi2c->I2Cx->DATA_CMD = fu16_MemAddress & 0xFF;
|
||||
|
||||
while (!__I2C_IS_TxFIFO_EMPTY(hi2c->I2Cx));
|
||||
|
||||
/* DevAddress NACK */
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
goto _exit_i2c_write;
|
||||
}
|
||||
|
||||
while (fu32_Size - 1 > 0)
|
||||
{
|
||||
if (!__I2C_IS_TxFIFO_FULL(hi2c->I2Cx))
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = *fp_Data++;
|
||||
|
||||
fu32_Size--;
|
||||
}
|
||||
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
goto _exit_i2c_write;
|
||||
}
|
||||
}
|
||||
|
||||
/* Last byte with stop */
|
||||
while (__I2C_IS_TxFIFO_FULL(hi2c->I2Cx));
|
||||
hi2c->I2Cx->DATA_CMD = *fp_Data | CMD_STOP;
|
||||
|
||||
while(__I2C_IS_BUSY(hi2c->I2Cx));
|
||||
|
||||
//while(i2c_memory_is_busy(hi2c, fu16_DevAddress));
|
||||
|
||||
return true;
|
||||
|
||||
_exit_i2c_write:
|
||||
|
||||
__NOP();
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* return: =read lenth succeed; <0 failed
|
||||
read reg addr not need
|
||||
just used for reading xy cord info*/
|
||||
int chsc6x_i2c_read(unsigned char id, unsigned char *p_data, unsigned short lenth)
|
||||
{
|
||||
bool ret = i2c_memory_chsc6x_read_only(&i2c_touchpad_handle, id, p_data, lenth);
|
||||
// bool ret = i2c_memory_chsc6x_read(&i2c_touchpad_handle, id, 0, p_data, lenth);
|
||||
if (ret) {
|
||||
return lenth;
|
||||
}else{
|
||||
return -1;
|
||||
}
|
||||
|
||||
// return i2cRead(id, lenth, p_data);
|
||||
}
|
||||
|
||||
/* RETURN:0->pass else->fail */
|
||||
int chsc6x_read_bytes_u16addr_sub(unsigned char id, unsigned short adr, unsigned char *rxbuf, unsigned short lenth)
|
||||
{
|
||||
bool ret = i2c_memory_chsc6x_read(&i2c_touchpad_handle, id, adr, rxbuf, lenth);
|
||||
if (ret) {
|
||||
return 0;
|
||||
}else{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* RETURN:0->pass else->fail */
|
||||
int chsc6x_write_bytes_u16addr_sub(unsigned char id, unsigned short adr, unsigned char *txbuf, unsigned short lenth)
|
||||
{
|
||||
bool ret = i2c_memory_chsc6x_write(&i2c_touchpad_handle, id, adr, txbuf, lenth);
|
||||
if(ret) {
|
||||
return 0;
|
||||
}else{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
void chsc6x_msleep(int ms)
|
||||
{
|
||||
touchpad_delay_ms(ms);
|
||||
}
|
||||
|
||||
void chsc6x_tp_reset(void)
|
||||
{
|
||||
touchpad_reset_clear();
|
||||
touchpad_delay_ms(30);//30ms
|
||||
touchpad_reset_set();
|
||||
touchpad_delay_ms(30);//30ms
|
||||
}
|
||||
|
||||
void chsc6x_tp_reset_active(void)
|
||||
{
|
||||
touchpad_reset_clear();
|
||||
touchpad_delay_ms(30);//30ms
|
||||
touchpad_reset_set();
|
||||
touchpad_delay_ms(30);//30ms
|
||||
}
|
||||
|
||||
51
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_platform.h
Normal file
51
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_platform.h
Normal file
@ -0,0 +1,51 @@
|
||||
#ifndef __CHSC6X_PLATFORM_H__
|
||||
#define __CHSC6X_PLATFORM_H__
|
||||
#include <stdio.h>
|
||||
|
||||
#if 0
|
||||
#define chsc6x_info(x...) pr_notice("[chsc6x] " x)
|
||||
#define chsc6x_err(x...) pr_err("[chsc6x][error] " x)
|
||||
#else
|
||||
#if 0
|
||||
#define chsc6x_info printf
|
||||
#define chsc6x_err printf
|
||||
#else
|
||||
#define chsc6x_info(x...)
|
||||
#define chsc6x_err(x...)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CHSC6X_I2C_ID (0x5c) //8bit
|
||||
|
||||
#define CHSC6X_MAX_POINTS_NUM (1)
|
||||
#define CHSC6X_RES_MAX_X (370)
|
||||
#define CHSC6X_RES_MAX_Y (370)
|
||||
|
||||
/*MACRO SWITCH for driver update TP FW */
|
||||
#define CHSC6X_AUTO_UPGRADE (0)
|
||||
|
||||
/*MACRO SWITCH for multi TP_VENDOR Compatible update TP FW */
|
||||
#define CHSC6X_MUL_VENDOR_UPGRADE (0)
|
||||
|
||||
#define MAX_IIC_WR_LEN (8)
|
||||
#define MAX_IIC_RD_LEN (16)
|
||||
|
||||
|
||||
/* fail : <0 */
|
||||
int chsc6x_i2c_read(unsigned char id, unsigned char *p_data, unsigned short lenth);
|
||||
|
||||
/* RETURN:0->pass else->fail */
|
||||
int chsc6x_read_bytes_u16addr_sub(unsigned char id, unsigned short adr, unsigned char *rxbuf, unsigned short lenth);
|
||||
|
||||
/* RETURN:0->pass else->fail */
|
||||
int chsc6x_write_bytes_u16addr_sub(unsigned char id, unsigned short adr, unsigned char *txbuf, unsigned short lenth);
|
||||
|
||||
void chsc6x_msleep(int ms);
|
||||
|
||||
void chsc6x_tp_reset(void);
|
||||
|
||||
void chsc6x_tp_reset_active(void);
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
119
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_ramcode.h
Normal file
119
fr3092_mcu/components/drivers/bsp/touchpad/chsc6x_ramcode.h
Normal file
@ -0,0 +1,119 @@
|
||||
#ifndef __CHSC6X_RAMCODE_H__
|
||||
#define __CHSC6X_RAMCODE_H__
|
||||
|
||||
const unsigned char fw_fcode_burn[1784] = {
|
||||
0x08,0x80,0x6F,0x6D,0x00,0x00,0xF8,0x06,0x4B,0x4E,0x4C,0x54,0x80,0x01,0x88,0x00,
|
||||
0x34,0x80,0xC0,0x46,0x00,0xA0,0x17,0x09,0x17,0x0A,0x08,0x50,0x04,0xB1,0x91,0x02,
|
||||
0xFB,0xCB,0x0C,0x08,0xC0,0x6B,0x0D,0x08,0x85,0x06,0x0B,0x08,0xC0,0x6B,0x0C,0x08,
|
||||
0x85,0x06,0x0C,0x09,0x40,0xA0,0x08,0x40,0x40,0xA0,0x48,0x40,0x0A,0x09,0x0B,0x0A,
|
||||
0x0B,0x0B,0x08,0x58,0x10,0x50,0x04,0xB1,0x04,0xB2,0x9A,0x02,0xF9,0xCB,0x00,0x90,
|
||||
0xF5,0x9A,0xC0,0x46,0x12,0x00,0x00,0x00,0x13,0x00,0x00,0x00,0xF0,0x9D,0x80,0x00,
|
||||
0xF0,0x9C,0x80,0x00,0x0C,0x06,0x80,0x00,0xF8,0x06,0x00,0x00,0x04,0x8D,0x80,0x00,
|
||||
0x04,0x8D,0x80,0x00,0x04,0x8D,0x80,0x00,0x00,0xA0,0x80,0x00,0x30,0x00,0x00,0x00,
|
||||
0x4D,0x03,0x00,0x00,0x31,0x00,0x00,0x00,0x15,0x03,0x00,0x00,0x33,0x00,0x00,0x00,
|
||||
0xD9,0x04,0x00,0x00,0x32,0x00,0x00,0x00,0xD1,0x02,0x00,0x00,0x30,0x65,0x07,0x0C,
|
||||
0x01,0xA3,0x23,0x40,0x05,0xF6,0x1C,0xA0,0x00,0x90,0x9E,0x98,0x00,0xA3,0x23,0x40,
|
||||
0x03,0x0B,0x2D,0xFE,0x1D,0x40,0x00,0x90,0xC7,0x98,0x30,0x6D,0x0D,0x00,0x80,0x00,
|
||||
0x0C,0x00,0x80,0x00,0xF0,0x65,0xFA,0xA0,0xC0,0xF0,0x00,0x90,0x8D,0x98,0x05,0xA0,
|
||||
0xFF,0x97,0xE4,0x9F,0x0A,0x0C,0x0B,0x0D,0x00,0xA6,0x01,0xA7,0x05,0x80,0xC8,0xA0,
|
||||
0x01,0xBC,0x00,0x90,0x81,0x98,0x00,0xAC,0x05,0xC0,0x2E,0x40,0x00,0x90,0xAC,0x98,
|
||||
0x2B,0x48,0x1F,0x02,0xF3,0xC1,0x04,0x0B,0x01,0xA2,0x1A,0x40,0xF0,0x6D,0xC0,0x46,
|
||||
0x80,0x96,0x98,0x00,0x0C,0x00,0x80,0x00,0x0D,0x00,0x80,0x00,0x30,0x65,0x07,0x0C,
|
||||
0x03,0xFC,0x05,0xEC,0x23,0x40,0x00,0x90,0x97,0x98,0x2B,0xFA,0x23,0x40,0x00,0x90,
|
||||
0x93,0x98,0x25,0x40,0x00,0x90,0x90,0x98,0x30,0x6D,0xC0,0x46,0x0C,0x00,0x80,0x00,
|
||||
0x10,0x65,0x04,0xEC,0x06,0xA0,0xFF,0x97,0xB1,0x9F,0x20,0xA0,0xFF,0x97,0xAE,0x9F,
|
||||
0x20,0xEC,0xFF,0x97,0xE3,0x9F,0x03,0x0B,0x01,0xA2,0x1A,0x40,0xFF,0x97,0xBA,0x9F,
|
||||
0x10,0x6D,0xC0,0x46,0x0D,0x00,0x80,0x00,0xF0,0x65,0x04,0xEC,0x03,0xA0,0x0D,0xEC,
|
||||
0x16,0xEC,0x0E,0x0F,0xFF,0x97,0x9A,0x9F,0x20,0xEC,0xFF,0x97,0xCF,0x9F,0x00,0xA3,
|
||||
0x3B,0x40,0x00,0x90,0x69,0x98,0x0A,0x0B,0x0A,0xA2,0x1A,0x40,0x00,0x90,0x64,0x98,
|
||||
0x00,0xAD,0x07,0xC0,0x00,0xA4,0x3B,0x48,0x33,0x15,0x01,0xB4,0x00,0x90,0x5C,0x98,
|
||||
0xAC,0x02,0xF8,0xC1,0x02,0x0B,0x01,0xA2,0x1A,0x40,0xF0,0x6D,0x0C,0x00,0x80,0x00,
|
||||
0x0D,0x00,0x80,0x00,0xF0,0x65,0x04,0xEC,0x06,0xA0,0x0D,0xEC,0x16,0xEC,0xFF,0x97,
|
||||
0x75,0x9F,0x02,0xA0,0xFF,0x97,0x72,0x9F,0x20,0xEC,0xFF,0x97,0xA7,0x9F,0x00,0xAD,
|
||||
0x08,0xC0,0x07,0x0F,0x00,0xA4,0x33,0x1D,0x01,0xB4,0x3B,0x40,0x00,0x90,0x3C,0x98,
|
||||
0xA5,0x02,0xF8,0xC8,0x03,0x0B,0x01,0xA2,0x1A,0x40,0xFF,0x97,0x73,0x9F,0xF0,0x6D,
|
||||
0x0C,0x00,0x80,0x00,0x0D,0x00,0x80,0x00,0x06,0x09,0x0B,0x58,0x81,0x60,0x00,0x33,
|
||||
0x43,0xF0,0x18,0xE8,0xC0,0xF0,0x0A,0x58,0x00,0x3B,0xD3,0xEA,0x83,0x02,0xFA,0xC9,
|
||||
0x01,0x60,0x70,0x07,0x30,0x06,0x80,0x00,0x10,0x65,0x94,0xE0,0x00,0xAC,0x05,0xCD,
|
||||
0x00,0xA3,0x04,0xD9,0x01,0xB3,0x04,0xD0,0xA3,0x02,0xFA,0xC1,0x10,0x6D,0xC0,0x46,
|
||||
0x10,0x65,0x09,0xF4,0x49,0xFC,0x03,0xEC,0x00,0xA0,0x00,0xA9,0x0B,0xC0,0x4C,0xEE,
|
||||
0x24,0xF4,0xE4,0xFB,0x02,0xB4,0x00,0xA2,0x99,0x1A,0x40,0xE8,0x00,0xF4,0x02,0xB2,
|
||||
0x00,0xFC,0xA2,0x02,0xF8,0xC1,0x10,0x6D,0x30,0x65,0x06,0x0D,0x2B,0x48,0xDA,0xF6,
|
||||
0x06,0xC5,0x10,0xA4,0x1C,0xA0,0xFF,0x97,0xC7,0x9F,0x2B,0x48,0x1C,0x02,0xF9,0xC1,
|
||||
0x30,0x6D,0xC0,0x46,0x0D,0x00,0x80,0x00,0x01,0x0B,0x01,0xA2,0x1A,0x40,0x70,0x07,
|
||||
0x0D,0x00,0x80,0x00,0x01,0x0B,0x00,0xA2,0x1A,0x40,0x70,0x07,0x0D,0x00,0x80,0x00,
|
||||
0x01,0x0B,0x18,0x40,0x70,0x07,0xC0,0x46,0x0C,0x00,0x80,0x00,0x01,0x0B,0x18,0x40,
|
||||
0x70,0x07,0xC0,0x46,0x0D,0x00,0x80,0x00,0x01,0x0B,0x18,0x48,0x70,0x07,0xC0,0x46,
|
||||
0x0C,0x00,0x80,0x00,0x10,0x65,0x03,0x0C,0x00,0xA3,0x23,0x40,0xFF,0x97,0xCC,0x9F,
|
||||
0x20,0x48,0x10,0x6D,0x0C,0x00,0x80,0x00,0x10,0x65,0x04,0x0C,0x00,0xA3,0x23,0x40,
|
||||
0xFF,0x97,0xC2,0x9F,0x23,0x48,0x01,0xA0,0x18,0x00,0x10,0x6D,0x0C,0x00,0x80,0x00,
|
||||
0x30,0x65,0x80,0xA3,0xC2,0x28,0x5B,0xF1,0x9A,0x02,0x04,0xC0,0x0C,0x0B,0x1B,0x58,
|
||||
0x05,0xA2,0x5A,0x40,0x30,0x6D,0x84,0x28,0x45,0x28,0x00,0xAC,0x0B,0xC0,0x2D,0xF3,
|
||||
0x28,0xEC,0x01,0xBC,0xFF,0x97,0x1C,0x9F,0x24,0xF4,0x80,0xA3,0x5B,0xF1,0x24,0xFC,
|
||||
0xED,0xE8,0x00,0xAC,0xF4,0xC1,0x02,0x0B,0x1B,0x58,0x00,0xA2,0x5A,0x40,0xE9,0x87,
|
||||
0x04,0x8D,0x80,0x00,0x30,0x65,0xC2,0x28,0x84,0x28,0x43,0x28,0x09,0x0D,0x12,0xF4,
|
||||
0x10,0xEC,0x18,0x03,0x2A,0xEC,0x21,0xEC,0xFF,0x97,0x16,0x9F,0x28,0xEC,0x21,0xEC,
|
||||
0x00,0x90,0xC4,0x99,0x04,0x0B,0x1B,0x58,0x00,0xA2,0x58,0x20,0x00,0xFC,0x98,0x20,
|
||||
0x5A,0x40,0x30,0x6D,0x00,0x90,0x80,0x00,0x04,0x8D,0x80,0x00,0xF0,0x65,0x5F,0x06,
|
||||
0x56,0x06,0x4D,0x06,0x44,0x06,0xF0,0x64,0x83,0x28,0x42,0x28,0x04,0xEC,0x19,0xEC,
|
||||
0x38,0x08,0x92,0x06,0x99,0x06,0x00,0x90,0xA9,0x99,0xA3,0x29,0xE2,0x28,0x1B,0xF4,
|
||||
0x9B,0xE8,0x83,0x02,0x09,0xC0,0x34,0x0B,0x1B,0x58,0x03,0xA2,0x5A,0x40,0x3C,0x6C,
|
||||
0x90,0x06,0x99,0x06,0xA2,0x06,0xAB,0x06,0xF0,0x6D,0x54,0x06,0x23,0xF5,0x00,0xAB,
|
||||
0x4E,0xC0,0x00,0xA2,0x91,0x05,0x4F,0xC0,0x80,0xA3,0x5C,0xF0,0x4D,0x06,0x00,0xA7,
|
||||
0xA3,0x06,0x2C,0xEC,0x5D,0x05,0x01,0xC9,0x80,0xA4,0x64,0xF0,0x25,0x0B,0xB8,0x06,
|
||||
0xFE,0xE8,0xD0,0x04,0x40,0x06,0x21,0xEC,0x32,0xEC,0xFF,0x97,0xF3,0x9E,0x2D,0xEB,
|
||||
0x40,0x06,0x21,0xEC,0x32,0xEC,0xFF,0x97,0xED,0x9E,0x3F,0xE9,0x00,0xAD,0xE8,0xC1,
|
||||
0x80,0xA7,0x4D,0x06,0x00,0xA6,0x7F,0xF0,0x2C,0xEC,0xBD,0x02,0x01,0xC9,0x80,0xA4,
|
||||
0x64,0xF0,0x1A,0x0B,0x30,0xEC,0xF2,0xE8,0x50,0x04,0x21,0xEC,0x2D,0xEB,0xFF,0x97,
|
||||
0xB3,0x9E,0x36,0xE9,0x00,0xAD,0xEF,0xC1,0x13,0x0B,0x18,0x58,0x11,0x0B,0x45,0x40,
|
||||
0x1A,0x48,0x12,0x0B,0x1B,0x48,0x9A,0x02,0x0F,0xC1,0x00,0xA3,0x07,0x80,0x0D,0x0C,
|
||||
0x19,0xE9,0x0E,0x0C,0x1A,0xE9,0x09,0x48,0x12,0x48,0x91,0x02,0x05,0xC1,0x01,0xB3,
|
||||
0x99,0x05,0xF4,0xC8,0x00,0xA3,0x43,0x20,0xA9,0x87,0x09,0xA3,0x43,0x40,0xA6,0x87,
|
||||
0x50,0x06,0xFF,0x97,0x7D,0x9E,0xAC,0x87,0x03,0x0B,0x18,0x58,0x4A,0x06,0x42,0x40,
|
||||
0xF0,0x87,0xC0,0x46,0x00,0x90,0x80,0x00,0x04,0x8D,0x80,0x00,0x80,0x94,0x80,0x00,
|
||||
0xF0,0x65,0x57,0x06,0x46,0x06,0xC0,0x64,0x80,0xA3,0x07,0xF4,0x00,0xA4,0xDB,0xF0,
|
||||
0x3F,0xFC,0x00,0xA5,0xA0,0x06,0x9A,0x06,0x3E,0xEC,0x57,0x05,0x01,0xC9,0x80,0xA6,
|
||||
0xF6,0xF0,0x36,0xF4,0x36,0xFC,0x40,0x06,0x31,0xEC,0x15,0x0A,0xFF,0x97,0x6C,0x9E,
|
||||
0x00,0xAE,0x19,0xC0,0x70,0xEE,0x13,0x0B,0x00,0xF4,0x00,0xFC,0xC0,0xE8,0x42,0x06,
|
||||
0x01,0xBB,0x19,0x48,0x64,0xE8,0x51,0x03,0x01,0xB2,0x6D,0xE8,0x24,0xF4,0x2D,0xF4,
|
||||
0x12,0xF4,0x01,0xB3,0x24,0xFC,0x2D,0xFC,0x12,0xFC,0x83,0x02,0xF1,0xC1,0x33,0xEC,
|
||||
0x43,0x04,0x1B,0xF4,0x1B,0xFC,0x98,0x06,0xBF,0xEB,0x3F,0xF4,0x3F,0xFC,0x00,0xAF,
|
||||
0xD2,0xC1,0x28,0xF4,0x20,0x03,0x0C,0x6C,0x90,0x06,0x9A,0x06,0xF0,0x6D,0xC0,0x46,
|
||||
0x00,0x90,0x80,0x00,0x01,0x90,0x80,0x00,0xF0,0x65,0x19,0x0C,0x00,0xA0,0x08,0xA1,
|
||||
0x22,0xEC,0xFF,0x97,0x39,0x9E,0x23,0x58,0x01,0xB3,0x1F,0xC0,0x15,0x0B,0x1C,0x28,
|
||||
0x80,0xA3,0x1B,0xF2,0xA3,0x02,0x00,0xC2,0xF0,0x6D,0x13,0x0B,0x1E,0x28,0x13,0x0B,
|
||||
0xF6,0xE8,0x73,0xEE,0x9E,0x01,0x00,0xAE,0xF6,0xC1,0x20,0xEC,0xFF,0x97,0xA0,0x9F,
|
||||
0x0B,0x0D,0x07,0xEC,0x08,0xA1,0x20,0xEC,0x2A,0xEC,0xFF,0x97,0x1D,0x9E,0x2B,0x58,
|
||||
0xBB,0x02,0xE9,0xC1,0x0A,0x0B,0x1B,0x58,0x5E,0x40,0xE5,0x87,0x09,0x0B,0x1B,0x58,
|
||||
0x01,0xB3,0xDB,0xC1,0x06,0x0B,0x1B,0x58,0x08,0xA2,0x5A,0x40,0xDC,0x87,0xC0,0x46,
|
||||
0x00,0x90,0x80,0x00,0x06,0x90,0x80,0x00,0x02,0x90,0x80,0x00,0xCA,0xCA,0xFF,0xFF,
|
||||
0x04,0x8D,0x80,0x00,0x04,0x90,0x80,0x00,0x70,0x65,0x22,0x0D,0x2B,0x58,0x0F,0xA2,
|
||||
0x1A,0x40,0x09,0xA2,0x5A,0x40,0x0C,0xA1,0x04,0xEC,0xFF,0x97,0x59,0x9E,0x23,0x48,
|
||||
0x00,0xA8,0x13,0xC1,0x62,0x48,0xD2,0xE8,0xFF,0xAA,0x0F,0xC1,0x1A,0x0A,0x11,0x48,
|
||||
0x99,0x02,0x2B,0xC0,0x11,0x4A,0x99,0x02,0x2A,0xC0,0x11,0x4C,0x99,0x02,0x11,0xC0,
|
||||
0x11,0x4E,0x03,0xA0,0x99,0x02,0x0E,0xC0,0x28,0x58,0x03,0x80,0x28,0x58,0x03,0xA3,
|
||||
0x43,0x40,0x23,0x48,0x03,0x40,0x06,0xA1,0xFF,0x97,0x3A,0x9E,0x2B,0x58,0x40,0x02,
|
||||
0xD8,0x20,0x70,0x6D,0x02,0xA0,0x0D,0x09,0x00,0xA3,0x0B,0x40,0x80,0xB1,0x0B,0x40,
|
||||
0x0B,0x0E,0xC3,0xF0,0x05,0xA1,0xD2,0xE8,0x53,0x58,0x20,0xEC,0x31,0x40,0x00,0x90,
|
||||
0x73,0x98,0x01,0xA3,0x33,0x40,0x28,0x58,0x23,0x48,0xE3,0x87,0x00,0xA0,0xEA,0x87,
|
||||
0x01,0xA0,0xE8,0x87,0x04,0x8D,0x80,0x00,0x7C,0x00,0x00,0x00,0x00,0x9E,0x80,0x00,
|
||||
0x03,0x00,0x80,0x00,0x30,0x65,0x0D,0x0C,0x63,0x4A,0x35,0xAB,0x00,0xC0,0x30,0x6D,
|
||||
0xFA,0xA0,0x80,0xF0,0xFF,0x97,0xF0,0x9D,0x09,0x0D,0x21,0xEC,0x10,0xA2,0x28,0xEC,
|
||||
0xFF,0x97,0xFA,0x9D,0x28,0xEC,0xFF,0x97,0x9F,0x9F,0x06,0x08,0x06,0x09,0x10,0xA2,
|
||||
0xFF,0x97,0xF2,0x9D,0x30,0xA3,0x63,0x42,0xE9,0x87,0xC0,0x46,0x00,0x9F,0x80,0x00,
|
||||
0x80,0x9F,0x80,0x00,0x40,0x9F,0x80,0x00,0xC0,0x9F,0x80,0x00,0x00,0x65,0x13,0x0B,
|
||||
0x13,0x0A,0x19,0x58,0x0A,0x00,0x1A,0x50,0x12,0x0B,0x55,0xA2,0x1A,0x40,0x12,0x0A,
|
||||
0x12,0x0B,0x1A,0x20,0x12,0x0A,0x13,0x0B,0x1A,0x50,0x13,0x0A,0xFF,0xA3,0x1B,0xF6,
|
||||
0x13,0x50,0x01,0xA3,0x5B,0x02,0x04,0xB2,0x13,0x20,0x10,0x0B,0x00,0xA2,0x10,0x09,
|
||||
0x1A,0x40,0x01,0xA3,0x0B,0x40,0x10,0xB1,0x0A,0x50,0x0E,0x0A,0x13,0x40,0x80,0xA3,
|
||||
0x1B,0xF4,0x1F,0xA2,0x1A,0x40,0xFF,0x97,0xB5,0x9F,0xFC,0x87,0x40,0x06,0x80,0x00,
|
||||
0xFF,0xFF,0xFF,0xFE,0x10,0x04,0x80,0x00,0x00,0x9E,0xFF,0xFF,0x28,0x00,0x80,0x00,
|
||||
0xC0,0x9F,0x80,0x00,0x04,0x8D,0x80,0x00,0x60,0x00,0x80,0x00,0x68,0x00,0x80,0x00,
|
||||
0x20,0x06,0x80,0x00,0x03,0x00,0x80,0x00,0x18,0x07,0xC0,0x46,0x30,0x65,0x0D,0xF4,
|
||||
0x2D,0xFC,0x03,0xEC,0x00,0xA0,0x00,0xAD,0x14,0xC0,0x19,0x48,0x00,0xA4,0x01,0xB3,
|
||||
0x00,0xA2,0x01,0x80,0x19,0x48,0x01,0xB3,0x08,0xE8,0x51,0x03,0x01,0xB2,0x64,0xE8,
|
||||
0x12,0xF4,0x00,0xF4,0x24,0xF4,0x12,0xFC,0x00,0xFC,0x24,0xFC,0x95,0x02,0xF1,0xC8,
|
||||
0x24,0xF4,0x20,0x03,0x30,0x6D,0xC0,0x46
|
||||
};
|
||||
|
||||
#endif
|
||||
935
fr3092_mcu/components/drivers/bsp/touchpad/driver_chsc5816.c
Normal file
935
fr3092_mcu/components/drivers/bsp/touchpad/driver_chsc5816.c
Normal file
@ -0,0 +1,935 @@
|
||||
/*===============================================================================================*/
|
||||
/**
|
||||
* @file touch.c
|
||||
*
|
||||
* @version v1.0
|
||||
*/
|
||||
/*=================================================================================================
|
||||
Rootlink Confidential Proprietary
|
||||
Advanced Technology and Software Operations
|
||||
|
||||
(c) Copyright Rootlink 2015 - , All Rights Reserved
|
||||
|
||||
Revision History:
|
||||
|
||||
Modification Tracking
|
||||
Author Date Number Description of Changes
|
||||
-------- -------- ------- ------------------------
|
||||
|
||||
Portability:
|
||||
Indicate if this module is portable to other compilers or
|
||||
platforms. If not, indicate specific reasons why is it not portable.
|
||||
|
||||
===================================================================================================
|
||||
INCLUDE FILES
|
||||
=================================================================================================*/
|
||||
#include <stdint.h>
|
||||
|
||||
#include "fr30xx.h"
|
||||
#include "chsc5816_ctp.h"
|
||||
|
||||
#if 0
|
||||
#define PRINT_DBG printf
|
||||
#else
|
||||
#define PRINT_DBG(...)
|
||||
#endif
|
||||
|
||||
#define RETRY 1000
|
||||
#define _TOUCH_DOWN 0
|
||||
#define _TOUCH_UP 1
|
||||
#define _TOUCH_CONTACT 2
|
||||
#define CHSC5816_ADDRESS (0x2e<<1)
|
||||
|
||||
#define _XSIZE_PHYS 368
|
||||
#define _YSIZE_PHYS 448
|
||||
|
||||
#define __CHSC5816_RESET_SET() touchpad_reset_set()
|
||||
#define __CHSC5816_RESET_CLEAR() touchpad_reset_clear()
|
||||
#define HAL_Delay(counter) touchpad_delay_ms(counter)
|
||||
|
||||
extern I2C_HandleTypeDef i2c_touchpad_handle;
|
||||
|
||||
static struct sm_touch_dev st_dev;
|
||||
static uint8_t counter;
|
||||
|
||||
void touchpad_reset_set(void);
|
||||
void touchpad_reset_clear(void);
|
||||
void touchpad_delay_ms(uint32_t counter);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn i2c_memory_read
|
||||
*
|
||||
* @brief i2c memory read.
|
||||
*/
|
||||
bool i2c_memory_chsc5816_read(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint32_t fu32_MemAddress, uint8_t *fp_Data, uint32_t fu32_Size)
|
||||
{
|
||||
uint32_t lu32_RxCount = fu32_Size;
|
||||
|
||||
counter = 0;
|
||||
|
||||
if (fu32_Size == 0)
|
||||
goto _exit_i2c_read;
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->TAR.TAR = fu16_DevAddress >> 1;
|
||||
|
||||
__I2C_ENABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->DATA_CMD = (fu32_MemAddress >> 24) & 0xFF;
|
||||
hi2c->I2Cx->DATA_CMD = (fu32_MemAddress >> 16) & 0xFF;
|
||||
|
||||
while (!__I2C_IS_TxFIFO_EMPTY(hi2c->I2Cx));
|
||||
|
||||
/* DevAddress NACK */
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
counter = 1;
|
||||
|
||||
goto _exit_i2c_read;
|
||||
}
|
||||
|
||||
hi2c->I2Cx->DATA_CMD = (fu32_MemAddress >> 8) & 0xFF;
|
||||
hi2c->I2Cx->DATA_CMD = fu32_MemAddress & 0xFF;
|
||||
|
||||
|
||||
if (fu32_Size > 1)
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_RESTART | CMD_READ;
|
||||
|
||||
while (fu32_Size - 2)
|
||||
{
|
||||
if (!__I2C_IS_TxFIFO_FULL(hi2c->I2Cx))
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_READ;
|
||||
|
||||
fu32_Size--;
|
||||
}
|
||||
|
||||
while (!__I2C_IS_RxFIFO_EMPTY(hi2c->I2Cx))
|
||||
{
|
||||
*fp_Data++ = hi2c->I2Cx->DATA_CMD & 0xFF;
|
||||
|
||||
lu32_RxCount--;
|
||||
}
|
||||
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
counter = 2;
|
||||
|
||||
goto _exit_i2c_read;
|
||||
}
|
||||
}
|
||||
|
||||
/* Last byte with stop */
|
||||
while (__I2C_IS_TxFIFO_FULL(hi2c->I2Cx));
|
||||
hi2c->I2Cx->DATA_CMD = CMD_READ | CMD_STOP;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = CMD_RESTART | CMD_READ | CMD_STOP;
|
||||
}
|
||||
|
||||
while (lu32_RxCount)
|
||||
{
|
||||
if (!__I2C_IS_RxFIFO_EMPTY(hi2c->I2Cx))
|
||||
{
|
||||
*fp_Data++ = hi2c->I2Cx->DATA_CMD & 0xFF;
|
||||
|
||||
lu32_RxCount--;
|
||||
}
|
||||
}
|
||||
|
||||
while(__I2C_IS_BUSY(hi2c->I2Cx));
|
||||
|
||||
return true;
|
||||
|
||||
_exit_i2c_read:
|
||||
PRINT_DBG("I2c r:%d\n",counter);
|
||||
|
||||
__NOP();
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* @fn i2c_memory_write
|
||||
*
|
||||
* @brief i2c memory write.
|
||||
*/
|
||||
bool i2c_memory_chsc5816_write(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size)
|
||||
{
|
||||
counter = 0;
|
||||
|
||||
if (fu32_Size < 2)
|
||||
goto _exit_i2c_write;
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->TAR.TAR = fu16_DevAddress >> 1;
|
||||
|
||||
__I2C_ENABLE(hi2c->I2Cx);
|
||||
|
||||
hi2c->I2Cx->DATA_CMD = *fp_Data++;
|
||||
hi2c->I2Cx->DATA_CMD = *fp_Data++;
|
||||
|
||||
while (!__I2C_IS_TxFIFO_EMPTY(hi2c->I2Cx));
|
||||
|
||||
/* DevAddress NACK */
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
counter = 1;
|
||||
goto _exit_i2c_write;
|
||||
}
|
||||
|
||||
fu32_Size -= 2;
|
||||
|
||||
while (fu32_Size - 1 > 0)
|
||||
{
|
||||
if (!__I2C_IS_TxFIFO_FULL(hi2c->I2Cx))
|
||||
{
|
||||
hi2c->I2Cx->DATA_CMD = *fp_Data++;
|
||||
|
||||
fu32_Size--;
|
||||
}
|
||||
|
||||
if (i2c_get_int_status(hi2c, INT_TX_ABRT))
|
||||
{
|
||||
i2c_clear_int_status(hi2c, INT_TX_ABRT);
|
||||
|
||||
__I2C_DISABLE(hi2c->I2Cx);
|
||||
|
||||
counter = 2;
|
||||
goto _exit_i2c_write;
|
||||
}
|
||||
}
|
||||
|
||||
/* Last byte with stop */
|
||||
while (__I2C_IS_TxFIFO_FULL(hi2c->I2Cx));
|
||||
hi2c->I2Cx->DATA_CMD = *fp_Data | CMD_STOP;
|
||||
|
||||
while(__I2C_IS_BUSY(hi2c->I2Cx));
|
||||
|
||||
//while(i2c_memory_is_busy(hi2c, fu16_DevAddress));
|
||||
|
||||
return true;
|
||||
|
||||
_exit_i2c_write:
|
||||
PRINT_DBG("I2c w:%d\n",counter);
|
||||
|
||||
__NOP();
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
void semi_touch_power_int(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static void semi_touch_msdelay(uint32_t millisecs)
|
||||
{
|
||||
HAL_Delay(millisecs);
|
||||
}
|
||||
|
||||
static void semi_touch_reset(void)
|
||||
{
|
||||
__CHSC5816_RESET_SET();
|
||||
HAL_Delay(10);
|
||||
__CHSC5816_RESET_CLEAR();
|
||||
HAL_Delay(5);
|
||||
__CHSC5816_RESET_SET();
|
||||
HAL_Delay(200);
|
||||
}
|
||||
|
||||
int32_t semi_touch_iic_write(uint32_t reg, uint8_t* pdata, uint16_t len)
|
||||
{
|
||||
|
||||
if(i2c_memory_chsc5816_write(&i2c_touchpad_handle, (uint16_t)CHSC5816_ADDRESS, pdata, len) == 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return SEMI_DRV_ERR_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
reg : must 4B aligned
|
||||
len : must multiple of 4
|
||||
*/
|
||||
int32_t semi_i2c_read_bytes(uint32_t reg, uint8_t* pdata, uint16_t len)
|
||||
{
|
||||
if(i2c_memory_chsc5816_read(&i2c_touchpad_handle, (uint16_t)CHSC5816_ADDRESS, reg, pdata, len) == 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return SEMI_DRV_ERR_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
reg - register address, must 4B aligned
|
||||
buffer - data buffer
|
||||
len - data length, must 4B aligned
|
||||
|
||||
return:
|
||||
0 - pass
|
||||
others - fail
|
||||
*/
|
||||
int32_t semi_touch_read_bytes(uint32_t reg, uint8_t* buffer, uint16_t len)
|
||||
{
|
||||
int32_t ret = SEMI_DRV_ERR_OK;
|
||||
uint16_t once;
|
||||
uint32_t retry;
|
||||
|
||||
while(len > 0){
|
||||
once = (len>MAX_IO_BUFFER_LEN)?MAX_IO_BUFFER_LEN:len;
|
||||
|
||||
ret = -1;
|
||||
for(retry=0; retry<3; retry++){
|
||||
if(semi_i2c_read_bytes(reg, buffer,once) == SEMI_DRV_ERR_OK){
|
||||
ret = SEMI_DRV_ERR_OK;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(ret != SEMI_DRV_ERR_OK){
|
||||
break;
|
||||
}
|
||||
|
||||
reg += once;
|
||||
buffer += once;
|
||||
len -= once;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
reg - register address, must 4B aligned
|
||||
buffer - data buffer
|
||||
len - data length, must 4B aligned
|
||||
|
||||
return:
|
||||
0 - pass
|
||||
others - fail
|
||||
*/
|
||||
int32_t semi_touch_write_bytes(uint32_t reg, uint8_t* buffer, uint16_t len)
|
||||
{
|
||||
int32_t ret = SEMI_DRV_ERR_OK;
|
||||
uint16_t once;
|
||||
uint32_t k, retry;
|
||||
uint8_t writeBuff[MAX_IO_BUFFER_LEN];
|
||||
|
||||
while(len > 0){
|
||||
once = (len<(MAX_IO_BUFFER_LEN-4))?len:(MAX_IO_BUFFER_LEN-4);
|
||||
|
||||
writeBuff[0] = (uint8_t)(reg>>24);
|
||||
writeBuff[1] = (uint8_t)(reg>>16);
|
||||
writeBuff[2] = (uint8_t)(reg>>8);
|
||||
writeBuff[3] = (uint8_t)(reg);
|
||||
for(k=0; k<once; k++){
|
||||
writeBuff[k+4] = buffer[k];
|
||||
}
|
||||
|
||||
ret = -1;
|
||||
for(retry=0; retry<3; retry++){
|
||||
if(semi_touch_iic_write(reg, writeBuff, once+4) == SEMI_DRV_ERR_OK){
|
||||
ret = SEMI_DRV_ERR_OK;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(ret != SEMI_DRV_ERR_OK){
|
||||
break;
|
||||
}
|
||||
|
||||
reg += once;
|
||||
buffer += once;
|
||||
len -= once;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int32_t semi_touch_write_and_check(uint32_t addr, uint8_t* buffer, uint16_t len)
|
||||
{
|
||||
int32_t ret = 0, once = 0, index = 0, retry = 0;
|
||||
uint8_t cmp_buffer[MAX_IO_BUFFER_LEN-4];
|
||||
|
||||
while(len > 0){
|
||||
retry = 0;
|
||||
do{
|
||||
ret = SEMI_DRV_ERR_OK;
|
||||
once = (len<(MAX_IO_BUFFER_LEN-4))?len:(MAX_IO_BUFFER_LEN-4);
|
||||
ret = semi_touch_write_bytes(addr, buffer, once);
|
||||
ret = semi_touch_read_bytes(addr, cmp_buffer, once);
|
||||
for(index = 0; index < once; index++){
|
||||
if(cmp_buffer[index] != buffer[index]){
|
||||
ret = -SEMI_DRV_ERR_CHECKSUM;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(SEMI_DRV_ERR_OK == ret){
|
||||
break;
|
||||
}
|
||||
}while(++retry < 3);
|
||||
|
||||
if(SEMI_DRV_ERR_OK != ret){
|
||||
break;
|
||||
}
|
||||
|
||||
addr += once;
|
||||
buffer += once;
|
||||
len -= once;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int32_t semi_touch_run_ram_code(const uint8_t* bin_code, uint16_t len)
|
||||
{
|
||||
int32_t retry;
|
||||
int32_t ret = 0, reg_value = 0;
|
||||
|
||||
for(retry = 0; retry < 5; retry++){
|
||||
//reset mcu
|
||||
semi_touch_reset();
|
||||
|
||||
//hold mcu
|
||||
reg_value = 0x12044000;
|
||||
ret = semi_touch_write_bytes(0x40007000, (uint8_t*)®_value, 4);
|
||||
if(ret != 0){
|
||||
continue;
|
||||
}
|
||||
|
||||
//open auto feed
|
||||
reg_value = 0x0000925a;
|
||||
ret = semi_touch_write_bytes(0x40007010, (uint8_t*)®_value, 4);
|
||||
if(ret != 0){
|
||||
continue;
|
||||
}
|
||||
|
||||
//run ramcode
|
||||
ret = semi_touch_write_and_check(0x20000000, (uint8_t* )bin_code, len);
|
||||
if(ret != 0){
|
||||
continue;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
if(ret != 0){
|
||||
return -1;
|
||||
}
|
||||
|
||||
//remap
|
||||
reg_value = 0x12044002;
|
||||
ret = semi_touch_write_bytes(0x40007000, (uint8_t*)®_value, 4);
|
||||
if(ret != 0){
|
||||
return -1;
|
||||
}
|
||||
|
||||
//release mcu
|
||||
reg_value = 0x12044003;
|
||||
ret = semi_touch_write_bytes(0x40007000, (uint8_t*)®_value, 4);
|
||||
if(ret != 0){
|
||||
return -1;
|
||||
}
|
||||
|
||||
semi_touch_msdelay(30);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint16_t caculate_checksum_u16(uint16_t *buf, uint16_t length)
|
||||
{
|
||||
uint16_t sum, len, i;
|
||||
|
||||
sum = 0;
|
||||
|
||||
len = length >> 1;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
sum += buf[i];
|
||||
}
|
||||
|
||||
return sum;
|
||||
}
|
||||
|
||||
static uint32_t caculate_checksum_ex(uint8_t * buf, uint16_t length)
|
||||
{
|
||||
uint32_t combchk = 0;
|
||||
uint16_t k = 0, check = 0, checkex = 0;
|
||||
|
||||
for (k = 0; k < length; k++) {
|
||||
check += buf[k];
|
||||
checkex += (uint16_t)(k * buf[k]);
|
||||
}
|
||||
|
||||
combchk = (checkex<<16) | check;
|
||||
|
||||
return combchk;
|
||||
}
|
||||
|
||||
static int32_t cmd_send_to_tp(struct m_ctp_cmd_std_t *ptr_cmd, struct m_ctp_rsp_std_t *ptr_rsp,
|
||||
int32_t once_delay, int32_t poolgap)
|
||||
{
|
||||
int32_t ret = -SEMI_DRV_ERR_HAL_IO;
|
||||
uint32_t retry = 0;
|
||||
uint32_t cmd_rsp_ok = 0;
|
||||
|
||||
ptr_cmd->tag = 0xE9;
|
||||
ptr_cmd->chk = 1 + ~caculate_checksum_u16((uint16_t*)&ptr_cmd->d0, sizeof(struct m_ctp_cmd_std_t) - 2);
|
||||
ret = semi_touch_write_bytes(0x20000000, (uint8_t*)ptr_cmd, sizeof(struct m_ctp_cmd_std_t));
|
||||
if(ret != 0){ // TODO: need confirm!!!
|
||||
return -1;
|
||||
}
|
||||
|
||||
semi_touch_msdelay(once_delay);
|
||||
while(retry++ < 20){
|
||||
semi_touch_msdelay(poolgap);
|
||||
ret = semi_touch_read_bytes(0x20000000, (uint8_t*)ptr_rsp, sizeof(struct m_ctp_rsp_std_t));
|
||||
if(ret != 0){ // TODO: need confirm!!!
|
||||
return -1;
|
||||
}
|
||||
|
||||
if(ptr_cmd->id != ptr_rsp->id){
|
||||
continue;
|
||||
}
|
||||
|
||||
if(!caculate_checksum_u16((uint16_t*)ptr_rsp, sizeof(struct m_ctp_rsp_std_t))){
|
||||
if(0 == ptr_rsp->cc){ //success
|
||||
cmd_rsp_ok = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ret = -1;
|
||||
if(cmd_rsp_ok == 1){
|
||||
ret = SEMI_DRV_ERR_OK;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
return:
|
||||
0(SEMI_DRV_ERR_OK) ->success
|
||||
others ->fail
|
||||
*/
|
||||
static int32_t semi_touch_nvm_read(uint8_t *pdes, uint32_t adr, uint32_t len)
|
||||
{
|
||||
int32_t ret = -1;
|
||||
uint32_t left = len;
|
||||
uint32_t local_check, retry;
|
||||
struct m_ctp_cmd_std_t cmd_send_tp;
|
||||
struct m_ctp_rsp_std_t ack_from_tp;
|
||||
|
||||
cmd_send_tp.id = CMD_MEM_RD;
|
||||
|
||||
while (left) {
|
||||
len = (left > 1024) ? 1024 : left;
|
||||
|
||||
cmd_send_tp.d0 = adr & 0xffff;
|
||||
cmd_send_tp.d1 = len;
|
||||
cmd_send_tp.d2 = 0;
|
||||
cmd_send_tp.d3 = NVM_R;
|
||||
cmd_send_tp.d5 = (adr >> 16) & 0xffff;
|
||||
|
||||
retry = 0;
|
||||
while (retry++ < 3) {
|
||||
ack_from_tp.id = CMD_NA;
|
||||
ret = cmd_send_to_tp(&cmd_send_tp, &ack_from_tp, 20, 10);
|
||||
if(SEMI_DRV_ERR_OK != ret){
|
||||
continue;
|
||||
}
|
||||
|
||||
semi_touch_read_bytes(TP_RD_BUFF_ADDR, pdes, len);
|
||||
|
||||
local_check = caculate_checksum_ex(pdes, len);
|
||||
if ((ack_from_tp.d0 != (uint16_t)local_check) ||
|
||||
(ack_from_tp.d1 != (uint16_t)(local_check >> 16))){
|
||||
ret = -SEMI_DRV_ERR_CHECKSUM;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
adr += len;
|
||||
left -= len;
|
||||
pdes += len;
|
||||
if(ret != SEMI_DRV_ERR_OK){
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int32_t semi_touch_nvm_write(uint8_t *psrc, uint32_t adr, uint32_t len)
|
||||
{
|
||||
int32_t ret = -1;
|
||||
uint32_t left = len;
|
||||
uint32_t retry, combChk;
|
||||
struct m_ctp_cmd_std_t cmd_send_tp;
|
||||
struct m_ctp_rsp_std_t ack_from_tp;
|
||||
|
||||
cmd_send_tp.id = CMD_MEM_WR;
|
||||
|
||||
while (left) {
|
||||
len = (left > 1024) ? 1024 : left;
|
||||
combChk = caculate_checksum_ex(psrc, len);
|
||||
|
||||
cmd_send_tp.d0 = adr & 0xffff; /* addrss space[0,64K) */
|
||||
cmd_send_tp.d1 = len;
|
||||
cmd_send_tp.d3 = NVM_W;
|
||||
cmd_send_tp.d2 = (uint16_t) combChk;
|
||||
cmd_send_tp.d4 = (uint16_t) (combChk >> 16);
|
||||
cmd_send_tp.d5 = (adr >> 16) & 0xffff;
|
||||
|
||||
retry = 0;
|
||||
while (++retry <= 3) {
|
||||
ret = semi_touch_write_bytes(TP_WR_BUFF_ADDR, psrc, len);
|
||||
if(SEMI_DRV_ERR_OK != ret) continue;
|
||||
|
||||
ack_from_tp.id = CMD_NA;
|
||||
ret = cmd_send_to_tp(&cmd_send_tp, &ack_from_tp, 200, 20);
|
||||
if(SEMI_DRV_ERR_OK != ret) continue;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
left -= len;
|
||||
adr += len;
|
||||
psrc += len;
|
||||
if(ret != SEMI_DRV_ERR_OK){
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int32_t semi_touch_burn_erase(void)
|
||||
{
|
||||
struct m_ctp_cmd_std_t cmd_send_tp;
|
||||
struct m_ctp_rsp_std_t ack_from_tp;
|
||||
|
||||
cmd_send_tp.id = CMD_FLASH_ERASE;
|
||||
cmd_send_tp.d0 = 0x01;
|
||||
|
||||
return cmd_send_to_tp(&cmd_send_tp, &ack_from_tp, 1000, 40);
|
||||
}
|
||||
|
||||
/*
|
||||
This function push IC into NVM mode, call it carefully and must reset
|
||||
IC to enter normal mode.
|
||||
return:
|
||||
0(SEMI_DRV_ERR_OK) ->success
|
||||
others ->fail
|
||||
*/
|
||||
static int32_t semi_touch_enter_burn_mode(void)
|
||||
{
|
||||
struct m_ctp_cmd_std_t cmd_send_tp;
|
||||
struct m_ctp_rsp_std_t ack_from_tp;
|
||||
|
||||
ack_from_tp.d0 = 0;
|
||||
cmd_send_tp.id = CMD_IDENTITY;
|
||||
cmd_send_to_tp(&cmd_send_tp, &ack_from_tp, 20, 5);
|
||||
if((ack_from_tp.d0 == 0xE9A2) && (ack_from_tp.d1 == 0x165d)){
|
||||
return SEMI_DRV_ERR_OK;
|
||||
}
|
||||
|
||||
if(semi_touch_run_ram_code(fw_5816_burn, sizeof(fw_5816_burn)) != 0){
|
||||
return -1;
|
||||
}
|
||||
|
||||
cmd_send_tp.id = CMD_IDENTITY;
|
||||
if(cmd_send_to_tp(&cmd_send_tp, &ack_from_tp, 20, 5) != 0){
|
||||
return -1;
|
||||
}
|
||||
if((ack_from_tp.d0 == 0xE9A2) && (ack_from_tp.d1 == 0x165d)){
|
||||
return SEMI_DRV_ERR_OK;
|
||||
}
|
||||
|
||||
return -SEMI_DRV_ERR_HAL_IO;
|
||||
}
|
||||
|
||||
|
||||
static int32_t semi_get_backup_pid(uint32_t *id)
|
||||
{
|
||||
st_dev.ctp_status = CTP_UPGRAD_RUNING;
|
||||
|
||||
if(semi_touch_enter_burn_mode() != SEMI_DRV_ERR_OK){
|
||||
return -1;
|
||||
}
|
||||
|
||||
return semi_touch_nvm_read((uint8_t *)id, VID_PID_BACKUP_ADDR, 4);
|
||||
}
|
||||
|
||||
static int32_t semi_touch_update_check(void)
|
||||
{
|
||||
uint32_t pvid;
|
||||
uint8_t * pfw;
|
||||
uint32_t * plist;
|
||||
int32_t k, idx_active;
|
||||
uint16_t upd_boot_ver = 0;
|
||||
struct chsc_updfile_header *upd_header;
|
||||
|
||||
st_dev.needUpd = 0;
|
||||
st_dev.updPdata = 0;
|
||||
st_dev.newBootLen = 0;
|
||||
if(st_dev.setup_ok == 0){
|
||||
if(semi_get_backup_pid(&pvid) == 0){
|
||||
st_dev.vid_pid = pvid;
|
||||
}
|
||||
}
|
||||
|
||||
if((uint32_t)chsc_upd_data & 3){
|
||||
PRINT_DBG("chsc::illegal memory buffer, must 4B aliged\n");
|
||||
return -SEMI_DRV_INVALID_PARAM;
|
||||
}
|
||||
|
||||
upd_header = (struct chsc_updfile_header *)chsc_upd_data;
|
||||
|
||||
if((upd_header->sig != 0x43534843) || (upd_header->n_match == 0)) {
|
||||
PRINT_DBG("chsc::illegal upd_header\n");
|
||||
return -SEMI_DRV_ERR_NOT_MATCH;
|
||||
}
|
||||
|
||||
if((upd_header->len_boot <= 15*1024) || (upd_header->len_boot >= 40*1024)) {
|
||||
PRINT_DBG("chsc::illegal upd_header\n");
|
||||
return -SEMI_DRV_ERR_NOT_MATCH;
|
||||
}
|
||||
|
||||
plist = (uint32_t *)((uint8_t *)chsc_upd_data + sizeof(struct chsc_updfile_header));
|
||||
pfw = (uint8_t *)plist + (upd_header->n_match*4) + upd_header->len_cfg;
|
||||
|
||||
if((pfw[0x30] != 0x16) || (pfw[0x31] != 0x58)){
|
||||
PRINT_DBG("chsc:no chsc5816 fw found\n");
|
||||
return -SEMI_DRV_ERR_NOT_MATCH;
|
||||
}
|
||||
|
||||
st_dev.updPdata = pfw;
|
||||
st_dev.newBootLen = upd_header->len_boot;
|
||||
|
||||
idx_active = -1;
|
||||
upd_boot_ver = (pfw[0x3f] << 8) + pfw[0x3e];
|
||||
for (k=0; k<upd_header->n_match; k++) {
|
||||
pvid = plist[k];
|
||||
PRINT_DBG("chsc::pid_vid in list=0x%x\n", pvid);
|
||||
if ((pvid & PID_VID_MASK) == (st_dev.vid_pid & PID_VID_MASK)) {
|
||||
PRINT_DBG("chsc::running_ver=%d, upd_ver=%d\n", st_dev.fw_ver, upd_boot_ver);
|
||||
if((st_dev.fw_ver < upd_boot_ver) || (st_dev.setup_ok == 0)){
|
||||
idx_active = k;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if((st_dev.setup_ok == 0) && (idx_active < 0)){
|
||||
idx_active = 0;
|
||||
}
|
||||
|
||||
if(idx_active >= 0){
|
||||
st_dev.needUpd = 1;
|
||||
}
|
||||
|
||||
return SEMI_DRV_ERR_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
return:
|
||||
0 ->success
|
||||
others ->fail
|
||||
|
||||
*/
|
||||
static int32_t semi_touch_update(uint8_t *pdata, uint32_t len)
|
||||
{
|
||||
if((pdata == NULL) || (len<1024) || (len>0x9f00)){
|
||||
PRINT_DBG("chsc:semi_touch_update, not chsc5816 fw\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if((pdata[0x30] != 0x16) || (pdata[0x31] != 0x58)){
|
||||
PRINT_DBG("chsc:semi_touch_update, not chsc5816 fw\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if(semi_touch_enter_burn_mode() != 0){
|
||||
//kal_prompt_trace(MOD_WAP,"chsc::semi_touch_enter_burn_mode fail\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if(semi_touch_burn_erase() != 0){
|
||||
PRINT_DBG("chsc::semi_touch_burn_erase fail\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if(semi_touch_nvm_write(pdata, 0x00000000, len) != 0){
|
||||
PRINT_DBG("chsc::semi_touch_nvm_write fail\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return SEMI_DRV_ERR_OK;
|
||||
}
|
||||
|
||||
static void semi_touch_setup_check(void)
|
||||
{
|
||||
int32_t retry = 0;
|
||||
uint32_t naFlag = 0;
|
||||
img_header_t image_header;
|
||||
img_header_t image_confirm;
|
||||
|
||||
//clean boot status
|
||||
semi_touch_write_bytes(0x20000018, (uint8_t*)&naFlag, 4);
|
||||
|
||||
semi_touch_reset();
|
||||
|
||||
st_dev.fw_ver = 0;
|
||||
st_dev.vid_pid = 0;
|
||||
st_dev.setup_ok = 0;//default error
|
||||
|
||||
image_header.sig = 0;
|
||||
for(retry=0; retry<10; retry++){
|
||||
semi_touch_msdelay(10);
|
||||
|
||||
if(semi_touch_read_bytes(0x20000014, (uint8_t*)&image_header, sizeof(image_header)) != 0){
|
||||
continue;
|
||||
}
|
||||
|
||||
if(semi_touch_read_bytes(0x20000014, (uint8_t*)&image_confirm, sizeof(image_confirm)) != 0){
|
||||
continue;
|
||||
}
|
||||
if((image_header.sig != image_confirm.sig) ||
|
||||
(image_header.vid_pid != image_confirm.vid_pid) ||
|
||||
(image_header.raw_offet != image_confirm.raw_offet) ||
|
||||
(image_header.dif_offet != image_confirm.dif_offet) ||
|
||||
(image_header.fw_ver != image_confirm.fw_ver)){
|
||||
//kal_prompt_trace(MOD_WAP,"chsc::double check, retry\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
if(image_header.sig == 0x43534843){ //"CHSC"
|
||||
st_dev.fw_ver = image_header.fw_ver;
|
||||
st_dev.vid_pid = image_header.vid_pid;
|
||||
st_dev.raw_adr = image_confirm.raw_offet + 0x20000000;
|
||||
st_dev.setup_ok = 1;//pass
|
||||
st_dev.ctp_status = CTP_POINTING_WORK;
|
||||
break;
|
||||
}else if(image_header.sig == 0x4F525245){ //boot self check fail
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int32_t semi_touch_dect(void)
|
||||
{
|
||||
uint32_t u32Data, retry;
|
||||
|
||||
for(retry=0; retry<3; retry++){
|
||||
semi_touch_reset();
|
||||
|
||||
if(!semi_touch_read_bytes(0x20000000, (uint8_t *)&u32Data, 4)){
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
void semi_touch_irq_handler_imp(void)
|
||||
{
|
||||
#define _UI_MAX_POINTS 1
|
||||
#define GEST_CODE_ACT_LS 0x10 //left
|
||||
#define GEST_CODE_ACT_RS 0x20 //right
|
||||
#define GEST_CODE_ACT_US 0x30 //up
|
||||
#define GEST_CODE_ACT_DS 0x40 //down
|
||||
|
||||
int pointed = 0;
|
||||
union rpt_point_t* ppt;
|
||||
unsigned char gestCode;
|
||||
unsigned char data[8];
|
||||
int x, y;
|
||||
PRINT_DBG("semi_touch_irq_handler_imp\r\n");
|
||||
|
||||
if(semi_touch_read_bytes(0x2000002c, data, 8)){
|
||||
PRINT_DBG("chsc:read pixel data fail\n" );
|
||||
return;
|
||||
}
|
||||
|
||||
PRINT_DBG("imp = %x %x\r\n",data[0], data[1]);
|
||||
|
||||
pointed = 0;
|
||||
ppt = (union rpt_point_t*)&data[2];
|
||||
if((data[0] == 0xff) && (data[1] <= 2)){
|
||||
if(data[1] > 0){
|
||||
pointed = 1;
|
||||
x = (unsigned int)(ppt->rp.x_h4 << 8) | ppt->rp.x_l8;
|
||||
y = (unsigned int)(ppt->rp.y_h4 << 8) | ppt->rp.y_l8;
|
||||
}
|
||||
}else{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
bool semi_touch_read_coordinate(int16_t *x, int16_t *y)
|
||||
{
|
||||
int pointed = 0;
|
||||
union rpt_point_t* ppt;
|
||||
unsigned char data[8];
|
||||
|
||||
if(semi_touch_read_bytes(0x2000002c, data, 8)){
|
||||
PRINT_DBG("chsc:read pixel data fail\n" );
|
||||
return 0;
|
||||
}
|
||||
|
||||
pointed = 0;
|
||||
ppt = (union rpt_point_t*)&data[2];
|
||||
if((data[0] == 0xff) && (data[1] <= 2)){
|
||||
if(data[1] > 0){
|
||||
pointed = 1;
|
||||
*x = (unsigned int)(ppt->rp.x_h4 << 8) | ppt->rp.x_l8;
|
||||
*y = (unsigned int)(ppt->rp.y_h4 << 8) | ppt->rp.y_l8;
|
||||
PRINT_DBG("x = %d y = %d \r\n",*x, *y);
|
||||
}
|
||||
}
|
||||
|
||||
return pointed;
|
||||
}
|
||||
|
||||
int semi_touch_init()
|
||||
{
|
||||
semi_touch_power_int();
|
||||
|
||||
if(semi_touch_dect() != SEMI_DRV_ERR_OK){
|
||||
PRINT_DBG("chsc:no chsc5816\r\n" );
|
||||
return -1;
|
||||
}
|
||||
|
||||
semi_touch_setup_check();
|
||||
|
||||
semi_touch_update_check();
|
||||
|
||||
semi_touch_reset();
|
||||
st_dev.ctp_status = CTP_POINTING_WORK;
|
||||
|
||||
PRINT_DBG("chsc init ok\r\n" );
|
||||
|
||||
return 0;
|
||||
}
|
||||
170
fr3092_mcu/components/drivers/bsp/touchpad/driver_touchpad.c
Normal file
170
fr3092_mcu/components/drivers/bsp/touchpad/driver_touchpad.c
Normal file
@ -0,0 +1,170 @@
|
||||
#include <stdint.h>
|
||||
|
||||
#include "driver_touchpad.h"
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
//#define TOUCHPAD_SH8601A
|
||||
//#define TOUCHPAD_ICNA3310
|
||||
//#define TOUCHPAD_CHSC586
|
||||
//#define TOUCHPAD_CHSC6x
|
||||
//#define TOUCHPAD_CTP820
|
||||
#define TOUCHPAD_FT6336U
|
||||
|
||||
#ifdef TOUCHPAD_SH8601A
|
||||
#define TOUCHPAD_IIC_SLAVE_ADDRESS (0x2C<<1) // from sh8601a
|
||||
#endif
|
||||
#ifdef TOUCHPAD_ICNA3310
|
||||
#define TOUCHPAD_IIC_SLAVE_ADDRESS (0x48 << 1) // from icna3310
|
||||
#endif
|
||||
#ifdef TOUCHPAD_CTP820
|
||||
#define TOUCHPAD_IIC_SLAVE_ADDRESS (0x15 << 1) // from ctp820
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_FT6336U
|
||||
#define TOUCHPAD_IIC_SLAVE_ADDRESS (0x71) // from ft6336u
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CHSC586
|
||||
extern bool semi_touch_read_coordinate(int16_t *x, int16_t *y);
|
||||
extern int semi_touch_init();
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CHSC6x
|
||||
bool chsc6x_read_touch_info(int16_t *x, int16_t *y);
|
||||
void chsc6x_init(void);
|
||||
#endif
|
||||
|
||||
bool touchpad_read(int16_t *x, int16_t *y)
|
||||
{
|
||||
#ifdef TOUCHPAD_SH8601A
|
||||
uint8_t buffer[8];
|
||||
bool pressed = false;
|
||||
|
||||
i2c_memory_read(&i2c_touchpad_handle, TOUCHPAD_IIC_SLAVE_ADDRESS, 0, buffer, 8);
|
||||
|
||||
if (buffer[2] != 0) {
|
||||
*x = ((buffer[3]&0x0f)<<8) | buffer[4];
|
||||
*y = ((buffer[5]&0x0f)<<8) | buffer[6];
|
||||
pressed = true;
|
||||
}
|
||||
else {
|
||||
pressed = false;
|
||||
}
|
||||
|
||||
return pressed;
|
||||
#endif
|
||||
#ifdef TOUCHPAD_ICNA3310
|
||||
uint8_t buffer[9];
|
||||
bool pressed = false;
|
||||
|
||||
i2c_memory_read(&i2c_touchpad_handle, TOUCHPAD_IIC_SLAVE_ADDRESS, 0x1000, buffer, 9);
|
||||
|
||||
if (buffer[1] == 1) {
|
||||
*x = ((buffer[4]&0x0f)<<8) | buffer[3];
|
||||
*y = ((buffer[6]&0x0f)<<8) | buffer[5];
|
||||
pressed = true;
|
||||
}
|
||||
else {
|
||||
pressed = false;
|
||||
}
|
||||
|
||||
return pressed;
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CHSC586
|
||||
return semi_touch_read_coordinate(x, y);
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CHSC6x
|
||||
return chsc6x_read_touch_info(x, y);
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CTP820
|
||||
uint8_t buffer[7];
|
||||
bool pressed = false;
|
||||
|
||||
i2c_memory_read(&i2c_touchpad_handle, TOUCHPAD_IIC_SLAVE_ADDRESS, 0x00, buffer, 7);
|
||||
|
||||
if (buffer[2] == 1) {
|
||||
*x = ((buffer[3]&0x0f)<<8) | buffer[4];
|
||||
*y = ((buffer[5]&0x0f)<<8) | buffer[6];
|
||||
pressed = true;
|
||||
}
|
||||
else {
|
||||
pressed = false;
|
||||
}
|
||||
|
||||
return pressed;
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_FT6336U
|
||||
uint8_t buffer[7];
|
||||
bool pressed = false;
|
||||
i2c_memory_read(&i2c_touchpad_handle, TOUCHPAD_IIC_SLAVE_ADDRESS, 0x00, buffer, 7);
|
||||
if (buffer[2] == 1) {
|
||||
*x = ((buffer[3]&0x0f)<<8) | buffer[4];
|
||||
*y = ((buffer[5]&0x0f)<<8) | buffer[6];
|
||||
pressed = true;
|
||||
}
|
||||
else {
|
||||
pressed = false;
|
||||
}
|
||||
|
||||
return pressed;
|
||||
#endif
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void touchpad_init(void)
|
||||
{
|
||||
#ifdef TOUCHPAD_ICNA3310
|
||||
/* reset touch pad chip */
|
||||
__TOUCHPAD_RESET_SET();
|
||||
__TOUCHPAD_DELAY_MS(10);
|
||||
__TOUCHPAD_RESET_CLEAR();
|
||||
__TOUCHPAD_DELAY_MS(5);
|
||||
__TOUCHPAD_RESET_SET();
|
||||
__TOUCHPAD_DELAY_MS(200);
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CHSC586
|
||||
semi_touch_init();
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CHSC6x
|
||||
chsc6x_init();
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_CTP820
|
||||
/* reset touch pad chip */
|
||||
__TOUCHPAD_RESET_SET();
|
||||
__TOUCHPAD_DELAY_MS(10);
|
||||
__TOUCHPAD_RESET_CLEAR();
|
||||
__TOUCHPAD_DELAY_MS(10);
|
||||
__TOUCHPAD_RESET_SET();
|
||||
__TOUCHPAD_DELAY_MS(50);
|
||||
#endif
|
||||
|
||||
#ifdef TOUCHPAD_FT6336U
|
||||
/* reset touch pad chip */
|
||||
__TOUCHPAD_RESET_SET();
|
||||
__TOUCHPAD_RESET_CLEAR();
|
||||
vTaskDelay(10);
|
||||
__TOUCHPAD_RESET_SET();
|
||||
vTaskDelay(250);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void touchpad_sleep(void)
|
||||
{
|
||||
|
||||
#ifdef TOUCHPAD_CTP820
|
||||
uint8_t value = 0x03;
|
||||
i2c_memory_write(&i2c_touchpad_handle, TOUCHPAD_IIC_SLAVE_ADDRESS, 0xE5, &value, 1);
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
88
fr3092_mcu/components/drivers/bsp/touchpad/driver_touchpad.h
Normal file
88
fr3092_mcu/components/drivers/bsp/touchpad/driver_touchpad.h
Normal file
@ -0,0 +1,88 @@
|
||||
#ifndef _DRIVER_TOUCHPAD_H
|
||||
#define _DRIVER_TOUCHPAD_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "driver_i2c.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macro Variables definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#define __TOUCHPAD_RESET_SET() touchpad_reset_set()
|
||||
#define __TOUCHPAD_RESET_CLEAR() touchpad_reset_clear()
|
||||
#define __TOUCHPAD_DELAY_MS(counter) touchpad_delay_ms(counter)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Global Variables definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern I2C_HandleTypeDef i2c_touchpad_handle;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// External function definitions
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
/************************************************************************************
|
||||
* @fn touchpad_reset_set
|
||||
*
|
||||
* @brief Set touchpad driver RESET pin to HIGH, this function should be implemented by user..
|
||||
*/
|
||||
void touchpad_reset_set(void);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn touchpad_reset_clear
|
||||
*
|
||||
* @brief Set touchpad driver RESET pin to LOW, this function should be implemented by user.
|
||||
*/
|
||||
void touchpad_reset_clear(void);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn touchpad_delay_ms
|
||||
*
|
||||
* @brief Used in touchpad driver. co_delay_100us or vTaskDelay can be used for implementation
|
||||
* by user.
|
||||
*/
|
||||
void touchpad_delay_ms(uint32_t counter);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn touchpad_read
|
||||
*
|
||||
* @brief used to read data from touchpad, these data are update in interrupt
|
||||
*
|
||||
* @param x: current x position.
|
||||
* y: current y position.
|
||||
*
|
||||
* @return true: pressed and x, y value is valid; false: released
|
||||
*/
|
||||
bool touchpad_read(int16_t *x, int16_t *y);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn touchpad_init
|
||||
*
|
||||
* @brief used to init touchpad
|
||||
*/
|
||||
void touchpad_init(void);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn touchpad_sleep
|
||||
*
|
||||
* @brief touchpad go to sleep
|
||||
*/
|
||||
void touchpad_sleep(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // _DRIVER_TOUCHPAD_H
|
||||
870
fr3092_mcu/components/drivers/cmsis/cmsis_armcc.h
Normal file
870
fr3092_mcu/components/drivers/cmsis/cmsis_armcc.h
Normal file
@ -0,0 +1,870 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
1877
fr3092_mcu/components/drivers/cmsis/cmsis_armclang.h
Normal file
1877
fr3092_mcu/components/drivers/cmsis/cmsis_armclang.h
Normal file
File diff suppressed because it is too large
Load Diff
274
fr3092_mcu/components/drivers/cmsis/cmsis_compiler.h
Normal file
274
fr3092_mcu/components/drivers/cmsis/cmsis_compiler.h
Normal file
@ -0,0 +1,274 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
#define __forceinline static inline
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __forceinline
|
||||
#endif
|
||||
#define __IRQ __irq
|
||||
#define __FIQ __irq
|
||||
#define __ARRAY_EMPTY
|
||||
#define __BLEIRQ
|
||||
#define __MODULE__ "none.c"
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
2093
fr3092_mcu/components/drivers/cmsis/cmsis_gcc.h
Normal file
2093
fr3092_mcu/components/drivers/cmsis/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
916
fr3092_mcu/components/drivers/cmsis/cmsis_iccarm.h
Normal file
916
fr3092_mcu/components/drivers/cmsis/cmsis_iccarm.h
Normal file
@ -0,0 +1,916 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.0.5
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT restrict
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __WEAK
|
||||
#undef __WEAK
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
39
fr3092_mcu/components/drivers/cmsis/cmsis_version.h
Normal file
39
fr3092_mcu/components/drivers/cmsis/cmsis_version.h
Normal file
@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
1896
fr3092_mcu/components/drivers/cmsis/core_armv8mbl.h
Normal file
1896
fr3092_mcu/components/drivers/cmsis/core_armv8mbl.h
Normal file
File diff suppressed because it is too large
Load Diff
2960
fr3092_mcu/components/drivers/cmsis/core_armv8mml.h
Normal file
2960
fr3092_mcu/components/drivers/cmsis/core_armv8mml.h
Normal file
File diff suppressed because it is too large
Load Diff
888
fr3092_mcu/components/drivers/cmsis/core_cm0.h
Normal file
888
fr3092_mcu/components/drivers/cmsis/core_cm0.h
Normal file
@ -0,0 +1,888 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.3
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
|
||||
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1023
fr3092_mcu/components/drivers/cmsis/core_cm0plus.h
Normal file
1023
fr3092_mcu/components/drivers/cmsis/core_cm0plus.h
Normal file
File diff suppressed because it is too large
Load Diff
1899
fr3092_mcu/components/drivers/cmsis/core_cm23.h
Normal file
1899
fr3092_mcu/components/drivers/cmsis/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1933
fr3092_mcu/components/drivers/cmsis/core_cm3.h
Normal file
1933
fr3092_mcu/components/drivers/cmsis/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
2963
fr3092_mcu/components/drivers/cmsis/core_cm33.h
Normal file
2963
fr3092_mcu/components/drivers/cmsis/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
2118
fr3092_mcu/components/drivers/cmsis/core_cm4.h
Normal file
2118
fr3092_mcu/components/drivers/cmsis/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2660
fr3092_mcu/components/drivers/cmsis/core_cm7.h
Normal file
2660
fr3092_mcu/components/drivers/cmsis/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
1016
fr3092_mcu/components/drivers/cmsis/core_sc000.h
Normal file
1016
fr3092_mcu/components/drivers/cmsis/core_sc000.h
Normal file
File diff suppressed because it is too large
Load Diff
1903
fr3092_mcu/components/drivers/cmsis/core_sc300.h
Normal file
1903
fr3092_mcu/components/drivers/cmsis/core_sc300.h
Normal file
File diff suppressed because it is too large
Load Diff
197
fr3092_mcu/components/drivers/cmsis/mpu_armv7.h
Normal file
197
fr3092_mcu/components/drivers/cmsis/mpu_armv7.h
Normal file
@ -0,0 +1,197 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U
|
||||
#define ARM_MPU_AP_PRIV 1U
|
||||
#define ARM_MPU_AP_URO 2U
|
||||
#define ARM_MPU_AP_FULL 3U
|
||||
#define ARM_MPU_AP_PRO 5U
|
||||
#define ARM_MPU_AP_RO 6U
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(MPU_RASR_ENABLE_Msk))
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
333
fr3092_mcu/components/drivers/cmsis/mpu_armv8.h
Normal file
333
fr3092_mcu/components/drivers/cmsis/mpu_armv8.h
Normal file
@ -0,0 +1,333 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Pos) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
70
fr3092_mcu/components/drivers/cmsis/tz_context.h
Normal file
70
fr3092_mcu/components/drivers/cmsis/tz_context.h
Normal file
@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@ -0,0 +1,293 @@
|
||||
;************************* (C) COPYRIGHT 2023 FreqChip ***************************
|
||||
;* File Name : startup_fr30xx.s
|
||||
;* Author : FreqChip Firmware Team
|
||||
;* Version : V1.0.0
|
||||
;* Date : 2022
|
||||
;* Description : fr30xx Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2022 FreqChip.
|
||||
;* All rights reserved.
|
||||
;*******************************************************************************
|
||||
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
|
||||
;<h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
|
||||
Stack_Size EQU 0x00001000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
__stack_limit
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
;<h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
;</h>
|
||||
|
||||
Heap_Size EQU 0x00019000
|
||||
|
||||
IF Heap_Size != 0 ; Heap is provided
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
ENDIF
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; -14 NMI Handler
|
||||
DCD HardFault_Handler ; -13 Hard Fault Handler
|
||||
DCD MemManage_Handler ; -12 MPU Fault Handler
|
||||
DCD BusFault_Handler ; -11 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; -10 Usage Fault Handler
|
||||
DCD SecureFault_Handler ; -9 Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; -5 SVCall Handler
|
||||
DCD DebugMon_Handler ; -4 Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; -2 PendSV Handler
|
||||
DCD SysTick_Handler ; -1 SysTick Handler
|
||||
|
||||
; Interrupts
|
||||
DCD timer0_irq ; 0 Interrupt 0
|
||||
DCD timer1_irq ; 1 Interrupt 1
|
||||
DCD timer2_irq ; 2 timer2
|
||||
DCD timer3_irq ; 3 timer3
|
||||
DCD dma0_irq ; 4 dma0
|
||||
DCD dma1_irq ; 5 dma1
|
||||
DCD sdioh0_irq ; 6 sdioh
|
||||
DCD sdioh1_irq ; 7 sdiod
|
||||
DCD ipc_mcu_irq ; 8 ipc mcu
|
||||
DCD usbotg_irq ; 9 usbotg
|
||||
DCD iir_irq ; 10 iir
|
||||
DCD blend_irq ; 11 trigfunc
|
||||
DCD fft_irq ; 12 fft
|
||||
DCD sec_aes_irq ; 13 Interrupt 13
|
||||
DCD Interrupt14_Handler ; 14 Interrupt 14
|
||||
DCD Interrupt15_Handler ; 15 Interrupt 15
|
||||
DCD gpioa_irq ; 16 GPIOA
|
||||
DCD gpiob_irq ; 17 GPIOB
|
||||
DCD gpioc_irq ; 18 GPIOC
|
||||
DCD gpiod_irq ; 19 GPIOD
|
||||
DCD uart0_irq ; 20 uart0
|
||||
DCD uart1_irq ; 21 uart1
|
||||
DCD uart2_irq ; 22 uart2
|
||||
DCD uart3_irq ; 23 uart3
|
||||
DCD uart4_irq ; 24 uart4
|
||||
DCD uart5_irq ; 25 uart5
|
||||
DCD i2c0_irq ; 26 i2c0
|
||||
DCD i2c1_irq ; 27 i2c1
|
||||
DCD i2c2_irq ; 28 i2c2
|
||||
DCD i2c3_irq ; 29 i2c3
|
||||
DCD i2c4_irq ; 30 i2c4
|
||||
DCD i2c5_irq ; 31 i2c5
|
||||
DCD spim0_irq ; 32 spim0
|
||||
DCD spim1_irq ; 33 spim1
|
||||
DCD spim2_irq ; 34 spim2
|
||||
DCD spis0_irq ; 35 spis0
|
||||
DCD spis1_irq ; 36 spis1
|
||||
DCD spimx8_0_irq ; 37 spimx8_0
|
||||
DCD spimx8_1_irq ; 38 spimx8_1
|
||||
DCD i2s0_irq ; 39 i2s0
|
||||
DCD i2s1_irq ; 40 i2s1
|
||||
DCD i2s2_irq ; 41 i2s2
|
||||
DCD pdm0_irq ; 42 pdm0
|
||||
DCD pdm1_irq ; 43 pdm1
|
||||
DCD pdm2_irq ; 44 pdm2
|
||||
DCD adc_irq ; 45 adc
|
||||
DCD codec_irq ; 46 codec
|
||||
DCD spdif_irq ; 47 spdif
|
||||
DCD sbc_dec_irq ; 48 sbc_dec
|
||||
DCD sbc_enc_irq ; 49 sbc_enc
|
||||
DCD mp3dec_irq ; 50 mp3dec
|
||||
DCD parallel0_irq ; 51 parallel0
|
||||
DCD Interrupt52_Handler ; 52 Interrupt 52
|
||||
DCD cali_irq ; 53 cali
|
||||
DCD trng_irq ; 54 trng
|
||||
DCD tick_irq ; 55 Interrupt 55
|
||||
DCD Interrupt56_Handler ; 56 Interrupt 56
|
||||
DCD Interrupt57_Handler ; 57 Interrupt 57
|
||||
DCD Interrupt58_Handler ; 58 Interrupt 58
|
||||
DCD Interrupt59_Handler ; 59 Interrupt 59
|
||||
DCD timer4_irq ; 60 timer4
|
||||
DCD timer5_irq ; 61 timer5
|
||||
DCD Interrupt62_Handler ; 62 Interrupt 62
|
||||
DCD ipc_dsp_irq ; 63 Interrupt 63
|
||||
DCD yuv2rgb_irq ; 64 yuv2rgb
|
||||
DCD pmu_irq ; 65 pmu
|
||||
DCD 0xAA55AA55 ; app check data
|
||||
DCD 0x00000001 ; app version
|
||||
DCD 0 ; code length
|
||||
|
||||
; SPACE (470 * 4) ; Interrupts 10 .. 480 are left out
|
||||
__Vectors_End
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =__stack_limit
|
||||
MSR MSPLIM, R0 ; Non-secure version of MSPLIM is RAZ/WI
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Macro to define default exception/interrupt handlers.
|
||||
; Default handler are weak symbols with an endless loop.
|
||||
; They can be overwritten by real handlers.
|
||||
MACRO
|
||||
Set_Default_Handler $Handler_Name
|
||||
$Handler_Name PROC
|
||||
EXPORT $Handler_Name [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MEND
|
||||
|
||||
|
||||
; Default exception/interrupt handler
|
||||
|
||||
Set_Default_Handler NMI_Handler
|
||||
Set_Default_Handler HardFault_Handler
|
||||
Set_Default_Handler MemManage_Handler
|
||||
Set_Default_Handler BusFault_Handler
|
||||
Set_Default_Handler UsageFault_Handler
|
||||
Set_Default_Handler SecureFault_Handler
|
||||
Set_Default_Handler SVC_Handler
|
||||
Set_Default_Handler DebugMon_Handler
|
||||
Set_Default_Handler PendSV_Handler
|
||||
Set_Default_Handler SysTick_Handler
|
||||
|
||||
Set_Default_Handler timer0_irq
|
||||
Set_Default_Handler timer1_irq
|
||||
Set_Default_Handler timer2_irq
|
||||
Set_Default_Handler timer3_irq
|
||||
Set_Default_Handler dma0_irq
|
||||
Set_Default_Handler dma1_irq
|
||||
Set_Default_Handler sdioh0_irq
|
||||
Set_Default_Handler sdioh1_irq
|
||||
Set_Default_Handler ipc_mcu_irq
|
||||
Set_Default_Handler usbotg_irq
|
||||
Set_Default_Handler iir_irq
|
||||
Set_Default_Handler blend_irq
|
||||
Set_Default_Handler fft_irq
|
||||
Set_Default_Handler sec_aes_irq
|
||||
Set_Default_Handler Interrupt14_Handler
|
||||
Set_Default_Handler Interrupt15_Handler
|
||||
Set_Default_Handler gpioa_irq
|
||||
Set_Default_Handler gpiob_irq
|
||||
Set_Default_Handler gpioc_irq
|
||||
Set_Default_Handler gpiod_irq
|
||||
Set_Default_Handler uart0_irq
|
||||
Set_Default_Handler uart1_irq
|
||||
Set_Default_Handler uart2_irq
|
||||
Set_Default_Handler uart3_irq
|
||||
Set_Default_Handler uart4_irq
|
||||
Set_Default_Handler uart5_irq
|
||||
Set_Default_Handler i2c0_irq
|
||||
Set_Default_Handler i2c1_irq
|
||||
Set_Default_Handler i2c2_irq
|
||||
Set_Default_Handler i2c3_irq
|
||||
Set_Default_Handler i2c4_irq
|
||||
Set_Default_Handler i2c5_irq
|
||||
Set_Default_Handler spim0_irq
|
||||
Set_Default_Handler spim1_irq
|
||||
Set_Default_Handler spim2_irq
|
||||
Set_Default_Handler spis0_irq
|
||||
Set_Default_Handler spis1_irq
|
||||
Set_Default_Handler spimx8_0_irq
|
||||
Set_Default_Handler spimx8_1_irq
|
||||
Set_Default_Handler i2s0_irq
|
||||
Set_Default_Handler i2s1_irq
|
||||
Set_Default_Handler i2s2_irq
|
||||
Set_Default_Handler pdm0_irq
|
||||
Set_Default_Handler pdm1_irq
|
||||
Set_Default_Handler pdm2_irq
|
||||
Set_Default_Handler adc_irq
|
||||
Set_Default_Handler codec_irq
|
||||
Set_Default_Handler spdif_irq
|
||||
Set_Default_Handler sbc_dec_irq
|
||||
Set_Default_Handler sbc_enc_irq
|
||||
Set_Default_Handler mp3dec_irq
|
||||
Set_Default_Handler parallel0_irq
|
||||
Set_Default_Handler Interrupt52_Handler
|
||||
Set_Default_Handler cali_irq
|
||||
Set_Default_Handler trng_irq
|
||||
Set_Default_Handler tick_irq
|
||||
Set_Default_Handler Interrupt56_Handler
|
||||
Set_Default_Handler Interrupt57_Handler
|
||||
Set_Default_Handler Interrupt58_Handler
|
||||
Set_Default_Handler Interrupt59_Handler
|
||||
Set_Default_Handler timer4_irq
|
||||
Set_Default_Handler timer5_irq
|
||||
Set_Default_Handler Interrupt62_Handler
|
||||
Set_Default_Handler ipc_dsp_irq
|
||||
Set_Default_Handler yuv2rgb_irq
|
||||
Set_Default_Handler pmu_irq
|
||||
ALIGN
|
||||
|
||||
|
||||
; User setup Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
259
fr3092_mcu/components/drivers/device/fr30xx/fr30xx.h
Normal file
259
fr3092_mcu/components/drivers/device/fr30xx/fr30xx.h
Normal file
@ -0,0 +1,259 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file fr30xx.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @brief CMSIS fr30xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
* - Configuration of the Processor and Core Peripherals
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __FR30XX_H__
|
||||
#define __FR30XX_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @group Peripheral_interrupt_number_definition
|
||||
* @{
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M33 Processor Exceptions Numbers ************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M33 Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M33 SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M33 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M33 System Tick Interrupt */
|
||||
|
||||
/****** CMSDK Specific Interrupt Numbers *******************************************************/
|
||||
TIMER0_IRQn = 0, /*!< */
|
||||
TIMER1_IRQn = 1, /*!< */
|
||||
TIMER2_IRQn = 2, /*!< */
|
||||
TIMER3_IRQn = 3, /*!< */
|
||||
DMA0_IRQn = 4,
|
||||
DMA1_IRQn = 5, /*!< */
|
||||
SDIOH0_IRQn = 6, /*!< */
|
||||
SDIOH1_IRQn = 7, /*!< */
|
||||
IPC_MCU_IRQn = 8, /*!< */
|
||||
USBOTG_IRQn = 9, /*!< */
|
||||
IIR_IRQn = 10, /*!< */
|
||||
BLEND_IRQn = 11, /*!< */
|
||||
FFT_IRQn = 12, /*!< */
|
||||
SEC_AES_IRQn = 13, /*!< */
|
||||
GPIOA_IRQn = 16, /*!< */
|
||||
GPIOB_IRQn = 17, /*!< */
|
||||
GPIOC_IRQn = 18, /*!< */
|
||||
GPIOD_IRQn = 19, /*!< */
|
||||
UART0_IRQn = 20, /*!< */
|
||||
UART1_IRQn = 21, /*!< */
|
||||
UART2_IRQn = 22, /*!< */
|
||||
UART3_IRQn = 23, /*!< */
|
||||
UART4_IRQn = 24,
|
||||
UART5_IRQn = 25,
|
||||
I2C0_IRQn = 26,
|
||||
I2C1_IRQn = 27,
|
||||
I2C2_IRQn = 28,
|
||||
I2C3_IRQn = 29,
|
||||
I2C4_IRQn = 30,
|
||||
I2C5_IRQn = 31,
|
||||
SPIM0_IRQn = 32,
|
||||
SPIM1_IRQn = 33,
|
||||
SPIM2_IRQn = 34,
|
||||
SPIS0_IRQn = 35,
|
||||
SPIS1_IRQn = 36,
|
||||
SPIMX8_0_IRQn = 37,
|
||||
SPIMX8_1_IRQn = 38,
|
||||
I2S0_IRQn = 39,
|
||||
I2S1_IRQn = 40,
|
||||
I2S2_IRQn = 41,
|
||||
PDM0_IRQn = 42,
|
||||
PDM1_IRQn = 43,
|
||||
PDM2_IRQn = 44,
|
||||
ADC_IRQn = 45,
|
||||
CODEC_IRQn = 46,
|
||||
SPDIF_IRQn = 47,
|
||||
SBCDEC_IRQn = 48,
|
||||
SBCENC_IRQn = 49,
|
||||
MP3DEC_IRQn = 50,
|
||||
PARALLEL_IRQn = 51,
|
||||
CALI_IRQn = 53,
|
||||
TRNG_IRQn = 54,
|
||||
TICK_IRQn = 55,
|
||||
TIMER4_IRQn = 60,
|
||||
TIMER5_IRQn = 61,
|
||||
IPC_DSP_IRQn = 63,
|
||||
YUV2RGB_IRQn = 64,
|
||||
PMU_IRQn = 65,
|
||||
}IRQn_Type;
|
||||
#endif // defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
|
||||
|
||||
#ifdef __XTENSA__
|
||||
typedef enum IRQn
|
||||
{
|
||||
DSP_IPC_IRQn = 7,
|
||||
}IRQn_Type;
|
||||
#endif // __XTENSA__
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
|
||||
/**
|
||||
* @brief Configuration of the Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM33_REV 0x0003U /*!< Core revision r0p4 */
|
||||
#define __SAUREGION_PRESENT 0 /*!< SAU regions present */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present */
|
||||
#define __VTOR_PRESENT 1 /*!< VTOR present */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __DSP_PRESENT 1 /*!< DSP present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
|
||||
|
||||
#include "core_cm33.h"
|
||||
#if __SAUREGION_PRESENT == 1
|
||||
#include "arm_cmse.h"
|
||||
#endif
|
||||
#endif // defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)
|
||||
|
||||
#ifdef __XTENSA__
|
||||
#define __WEAK __attribute__((weak))
|
||||
#define __STATIC_INLINE __attribute__((always_inline))
|
||||
#endif // __XTENSA__
|
||||
|
||||
/** @group Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_DAC_BASE (0x08000000)
|
||||
|
||||
#define DMAC0_BASE (0x10000000)
|
||||
#define USB_OTG_BASE (0x10010000)
|
||||
#define APB_BASE (0x10100000)
|
||||
#define SBC_DEC_BASE (0x10100000)
|
||||
#define SBC_ENC_BASE (0x10110000)
|
||||
#define MP3_DEC_BASE (0x10120000)
|
||||
#define CRC_BASE (0x10130000)
|
||||
#define EFUSE_SISO_BASE (0x10140000)
|
||||
#define EFUSE_PIPO_BASE (0x10150000)
|
||||
#define SYSTEM_TIMER_BASE (0x10160000)
|
||||
#define FREE_COUNTER_BASE (0x10170000)
|
||||
#define CAN0_BASE (0x10180000)
|
||||
#define CAN1_BASE (0x10190000)
|
||||
#define SEC_BASE (0x11000000)
|
||||
|
||||
#define DSP_FLASH_DAC_BASE (0x28000000)
|
||||
|
||||
#define PSRAM_DAC_BASE (0x38000000)
|
||||
#define SDIOH0_BASE (0x40000000)
|
||||
#define SDIOH1_BASE (0x40010000)
|
||||
#define DMAC1_BASE (0x40020000)
|
||||
#define BLEND_AHB0_BASE (0x40030000)
|
||||
#define BLEND_AHB1_BASE (0x40040000)
|
||||
|
||||
#define GPIOA_BASE (0x50000000)
|
||||
#define GPIOB_BASE (0x50008000)
|
||||
#define UART0_BASE (0x50010000)
|
||||
#define UART1_BASE (0x50018000)
|
||||
#define I2C0_BASE (0x50020000)
|
||||
#define I2C1_BASE (0x50028000)
|
||||
#define SPIM0_BASE (0x50030000)
|
||||
#define SPIS0_BASE (0x50040000)
|
||||
#define PWM0_BASE (0x50050000)
|
||||
#define I2S0_BASE (0x50060000)
|
||||
#define PDM0_BASE (0x50070000)
|
||||
#define IIR_BASE (0x50080000)
|
||||
#define TRI_FUNC_BASE (0x50090000)
|
||||
#define FFT_BASE (0x500A0000)
|
||||
#define AHBC_CACHE_BASE (0x500B0000)
|
||||
#define PSRAM_OSPI_BASE (0x500B8000)
|
||||
#define SPIMX8_0_BASE (0x500C0000)
|
||||
#define PARALLEL_BASE (0x500D0000)
|
||||
|
||||
#define GPIOC_BASE (0x50100000)
|
||||
#define GPIOD_BASE (0x50108000)
|
||||
#define UART2_BASE (0x50110000)
|
||||
#define UART3_BASE (0x50118000)
|
||||
#define I2C2_BASE (0x50120000)
|
||||
#define I2C3_BASE (0x50128000)
|
||||
#define SPIM1_BASE (0x50130000)
|
||||
#define SPIS1_BASE (0x50140000)
|
||||
#define PWM1_BASE (0x50150000)
|
||||
#define I2S1_BASE (0x50160000)
|
||||
#define PDM1_BASE (0x50170000)
|
||||
#define SPDIF_BASE (0x50180000)
|
||||
#define CODEC_BASE (0x50190000)
|
||||
#define SPIMX8_1_BASE (0x501C0000)
|
||||
|
||||
#define DSP_CTRL_BASE (0x50200000)
|
||||
#define UART4_BASE (0x50210000)
|
||||
#define UART5_BASE (0x50218000)
|
||||
#define I2C4_BASE (0x50220000)
|
||||
#define I2C5_BASE (0x50228000)
|
||||
#define SPIM2_BASE (0x50230000)
|
||||
#define DSP_TIM0_BASE (0x50240000)
|
||||
#define DSP_TIM1_BASE (0x50240014)
|
||||
#define DSP_WDT_BASE (0x50250000)
|
||||
#define I2S2_BASE (0x50260000)
|
||||
#define PDM2_BASE (0x50270000)
|
||||
#define DSP_IPC_BASE (0x50280000)
|
||||
#define DSP_QSPI_BASE (0x50290000)
|
||||
#define YUV2RGB_BASE (0x502A0000)
|
||||
|
||||
#define SYSTEM_REG_BASE (0xE0050000)
|
||||
#define TIM0_BASE (0xE0060000)
|
||||
#define TIM1_BASE (0xE0060014)
|
||||
#define TIM2_BASE (0xE0068000)
|
||||
#define TIM3_BASE (0xE0068014)
|
||||
#define FRSPIM_BASE (0xE0080000)
|
||||
#define IPC_BASE (0xE0090000)
|
||||
#define CALIB_BASE (0xE00A0000)
|
||||
#define FLASH_CACHE_BASE (0xE00B0000)
|
||||
#define FLASH_QSPI_BASE (0xE00C0000)
|
||||
#define TRNG_BASE (0xE00D0000)
|
||||
#define ADC_BASE (0xE00E0000)
|
||||
#define SARADC_BASE (0xE00F0000)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the system clock calculation.
|
||||
*/
|
||||
#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the system clock calculation.
|
||||
*/
|
||||
#define HSI_VALUE 24000000U /*!< Value of the Internal oscillator in Hz */
|
||||
|
||||
/* Peripheral drive */
|
||||
#include "driver_common.h"
|
||||
/* System driver */
|
||||
#include "system_fr30xx.h"
|
||||
/* trim relative */
|
||||
#include "trim_fr30xx.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __FR30XX_H__
|
||||
657
fr3092_mcu/components/drivers/device/fr30xx/system_fr30xx.c
Normal file
657
fr3092_mcu/components/drivers/device/fr30xx/system_fr30xx.c
Normal file
@ -0,0 +1,657 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file system_fr30xx.c
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Device Peripheral Access Layer System Source File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "fr30xx.h"
|
||||
|
||||
static uint32_t System_CORE_HSCLK = 24000000;
|
||||
static uint32_t System_SPLLCLK;
|
||||
static uint32_t System_AUPLLCLK;
|
||||
|
||||
uint32_t SystemCoreClock = 24000000;
|
||||
static uint32_t SystemDSPClock = 24000000;
|
||||
|
||||
static uint32_t System_LPRCCLK = 57000;
|
||||
|
||||
static uint32_t system_prevent_sleep_label = SYSTEM_PREVENT_SLEEP_TYPE_DISABLE;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief System Misc Init.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* free counter enable */
|
||||
__SYSTEM_FREE_COUNTER_CLK_ENABLE();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn System_CORE_HSCLK_CFG
|
||||
*
|
||||
* @brief CORE HSCLK config.
|
||||
*/
|
||||
void System_CORE_HSCLK_config(System_CORE_HSCLKConfig_t *COREHConfig)
|
||||
{
|
||||
if (COREHConfig->CORE_HSCLK_Source == CORE_HSCLK_SEL_HES)
|
||||
{
|
||||
__SYSTEM_CORE_HIGH_CLK_SELECT_OSC();
|
||||
System_CORE_HSCLK = HSE_VALUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
__SYSTEM_CORE_HIGH_CLK_SELECT_RC();
|
||||
System_CORE_HSCLK = HSI_VALUE;
|
||||
}
|
||||
}
|
||||
/*********************************************************************
|
||||
* @fn System_SPLL_config
|
||||
*
|
||||
* @brief SPLL config.
|
||||
*
|
||||
* @param PLLConfig : SPLL config parameter.
|
||||
* @param fu32_timeout : Wait for SPLL stable timeout, unit 5us.
|
||||
*
|
||||
* @return -1: SPLL stable timeout.
|
||||
* 0: succeed.
|
||||
*/
|
||||
int System_SPLL_config(System_PLLConfig_t *PLLConfig, uint32_t fu32_timeout)
|
||||
{
|
||||
int PLL_stability_flag = 0;
|
||||
|
||||
#define SPLL_ANALOG_POWER_ENABLE (0XC04B1820)
|
||||
#define SPLL_ANALOG_POWER_DISABLE (0XC04B1827)
|
||||
#define SPLL_ANALOG_POWER_ENABLE_WITHOUT_M (0X404B1820)
|
||||
|
||||
if (PLLConfig->PowerEn)
|
||||
{
|
||||
SYSTEM->SPLLConfig3.PLL_N = PLLConfig->PLL_N;
|
||||
SYSTEM->SPLLConfig3.PLL_M = PLLConfig->PLL_M;
|
||||
if (PLLConfig->PLL_M)
|
||||
SYSTEM->SPLLConfig0 = SPLL_ANALOG_POWER_ENABLE;
|
||||
else
|
||||
SYSTEM->SPLLConfig0 = SPLL_ANALOG_POWER_ENABLE_WITHOUT_M;
|
||||
|
||||
/* Wait for PLL stability timeout, unit 5us */
|
||||
for (int i = 0; i < fu32_timeout; i++)
|
||||
{
|
||||
system_delay_us(5);
|
||||
if (SYSTEM->SPLLConfig1 & 0x08)
|
||||
{
|
||||
PLL_stability_flag = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (PLL_stability_flag)
|
||||
{
|
||||
__SYSTEM_SPLL_CLK_DIV2_ENABLE();
|
||||
System_SPLLCLK = (PLLConfig->PLL_N*HSE_VALUE) + ((double)PLLConfig->PLL_M*HSE_VALUE)/0xFFFF;
|
||||
}
|
||||
else
|
||||
{
|
||||
System_SPLLCLK = 0;
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SYSTEM->SPLLConfig0 = SPLL_ANALOG_POWER_DISABLE;
|
||||
System_SPLLCLK = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*********************************************************************
|
||||
* @fn System_AUPLL_config
|
||||
*
|
||||
* @brief AUPLL config.
|
||||
*
|
||||
* @param PLLConfig : AUPLL config parameter.
|
||||
* @param fu32_timeout : Wait for AUPLL stable timeout, unit 5us.
|
||||
*
|
||||
* @return -1: AUPLL stable timeout.
|
||||
* 0: succeed.
|
||||
*/
|
||||
int System_AUPLL_config(System_PLLConfig_t *PLLConfig, uint32_t fu32_timeout)
|
||||
{
|
||||
int PLL_stability_flag = 0;
|
||||
|
||||
#define AUPLL_ANALOG_POWER_ENABLE (0XC04B1820)
|
||||
#define AUPLL_ANALOG_POWER_DISABLE (0XC04B1827)
|
||||
#define AUPLL_ANALOG_POWER_ENABLE_WITHOUT_M (0X404B1820)
|
||||
|
||||
if (PLLConfig->PowerEn)
|
||||
{
|
||||
SYSTEM->AUPLLConfig3.PLL_N = PLLConfig->PLL_N;
|
||||
SYSTEM->AUPLLConfig3.PLL_M = PLLConfig->PLL_M;
|
||||
if (PLLConfig->PLL_M)
|
||||
SYSTEM->AUPLLConfig0 = AUPLL_ANALOG_POWER_ENABLE;
|
||||
else
|
||||
SYSTEM->AUPLLConfig0 = AUPLL_ANALOG_POWER_ENABLE_WITHOUT_M;
|
||||
|
||||
/* Wait for PLL stability timeout, unit 5us */
|
||||
for (int i = 0; i < fu32_timeout; i++)
|
||||
{
|
||||
system_delay_us(5);
|
||||
if (SYSTEM->AUPLLConfig1 & 0x08)
|
||||
{
|
||||
PLL_stability_flag = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (PLL_stability_flag)
|
||||
{
|
||||
System_AUPLLCLK = (PLLConfig->PLL_N*HSE_VALUE) + ((double)PLLConfig->PLL_M*HSE_VALUE)/0xFFFF;
|
||||
}
|
||||
else
|
||||
{
|
||||
System_SPLLCLK = 0;
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SYSTEM->AUPLLConfig0 = AUPLL_ANALOG_POWER_DISABLE;
|
||||
System_AUPLLCLK = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*********************************************************************
|
||||
* @fn System_MCU_clock_Config
|
||||
*
|
||||
* @brief MCU clock congfig.
|
||||
*/
|
||||
void System_MCU_clock_Config(System_ClkConfig_t *ClkConfig)
|
||||
{
|
||||
/* MCU clock source select CORE_HSCLK */
|
||||
if (ClkConfig->MCU_Clock_Source == MCU_CLK_SEL_CORE_HSCLK)
|
||||
{
|
||||
__SYSTEM_MCU_CLK_DIV(ClkConfig->MCU_DIV);
|
||||
__SYSTEM_MCU_CLK_SELECT_COREH();
|
||||
|
||||
SystemDSPClock = System_CORE_HSCLK;
|
||||
SystemCoreClock = System_CORE_HSCLK / ClkConfig->MCU_DIV;
|
||||
}
|
||||
/* MCU clock source select SPLLCLK */
|
||||
else
|
||||
{
|
||||
__SYSTEM_SOC_CLK_DIV(ClkConfig->SOC_DIV);
|
||||
__SYSTEM_MCU_CLK_DIV(ClkConfig->MCU_DIV);
|
||||
__SYSTEM_MCU_CLK_SELECT_SPLL();
|
||||
|
||||
SystemDSPClock = System_SPLLCLK / ClkConfig->SOC_DIV;
|
||||
SystemCoreClock = SystemDSPClock / ClkConfig->MCU_DIV;
|
||||
}
|
||||
__SYSTEM_APB0_CLK_RATIO(ClkConfig->APB0_DIV);
|
||||
__SYSTEM_APB1_CLK_RATIO(ClkConfig->APB1_DIV);
|
||||
__SYSTEM_APB2_CLK_RATIO(ClkConfig->APB2_DIV);
|
||||
__SYSTEM_APB3_CLK_RATIO(ClkConfig->APB3_DIV);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn System_get_CoreClock/
|
||||
* System_get_DSPClock/
|
||||
* System_get_CORE_HSCLK/
|
||||
* System_get_SPLLCLK/
|
||||
* System_get_AUPLLCLK/
|
||||
*
|
||||
* @brief get system clock.unit HZ.
|
||||
*/
|
||||
__RAM_CODE uint32_t system_get_CoreClock(void)
|
||||
{
|
||||
return SystemCoreClock;
|
||||
}
|
||||
uint32_t system_get_DSPClock(void)
|
||||
{
|
||||
return SystemDSPClock;
|
||||
}
|
||||
uint32_t system_get_CORE_HSCLK(void)
|
||||
{
|
||||
return System_CORE_HSCLK;
|
||||
}
|
||||
uint32_t system_get_SPLLCLK(void)
|
||||
{
|
||||
return System_SPLLCLK;
|
||||
}
|
||||
uint32_t system_get_AUPLLCLK(void)
|
||||
{
|
||||
return System_AUPLLCLK;
|
||||
}
|
||||
uint32_t system_get_LPRCCLK(void)
|
||||
{
|
||||
return System_LPRCCLK;
|
||||
}
|
||||
void system_set_LPRCCLK(uint32_t clk)
|
||||
{
|
||||
System_LPRCCLK = clk;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn system_get_peripheral_clock
|
||||
*
|
||||
* @brief get peripheral clock. unit HZ
|
||||
*
|
||||
* @param fe_peripheral : peripheral select.
|
||||
*
|
||||
* @return peripheral clock unit HZ.
|
||||
*/
|
||||
uint32_t system_get_peripheral_clock(per_clock_index_t peripheral)
|
||||
{
|
||||
uint32_t PerClock;
|
||||
|
||||
switch (peripheral)
|
||||
{
|
||||
case PER_CLK_UARTx:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.UART_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.UART_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.UART_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_GPIOx:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.GPIO_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.GPIO_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.GPIO_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_I2Cx:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.I2C_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.I2C_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.I2C_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_TIMER01:{
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.TIMER01_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_TIMER23:{
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.TIMER23_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_SPIS:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV0.SSIS_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.SSIS_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_SPIMX8_0:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV0.MSPI0_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.MSPI0_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_SPIMX8_1:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV0.MSPI1_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.MSPI1_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_PWM:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.SSIS_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV2.PWM_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.PWM_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_PDM0:
|
||||
case PER_CLK_PDM1:
|
||||
case PER_CLK_PDM2:
|
||||
{
|
||||
uint32_t PDMx_CLK_SEL, PDMx_CLK_DIV;
|
||||
if (peripheral == PER_CLK_PDM0) {
|
||||
PDMx_CLK_SEL = SYSTEM->ClockSEL1.PDM0_CLK_SEL;
|
||||
PDMx_CLK_DIV = SYSTEM->AudioClockDIV.PDM0_CLK_DIV;
|
||||
}
|
||||
else if (peripheral == PER_CLK_PDM1){
|
||||
PDMx_CLK_SEL = SYSTEM->ClockSEL1.PDM1_CLK_SEL;
|
||||
PDMx_CLK_DIV = SYSTEM->AudioClockDIV.PDM1_CLK_DIV;
|
||||
}
|
||||
else{
|
||||
PDMx_CLK_SEL = SYSTEM->ClockSEL1.PDM2_CLK_SEL;
|
||||
PDMx_CLK_DIV = SYSTEM->AudioClockDIV.PDM2_CLK_DIV;
|
||||
}
|
||||
|
||||
/* clock from HCLK */
|
||||
if (PDMx_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (PDMx_CLK_DIV + 1);
|
||||
/* clock from AUPLL */
|
||||
else if (PDMx_CLK_SEL == 1)
|
||||
PerClock = system_get_AUPLLCLK() / (PDMx_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_SDIOH0:
|
||||
{
|
||||
/* clock from HCLK */
|
||||
if (SYSTEM->ClockSEL0.SDIOH0_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.SDIOH0_CLK_DIV + 1);
|
||||
/* clock from SPLL */
|
||||
else if (SYSTEM->ClockSEL0.SDIOH0_CLK_SEL == 1)
|
||||
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH0_CLK_DIV + 1);
|
||||
/* clock from AUPLL */
|
||||
else
|
||||
PerClock = system_get_AUPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH0_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_SDIOH1:
|
||||
{
|
||||
/* clock from HCLK */
|
||||
if (SYSTEM->ClockSEL0.SDIOH1_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.SDIOH1_CLK_DIV + 1);
|
||||
/* clock from SPLL */
|
||||
else if (SYSTEM->ClockSEL0.SDIOH1_CLK_SEL == 1)
|
||||
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH1_CLK_DIV + 1);
|
||||
/* clock from AUPLL */
|
||||
else
|
||||
PerClock = system_get_AUPLLCLK() / (SYSTEM->BlockClockDIV0.SDIOH1_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_CANx:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.MCAN_CLK_SEL)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV2.MCAN_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV2.MCAN_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_I2Sx:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL1.I2S_CLK_SEL == 2)
|
||||
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->AudioClockDIV.I2S_CLK_DIV + 1);
|
||||
else if (SYSTEM->ClockSEL1.I2S_CLK_SEL == 1)
|
||||
PerClock = (system_get_SPLLCLK()) / (SYSTEM->AudioClockDIV.I2S_CLK_DIV + 1);
|
||||
else if (SYSTEM->ClockSEL1.I2S_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->AudioClockDIV.I2S_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_OSPI:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.OSPI_CLK_SEL == 2)
|
||||
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->BlockClockDIV0.OSPI_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL0.OSPI_CLK_SEL == 1)
|
||||
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.OSPI_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL0.OSPI_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.OSPI_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_QSPI0:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.QSPI0_CLK_SEL == 2)
|
||||
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->BlockClockDIV0.QSPI0_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL0.QSPI0_CLK_SEL == 1)
|
||||
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.QSPI0_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL0.QSPI0_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.QSPI0_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_QSPI1:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.QSPI1_CLK_SEL == 2)
|
||||
PerClock = (system_get_AUPLLCLK()) / (SYSTEM->BlockClockDIV0.QSPI1_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL0.QSPI1_CLK_SEL == 1)
|
||||
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV0.QSPI1_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL0.QSPI1_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV0.QSPI1_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_SPIMx:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.SSIM_CLK_SEL == 1)
|
||||
PerClock = system_get_SPLLCLK() / (SYSTEM->BlockClockDIV1.SSIM_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.SSIM_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_SBC:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL1.SBC_CLK_SEL == 1)
|
||||
PerClock = system_get_SPLLCLK() / (SYSTEM->AudioClockDIV.SBC_CLK_DIV + 1);
|
||||
else
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->AudioClockDIV.SBC_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
case PER_CLK_PARALLEL:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL0.PARALLEL_CLK_SEL == 2)
|
||||
PerClock = (system_get_AUPLLCLK()/2) / (SYSTEM->BlockClockDIV1.PARALLEL_CLK_DIV + 1);
|
||||
else if (SYSTEM->ClockSEL0.PARALLEL_CLK_SEL == 1)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->BlockClockDIV1.PARALLEL_CLK_DIV + 1);
|
||||
else if (SYSTEM->ClockSEL0.PARALLEL_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->BlockClockDIV1.PARALLEL_CLK_DIV + 1);
|
||||
|
||||
}break;
|
||||
|
||||
case PER_CLK_SPDIF:
|
||||
{
|
||||
/* clock from SPLL */
|
||||
if (SYSTEM->ClockSEL1.SPDIF_CLK_SEL == 2)
|
||||
PerClock = (system_get_AUPLLCLK()/2) / (SYSTEM->AudioClockDIV.SPDIF_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL1.SPDIF_CLK_SEL == 1)
|
||||
PerClock = (system_get_SPLLCLK()/2) / (SYSTEM->AudioClockDIV.SPDIF_CLK_DIV + 1);
|
||||
else if(SYSTEM->ClockSEL1.SPDIF_CLK_SEL == 0)
|
||||
PerClock = system_get_CORE_HSCLK() / (SYSTEM->AudioClockDIV.SPDIF_CLK_DIV + 1);
|
||||
}break;
|
||||
|
||||
default: PerClock = 0;break;
|
||||
}
|
||||
return PerClock;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn system_dmac_request_id_config
|
||||
*
|
||||
* @brief dmac request id config.
|
||||
*
|
||||
* @param fe_source : dma request source.
|
||||
* @param fe_id : user select request id.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void system_dmac_request_id_config(dmac_request_source_t fe_source, dmac_request_id_t fe_id)
|
||||
{
|
||||
uint8_t lu8_RequestSource;
|
||||
uint8_t lu8_RequestIDReg;
|
||||
|
||||
lu8_RequestIDReg = fe_source / 4;
|
||||
lu8_RequestSource = fe_source % 4;
|
||||
|
||||
SYSTEM->DmacHsCfg[lu8_RequestIDReg] &= ~(0x1F << lu8_RequestSource * 8);
|
||||
SYSTEM->DmacHsCfg[lu8_RequestIDReg] |= fe_id << (lu8_RequestSource * 8);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn system_delay_us
|
||||
*
|
||||
* @brief system delay unit us, use system free counter.
|
||||
*
|
||||
* @param fu32_delay: delay unit us.
|
||||
*/
|
||||
__RAM_CODE void system_delay_us(uint32_t fu32_delay)
|
||||
{
|
||||
uint32_t backups_tack = FREE_COUNTER_VALUE;
|
||||
|
||||
while(backups_tack - FREE_COUNTER_VALUE < fu32_delay);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn system_cache_enable
|
||||
*
|
||||
* @brief cache enable.
|
||||
*
|
||||
* @param invalid_ram : true: invalidating the cache SRAM.
|
||||
* false: hold the cache SRAM.
|
||||
*/
|
||||
__RAM_CODE void system_cache_enable(bool invalid_ram)
|
||||
{
|
||||
uint32_t prim;
|
||||
|
||||
// manul enable the cache and invalidating the SRAM
|
||||
prim = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
switch (*(volatile uint32_t *)(FLASH_CACHE_BASE + 4) & 0x03) {
|
||||
case 0x01: // enabling
|
||||
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x03) != 0x02);
|
||||
case 0x02: // enabled
|
||||
break;
|
||||
case 0x03: // disabling
|
||||
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x03) != 0x00);
|
||||
default:
|
||||
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x38;
|
||||
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3c;
|
||||
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x10) == 0);
|
||||
if(invalid_ram)
|
||||
{
|
||||
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3e;
|
||||
while((*(volatile uint32_t *)FLASH_CACHE_BASE) & 0x02);
|
||||
}
|
||||
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3d;
|
||||
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+4)) & 0x03) != 0x02);
|
||||
break;
|
||||
}
|
||||
if(!prim)
|
||||
{
|
||||
__enable_irq();
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn system_cache_disable
|
||||
*
|
||||
* @brief cache disable.
|
||||
*
|
||||
*/
|
||||
__RAM_CODE void system_cache_disable(void)
|
||||
{
|
||||
uint32_t prim;
|
||||
|
||||
// manul disable the cache
|
||||
prim = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x3c;
|
||||
*(volatile uint32_t *)FLASH_CACHE_BASE = 0x38;
|
||||
while(((*(volatile uint32_t *)(FLASH_CACHE_BASE+0x04)) & 0x03) != 0x00);
|
||||
|
||||
if(!prim)
|
||||
{
|
||||
__enable_irq();
|
||||
}
|
||||
}
|
||||
|
||||
void system_prevent_sleep_set(uint32_t type)
|
||||
{
|
||||
GLOBAL_INT_DISABLE();
|
||||
system_prevent_sleep_label |= type;
|
||||
GLOBAL_INT_RESTORE();
|
||||
}
|
||||
|
||||
void system_prevent_sleep_clear(uint32_t type)
|
||||
{
|
||||
GLOBAL_INT_DISABLE();
|
||||
system_prevent_sleep_label &= (~type);
|
||||
GLOBAL_INT_RESTORE();
|
||||
}
|
||||
|
||||
uint32_t system_prevent_sleep_get(void)
|
||||
{
|
||||
return system_prevent_sleep_label;
|
||||
}
|
||||
|
||||
void system_reset(void)
|
||||
{
|
||||
__disable_irq();
|
||||
// reboot
|
||||
iwdt_Init_t iwdt_env;
|
||||
iwdt_env.iwdt_Count = 300;
|
||||
iwdt_env.iwdt_Timeout = 10;
|
||||
iwdt_env.iwdt_int_Enable = WDT_INT_DISABLE;
|
||||
iwdt_init(iwdt_env);
|
||||
iwdt_Enable();
|
||||
// ool_write(PMU_REG_IOLDO1_CTRL_0, (ool_read(PMU_REG_IOLDO1_CTRL_0) & 0xf0) | 0x01);
|
||||
while(1);
|
||||
}
|
||||
|
||||
/* ====================================================================================================== */
|
||||
/* =============================== GLOBAL interrupt controller ===================================== */
|
||||
/* ====================================================================================================== */
|
||||
void GLOBAL_INT_START(void)
|
||||
{
|
||||
__asm (
|
||||
"CPSIE i \n"
|
||||
);
|
||||
}
|
||||
|
||||
void GLOBAL_INT_STOP(void)
|
||||
{
|
||||
__asm (
|
||||
"CPSID i \n"
|
||||
);
|
||||
}
|
||||
|
||||
__RAM_CODE void CPU_SR_Restore(uint32_t org_base_pri)
|
||||
{
|
||||
__asm (
|
||||
"MSR BASEPRI, %[org]\n"
|
||||
:
|
||||
: [org]"r"(org_base_pri)
|
||||
:
|
||||
);
|
||||
}
|
||||
|
||||
__RAM_CODE uint32_t CPU_SR_Save(uint32_t new_basepri)
|
||||
{
|
||||
uint32_t old_basepri;
|
||||
__asm (
|
||||
"MRS R4, BASEPRI\n"
|
||||
"MSR BASEPRI, %[new]\n"
|
||||
"MOV %[old], R4 \n"
|
||||
: [old]"=r"(old_basepri)
|
||||
: [new]"r"(new_basepri)
|
||||
: "r4"
|
||||
);
|
||||
return old_basepri;
|
||||
}
|
||||
1755
fr3092_mcu/components/drivers/device/fr30xx/system_fr30xx.h
Normal file
1755
fr3092_mcu/components/drivers/device/fr30xx/system_fr30xx.h
Normal file
File diff suppressed because it is too large
Load Diff
81
fr3092_mcu/components/drivers/device/fr30xx/trim_fr30xx.c
Normal file
81
fr3092_mcu/components/drivers/device/fr30xx/trim_fr30xx.c
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file trim_fr30xx.c
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Config Chip analog/digit/RF using Chip Probing(CP) and
|
||||
Final Test(FT) trim parameters.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "fr30xx.h"
|
||||
#include "crc32.h"
|
||||
|
||||
static struct_ADC_Cal_Param_t ADC_Cal_Param;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn trim_cp_config
|
||||
*
|
||||
* @brief Config Chip analog/digit/RF using Chip Probing(CP) trim parameters.
|
||||
*
|
||||
* @param none.
|
||||
* @return none.
|
||||
*/
|
||||
void trim_cp_config(void)
|
||||
{
|
||||
/* ------------------------- */
|
||||
/* FT trim */
|
||||
/* ------------------------- */
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn trim_ft_config
|
||||
*
|
||||
* @brief Config Chip analog/digit/RF using Final Test(FT) trim parameters.
|
||||
*
|
||||
* @param none.
|
||||
* @return none.
|
||||
*/
|
||||
void trim_ft_config(void)
|
||||
{
|
||||
uint32_t FT_CRC;
|
||||
struct_FT_Trim_t FT_Trim_Param;
|
||||
|
||||
flash_OTP_read(QSPI0,0x1000,sizeof(FT_Trim_Param),(uint8_t*)&FT_Trim_Param);
|
||||
|
||||
FT_CRC = crc32(0x00000000, (void *)&FT_Trim_Param, (uint32_t)&FT_Trim_Param.u32_crc - (uint32_t)&FT_Trim_Param);
|
||||
|
||||
if(FT_CRC == FT_Trim_Param.u32_crc)
|
||||
{
|
||||
if(FT_Trim_Param.u16_Version == 0xA001)
|
||||
{
|
||||
/* configure IOLDO output to 3.3v */
|
||||
ool_write(PMU_REG_IOLDO1_CTRL_0, 0x0a);
|
||||
/* config SBG */
|
||||
ool_write(PMU_REG_SBG_CFG,FT_Trim_Param.u16_ioldo);
|
||||
|
||||
//Get the adc calibration value
|
||||
ADC_Cal_Param.u16_slopeA = FT_Trim_Param.Param.V1.u16_SlopeA;
|
||||
ADC_Cal_Param.u16_slopeB = FT_Trim_Param.Param.V1.u16_SlopeB;
|
||||
ADC_Cal_Param.s32_constantA = FT_Trim_Param.Param.V1.s32_ConstantA;
|
||||
ADC_Cal_Param.s32_constantB = FT_Trim_Param.Param.V1.s32_ConstantB;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn trim_get_adc_cal_param
|
||||
*
|
||||
* @brief get adc ft calibration param.
|
||||
*/
|
||||
struct_ADC_Cal_Param_t *trim_get_adc_cal_param(void)
|
||||
{
|
||||
return &ADC_Cal_Param;
|
||||
}
|
||||
|
||||
93
fr3092_mcu/components/drivers/device/fr30xx/trim_fr30xx.h
Normal file
93
fr3092_mcu/components/drivers/device/fr30xx/trim_fr30xx.h
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file trim_fr30xx.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Header file of trim HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __TRIM_FR1010_H__
|
||||
#define __TRIM_FR1010_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup trim_Parameter_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ trim Parameter Section Start ################################ */
|
||||
|
||||
/*--------------------------------------------------*/
|
||||
/* CP trim Parameter */
|
||||
/*--------------------------------------------------*/
|
||||
typedef __PACKED_STRUCT
|
||||
{
|
||||
/* --------- vendor-specific --------- */
|
||||
volatile uint32_t Version : 2;
|
||||
volatile uint32_t BBG_CODE : 5;
|
||||
volatile uint32_t SYSLDO_CODE : 4;
|
||||
volatile uint32_t BFB_CODE : 3;
|
||||
volatile uint32_t DLDO_CODE : 3;
|
||||
volatile uint32_t IOLDO_CODE : 3;
|
||||
volatile uint32_t SBG_CODE : 4;
|
||||
volatile uint32_t PKVDD_CODE : 4;
|
||||
volatile uint32_t rsv_0 : 2;
|
||||
volatile uint32_t LOT_ID : 10;
|
||||
volatile uint32_t WaferID : 5;
|
||||
volatile uint32_t XY : 16;
|
||||
volatile uint32_t Year_Week : 14;
|
||||
|
||||
volatile uint32_t rsv_1 : 20;
|
||||
/* --------- vendor-specific END--------- */
|
||||
}struct_CP_Trim_t;
|
||||
|
||||
/*--------------------------------------------------*/
|
||||
/* FT trim Parameter */
|
||||
/*--------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t u16_Version;
|
||||
uint16_t u16_ioldo;
|
||||
|
||||
union {
|
||||
struct{
|
||||
int32_t s32_ConstantA;
|
||||
int32_t s32_ConstantB;
|
||||
uint16_t u16_SlopeA;
|
||||
uint16_t u16_SlopeB;
|
||||
}V1;
|
||||
|
||||
}Param;
|
||||
|
||||
uint32_t u32_crc;
|
||||
|
||||
}struct_FT_Trim_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t u16_slopeA;
|
||||
uint32_t u16_slopeB;
|
||||
int32_t s32_constantA;
|
||||
int32_t s32_constantB;
|
||||
}struct_ADC_Cal_Param_t;
|
||||
|
||||
/* ################################ trim Parameter Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
void trim_cp_config(void);
|
||||
void trim_ft_config(void);
|
||||
|
||||
bool ft_trim_get_param(void);
|
||||
struct_ADC_Cal_Param_t *trim_get_adc_cal_param(void);
|
||||
#endif // __TRIM_FR1010_H__
|
||||
252
fr3092_mcu/components/drivers/peripheral/Inc/driver_adc.h
Normal file
252
fr3092_mcu/components/drivers/peripheral/Inc/driver_adc.h
Normal file
@ -0,0 +1,252 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_adc.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of ADC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_ADC_H__
|
||||
#define __DRIVER_ADC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup ADC_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
#define ADC_MAX_CHANNELS (8)
|
||||
#define ADC_MAX_IO_INPUT_MAP (4)
|
||||
|
||||
/* Control Register for ADC */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_ConvertEN : 1;
|
||||
uint32_t ADC_Reset : 1;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t ADC_SoftTrigger : 1;
|
||||
uint32_t rsv_1 : 28;
|
||||
}REG_ADC_Control_t;
|
||||
|
||||
/* Config Register for ADC */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_ChannelMax : 4;
|
||||
uint32_t ADC_ConvertMode : 1;
|
||||
uint32_t ADC_TriggerMode : 1;
|
||||
uint32_t ADC_FIFO_EN : 1;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t ADC_SoftTriggerChannel : 4;
|
||||
uint32_t rsv_1 : 20;
|
||||
}REG_ADC_Config_t;
|
||||
|
||||
/* Timing Register for ADC */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Clock_DIV : 8;
|
||||
uint32_t rsv_0 : 8;
|
||||
uint32_t SetupCycle : 6;
|
||||
uint32_t SampleCycle : 5;
|
||||
uint32_t TimeoutCycle : 5;
|
||||
}REG_ADC_Timing_t;
|
||||
|
||||
/* ----------------------------------------------*/
|
||||
/* ADC Registers */
|
||||
/* ----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_ADC_Control_t Control; /* Offset 0x00 */
|
||||
volatile REG_ADC_Config_t Config; /* Offset 0x04 */
|
||||
volatile REG_ADC_Timing_t Timing; /* Offset 0x08 */
|
||||
volatile uint32_t rsv_0; /* Offset 0x0C */
|
||||
volatile uint32_t rsv_1; /* Offset 0x10 */
|
||||
volatile uint32_t rsv_2; /* Offset 0x14 */
|
||||
volatile uint32_t Channel_Status; /* Offset 0x18 */
|
||||
volatile uint32_t rsv_3; /* Offset 0x1C */
|
||||
volatile uint32_t ADC_INT_Enble; /* Offset 0x20 */
|
||||
volatile uint32_t ADC_INT_Status; /* Offset 0x24 */
|
||||
volatile uint32_t ADC_INT_Raws; /* Offset 0x28 */
|
||||
volatile uint32_t ACT0; /* Offset 0x2C */
|
||||
volatile uint32_t ACT1; /* Offset 0x30 */
|
||||
volatile uint32_t ChannelMap[8]; /* Offset 0x34 ~ 0x50 */
|
||||
volatile uint32_t rsv0[8];
|
||||
volatile uint32_t ChannelData[8]; /* Offset 0x74 ~ 0x90 */
|
||||
}struct_ADC_t;
|
||||
|
||||
#define ADC ((struct_ADC_t *)ADC_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup ADC_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization, Config Section Start ################################ */
|
||||
|
||||
#define ADC_INT_CONVERT_ERR (0x10)
|
||||
#define ADC_INT_CHANNEL_VALID (0x08)
|
||||
|
||||
#define ADC_ACT0_REF_1P2V (0x1A036)
|
||||
#define ADC_ACT0_REF_IOLDO (0xDA036)
|
||||
|
||||
#define ADC_ACT1_VBE_EN (0x02)
|
||||
#define ADC_ACT1_VBAT_EN (0x04)
|
||||
#define ADC_ACT1_IS (0x40)
|
||||
|
||||
/* ADC interrupt index */
|
||||
typedef enum
|
||||
{
|
||||
ADC_CHANNEL_MAP_PMU_P4, /* PMU P4 */
|
||||
ADC_CHANNEL_MAP_PMU_P5, /* PMU P5 */
|
||||
ADC_CHANNEL_MAP_PMU_P6, /* PMU P6 */
|
||||
ADC_CHANNEL_MAP_PMU_P7, /* PMU P7 */
|
||||
ADC_CHANNEL_MAP_VBE, /* VBE */
|
||||
ADC_CHANNEL_MAP_VBAT, /* 1/4 VBAT */
|
||||
}enum_ADC_Channel_Map_t;
|
||||
|
||||
/* ADC interrupt index */
|
||||
typedef enum
|
||||
{
|
||||
ADC_FIFO_EMPTY = 0x01,
|
||||
ADC_FIFO_FULL = 0x02,
|
||||
ADC_FIFO_ALMOST_FULL = 0x04,
|
||||
ADC_CHANNEL_VALID = 0x08,
|
||||
ADC_ERR = 0x10,
|
||||
}enum_ADC_int_index_t;
|
||||
|
||||
/* ADC convert mode */
|
||||
typedef enum
|
||||
{
|
||||
ADC_SINGLE_MODE,
|
||||
ADC_LOOP_MODE,
|
||||
}enum_ADC_convert_mode_t;
|
||||
|
||||
/* ADC FIFO mode */
|
||||
typedef enum
|
||||
{
|
||||
ADC_FIFO_DISABLE,
|
||||
ADC_FIFO_ENABLE,
|
||||
}enum_ADC_FIFO_EN_t;
|
||||
|
||||
/* ADC convert mode */
|
||||
typedef enum
|
||||
{
|
||||
ADC_HARDWARE_TRIGGER,
|
||||
ADC_SOFTWARE_TRIGGER,
|
||||
}enum_ADC_trigger_mode_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ADC_REF_IOLDO,
|
||||
ADC_REF_1P2V,
|
||||
}enum_ADC_reference_t;
|
||||
|
||||
/**
|
||||
* @brief hard trigger config definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Convert_Mode; /*!< Specifies the convert mode, single or loop.
|
||||
This parameter can be a value @ref enum_ADC_convert_mode_t */
|
||||
|
||||
uint32_t ADC_Channel_Max; /*!< Specifies the number of Maximum conversion channels.
|
||||
This parameter can be a value between 1 ~ 8 */
|
||||
}struct_HardTriggerConfig_t;
|
||||
|
||||
/**
|
||||
* @brief ADC Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Reference; /*!< Specifies the reference source of ADC.
|
||||
This parameter can be a value @ref enum_ADC_reference_t */
|
||||
|
||||
uint32_t ADC_TriggerMode; /*!< Specifies the number of ADC Trigger Mode.
|
||||
This parameter can be a value @ref enum_ADC_trigger_mode_t */
|
||||
|
||||
struct_HardTriggerConfig_t HardTriggerConfig; /*!< ADC hard trigger config parameters */
|
||||
|
||||
}adc_InitConfig_t;
|
||||
|
||||
/* ################################ Initialization, Config Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* ADC hard Convert Enable/Disable */
|
||||
#define __ADC_CONVERT_ENABLE() (ADC->Control.ADC_ConvertEN = 1)
|
||||
#define __ADC_CONVERT_DISABLE() (ADC->Control.ADC_ConvertEN = 0)
|
||||
|
||||
/* ADC State machine Reset */
|
||||
#define __ADC_RESET() (ADC->Control.ADC_Reset = 1)
|
||||
/* soft trigger convert */
|
||||
#define __ADC_SOFT_TRIGGER() (ADC->Control.ADC_SoftTrigger = 1)
|
||||
/* set soft trigger channel */
|
||||
#define __ADC_SET_SOFT_TRIGGER_CHANNEL(__CHANNEL__) (ADC->Config.ADC_SoftTriggerChannel = __CHANNEL__)
|
||||
|
||||
/* Set max channel */
|
||||
#define __ADC_SET_MAX_CHANNEL(__MAXCH__) (ADC->Config.ADC_ChannelMax = __MAXCH__)
|
||||
/* Set convert mode */
|
||||
#define __ADC_SET_CONVERT_MODE(__MODE__) (ADC->Config.ADC_ConvertMode = __MODE__)
|
||||
/* Set trigger mode */
|
||||
#define __ADC_SET_TRIGGER_MODE(__MODE__) (ADC->Config.ADC_TriggerMode = __MODE__)
|
||||
|
||||
/* set adc clock div */
|
||||
#define __ADC_SET_CLK_DIV(__DIV__) (ADC->Timing.Clock_DIV = __DIV__)
|
||||
/* set convert setup/sample/timout cycle */
|
||||
#define __ADC_SET_SETUP_CYCLE(__CYCLE__) (ADC->Timing.SetupCycle = __CYCLE__)
|
||||
#define __ADC_SET_SAMPLE_CYCLE(__CYCLE__) (ADC->Timing.SampleCycle = __CYCLE__)
|
||||
#define __ADC_SET_TIMEOUT_CYCLE(__CYCLE__) (ADC->Timing.TimeoutCycle = __CYCLE__)
|
||||
|
||||
/* Get ADC Channel status */
|
||||
#define __ADC_GET_CHANNEL_STATUS() (ADC->Channel_Status)
|
||||
|
||||
/* ADC interrupt enable/disable */
|
||||
#define __ADC_INT_ENABLE(__INDEX__) (ADC->ADC_INT_Enble |= __INDEX__)
|
||||
#define __ADC_INT_DISABLE(__INDEX__) (ADC->ADC_INT_Enble &= ~(__INDEX__))
|
||||
#define __ADC_GET_INT_STATUS() (ADC->ADC_INT_Raws)
|
||||
|
||||
/* Set channel map */
|
||||
#define __ADC_SET_CHANNEL_MAP(__CHANNEL__, __MAP__) (ADC->ChannelMap[__CHANNEL__] = __MAP__)
|
||||
/* Get channel data */
|
||||
#define __ADC_GET_CHANNEL_DATA(__CHANNEL__) (ADC->ChannelData[__CHANNEL__])
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* adc_init */
|
||||
void adc_init(adc_InitConfig_t InitConfig);
|
||||
|
||||
/* adc_convert_start/stop */
|
||||
void adc_convert_start(void);
|
||||
void adc_convert_start_IT(void);
|
||||
void adc_convert_stop(void);
|
||||
|
||||
void adc_channel_valid_int_enable(void);
|
||||
void adc_channel_valid_int_dsiable(void);
|
||||
|
||||
/* adc_soft_trigger_convert */
|
||||
void adc_soft_trigger_convert(uint8_t fu8_Channel);
|
||||
|
||||
/* adc_get_channel_valid_status */
|
||||
bool adc_get_channel_valid_status(uint8_t fu8_Channel);
|
||||
/* adc_get_channel_data */
|
||||
uint32_t adc_get_channel_data(uint8_t fu8_Channel);
|
||||
|
||||
/* adc_set_channel_maping */
|
||||
void adc_set_channel_maping(uint8_t fu8_Channel, enum_ADC_Channel_Map_t fe_Map);
|
||||
|
||||
#endif
|
||||
148
fr3092_mcu/components/drivers/peripheral/Inc/driver_aes.h
Normal file
148
fr3092_mcu/components/drivers/peripheral/Inc/driver_aes.h
Normal file
@ -0,0 +1,148 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_aes.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of aes module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_AES_H__
|
||||
#define __DRIVER_AES_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup AES_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/*AES CTRL REG 0x40*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t START : 1;//AES work enable,this bit only maintain active for one cycle and is cleared automatically
|
||||
uint32_t KEY_INT_EN : 1;//whehter key expand finish interrupt enable
|
||||
uint32_t DATA_INT_EN : 1;//whether encrypt or decrypt finish interrupt enable
|
||||
uint32_t CBC : 1;//CBC mode or ECB mode
|
||||
uint32_t KEY_LEN : 2;//00->128bit 01->192bit 10->256bit 11->reserved
|
||||
uint32_t OPCODE : 2;//00->encrypt 01->decrypt 10->keyexpand 11->reserved
|
||||
uint32_t ENDIAN_SEL : 1;//0->small endian for data register 1->big endian for data register
|
||||
uint32_t RSV : 23;
|
||||
} Bits;
|
||||
} REG_AES_CTRL_t;
|
||||
|
||||
/*AES STATE REG 0x44*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t BUSY : 1;//busy indication bit
|
||||
uint32_t KEY_INT_FLAG : 1;//key expand finish interrupt flag
|
||||
uint32_t DATA_INT_FLAG : 1;//data finish interrupt flag
|
||||
uint32_t RSV : 29;
|
||||
} Bits;
|
||||
} REG_AES_STATE_t;
|
||||
|
||||
/* ------------------------------------------------*/
|
||||
/* AES Register */
|
||||
/* ------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t DATAIN_0; /* Offset 0x00 */
|
||||
volatile uint32_t DATAIN_1; /* Offset 0x04 */
|
||||
volatile uint32_t DATAIN_2; /* Offset 0x08 */
|
||||
volatile uint32_t DATAIN_3; /* Offset 0x0C */
|
||||
volatile uint32_t KEY_0; /* Offset 0x10 */
|
||||
volatile uint32_t KEY_1; /* Offset 0x14 */
|
||||
volatile uint32_t KEY_2; /* Offser 0x18 */
|
||||
volatile uint32_t KEY_3; /* Offser 0x1c */
|
||||
volatile uint32_t KEY_4; /* Offser 0x20 */
|
||||
volatile uint32_t KEY_5; /* Offser 0x24 */
|
||||
volatile uint32_t KEY_6; /* Offser 0x28 */
|
||||
volatile uint32_t KEY_7; /* Offset 0x2C */
|
||||
volatile uint32_t IV_0; /* Offset 0x30 */
|
||||
volatile uint32_t IV_1; /* Offset 0x34 */
|
||||
volatile uint32_t IV_2; /* Offset 0x38 */
|
||||
volatile uint32_t IV_3; /* Offset 0x3C */
|
||||
volatile REG_AES_CTRL_t AES_CTRL; /* Offset 0x40 */
|
||||
volatile REG_AES_STATE_t AES_STATE; /* Offset 0x44 */
|
||||
volatile uint32_t DATAOUT_0; /* Offset 0x48 */
|
||||
volatile uint32_t DATAOUT_1; /* Offset 0x4C */
|
||||
volatile uint32_t DATAOUT_2; /* Offset 0x50 */
|
||||
volatile uint32_t DATAOUT_3; /* Offset 0x54 */
|
||||
}struct_SEC_AES_t;
|
||||
|
||||
#define SEC_AES ((struct_SEC_AES_t *)(SEC_BASE))
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup AES_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization Config Section Start ################################ */
|
||||
|
||||
#define AES_OPCODE_ENCRYPT (0)
|
||||
#define AES_OPCODE_DECRYPT (1)
|
||||
#define AES_OPCODE_KEY_EXPAND (2)
|
||||
|
||||
#define AES_CBC_MODE_DISABLE (0)
|
||||
#define AES_CBC_MODE_ENABLE (1)
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AES_ECB_128,
|
||||
AES_ECB_192,
|
||||
AES_ECB_256,
|
||||
|
||||
AES_CBC_128,
|
||||
AES_CBC_192,
|
||||
AES_CBC_256,
|
||||
}enum_AES_MODE_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AES_SMALL_ENDIAN, /* small endian for data register */
|
||||
AES_BIG_ENDIAN, /* big endian for data register */
|
||||
}enum_ENDIAN_t;
|
||||
|
||||
/* ################################ Initialization Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* get aes status */
|
||||
#define __AES_IS_BUSY() (SEC_AES->AES_STATE.Bits.BUSY)
|
||||
/* set aes opcode */
|
||||
#define __AES_SET_OPCODE(__OPCODE__) (SEC_AES->AES_CTRL.Bits.OPCODE = __OPCODE__)
|
||||
/* aes work start */
|
||||
#define __AES_WORK_START() (SEC_AES->AES_CTRL.Bits.START = 1)
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* AES config */
|
||||
void aes_config(enum_AES_MODE_t fe_Mode, enum_ENDIAN_t fe_Endian);
|
||||
|
||||
/* AES set key/iv */
|
||||
void aes_set_encrypt_key(uint8_t *key);
|
||||
void aes_set_encrypt_iv(uint8_t *iv);
|
||||
|
||||
/* AES encrypt/decrypt */
|
||||
void aes_encrypt(uint8_t *fp_Data_In, uint32_t fu32_Size, uint8_t *fp_Data_Out);
|
||||
void aes_decrypt(uint8_t *fp_Data_In, uint32_t fu32_Size, uint8_t *fp_Data_Out);
|
||||
|
||||
#endif
|
||||
466
fr3092_mcu/components/drivers/peripheral/Inc/driver_blend.h
Normal file
466
fr3092_mcu/components/drivers/peripheral/Inc/driver_blend.h
Normal file
@ -0,0 +1,466 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_blend.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of BLEND module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_BLEND_H__
|
||||
#define __DRIVER_BLEND_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup BLEND_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/*BLEND CTRL REG 0x00*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t BLEND_EN : 1;
|
||||
uint32_t RGB0_FF_RST : 1;
|
||||
uint32_t RGB1_FF_RST : 1;
|
||||
uint32_t MASK_FF_RST : 1;
|
||||
uint32_t ORGB_FF_RST : 1;
|
||||
uint32_t RSV : 27;
|
||||
} Bits;
|
||||
} REG_BLEND_CTRL_t;
|
||||
|
||||
/*BLEND CONFIG REG 0x04*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t BLEND_MODE : 2;
|
||||
uint32_t RGB0_FORMAT : 2;
|
||||
uint32_t RGB1_FORMAT : 2;
|
||||
uint32_t ORGB_FORMAT : 2;
|
||||
uint32_t ORGB_MODE : 1;
|
||||
uint32_t RGB0_CAL_EN : 1;
|
||||
uint32_t RGB1_CAL_EN : 1;
|
||||
uint32_t MASK_CAL_EN : 1;
|
||||
uint32_t R_MUL_TC_EN : 1;
|
||||
uint32_t G_MUL_TC_EN : 1;
|
||||
uint32_t B_MUL_TC_EN : 1;
|
||||
uint32_t A_MUL_TC_EN : 1;
|
||||
uint32_t ORGB_565_R_TC_EN : 1;
|
||||
uint32_t ORGB_565_G_TC_EN : 1;
|
||||
uint32_t ORGB_565_B_TC_EN : 1;
|
||||
uint32_t ORGB_332_R_TC_EN : 1;
|
||||
uint32_t ORGB_332_G_TC_EN : 1;
|
||||
uint32_t ORGB_332_B_TC_EN : 1;
|
||||
uint32_t RSV : 10;
|
||||
} Bits;
|
||||
} REG_BLEND_CFG_t;
|
||||
|
||||
|
||||
/*BLEND PIXEL REG 0x08*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t PIXEL_ALPHA : 8;
|
||||
uint32_t PIXEL_DATA : 24;
|
||||
} Bits;
|
||||
} REG_BLEND_PIXEL_t;
|
||||
|
||||
/*BLEND SRC ALPHA REG 0x0C*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t SRC_ALPHA : 8;
|
||||
uint32_t RSV : 24;
|
||||
} Bits;
|
||||
} REG_BLEND_SRC_ALPHA_t;
|
||||
|
||||
/*BLEND DMAC REG 0x10*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t RGB0_DMA_EN : 1;
|
||||
uint32_t RGB1_DMA_EN : 1;
|
||||
uint32_t MASK_DMA_EN : 1;
|
||||
uint32_t ORGB_DMA_EN : 1;
|
||||
uint32_t RSV : 28;
|
||||
} Bits;
|
||||
} REG_BLEND_DMAC_t;
|
||||
|
||||
/*BLEND INFIFO0 THRESHOLD CONTROL REG 0x14*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t RGB0_ALEMPTY_THR : 5;
|
||||
uint32_t RSV : 3;
|
||||
uint32_t RGB0_ALFULL_THR : 5;
|
||||
uint32_t RSV2 : 3;
|
||||
uint32_t RGB0_DMA_THR : 5;
|
||||
uint32_t RSV3 : 11;
|
||||
} Bits;
|
||||
} REG_BLEND_INFIFO0_THR_CTL_t;
|
||||
|
||||
/*BLEND INFIFO1 THRESHOLD CONTROL REG 0x18*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t RGB1_ALEMPTY_THR : 5;
|
||||
uint32_t RSV : 3;
|
||||
uint32_t RGB1_ALFULL_THR : 5;
|
||||
uint32_t RSV2 : 3;
|
||||
uint32_t RGB1_DMA_THR : 5;
|
||||
uint32_t RSV3 : 11;
|
||||
} Bits;
|
||||
} REG_BLEND_INFIFO1_THR_CTL_t;
|
||||
|
||||
/*BLEND INFIFOMASK THRESHOLD CONTROL REG 0x1C*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t MASK_ALEMPTY_THR : 5;
|
||||
uint32_t RSV : 3;
|
||||
uint32_t MASK_ALFULL_THR : 5;
|
||||
uint32_t RSV2 : 3;
|
||||
uint32_t MASK_DMA_THR : 5;
|
||||
uint32_t RSV3 : 11;
|
||||
} Bits;
|
||||
} REG_BLEND_INFIFOMASK_THR_CTL_t;
|
||||
|
||||
/*BLEND OUTFIFO THRESHOLD CONTROL REG 0x20*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t ORGB_ALEMPTY_THR : 5;
|
||||
uint32_t RSV1 : 3;
|
||||
uint32_t ORGB_ALFULL_THR : 5;
|
||||
uint32_t RSV2 : 3;
|
||||
uint32_t ORGB_DMA_THR : 5;
|
||||
uint32_t RSV3 : 3;
|
||||
uint32_t ORGB_FLOW_THR : 5;
|
||||
uint32_t RSV4 : 3;
|
||||
} Bits;
|
||||
} REG_BLEND_OUTFIFO_THR_CTL_t;
|
||||
|
||||
/*BLEND INTERRUPT CONTROL REG 0x24*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t RGB0_EMPTY_INT_EN : 1;
|
||||
uint32_t RGB0_ALEMPTY_INT_EN : 1;
|
||||
uint32_t RGB0_FULL_INT_EN : 1;
|
||||
uint32_t RGB0_ALFULL_INT_EN : 1;
|
||||
uint32_t RSV1 : 4;
|
||||
uint32_t RGB1_EMPTY_INT_EN : 1;
|
||||
uint32_t RGB1_ALEMPTY_INT_EN : 1;
|
||||
uint32_t RGB1_FULL_INT_EN : 1;
|
||||
uint32_t RGB1_ALFULL_INT_EN : 1;
|
||||
uint32_t RSV2 : 4;
|
||||
uint32_t MASK_EMPTY_INT_EN : 1;
|
||||
uint32_t MASK_ALEMPTY_INT_EN : 1;
|
||||
uint32_t MASK_FULL_INT_EN : 1;
|
||||
uint32_t MASK_ALFULL_INT_EN : 1;
|
||||
uint32_t RSV3 : 4;
|
||||
uint32_t ORGB_EMPTY_INT_EN : 1;
|
||||
uint32_t ORGB_ALEMPTY_INT_EN : 1;
|
||||
uint32_t ORGB_FULL_INT_EN : 1;
|
||||
uint32_t ORGB_ALFULL_INT_EN : 1;
|
||||
uint32_t RSV4 : 4;
|
||||
} Bits;
|
||||
} REG_BLEND_ISR_CTL_t;
|
||||
|
||||
/*BLEND INTERRUPT STATUS REG 0x28*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t RGB0_EMPTY_INT_STS : 1;
|
||||
uint32_t RGB0_ALEMPTY_INT_STS : 1;
|
||||
uint32_t RGB0_FULL_INT_STS : 1;
|
||||
uint32_t RGB0_ALFULL_INT_STS : 1;
|
||||
uint32_t RSV1 : 4;
|
||||
uint32_t RGB1_EMPTY_INT_STS : 1;
|
||||
uint32_t RGB1_ALEMPTY_INT_STS : 1;
|
||||
uint32_t RGB1_FULL_INT_STS : 1;
|
||||
uint32_t RGB1_ALFULL_INT_STS : 1;
|
||||
uint32_t RSV2 : 4;
|
||||
uint32_t MASK_EMPTY_INT_STS : 1;
|
||||
uint32_t MASK_ALEMPTY_INT_STS : 1;
|
||||
uint32_t MASK_FULL_INT_STS : 1;
|
||||
uint32_t MASK_ALFULL_INT_STS : 1;
|
||||
uint32_t RSV3 : 4;
|
||||
uint32_t ORGB_EMPTY_INT_STS : 1;
|
||||
uint32_t ORGB_ALEMPTY_INT_STS : 1;
|
||||
uint32_t ORGB_FULL_INT_STS : 1;
|
||||
uint32_t ORGB_ALFULL_INT_STS : 1;
|
||||
uint32_t RSV4 : 4;
|
||||
} Bits;
|
||||
} REG_BLEND_ISR_STATUS_t;
|
||||
|
||||
/*BLEND FIFO STATUS REG 0x2c*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t RGB0_EMPTY : 1;
|
||||
uint32_t RGB0_ALEMPTY : 1;
|
||||
uint32_t RGB0_FULL : 1;
|
||||
uint32_t RGB0_ALFULL : 1;
|
||||
uint32_t RSV1 : 4;
|
||||
uint32_t RGB1_EMPTY : 1;
|
||||
uint32_t RGB1_ALEMPTY : 1;
|
||||
uint32_t RGB1_FULL : 1;
|
||||
uint32_t RGB1_ALFULL : 1;
|
||||
uint32_t RSV2 : 4;
|
||||
uint32_t MASK_EMPTY : 1;
|
||||
uint32_t MASK_ALEMPTY : 1;
|
||||
uint32_t MASK_FULL : 1;
|
||||
uint32_t MASK_ALFULL : 1;
|
||||
uint32_t RSV3 : 4;
|
||||
uint32_t ORGB_EMPTY : 1;
|
||||
uint32_t ORGB_ALEMPTY : 1;
|
||||
uint32_t ORGB_FULL : 1;
|
||||
uint32_t ORGB_ALFULL : 1;
|
||||
uint32_t RSV4 : 4;
|
||||
} Bits;
|
||||
} REG_BLEND_FIFO_STATUS_t;
|
||||
|
||||
|
||||
/*BLEND FIFO COUNT REG 0x38*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t RGB0_FF_COUNT : 6;
|
||||
uint32_t RSV1 : 2;
|
||||
uint32_t RGB1_FF_COUNT : 6;
|
||||
uint32_t RSV2 : 2;
|
||||
uint32_t MASK_FF_COUNT : 6;
|
||||
uint32_t RSV3 : 2;
|
||||
uint32_t ORGB_FF_COUNT : 6;
|
||||
uint32_t RSV : 2;
|
||||
} Bits;
|
||||
} REG_BLEND_FIFO_COUNT_t;
|
||||
|
||||
/*BLEND PIXEL_THR REG 0x3C*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t O565_B_THR : 3;
|
||||
uint32_t O565_G_THR : 2;
|
||||
uint32_t O565_R_THR : 3;
|
||||
uint32_t RSV2 : 8;
|
||||
uint32_t O332_B_THR : 6;
|
||||
uint32_t O332_G_THR : 5;
|
||||
uint32_t O332_R_THR : 5;
|
||||
} Bits;
|
||||
} REG_BLEND_PIXEL_THR_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
REG_BLEND_CTRL_t CTRL; /* Offset 0x00 */
|
||||
REG_BLEND_CFG_t CONFIG; /* Offset 0x04 */
|
||||
REG_BLEND_PIXEL_t PIXEL; /* Offset 0x08*/
|
||||
REG_BLEND_SRC_ALPHA_t SRC_ALPHA; /* Offset 0x0c */
|
||||
REG_BLEND_DMAC_t DMAC; /* Offset 0x10 */
|
||||
REG_BLEND_INFIFO0_THR_CTL_t INFIFO0_THR_CTL; /* Offset 0x14 */
|
||||
REG_BLEND_INFIFO1_THR_CTL_t INFIFO1_THR_CTL; /* Offset 0x18 */
|
||||
REG_BLEND_INFIFOMASK_THR_CTL_t INFIFOMASK_THR_CTL; /* Offset 0x1C */
|
||||
REG_BLEND_OUTFIFO_THR_CTL_t OUTFIFO_THR_CTL; /* Offset 0x20 */
|
||||
REG_BLEND_ISR_CTL_t ISR_CTL; /* Offset 0x24 */
|
||||
REG_BLEND_ISR_STATUS_t ISR_STATUS; /* Offset 0x28 */
|
||||
REG_BLEND_FIFO_STATUS_t FIFO_STATUS; /* Offset 0x2C */
|
||||
uint32_t RGB0_DATA; /* Offset 0x30 */
|
||||
uint32_t RGB1_DATA; /* Offset 0x34 */
|
||||
REG_BLEND_FIFO_COUNT_t FIFO_COUNT; /* Offset 0x38 */
|
||||
REG_BLEND_PIXEL_THR_t PIXEL_THR; /* Offset 0x3c */
|
||||
}struct_BLEND_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t MASK_DATA;/* Offset 0x00 */
|
||||
uint32_t ORGB_DATA;/* Offset 0x04 */
|
||||
}struct_BLEND_AHB1_t;
|
||||
|
||||
#define BLEND_AHB0 ((volatile struct_BLEND_t *)BLEND_AHB0_BASE)
|
||||
#define BLEND_AHB1 ((volatile struct_BLEND_AHB1_t *)BLEND_AHB1_BASE)
|
||||
|
||||
|
||||
#define BLEND_RGB0_EMPTY_INT_STS (1<<0)
|
||||
#define BLEND_RGB0_ALEMPTY_INT_STS (1<<1)
|
||||
#define BLEND_RGB1_EMPTY_INT_STS (1<<8)
|
||||
#define BLEND_RGB1_ALEMPTY_INT_STS (1<<9)
|
||||
#define BLEND_MASK_EMPTY_INT_STS (1<<16)
|
||||
#define BLEND_MASK_ALEMPTY_INT_STS (1<<17)
|
||||
#define BLEND_ORGB_FULL_INT_STS (1<<26)
|
||||
#define BLEND_ORGB_ALFULL_INT_STS (1<<27)
|
||||
|
||||
|
||||
typedef enum{
|
||||
BLEND_RGB_TYPE_888 = 0,
|
||||
BLEND_RGB_TYPE_565 = 1,
|
||||
}enum_RGB_TYPE_t;
|
||||
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INRGB0_FORMAT : 2;
|
||||
uint32_t INRGB1_FORMAT : 2;
|
||||
uint32_t OUTRGB_FORMAT : 2;
|
||||
uint32_t SRC_IS_PURE : 1;
|
||||
uint32_t SRC_ALPHA : 8;
|
||||
uint32_t BLEND_MODE : 2;
|
||||
uint32_t DMA_IN_EN : 1;
|
||||
uint32_t DMA_OUT_EN : 1;
|
||||
uint32_t ISR_EN : 1;
|
||||
uint32_t MASK_CAL_EN : 1;
|
||||
uint32_t RSV : 11;
|
||||
} Bits;
|
||||
}struct_init_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t ALEMPTY_THR : 6;
|
||||
uint32_t DMA_THR : 6;
|
||||
uint32_t RSV : 20;
|
||||
} Bits;
|
||||
}struct_INFIFO_THR_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t ALFULL_THR : 6;
|
||||
uint32_t DMA_THR : 6;
|
||||
uint32_t RSV : 20;
|
||||
} Bits;
|
||||
}struct_OUTFIFO_THR_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t PIXEL : 24;
|
||||
uint32_t RSV : 8;
|
||||
} Bits;
|
||||
}struct_PURE_t;
|
||||
|
||||
typedef struct __BLEND_HandleTypeDef
|
||||
{
|
||||
struct_init_t BlendInit;
|
||||
|
||||
struct_PURE_t Pure;
|
||||
|
||||
struct_INFIFO_THR_t Infifo0Thr;
|
||||
|
||||
struct_INFIFO_THR_t Infifo1Thr;
|
||||
|
||||
struct_INFIFO_THR_t InfifoMaskThr;
|
||||
|
||||
struct_OUTFIFO_THR_t OutfifoThr;
|
||||
|
||||
uint32_t *SrcRgb; /*!< BLEND parameters in interrupt */
|
||||
uint32_t SrcSize;
|
||||
uint32_t *BackRgb;
|
||||
uint32_t BackSize;
|
||||
uint32_t *MaskRgb;
|
||||
uint32_t MaskSize;
|
||||
uint32_t *OutRgb;
|
||||
uint32_t OutSize;
|
||||
uint8_t gMaskRem;
|
||||
uint32_t PixelCount;
|
||||
|
||||
uint32_t SrcInIndex; /*!< BLEND RGB data index in handle */
|
||||
uint32_t BackInIndex;
|
||||
uint32_t MaskInIndex;
|
||||
uint32_t DataOutIndex;
|
||||
|
||||
void (*Callback)(struct __BLEND_HandleTypeDef *hblend); /*!< BLEND RGB out finish Callback */
|
||||
|
||||
}BLEND_HandleTypeDef;
|
||||
|
||||
typedef struct{
|
||||
uint8_t *SrcRgb;
|
||||
uint8_t *BackRgb;
|
||||
uint8_t *MaskRgb;
|
||||
uint8_t *OutRgb;
|
||||
uint32_t PixelCount;
|
||||
}BLEND_DataParam_t;
|
||||
|
||||
|
||||
|
||||
#define __BLEND_INT_RGB0_FIFO_EMPTY_ENABLE() (BLEND_AHB0->ISR_CTL.Bits.RGB0_EMPTY_INT_EN = 1)
|
||||
#define __BLEND_INT_RGB1_FIFO_EMPTY_ENABLE() (BLEND_AHB0->ISR_CTL.Bits.RGB1_EMPTY_INT_EN = 1)
|
||||
#define __BLEND_INT_MASK_FIFO_EMPTY_ENABLE() (BLEND_AHB0->ISR_CTL.Bits.MASK_EMPTY_INT_EN = 1)
|
||||
#define __BLEND_INT_ORGB_FIFO_ALFULL_ENABLE() (BLEND_AHB0->ISR_CTL.Bits.ORGB_ALFULL_INT_EN = 1)
|
||||
|
||||
#define __BLEND_INT_RGB0_FIFO_EMPTY_DISABLE() (BLEND_AHB0->ISR_CTL.Bits.RGB0_EMPTY_INT_EN = 0)
|
||||
#define __BLEND_INT_RGB1_FIFO_EMPTY_DISABLE() (BLEND_AHB0->ISR_CTL.Bits.RGB1_EMPTY_INT_EN = 0)
|
||||
#define __BLEND_INT_MASK_FIFO_EMPTY_DISABLE() (BLEND_AHB0->ISR_CTL.Bits.MASK_EMPTY_INT_EN = 0)
|
||||
#define __BLEND_INT_ORGB_FIFO_ALFULL_DISABLE() (BLEND_AHB0->ISR_CTL.Bits.ORGB_ALFULL_INT_EN = 0)
|
||||
|
||||
#define __RGB0_FIFO_IS_EMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.RGB0_EMPTY == 1)
|
||||
#define __RGB0_FIFO_IS_ALEMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.RGB0_ALEMPTY == 1)
|
||||
#define __RGB0_FIFO_IS_FULL() (BLEND_AHB0->FIFO_STATUS.Bits.RGB0_FULL == 1)
|
||||
#define __RGB0_FIFO_IS_ALFULL() (BLEND_AHB0->FIFO_STATUS.Bits.RGB0_ALFULL == 1)
|
||||
#define __RGB1_FIFO_IS_EMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.RGB1_EMPTY == 1)
|
||||
#define __RGB1_FIFO_IS_ALEMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.RGB1_ALEMPTY == 1)/*set almost empty to do*/
|
||||
#define __RGB1_FIFO_IS_FULL() (BLEND_AHB0->FIFO_STATUS.Bits.RGB1_FULL == 1)
|
||||
#define __RGB1_FIFO_IS_ALFULL() (BLEND_AHB0->FIFO_STATUS.Bits.RGB1_ALFULL == 1)
|
||||
#define __MASK_FIFO_IS_EMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.MASK_EMPTY == 1)
|
||||
#define __MASK_FIFO_IS_ALEMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.MASK_ALEMPTY == 1)
|
||||
#define __MASK_FIFO_IS_FULL() (BLEND_AHB0->FIFO_STATUS.Bits.MASK_FULL == 1)
|
||||
#define __MASK_FIFO_IS_ALFULL() (BLEND_AHB0->FIFO_STATUS.Bits.MASK_ALFULL == 1)
|
||||
#define __ORGB_FIFO_IS_FULL() (BLEND_AHB0->FIFO_STATUS.Bits.ORGB_FULL == 1)
|
||||
#define __ORGB_FIFO_IS_ALFULL() (BLEND_AHB0->FIFO_STATUS.Bits.ORGB_ALFULL == 1)
|
||||
#define __ORGB_FIFO_IS_EMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.ORGB_EMPTY == 1)
|
||||
#define __ORGB_FIFO_IS_ALEMPTY() (BLEND_AHB0->FIFO_STATUS.Bits.ORGB_ALEMPTY == 1)
|
||||
#define __ORGB_FIFO_IS_HALF_FULL() (BLEND_AHB0->FIFO_STATUS.Bits.ORGB_HALF_FULL == 1)
|
||||
|
||||
/* Initialize the blend module */
|
||||
void blend_init(BLEND_HandleTypeDef *hblend);
|
||||
/* Start blend to mix pixel without isr */
|
||||
void blend_start(BLEND_HandleTypeDef *hblend, BLEND_DataParam_t DataParam);
|
||||
/* Start blend to mix pixel with isr */
|
||||
void blend_start_IT(BLEND_HandleTypeDef *hblend, BLEND_DataParam_t DataParam);
|
||||
/* Blend module handle function in the blend isr */
|
||||
void blend_IRQHandler(BLEND_HandleTypeDef *hblend);
|
||||
|
||||
#endif
|
||||
154
fr3092_mcu/components/drivers/peripheral/Inc/driver_cache.h
Normal file
154
fr3092_mcu/components/drivers/peripheral/Inc/driver_cache.h
Normal file
@ -0,0 +1,154 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_cache.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of cache HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_CACHE_H__
|
||||
#define __DRIVER_CACHE_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup CACHE_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Enabling Register 0 */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ENABLE : 1;
|
||||
uint32_t FLUSH : 1;
|
||||
uint32_t BANK_FLUSH : 1;
|
||||
uint32_t rsv : 29;
|
||||
} REG_Enabling_t;
|
||||
|
||||
/* Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BIST_ACTIVE : 1;
|
||||
uint32_t BIST_END : 1;
|
||||
uint32_t BIST_OUT : 1;
|
||||
uint32_t WR_MODE : 2;
|
||||
uint32_t INST_POL : 1;
|
||||
uint32_t INST_ACTIVE : 1;
|
||||
uint32_t ADDR_RANG0_EN : 1;
|
||||
uint32_t ADDR_RANG0_POL : 1;
|
||||
uint32_t ADDR_RANG1_EN : 1;
|
||||
uint32_t ADDR_RANG1_POL : 1;
|
||||
uint32_t ADDR_RANG2_EN : 1;
|
||||
uint32_t ADDR_RANG2_POL : 1;
|
||||
uint32_t ADDR_RANG3_EN : 1;
|
||||
uint32_t ADDR_RANG3_POL : 1;
|
||||
uint32_t rsv : 17;
|
||||
} REG_Cache_Control_t;
|
||||
|
||||
/* Address Range 0 defination*/
|
||||
typedef struct {
|
||||
uint32_t bank :16;
|
||||
uint32_t mask :16;
|
||||
} REG_ADDR_RANGE0_t;
|
||||
|
||||
/* Address Range 1 defination*/
|
||||
typedef struct {
|
||||
uint32_t rsv_0 :8;
|
||||
uint32_t bank :8;
|
||||
uint32_t rsv_1 :8;
|
||||
uint32_t mask :8;
|
||||
} REG_ADDR_RANGE1_t;
|
||||
|
||||
/* Address Range 2 defination*/
|
||||
typedef struct {
|
||||
uint32_t rsv_0 :8;
|
||||
uint32_t bank :8;
|
||||
uint32_t rsv_1 :8;
|
||||
uint32_t mask :8;
|
||||
} REG_ADDR_RANGE2_t;
|
||||
|
||||
/* Address Range 3 defination*/
|
||||
typedef struct {
|
||||
uint32_t rsv_0 :8;
|
||||
uint32_t bank :8;
|
||||
uint32_t rsv_1 :8;
|
||||
uint32_t mask :8;
|
||||
} REG_ADDR_RANGE3_t;
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* CACHE Register */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_Enabling_t ENABLING; /* Offset 0x00 */
|
||||
volatile REG_Cache_Control_t CTRL; /* Offset 0x04 */
|
||||
volatile uint32_t BANK_FLUSH_ADDR; /* Offset 0x08 */
|
||||
volatile uint32_t BANK_FLUSH_MASK; /* Offset 0x0C */
|
||||
volatile REG_ADDR_RANGE0_t ADDR_RANGE0; /* Offset 0x10 */
|
||||
volatile REG_ADDR_RANGE1_t ADDR_RANGE1; /* Offset 0x14 */
|
||||
volatile REG_ADDR_RANGE2_t ADDR_RANGE2; /* Offset 0x18 */
|
||||
volatile REG_ADDR_RANGE3_t ADDR_RANGE3; /* Offset 0x1C */
|
||||
}struct_CACHE_t;
|
||||
|
||||
#define CACHE ((struct_CACHE_t *)AHBC_CACHE_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initializatio Config Section Start ################################ */
|
||||
|
||||
typedef enum {
|
||||
CACHE_WR_BYPASS,
|
||||
CACHE_WR_FLUSH,
|
||||
CACHE_WR_WRITE_THROUGH,
|
||||
} enum_CACHE_WR_MODE_T;
|
||||
|
||||
typedef enum {
|
||||
CACHE_POL_NON_CACHABLE,
|
||||
CACHE_POL_CACHABLE,
|
||||
} enum_CACHE_POL_T;
|
||||
|
||||
/* ################################ Initializatio Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define __CACHE_ENABLE(__CACHE__) (__CACHE__->ENABLING.ENABLE = 1)
|
||||
#define __CACHE_DISABLE(__CACHE__) (__CACHE__->ENABLING.ENABLE = 0)
|
||||
|
||||
#define __CACHE_FLUSH(__CACHE__) (__CACHE__->ENABLING.FLUSH = 1)
|
||||
|
||||
#define __CACHE_BANK_FLUSH(__CACHE__) (__CACHE__->ENABLING.BANK_FLUSH = 1)
|
||||
#define __CACHE_BANK_FLUSH_DONE(__CACHE__) (__CACHE__->ENABLING.BANK_FLUSH == 0)
|
||||
#define __CACHE_BANK_FLUSH_ADDR_SET(__CACHE__, addr) (__CACHE__->BANK_FLUSH_ADDR = addr)
|
||||
#define __CACHE_BANK_FLUSH_MASK_SET(__CACHE__, mask) (__CACHE__->BANK_FLUSH_MASK = mask)
|
||||
|
||||
#define __CACHE_BIST_START(__CACHE__) (__CACHE__->CTRL.BIST_ACTIVE = 1)
|
||||
#define __CACHE_BIST_END(__CACHE__) (__CACHE__->CTRL.BIST_END == 1)
|
||||
#define __CACHE_BIST_PASS(__CACHE__) (__CACHE__->CTRL.BIST_OUT == 0)
|
||||
|
||||
#define __CACHE_WR_MODE_SET(__CACHE__, mode) (__CACHE__->CTRL.WR_MODE = mode)
|
||||
#define __CACHE_WR_MODE_GET(__CACHE__, mode) (__CACHE__->CTRL.WR_MODE)
|
||||
|
||||
#define __CACHE_ADDR_RANGEx_ENABLE(__CACHE__, x) (__CACHE__->CTRL.ADDR_RANG##x##_EN = 1)
|
||||
#define __CACHE_ADDR_RANGEx_DISABLE(__CACHE__, x) (__CACHE__->CTRL.ADDR_RANG##x##_EN = 0)
|
||||
#define __CACHE_ADDR_RANGEx_POL_SET(__CACHE__, x, __pol) (__CACHE__->CTRL.ADDR_RANG##x##_POL = __pol)
|
||||
|
||||
#define __CACHE_ADDR_RANGEx_BANK_SET(__CACHE__, x, __bank) (__CACHE__->ADDR_RANGE##x.bank = (__bank))
|
||||
#define __CACHE_ADDR_RANGEx_MASK_SET(__CACHE__, x, __mask) (__CACHE__->ADDR_RANGE##x.mask = (__mask))
|
||||
|
||||
#endif // __DRIVER_CACHE_H__
|
||||
|
||||
127
fr3092_mcu/components/drivers/peripheral/Inc/driver_cali.h
Normal file
127
fr3092_mcu/components/drivers/peripheral/Inc/driver_cali.h
Normal file
@ -0,0 +1,127 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_cali.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Header file of Calibration HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_CALI_H__
|
||||
#define __DRIVER_CALI_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup CALI_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EN : 1;
|
||||
uint32_t UP_MODE : 1;
|
||||
uint32_t rsv_0 : 30;
|
||||
}REG_CALI_CTRL_t;
|
||||
|
||||
/* ------------------------------------------------*/
|
||||
/* UART Register */
|
||||
/* ------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_CALI_CTRL_t CTRL; /* Offset 0x00 */
|
||||
volatile uint32_t DONE; /* Offset 0x04 */
|
||||
volatile uint32_t INT_EN; /* Offset 0x08 */
|
||||
volatile uint32_t INT_STA; /* Offset 0x0C */
|
||||
volatile uint32_t LEN; /* Offset 0x10 */
|
||||
volatile uint32_t RESULT; /* Offset 0x14 */
|
||||
}struct_CALI_t;
|
||||
|
||||
#define CALI ((struct_CALI_t *)CALIB_BASE)
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CALI_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization Config Section Start ################################ */
|
||||
|
||||
/* FCR BIT position */
|
||||
typedef enum
|
||||
{
|
||||
CALI_UP_MODE_KEEP = 0x00, /*!< return the oldest unread data */
|
||||
CALI_UP_MODE_NORMAL = 0x01, /*!< return the latest calibration result */
|
||||
}enum_CALI_UP_MODE_t;
|
||||
|
||||
/*
|
||||
* @brief Calibration handle Structure definition
|
||||
*/
|
||||
typedef struct __Cali_HandleTypeDef
|
||||
{
|
||||
enum_CALI_UP_MODE_t mode; /*!< Calibration result fetch mode */
|
||||
uint16_t rc_cnt; /*!< how many RC cycles used to calibrate */
|
||||
|
||||
void (*DoneCallback)(struct __Cali_HandleTypeDef *hcali, /*!< Calibration Done Callback */
|
||||
uint32_t result);
|
||||
}CALI_HandleTypeDef;
|
||||
|
||||
/* ################################ InitializationbConfig Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* __CALI_ENABLE */
|
||||
/* __CALI_DISABLE */
|
||||
#define __CALI_ENABLE() (CALI->CTRL.EN = 0x01)
|
||||
#define __CALI_DISABLE() (CALI->CTRL.EN = 0x00)
|
||||
|
||||
/* __CALI_UP_MODE_SET */
|
||||
#define __CALI_UP_MODE_SET(m) (CALI->CTRL.UP_MODE = m)
|
||||
|
||||
/* __CALI_INT_ENABLE */
|
||||
/* __CALI_INT_DISABLE */
|
||||
#define __CALI_INT_ENABLE() (CALI->INT_EN = 0x01)
|
||||
#define __CALI_INT_DISABLE() (CALI->INT_EN = 0x00)
|
||||
|
||||
/* __CALI_INT_CLR */
|
||||
#define __CALI_INT_CLR() (CALI->INT_STA = 0x01)
|
||||
|
||||
/* __CALI_IS_DONE */
|
||||
#define __CALI_IS_DONE() (CALI->DONE == 0x01)
|
||||
|
||||
/* __CALI_CNT_SET */
|
||||
#define __CALI_CNT_SET(v) (CALI->LEN = v)
|
||||
|
||||
/* __CALI_RESULT_GET */
|
||||
#define __CALI_RESULT_GET() (CALI->RESULT)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* cali_IRQHandler */
|
||||
void cali_IRQHandler(CALI_HandleTypeDef *hcali);
|
||||
|
||||
/* cali_init */
|
||||
void cali_init(CALI_HandleTypeDef *hcali);
|
||||
|
||||
/* cali_start */
|
||||
uint32_t cali_start(CALI_HandleTypeDef *hcali);
|
||||
/* cali_start_IT */
|
||||
void cali_start_IT(CALI_HandleTypeDef *hcali);
|
||||
|
||||
/* cali_stop */
|
||||
void cali_stop(CALI_HandleTypeDef *hcali);
|
||||
|
||||
/* cali_calc_rc_freq */
|
||||
uint32_t cali_calc_rc_freq(CALI_HandleTypeDef *hcali, uint32_t result);
|
||||
|
||||
#endif // __DRIVER_CALI_H__
|
||||
1000
fr3092_mcu/components/drivers/peripheral/Inc/driver_can.h
Normal file
1000
fr3092_mcu/components/drivers/peripheral/Inc/driver_can.h
Normal file
File diff suppressed because it is too large
Load Diff
1511
fr3092_mcu/components/drivers/peripheral/Inc/driver_codec.h
Normal file
1511
fr3092_mcu/components/drivers/peripheral/Inc/driver_codec.h
Normal file
File diff suppressed because it is too large
Load Diff
121
fr3092_mcu/components/drivers/peripheral/Inc/driver_common.h
Normal file
121
fr3092_mcu/components/drivers/peripheral/Inc/driver_common.h
Normal file
@ -0,0 +1,121 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_common.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2020
|
||||
* @brief driver common header file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020 AisinoChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_COMMON_H__
|
||||
#define __DRIVER_COMMON_H__
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ======================= Use Uart to Debug print ======================== */
|
||||
/* ================================================================================ */
|
||||
#define UART_DEBUG_ENABLE (1)
|
||||
|
||||
#if (UART_DEBUG_ENABLE == 1)
|
||||
#define freq_printf printf
|
||||
#else
|
||||
#define freq_printf(format, ...) ((void)0)
|
||||
#endif
|
||||
|
||||
#include "driver_aes.h"
|
||||
|
||||
#include "driver_blend.h"
|
||||
|
||||
#include "driver_cache.h"
|
||||
|
||||
#include "driver_cali.h"
|
||||
|
||||
#include "driver_can.h"
|
||||
|
||||
#include "driver_codec.h"
|
||||
|
||||
#include "driver_crc.h"
|
||||
|
||||
#include "driver_dma.h"
|
||||
|
||||
#include "driver_efuse.h"
|
||||
|
||||
#include "driver_flash.h"
|
||||
|
||||
#include "driver_frspim.h"
|
||||
|
||||
#include "driver_gpio.h"
|
||||
|
||||
#include "driver_i2s.h"
|
||||
|
||||
#include "driver_i2c.h"
|
||||
|
||||
#include "driver_ipc.h"
|
||||
|
||||
#include "driver_iir.h"
|
||||
|
||||
#include "driver_fft.h"
|
||||
|
||||
#include "driver_mp3_dec.h"
|
||||
|
||||
#include "driver_parallel_interface.h"
|
||||
|
||||
#include "driver_pdm.h"
|
||||
|
||||
#include "driver_pmu.h"
|
||||
#include "driver_pmu_iwdt.h"
|
||||
#include "driver_pmu_rtc.h"
|
||||
|
||||
#include "driver_pwm.h"
|
||||
|
||||
#include "driver_qspi.h"
|
||||
|
||||
#include "driver_adc.h"
|
||||
|
||||
#include "driver_sbc_enc.h"
|
||||
|
||||
#include "driver_sbc_dec.h"
|
||||
|
||||
#include "driver_sd.h"
|
||||
|
||||
#include "driver_sd_card.h"
|
||||
|
||||
#include "driver_sd_mmc.h"
|
||||
|
||||
#include "driver_sha.h"
|
||||
|
||||
#include "driver_spi.h"
|
||||
|
||||
#include "driver_spdif.h"
|
||||
|
||||
#include "driver_tick.h"
|
||||
|
||||
#include "driver_timer.h"
|
||||
|
||||
#include "driver_trigfunc.h"
|
||||
|
||||
#include "driver_trng.h"
|
||||
|
||||
#include "driver_uart.h"
|
||||
|
||||
#include "driver_yuv2rgb.h"
|
||||
|
||||
#include "usb_core.h"
|
||||
#include "usb_dev.h"
|
||||
|
||||
#include "usb_audio.h"
|
||||
#include "usb_cdc.h"
|
||||
#include "usb_hid.h"
|
||||
#include "usb_winusb.h"
|
||||
#include "usb_mass_storage.h"
|
||||
|
||||
#endif
|
||||
79
fr3092_mcu/components/drivers/peripheral/Inc/driver_crc.h
Normal file
79
fr3092_mcu/components/drivers/peripheral/Inc/driver_crc.h
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_crc.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Header file of CRC module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_CRC_H__
|
||||
#define __DRIVER_CRC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup CRC_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
#define CRC_START (0x01)
|
||||
#define CRC_CLEAR (0x08)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CRC_CTRL; /* Offset 0x00 */
|
||||
volatile uint32_t CRC_STATUS; /* Offset 0x04 */
|
||||
volatile uint32_t CRC_FIFO_DATA; /* Offset 0x08*/
|
||||
volatile uint32_t CRC_RESULT; /* Offset 0x0C */
|
||||
}struct_CRC_t;
|
||||
|
||||
#define CRC ((struct_CRC_t *)CRC_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization_Config Section Start ################################ */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CRC_INITVALUE_0 = 0x08u,
|
||||
CRC_INITVALUE_1 = 0x18u,
|
||||
|
||||
CRC_MULTINOMIAL_16_1021 = 0x02u,
|
||||
CRC_MULTINOMIAL_16_8005 = 0x04u,
|
||||
CRC_MULTINOMIAL_32 = 0x06u,
|
||||
}HAL_CRC_Accumulate;
|
||||
|
||||
typedef enum
|
||||
{ // bit wide | polynomial | init value | Result XOR value | Input invert | Output invert
|
||||
CRC8 = (CRC_INITVALUE_0), // 8 | 07 | 00 | 00 | fasle | fasle
|
||||
CRC16_CCITT_FALSE = (CRC_INITVALUE_1 | CRC_MULTINOMIAL_16_1021), // 16 | 1021 | FFFF | FFFF | fasle | fasle
|
||||
CRC16_XMODEM = (CRC_INITVALUE_0 | CRC_MULTINOMIAL_16_1021), // 16 | 1021 | 0000 | 0000 | fasle | fasle
|
||||
CRC32_MPEG2 = (CRC_INITVALUE_1 | CRC_MULTINOMIAL_32), // 32 | 04C11DB7 | FFFFFFFF | 00000000 | fasle | fasle
|
||||
}enum_CRC_MODE_SEL_t;
|
||||
|
||||
/* ################################ Initialization_Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/* Initial crc with initial value and mode */
|
||||
void crc_init(enum_CRC_MODE_SEL_t fe_crc_mode);
|
||||
|
||||
/* CRC Calculate */
|
||||
uint32_t crc_Calculate(uint8_t *fp_Data, uint32_t fu32_size);
|
||||
|
||||
#endif
|
||||
482
fr3092_mcu/components/drivers/peripheral/Inc/driver_dma.h
Normal file
482
fr3092_mcu/components/drivers/peripheral/Inc/driver_dma.h
Normal file
@ -0,0 +1,482 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_dma.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_DMA_H__
|
||||
#define __DRIVER_DMA_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
#define DMA_CHANNELS_MAX (8)
|
||||
|
||||
|
||||
/** @addtogroup DMA_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Linked List Pointer Register for Channel */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LMS : 2; // Starting Address In Memory.
|
||||
uint32_t LOC : 30; // List Master Select.
|
||||
}REG_LLP_t;
|
||||
|
||||
/* Control Register for Channel */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t INT_EN : 1; // Interrupt Enable.
|
||||
uint32_t DST_TR_WIDTH : 3; // Destination Transfer Width.
|
||||
uint32_t SRC_TR_WIDTH : 3; // Source Transfer Width.
|
||||
uint32_t DINC : 2; // Destination Address Increment.
|
||||
uint32_t SINC : 2; // Source Address Increment.
|
||||
uint32_t DEST_MSIZE : 3; // Destination Burst Transaction Length.
|
||||
uint32_t SRC_MSIZE : 3; // Source Burst Transaction Length.
|
||||
uint32_t SRC_GATHER_EN : 1; // Source gather enable.
|
||||
uint32_t DST_SCATTER_EN : 1; // Destination scatter enable.
|
||||
uint32_t rsv_0 : 1; //
|
||||
uint32_t TT_FC : 3; // Transfer Type and Flow Control.
|
||||
uint32_t DMS : 2; // Destination Master Select.
|
||||
uint32_t SMS : 2; // Source Master Select.
|
||||
uint32_t LLP_DST_EN : 1; // Block chaining is enabled on the destination
|
||||
uint32_t LLP_SRC_EN : 1; // Block chaining is enabled on the source
|
||||
uint32_t rsv_1 : 3; //
|
||||
}REG_CTL1_t;
|
||||
|
||||
/* Control Register for Channel */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BLOCK_TS : 24; // Block Transfer Size.
|
||||
uint32_t rsv_0 : 7;
|
||||
uint32_t DONE : 1; // Done bit.
|
||||
}REG_CTL2_t;
|
||||
|
||||
/* Configuration Register for Channel */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t rsv_0 : 5;
|
||||
uint32_t CH_PRIOR : 3; // Channel Priority.
|
||||
uint32_t CH_SUSP : 1; // Channel Suspend.
|
||||
uint32_t FIFO_EMPTY : 1; // Channel FIFO status.
|
||||
uint32_t HS_SEL_DST : 1; // Destination Software or Hardware Handshaking Select.
|
||||
uint32_t HS_SEL_SRC : 1; // Source Software or Hardware Handshaking Select.
|
||||
uint32_t LOCK_CH_L : 2;
|
||||
uint32_t LOCK_B_L : 2;
|
||||
uint32_t LOCK_CH : 1;
|
||||
uint32_t LOCK_B : 1;
|
||||
uint32_t DST_HS_POL : 1; // Destination Handshaking Interface Polarity.
|
||||
uint32_t SRC_HS_POL : 1; // Source Handshaking Interface Polarity.
|
||||
uint32_t MAX_ABRST : 10;
|
||||
uint32_t RELOAD_SRC : 1; // Automatic Source Reload.
|
||||
uint32_t RELOAD_DST : 1;
|
||||
}REG_CFG1_t;
|
||||
|
||||
/* Configuration Register for Channel */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FCMODE : 1;
|
||||
uint32_t FIFO_MODE : 1;
|
||||
uint32_t PROTCTL : 3;
|
||||
uint32_t DS_UPD_EN : 1;
|
||||
uint32_t SS_UPD_EN : 1;
|
||||
uint32_t SRC_PER : 4;
|
||||
uint32_t DEST_PER : 4;
|
||||
uint32_t rsv_0 : 17;
|
||||
}REG_CFG2_t;
|
||||
|
||||
/* Source Gath Register for Channel */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SGI : 20;
|
||||
uint32_t SGC : 12;
|
||||
}REG_SGR_t;
|
||||
|
||||
/* Destination Scatter Register for Channel */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DSI : 20;
|
||||
uint32_t DSC : 12;
|
||||
}REG_DSR_t;
|
||||
|
||||
/* -------------------------------------------*/
|
||||
/* DAM Channel Register */
|
||||
/* -------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t SAR; // offset 0x00. Source Address for Channel
|
||||
volatile uint32_t rsv_0; // offset 0x04
|
||||
volatile uint32_t DAR; // offset 0x08. Destination Address Register for Channel
|
||||
volatile uint32_t rsv_1; // offset 0x0C
|
||||
volatile REG_LLP_t LLP; // offset 0x10. Linked List Pointer Register for Channel
|
||||
volatile uint32_t rsv_2; // offset 0x14
|
||||
volatile REG_CTL1_t CTL1; // offset 0x18. Control Register for Channel
|
||||
volatile REG_CTL2_t CTL2; // offset 0x1C. Control Register for Channel
|
||||
volatile uint32_t SSTAT; // offset 0x20. Source Status Register for Channel
|
||||
volatile uint32_t rsv_3; // offset 0x24
|
||||
volatile uint32_t DSTAT; // offset 0x28. Destination Status Register for Channel
|
||||
volatile uint32_t rsv_4; // offset 0x2C
|
||||
volatile uint32_t SSTATAR; // offset 0x30. Source Status Address Register for Channel
|
||||
volatile uint32_t rsv_5; // offset 0x34
|
||||
volatile uint32_t DSTATAR; // offset 0x38. Destination Status Address Register for Channel
|
||||
volatile uint32_t rsv_6; // offset 0x3C
|
||||
volatile REG_CFG1_t CFG1; // offset 0x40. Configuration Register for Channel
|
||||
volatile REG_CFG2_t CFG2; // offset 0x44. Configuration Register for Channel
|
||||
volatile REG_SGR_t SGR; // offset 0x48. Source Gather Register for Channel
|
||||
volatile uint32_t rsv_7; // offset 0x4C
|
||||
volatile REG_DSR_t DSR; // offset 0x50. Destination Scatter Register for Channel
|
||||
volatile uint32_t rsv_8; // offset 0x54
|
||||
}dma_channel_t;
|
||||
|
||||
|
||||
/* -------------------------------------------*/
|
||||
/* DAM Interrupt Register */
|
||||
/* -------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t RawTfr;
|
||||
volatile uint32_t rsv_0;
|
||||
volatile uint32_t RawBlock;
|
||||
volatile uint32_t rsv_1;
|
||||
volatile uint32_t RawSrcTran;
|
||||
volatile uint32_t rsv_2;
|
||||
volatile uint32_t RawDstDran;
|
||||
volatile uint32_t rsv_3;
|
||||
volatile uint32_t RawErr;
|
||||
volatile uint32_t rsv_4;
|
||||
volatile uint32_t StatusTfr;
|
||||
volatile uint32_t rsv_5;
|
||||
volatile uint32_t StatusBlock;
|
||||
volatile uint32_t rsv_6;
|
||||
volatile uint32_t StatusSrcTran;
|
||||
volatile uint32_t rsv_7;
|
||||
volatile uint32_t StatusDstTran;
|
||||
volatile uint32_t rsv_8;
|
||||
volatile uint32_t StatusErr;
|
||||
volatile uint32_t rsv_9;
|
||||
volatile uint32_t MaskTfr;
|
||||
volatile uint32_t rsv_10;
|
||||
volatile uint32_t MaskBlock;
|
||||
volatile uint32_t rsv_11;
|
||||
volatile uint32_t MaskSrcTran;
|
||||
volatile uint32_t rsv_12;
|
||||
volatile uint32_t MaskDstTran;
|
||||
volatile uint32_t rsv_13;
|
||||
volatile uint32_t MaskErr;
|
||||
volatile uint32_t rsv_14;
|
||||
volatile uint32_t ClearTfr;
|
||||
volatile uint32_t rsv_15;
|
||||
volatile uint32_t ClearBlock;
|
||||
volatile uint32_t rsv_16;
|
||||
volatile uint32_t ClearSrcTran;
|
||||
volatile uint32_t rsv_17;
|
||||
volatile uint32_t ClearDstTran;
|
||||
volatile uint32_t rsv_18;
|
||||
volatile uint32_t ClearErr;
|
||||
volatile uint32_t rsv_19;
|
||||
volatile uint32_t StatusInt;
|
||||
volatile uint32_t rsv_20;
|
||||
}dma_interrupt_t;
|
||||
|
||||
|
||||
/* ------------------------------------------------*/
|
||||
/* DAM Software Handshake Register */
|
||||
/* ------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t ReqSrcReg;
|
||||
volatile uint32_t rsv_0;
|
||||
volatile uint32_t ReqDstReg;
|
||||
volatile uint32_t rsv_1;
|
||||
volatile uint32_t SglRqSrcReg;
|
||||
volatile uint32_t rsv_2;
|
||||
volatile uint32_t SglRqDstReg;
|
||||
volatile uint32_t rsv_3;
|
||||
volatile uint32_t LstSrcReg;
|
||||
volatile uint32_t rsv_4;
|
||||
volatile uint32_t LstDstReg;
|
||||
volatile uint32_t rsv_5;
|
||||
}dma_software_handshake_t;
|
||||
|
||||
|
||||
/* -------------------------------------------*/
|
||||
/* DAM Miscellaneous Register */
|
||||
/* -------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t DMA_EN : 1;
|
||||
volatile uint32_t rsv_0 : 31;
|
||||
}REG_DmaCfg_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_DmaCfg_t DmaCfgReg;
|
||||
volatile uint32_t rsv_0;
|
||||
volatile uint32_t ChEnReg;
|
||||
}dma_miscellaneous_t;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
dma_channel_t Channels[DMA_CHANNELS_MAX];
|
||||
dma_interrupt_t Int_Reg;
|
||||
dma_software_handshake_t Software_Handshake_Reg;
|
||||
dma_miscellaneous_t Misc_Reg;
|
||||
}struct_DMA_t;
|
||||
|
||||
#define DMA0 ((struct_DMA_t *)DMAC0_BASE)
|
||||
#define DMA1 ((struct_DMA_t *)DMAC1_BASE)
|
||||
/* ################################ Register Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup DMA_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization, Config Section Start ################################ */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DMA_Channel0,
|
||||
DMA_Channel1,
|
||||
DMA_Channel2,
|
||||
DMA_Channel3,
|
||||
DMA_Channel4,
|
||||
DMA_Channel5,
|
||||
DMA_Channel6,
|
||||
DMA_Channel7,
|
||||
}dma_channel_select_t;
|
||||
|
||||
enum dma_data_flow_t
|
||||
{
|
||||
DMA_M2M_DMAC, // Memory to Memory and Flow Controller is dmac
|
||||
DMA_M2P_DMAC, // Memory to Peripheral and Flow Controller is dmac
|
||||
DMA_P2M_DMAC, // Peripheral to Memory and Flow Controller is dmac
|
||||
DMA_P2P_DMAC, // Peripheral to Peripheral and Flow Controller is dmac
|
||||
DMA_P2M_PER, // Peripheral to Memory and Flow Controller is Peripheral
|
||||
DMA_P2P_SRCPER, // Peripheral to Peripheral and Flow Controller is Source Peripheral
|
||||
DMA_M2P_PER, // Memory to Peripheral and Flow Controller is Peripheral
|
||||
DMA_P2P_DSTPER, // Peripheral to Peripheral and Flow Controller is Destination Peripheral
|
||||
};
|
||||
|
||||
enum dma_addr_inc_t
|
||||
{
|
||||
DMA_ADDR_INC_INC, // Increments the source/destination address
|
||||
DMA_ADDR_INC_DEC, // Decrements the source/destination address
|
||||
DMA_ADDR_INC_NO_CHANGE, // No change the source/destination address
|
||||
};
|
||||
|
||||
enum dma_transfer_width_t
|
||||
{
|
||||
DMA_TRANSFER_WIDTH_8,
|
||||
DMA_TRANSFER_WIDTH_16,
|
||||
DMA_TRANSFER_WIDTH_32,
|
||||
};
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DMA_BURST_LEN_1,
|
||||
DMA_BURST_LEN_4,
|
||||
DMA_BURST_LEN_8,
|
||||
DMA_BURST_LEN_16,
|
||||
DMA_BURST_LEN_32,
|
||||
DMA_BURST_LEN_64,
|
||||
DMA_BURST_LEN_128,
|
||||
DMA_BURST_LEN_256,
|
||||
}dma_burst_len_t;
|
||||
|
||||
enum dma_ahb_master_t
|
||||
{
|
||||
DMA_AHB_MASTER_1, /* access to 0x00000000~0x1FFFFFFF space */
|
||||
DMA_AHB_MASTER_2, /* access to 0x20000000~ space */
|
||||
DMA_AHB_MASTER_3, /* access to 0x20000000~ space */
|
||||
DMA_AHB_MASTER_4, /* access to 0x20000000~ space */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Data_Flow; /* This parameter can be a value of @ref dma_data_flow_t */
|
||||
|
||||
uint8_t Request_ID; /* This parameter can be a value of @ref dma_requeat_id_t */
|
||||
|
||||
uint8_t Source_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
|
||||
|
||||
uint8_t Desination_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
|
||||
|
||||
uint8_t Source_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
|
||||
|
||||
uint8_t Desination_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
|
||||
|
||||
uint8_t Source_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
|
||||
|
||||
uint8_t Desination_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
|
||||
|
||||
uint8_t Source_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
|
||||
|
||||
uint8_t Desination_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
|
||||
|
||||
}dma_InitParameter_t;
|
||||
|
||||
/**
|
||||
* @brief DAM handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
struct_DMA_t *DMAx; /* DMA registers base address */
|
||||
|
||||
dma_channel_select_t Channel; /* DMA registers base address */
|
||||
/* This parameter can be a value of @ref dma_channel_select_t */
|
||||
|
||||
dma_InitParameter_t Init; /* DMA initialization parameters */
|
||||
|
||||
}DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Link List Item Structure
|
||||
*/
|
||||
typedef struct DMA_NextLink
|
||||
{
|
||||
uint32_t SrcAddr; /* source address */
|
||||
|
||||
uint32_t DstAddr; /* desination address */
|
||||
|
||||
struct DMA_NextLink *Next; /* Next Link */
|
||||
|
||||
REG_CTL1_t CTL1; /* Control Register for Channel */
|
||||
REG_CTL2_t CTL2; /* Control Register for Channel */
|
||||
|
||||
}DMA_LLI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SrcAddr; /* source address */
|
||||
|
||||
uint32_t DstAddr; /* desination address */
|
||||
|
||||
uint32_t NextLink; /* Next Link Address */
|
||||
|
||||
uint32_t Data_Flow; /* This parameter can be a value of @ref dma_data_flow_t */
|
||||
|
||||
uint32_t Request_ID; /* This parameter can be a value of @ref dma_requeat_id_t */
|
||||
|
||||
uint8_t Source_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
|
||||
|
||||
uint8_t Desination_Master_Sel; /* This parameter can be a value of @ref dma_ahb_master_t */
|
||||
|
||||
uint32_t Source_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
|
||||
|
||||
uint32_t Desination_Inc; /* This parameter can be a value of @ref dma_addr_inc_t */
|
||||
|
||||
uint32_t Source_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
|
||||
|
||||
uint32_t Desination_Width; /* This parameter can be a value of @ref dma_transfer_width_t */
|
||||
|
||||
uint32_t Source_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
|
||||
|
||||
uint32_t Desination_Burst_Len; /* This parameter can be a value of @ref dma_burst_len_t */
|
||||
|
||||
uint32_t Size; /* This parameter can be a 12-bit Size */
|
||||
|
||||
uint8_t gather_enable; /* Enable Source Gather or not */
|
||||
|
||||
uint8_t scatter_enable; /* Enable Destination Scatter or not */
|
||||
|
||||
}dma_LinkParameter_t;
|
||||
|
||||
/* ################################ Initialization, Config Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* set DATA flow selection */
|
||||
#define __DMA_DATA_FLOW_CONTROL_SET(__DMAC__, __CHANNEL__, SEL) (__DMAC__->Channels[__CHANNEL__].CTL1.TT_FC = SEL)
|
||||
|
||||
/* APB Master selection configuration */
|
||||
#define __DMA_SRC_MASTER_SET(__DMAC__, __CHANNEL__, SEL) (__DMAC__->Channels[__CHANNEL__].CTL1.SMS = SEL)
|
||||
#define __DMA_DES_MASTER_SET(__DMAC__, __CHANNEL__, SEL) (__DMAC__->Channels[__CHANNEL__].CTL1.DMS = SEL)
|
||||
|
||||
/* Address increment configuration */
|
||||
#define __DMA_SRC_ADDR_INC_SET(__DMAC__, __CHANNEL__, INC) (__DMAC__->Channels[__CHANNEL__].CTL1.SINC = INC)
|
||||
#define __DMA_DES_ADDR_INC_SET(__DMAC__, __CHANNEL__, INC) (__DMAC__->Channels[__CHANNEL__].CTL1.DINC = INC)
|
||||
|
||||
/* Gather function enable,disable */
|
||||
#define __DMA_GATHER_FUNC_ENABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.SRC_GATHER_EN = 1)
|
||||
#define __DMA_GATHER_FUNC_DISABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.SRC_GATHER_EN = 0)
|
||||
/* Gather count, Gather interval */
|
||||
#define __DMA_GATHER_COUNT(__DMAC__, __CHANNEL__, __COUNT__) (__DMAC__->Channels[__CHANNEL__].SGR.SGC = __COUNT__)
|
||||
#define __DMA_GATHER_INTERVAL(__DMAC__, __CHANNEL__, __INTERVAL__) (__DMAC__->Channels[__CHANNEL__].SGR.SGI = __INTERVAL__)
|
||||
|
||||
/* Scatter function enable,disable */
|
||||
#define __DMA_SCATTER_FUNC_ENABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.DST_SCATTER_EN = 1)
|
||||
#define __DMA_SCATTER_FUNC_DISABLE(__DMAC__, __CHANNEL__) (__DMAC__->Channels[__CHANNEL__].CTL1.DST_SCATTER_EN = 0)
|
||||
/* Scatter count, Gather interval */
|
||||
#define __DMA_SCATTER_COUNT(__DMAC__, __CHANNEL__, __COUNT__) (__DMAC__->Channels[__CHANNEL__].DSR.DSC = __COUNT__)
|
||||
#define __DMA_SCATTER_INTERVAL(__DMAC__, __CHANNEL__, __INTERVAL__) (__DMAC__->Channels[__CHANNEL__].DSR.DSI = __INTERVAL__)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* dma_init */
|
||||
void dma_init(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_start */
|
||||
void dma_start(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DstAddr, uint32_t Size);
|
||||
|
||||
/* dma_start_interrupt */
|
||||
void dma_start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DstAddr, uint32_t Size);
|
||||
|
||||
/* dma_linked_list_init */
|
||||
void dma_linked_list_init(DMA_LLI_InitTypeDef *link, dma_LinkParameter_t *param);
|
||||
|
||||
/* dma_linked_list_start */
|
||||
void dma_linked_list_start(DMA_HandleTypeDef *hdma, DMA_LLI_InitTypeDef *link, dma_LinkParameter_t *param);
|
||||
|
||||
/* dma_linked_list_start_IT */
|
||||
void dma_linked_list_start_IT(DMA_HandleTypeDef *hdma, DMA_LLI_InitTypeDef *link, dma_LinkParameter_t *param);
|
||||
|
||||
/* dma_tfr_interrupt_enable */
|
||||
void dma_tfr_interrupt_enable(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_tfr_interrupt_disable */
|
||||
void dma_tfr_interrupt_disable(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_get_tfr_Status */
|
||||
bool dma_get_tfr_Status(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_clear_tfr_Status */
|
||||
void dma_clear_tfr_Status(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_error_interrupt_enable */
|
||||
void dma_error_interrupt_enable(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_error_interrupt_disable */
|
||||
void dma_error_interrupt_disable(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_get_error_Status */
|
||||
bool dma_get_error_Status(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* dma_clear_error_Status */
|
||||
void dma_clear_error_Status(DMA_HandleTypeDef *hdma);
|
||||
|
||||
#endif
|
||||
92
fr3092_mcu/components/drivers/peripheral/Inc/driver_efuse.h
Normal file
92
fr3092_mcu/components/drivers/peripheral/Inc/driver_efuse.h
Normal file
@ -0,0 +1,92 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_efuse.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of eFuse HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_EFUSE_H__
|
||||
#define __DRIVER_EFUSE_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup eFuse_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Control Register */
|
||||
/* bit2: Done */
|
||||
/* bit1: Read/Write */
|
||||
/* bit0: GO */
|
||||
#define EFUSE_SISO_READ_MODE (0x01)
|
||||
#define EFUSE_SISO_WRITE_MODE (0x03)
|
||||
#define EFUSE_SISO_CHECK_DONE (0x04)
|
||||
|
||||
/* ------------------------------------------------*/
|
||||
/* eFuse SISO Register */
|
||||
/* ------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t eFuse_Ctrl; /* Offset 0x00 */
|
||||
volatile uint32_t eFuse_Timing; /* Offset 0x04 */
|
||||
volatile uint32_t eFuse_Data0; /* Offset 0x08 */
|
||||
volatile uint32_t eFuse_Data1; /* Offset 0x0C */
|
||||
volatile uint32_t eFuse_Data2; /* Offset 0x10 */
|
||||
}struct_eFuse_SISO_t;
|
||||
|
||||
#define EFUSE_SISO ((struct_eFuse_SISO_t *)EFUSE_SISO_BASE)
|
||||
|
||||
|
||||
/* Control Register */
|
||||
/* bit4: Done */
|
||||
/* bit3: Read */
|
||||
/* bit2: Write */
|
||||
/* bit1: AVDDEN */
|
||||
/* bit0: GO */
|
||||
#define EFUSE_PIPO_CHECK_DONE (0x10)
|
||||
#define EFUSE_PIPO_READ_MODE (0x08)
|
||||
#define EFUSE_PIPO_WRITE_MODE (0x04)
|
||||
#define EFUSE_PIPO_AVDDEN (0x02)
|
||||
#define EFUSE_PIPO_GO (0x01)
|
||||
|
||||
/* ------------------------------------------------*/
|
||||
/* eFuse PIPO Register */
|
||||
/* ------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t eFuse_Ctrl; /* Offset 0x00 */
|
||||
volatile uint32_t eFuse_Length; /* Offset 0x04 */
|
||||
volatile uint32_t eFuse_Addr; /* Offset 0x08 */
|
||||
volatile uint32_t eFuse_WData; /* Offset 0x0C */
|
||||
volatile uint32_t eFuse_RData; /* Offset 0x10 */
|
||||
}struct_eFuse_PIPO_t;
|
||||
|
||||
#define EFUSE_PIPO ((struct_eFuse_PIPO_t *)EFUSE_PIPO_BASE)
|
||||
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* eFuse_siso_read */
|
||||
/* eFuse_siso_write */
|
||||
void eFuse_siso_read(uint32_t *fp_Data);
|
||||
void eFuse_siso_write(uint32_t *fp_Data);
|
||||
void eFuse_pipo_read(uint8_t fu8_Addr, uint8_t *fp_Data);
|
||||
void eFuse_pipo_write(uint8_t fu8_Addr, uint8_t fu8_Data);
|
||||
|
||||
#endif
|
||||
80
fr3092_mcu/components/drivers/peripheral/Inc/driver_exti.h
Normal file
80
fr3092_mcu/components/drivers/peripheral/Inc/driver_exti.h
Normal file
@ -0,0 +1,80 @@
|
||||
#ifndef _EXTI_H
|
||||
#define _EXTI_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "plf.h"
|
||||
#include "driver_iomux.h"
|
||||
|
||||
enum ext_int_type_t
|
||||
{
|
||||
EXT_INT_TYPE_LOW,
|
||||
EXT_INT_TYPE_HIGH,
|
||||
EXT_INT_TYPE_POS,
|
||||
EXT_INT_TYPE_NEG,
|
||||
};
|
||||
|
||||
|
||||
struct exti_ctrl_t //EXTINTCTL. 0x14
|
||||
{
|
||||
uint32_t pa_exti_en: 8; //exti intr connect to gpio PA ctrl
|
||||
uint32_t pb_exti_en: 8; //exti intr connect to gpio PB ctrl
|
||||
uint32_t resv: 16;
|
||||
};
|
||||
struct exti_status_t //EXTINTSTS 0x18
|
||||
{
|
||||
uint32_t pa_exti_sts: 8; //PA exti intr status
|
||||
uint32_t pb_exti_sts: 8; //PB exti intr status
|
||||
uint32_t resv: 16;
|
||||
};
|
||||
struct exti_type_t //EXTINTTYPE offset@0x1C
|
||||
{
|
||||
uint32_t pa0_exti_type: 2; //external intr source sel.
|
||||
uint32_t pa1_exti_type: 2; //external intr source sel.
|
||||
uint32_t pa2_exti_type: 2; //external intr source sel.
|
||||
uint32_t pa3_exti_type: 2; //external intr source sel.
|
||||
uint32_t pa4_exti_type: 2; //external intr source sel.
|
||||
uint32_t pa5_exti_type: 2; //external intr source sel.
|
||||
uint32_t pa6_exti_type: 2; //external intr source sel.
|
||||
uint32_t pa7_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb0_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb1_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb2_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb3_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb4_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb5_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb6_exti_type: 2; //external intr source sel.
|
||||
uint32_t pb7_exti_type: 2; //external intr source sel.
|
||||
};
|
||||
struct exti_cnt_t //EXTINTCNT00 offset:0x20
|
||||
{
|
||||
uint32_t pre_cnt: 12; //Precaler Value: set the external interrupt source 0 CNT_CLK: CNT_CLK=PCLK/(1+ Precaler Value)
|
||||
uint32_t des_cnt: 4; //Counter Value. (only useful for level trigger mode)
|
||||
uint32_t resv: 16;
|
||||
};
|
||||
|
||||
|
||||
struct exti_reg_t
|
||||
{
|
||||
struct exti_ctrl_t exti_ctrl; //EXTINTCTL. 0x14
|
||||
struct exti_status_t exti_sts; //EXTINTSTS 0x18
|
||||
struct exti_type_t exti_type; //EXTINTTYPE offset@0x1C
|
||||
struct exti_cnt_t exti_cnt[16]; //EXTINTCNT00~EXTINTCNT15 offset:0x20~0x
|
||||
};
|
||||
|
||||
extern volatile struct exti_reg_t *extiAB_regs;
|
||||
extern volatile struct exti_reg_t *extiCD_regs;
|
||||
extern volatile struct exti_reg_t *extiEF_regs;
|
||||
extern volatile struct exti_reg_t *extiGH_regs;
|
||||
|
||||
|
||||
void exti_enable(enum system_port_t port,enum system_port_bit_t bit);
|
||||
void exti_disable(enum system_port_t port,enum system_port_bit_t bit);
|
||||
uint8_t exti_get_src(enum system_port_t port);
|
||||
void exti_intr_clr(enum system_port_t port,uint8_t bits);
|
||||
void exti_set_type(enum system_port_t port,enum system_port_bit_t bit, enum ext_int_type_t type);
|
||||
void exti_set_debounce_cnt(enum system_port_t port,enum system_port_bit_t bit, uint32_t clk, uint8_t cnt);
|
||||
|
||||
|
||||
|
||||
#endif //_EXTI_H
|
||||
|
||||
185
fr3092_mcu/components/drivers/peripheral/Inc/driver_fft.h
Normal file
185
fr3092_mcu/components/drivers/peripheral/Inc/driver_fft.h
Normal file
@ -0,0 +1,185 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_fft.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Header file of FFT module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_FFT_H__
|
||||
#define __DRIVER_FFT_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup FFT_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/*FFT CTRL REG 0x00*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t NP_SEL : 2; // fft sample number point select
|
||||
uint32_t MODE_SEL : 1; // fft calculate mode select
|
||||
uint32_t RSV : 29;
|
||||
} Bits;
|
||||
} REG_FFT_CTRL_t;
|
||||
|
||||
/*FFT DMA CONFIG REG 0x04*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t DMACR : 2; //dma clear
|
||||
uint32_t RSV1 : 6;
|
||||
uint32_t DMA_OUT_THR : 8; //dma_out_req start threshold
|
||||
uint32_t DMA_IN_THR : 8; //dma_in_req start threshold
|
||||
uint32_t RSV : 8;
|
||||
} Bits;
|
||||
} REG_FFT_DMA_t;
|
||||
|
||||
/*FFT INTERRUPT CLEAR REG 0x08*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INT_EN : 1; //FFT interrupt enable
|
||||
uint32_t RSV1 : 7;
|
||||
uint32_t INT_STATUS : 1; //FFT interrupt status
|
||||
uint32_t RSV2 : 22;
|
||||
} Bits;
|
||||
} REG_FFT_ISRCR_t;
|
||||
|
||||
/*FFT SOFT RESET REG 0x0c*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t NRST : 1; //FFT soft reset
|
||||
uint32_t RSV : 31;
|
||||
} Bits;
|
||||
} REG_FFT_SOFTRST_t;
|
||||
|
||||
/*FFT STATUS REG 0x14*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t IDLE : 1; // FFT status is idle
|
||||
uint32_t CAL_DONE : 1; // FFT calculate done
|
||||
uint32_t RSV : 30;
|
||||
} Bits;
|
||||
} REG_FFT_STATUS_t;
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* FFT Registers */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_FFT_CTRL_t FFT_CTRL; /* Offset 0x00 */
|
||||
volatile REG_FFT_DMA_t FFT_DMA; /* Offset 0x04 */
|
||||
volatile REG_FFT_ISRCR_t FFT_ISRCR; /* Offset 0x08 */
|
||||
volatile REG_FFT_SOFTRST_t FFT_SOFTRST_IIRFLT; /* Offset 0x0C */
|
||||
volatile uint32_t rsv1; /* Offset 0x10 */
|
||||
volatile REG_FFT_STATUS_t FFT_STATUS; /* Offset 0x14 */
|
||||
volatile uint32_t rsv2[26]; /* Offser 0x18 ~ 0x7c*/
|
||||
volatile uint32_t FFT_ACCESSRAM; /* Offset 0x80 */
|
||||
}struct_FFT_t;
|
||||
|
||||
#define FFT ((struct_FFT_t *)FFT_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FFT_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization Config Section Start ################################ */
|
||||
typedef enum
|
||||
{
|
||||
FFT_128 = 0,
|
||||
FFT_256 = 1,
|
||||
FFT_512 = 2,
|
||||
}FFT_Samples_t ;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FFT_CAL_MODE = 0, /* FFT calculate */
|
||||
IFFT_CAL_MODE = 1, /* FFT inverse calculation */
|
||||
}FFT_Cal_Mode_t ;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FFT_Samples; /*!< Specifies the number of Sample.
|
||||
This parameter can be a value of @ref fft_samples_t. */
|
||||
|
||||
uint32_t FFT_Cal_Mode; /*!< Specifies the FFT calculate mode.
|
||||
This parameter can be a value of @ref FFT_Cal_Mode_t. */
|
||||
}struct_FFT_Init_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
struct_FFT_Init_t FFT_Init;
|
||||
|
||||
uint32_t BlockCNT;
|
||||
uint32_t BlockSize;
|
||||
uint32_t DataIndex;
|
||||
uint32_t DataOutIndex;
|
||||
uint32_t *DataIn;
|
||||
uint32_t *DataOut;
|
||||
bool FFT_Busy;
|
||||
}FFT_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization/Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* FFT reset */
|
||||
#define __FFT_RESET_ENABLE() (FFT->FFT_SOFTRST_IIRFLT.Bits.NRST = 0)
|
||||
#define __FFT_RESET_DISABLE() (FFT->FFT_SOFTRST_IIRFLT.Bits.NRST = 1)
|
||||
|
||||
/* FFT int enable/disable/clear */
|
||||
#define __FFT_INT_ENALE() (FFT->FFT_ISRCR.Bits.INT_EN = 1)
|
||||
#define __FFT_INT_DISALE() (FFT->FFT_ISRCR.Bits.INT_EN = 0)
|
||||
#define __FFT_INT_STATUS_CLEAR() (FFT->FFT_ISRCR.Bits.INT_STATUS = 0)
|
||||
|
||||
/* FFT calculate id done */
|
||||
#define __FFT_CAL_IS_DONE() (FFT->FFT_STATUS.Bits.CAL_DONE == 1)
|
||||
/* FFT is dile */
|
||||
#define __FFT_IS_IDLE() (FFT->FFT_STATUS.Bits.IDLE == 1)
|
||||
|
||||
/* FFT DMA config */
|
||||
#define __FFT_DMA_ENABLE() (FFT->FFT_DMA.Bits.DMACR = 3)
|
||||
#define __FFT_DMA_IN_THR(__THR__) (FFT->FFT_DMA.Bits.DMA_IN_THR = __THR__)
|
||||
#define __FFT_DMA_OUT_THR(__THR__) (FFT->FFT_DMA.Bits.DMA_OUT_THR = __THR__)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Initialize the fft module */
|
||||
void fft_init(FFT_HandleTypeDef *hfft);
|
||||
/* FFt start */
|
||||
void fft_start(FFT_HandleTypeDef *hfft, uint32_t *fp_Data_In, uint32_t *fp_Data_Out, uint32_t fu32_BlockCNT);
|
||||
/* FFT start with isr */
|
||||
int fft_start_IT(FFT_HandleTypeDef *hfft, uint32_t *fp_Data_In, uint32_t *fp_Data_Out, uint32_t fu32_BlockCNT);
|
||||
/* FFT interrupt handler */
|
||||
void fft_IRQHandler(FFT_HandleTypeDef *hfft);
|
||||
|
||||
#endif
|
||||
125
fr3092_mcu/components/drivers/peripheral/Inc/driver_flash.h
Normal file
125
fr3092_mcu/components/drivers/peripheral/Inc/driver_flash.h
Normal file
@ -0,0 +1,125 @@
|
||||
/*
|
||||
* flash.h
|
||||
*
|
||||
* Created on: 2018-1-25
|
||||
* Author: owen
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_FLASH_H
|
||||
#define _DRIVER_FLASH_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "driver_qspi.h"
|
||||
|
||||
#define FLASH_READ_DEVICE_ID 0x90
|
||||
#define FLASH_READ_IDENTIFICATION 0x9F
|
||||
|
||||
#define FLASH_AAI_PROGRAM_OPCODE 0xAF
|
||||
#define FLASH_PAGE_PROGRAM_OPCODE 0x02
|
||||
#define FLASH_READ_OPCODE 0x03
|
||||
#define FLASH_FAST_READ_OPCODE 0x0B
|
||||
#define FLASH_FAST_DTR_READ_OPCODE 0x0D
|
||||
#define FLASH_READ_DUAL_OPCODE 0xBB
|
||||
#define FLASH_READ_DTR_DUAL_OPCODE 0xBD
|
||||
#define FLASH_READ_DUAL_OPCODE_2 0x3B
|
||||
#define FLASH_PAGE_DUAL_PROGRAM_OPCODE 0xA2
|
||||
#define FLASH_PAGE_QUAL_READ_OPCODE 0xEB
|
||||
#define FLASH_PAGE_DTR_QUAL_READ_OPCODE 0xED
|
||||
#define FLASH_PAGE_QUAL_READ_OPCODE_2 0x6B
|
||||
#define FLASH_PAGE_QUAL_PROGRAM_OPCODE 0x32
|
||||
|
||||
|
||||
#define FLASH_CHIP_ERASE_OPCODE 0x60
|
||||
#define FLASH_SECTORE_ERASE_OPCODE 0x20
|
||||
#define FLASH_BLOCK_32K_ERASE_OPCODE 0x52
|
||||
#define FLASH_BLOCK_64K_ERASE_OPCODE 0xD8
|
||||
#define FLASH_ST_SECTORE_ERASE_OPCODE 0xD8
|
||||
#define FLASH_ST_BULK_ERASE_OPCODE 0xC7
|
||||
|
||||
#define FLASH_WRITE_DISABLE_OPCODE 0x04
|
||||
#define FLASH_WRITE_ENABLE_OPCODE 0x06
|
||||
#define FLASH_WRITE_STATUS_REG_OPCODE 0x01
|
||||
#define FLASH_READ_STATUS_REG_OPCODE 0x05
|
||||
#define FLASH_READ_STATUS_HIGH_REG_OPCODE 0x35
|
||||
|
||||
#define FLASH_SEC_REG_READ_OPCODE (0x48)
|
||||
#define FLASH_SEC_REG_PROGRAM_OPCODE (0x42)
|
||||
#define FLASH_SEC_REG_ERASE_OPCODE (0x44)
|
||||
|
||||
#define FLASH_ST_ID 0x20
|
||||
#define FLASH_SST_ID 0xBF
|
||||
|
||||
#define FLASH_OP_TYPE_ERASE 0
|
||||
#define FLASH_OP_TYPE_WRITE 1
|
||||
|
||||
enum flash_rd_type_t {
|
||||
FLASH_RD_TYPE_SINGLE,
|
||||
FLASH_RD_TYPE_SINGLE_FAST,
|
||||
FLASH_RD_TYPE_DUAL,
|
||||
FLASH_RD_TYPE_DUAL_FAST,
|
||||
FLASH_RD_TYPE_QUAD,
|
||||
FLASH_RD_TYPE_QUAD_FAST,
|
||||
FLASH_RD_TYPE_DTR_SINGLE_FAST,
|
||||
FLASH_RD_TYPE_DTR_DUAL_FAST,
|
||||
FLASH_RD_TYPE_DTR_QUAD_FAST,
|
||||
};
|
||||
|
||||
enum flash_wr_type_t {
|
||||
FLASH_WR_TYPE_SINGLE,
|
||||
FLASH_WR_TYPE_DUAL,
|
||||
FLASH_WR_TYPE_QUAD,
|
||||
};
|
||||
|
||||
void flash_set_read_fast_quad(struct qspi_regs_t *qspi);
|
||||
void flash_set_read_quad(struct qspi_regs_t *qspi);
|
||||
void flash_set_read_fast_dual(struct qspi_regs_t *qspi);
|
||||
void flash_set_read_dual(struct qspi_regs_t *qspi);
|
||||
void flash_set_read_fast_single(struct qspi_regs_t *qspi);
|
||||
void flash_set_read_single(struct qspi_regs_t *qspi);
|
||||
void flash_set_write_quad(struct qspi_regs_t *qspi);
|
||||
void flash_set_write_dual(struct qspi_regs_t *qspi);
|
||||
void flash_set_write_single(struct qspi_regs_t *qspi);
|
||||
|
||||
uint16_t flash_read_status(struct qspi_regs_t *qspi, bool read_high);
|
||||
void flash_write_status(struct qspi_regs_t *qspi, uint16_t status_entity, bool write_high);
|
||||
void flash_write_status_volatile(struct qspi_regs_t *qspi, uint16_t status, bool write_high);
|
||||
void flash_write_status_2(struct qspi_regs_t *qspi, uint8_t status);
|
||||
void flash_write_status_2_volatile(struct qspi_regs_t *qspi, uint8_t status);
|
||||
uint8_t flash_write(struct qspi_regs_t *qspi, uint32_t offset, uint32_t length, const uint8_t *buffer);
|
||||
uint8_t flash_read(struct qspi_regs_t *qspi, uint32_t offset, uint32_t length, uint8_t *buffer);
|
||||
uint8_t flash_erase(struct qspi_regs_t *qspi, uint32_t offset, uint32_t size);
|
||||
void flash_chip_erase(struct qspi_regs_t *qspi);
|
||||
void flash_enter_deep_sleep(struct qspi_regs_t *qspi);
|
||||
void flash_exit_deep_sleep(struct qspi_regs_t *qspi);
|
||||
void flash_enable_quad(struct qspi_regs_t *qspi);
|
||||
void flash_set_IO_DRV(struct qspi_regs_t *qspi, uint8_t drv);
|
||||
void flash_set_capture_delay(struct qspi_regs_t *qspi, uint8_t delay);
|
||||
void flash_init_controller(struct qspi_regs_t *qspi, enum flash_rd_type_t rd_type, enum flash_wr_type_t wr_type);
|
||||
uint32_t flash_init(struct qspi_regs_t *qspi);
|
||||
uint32_t flash_read_id(struct qspi_regs_t *qspi);
|
||||
void flash_set_baudrate(struct qspi_regs_t *qspi, uint8_t baudrate);
|
||||
|
||||
void flash_OTP_read(struct qspi_regs_t *qspi,uint32_t offset, uint32_t length, uint8_t *buffer);
|
||||
void flash_OTP_write(struct qspi_regs_t *qspi,uint32_t offset, uint32_t length, uint8_t *buffer);
|
||||
void flash_OTP_erase(struct qspi_regs_t *qspi,uint32_t offset);
|
||||
|
||||
/************************************************************************************
|
||||
* @fn flash_protect_bit_set
|
||||
*
|
||||
* @brief set flash protection relevant bits.
|
||||
*
|
||||
* @param qspi: qspi controller base address
|
||||
* bits: flash protection bits in status 1, BIT4:0 is valid.
|
||||
* cmp: flash protection compare bit in status 2.
|
||||
* 0xff means this field should be ignored
|
||||
* BIT7: clear or set CMP bit
|
||||
* BIT0-2: CMP bit offset in status 2
|
||||
* wr_volatile: write status registers in volatile mode or not
|
||||
* status_2_separate: write status 2 together with status 1 or separately
|
||||
*/
|
||||
void flash_protect_bit_set(struct qspi_regs_t *qspi, uint8_t bits, uint8_t cmp, uint8_t wr_volatile, uint8_t status_2_separate);
|
||||
|
||||
#endif /* _DRIVER_FLASH_H */
|
||||
|
||||
72
fr3092_mcu/components/drivers/peripheral/Inc/driver_frspim.h
Normal file
72
fr3092_mcu/components/drivers/peripheral/Inc/driver_frspim.h
Normal file
@ -0,0 +1,72 @@
|
||||
/**
|
||||
****************************************************************************************
|
||||
*
|
||||
* @file frspim.h
|
||||
*
|
||||
* @brief Common header file for all radios.
|
||||
*
|
||||
* Copyright (C) RivieraWaves 2009-2013
|
||||
*
|
||||
*
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef FRSPIM_H_
|
||||
#define FRSPIM_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
struct frspim_ctrl_t{
|
||||
uint32_t go:1; /*Write:0--no action,1--transmit start(hw clear)*/
|
||||
uint32_t done:1; /*Read:0--idle,1--busy*/
|
||||
uint32_t sel:2; /*channel select*/
|
||||
uint32_t len:3; /*TX/RX byte(1:4)*/
|
||||
uint32_t rsv0:1;
|
||||
uint32_t op:1; /*1--write,0--read*/
|
||||
uint32_t rsv1:3;
|
||||
uint32_t ratio:2; /*sclk = p_clk/(1+ratio)*2*/
|
||||
uint32_t rsv2:2;
|
||||
uint32_t addr:8;
|
||||
uint32_t rsv3:8;
|
||||
};
|
||||
|
||||
struct frspim_wdat_t{
|
||||
uint32_t wbyte0:8;
|
||||
uint32_t wbyte1:8;
|
||||
uint32_t wbyte2:8;
|
||||
uint32_t wbyte3:8;
|
||||
};
|
||||
|
||||
struct frspim_rdat_t{
|
||||
uint32_t rbyte0:8;
|
||||
uint32_t rbyte1:8;
|
||||
uint32_t rbyte2:8;
|
||||
uint32_t rbyte3:8;
|
||||
};
|
||||
|
||||
struct frspim_reg_t{
|
||||
struct frspim_ctrl_t ctrl;
|
||||
struct frspim_wdat_t wdat;
|
||||
struct frspim_rdat_t rdat;
|
||||
};
|
||||
|
||||
#define FR_SPI_CODEC_CHAN 1
|
||||
#define FR_SPI_PMU_CHAN 0
|
||||
|
||||
#define ool_write(addr, data) frspim_wr(FR_SPI_PMU_CHAN,(addr),1, (data))
|
||||
#define ool_read(addr) (uint8_t)frspim_rd(FR_SPI_PMU_CHAN,(addr),1)
|
||||
|
||||
#define ool_write16(addr,data) frspim_wr(FR_SPI_PMU_CHAN,(addr),2, (data))
|
||||
#define ool_read16(addr) (uint16_t)frspim_rd(FR_SPI_PMU_CHAN,(addr),2)
|
||||
|
||||
#define ool_write32(addr,data) frspim_wr(FR_SPI_PMU_CHAN,(addr),4, (data))
|
||||
#define ool_read32(addr) (uint32_t)frspim_rd(FR_SPI_PMU_CHAN,(addr),4)
|
||||
|
||||
void frspim_init(uint8_t ratio);
|
||||
uint32_t frspim_rd (uint8_t chan_num, uint8_t addr, uint8_t len);
|
||||
void frspim_wr (uint8_t chan_num, uint8_t addr, uint8_t len, uint32_t val);
|
||||
|
||||
uint32_t frspim_rd_ram (uint8_t chan_num, uint8_t addr, uint8_t len);
|
||||
void frspim_wr_ram (uint8_t chan_num, uint8_t addr, uint8_t len, uint32_t val);
|
||||
#endif
|
||||
|
||||
231
fr3092_mcu/components/drivers/peripheral/Inc/driver_gpio.h
Normal file
231
fr3092_mcu/components/drivers/peripheral/Inc/driver_gpio.h
Normal file
@ -0,0 +1,231 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_gpio.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_GPIO_H__
|
||||
#define __DRIVER_GPIO_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup GPIO_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* GPIO Registers */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t GPIO_OutputEN; /* Offset 0x00 */
|
||||
volatile uint32_t GPIO_IN_DATA; /* Offset 0x04 */
|
||||
volatile uint32_t GPIO_OUT_DATA; /* Offset 0x08 */
|
||||
volatile uint32_t GPIO_BIT_SET; /* Offset 0x0C */
|
||||
volatile uint32_t GPIO_BIT_CLEAR; /* Offset 0x10 */
|
||||
|
||||
volatile uint32_t EXTI_EN; /* Offset 0x14 */
|
||||
volatile uint32_t EXTI_INT_EN; /* Offset 0x18 */
|
||||
volatile uint32_t EXTI_INT_STATUS; /* Offset 0x1C */
|
||||
volatile uint32_t EXTI_TYPE; /* Offset 0x20 */
|
||||
volatile uint32_t EXTI_CNT[16]; /* Offset 0x24 */
|
||||
}struct_GPIO_t;
|
||||
|
||||
#define GPIO_TypeDef struct_GPIO_t
|
||||
|
||||
#define GPIOA (( GPIO_TypeDef *)GPIOA_BASE)
|
||||
#define GPIOB (( GPIO_TypeDef *)GPIOB_BASE)
|
||||
#define GPIOC (( GPIO_TypeDef *)GPIOC_BASE)
|
||||
#define GPIOD (( GPIO_TypeDef *)GPIOD_BASE)
|
||||
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup ADC_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_line_index
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 ((uint16_t)0x0001) /* EXTI Line index 0 */
|
||||
#define EXTI_LINE_1 ((uint16_t)0x0002) /* EXTI Line index 1 */
|
||||
#define EXTI_LINE_2 ((uint16_t)0x0004) /* EXTI Line index 2 */
|
||||
#define EXTI_LINE_3 ((uint16_t)0x0008) /* EXTI Line index 3 */
|
||||
#define EXTI_LINE_4 ((uint16_t)0x0010) /* EXTI Line index 4 */
|
||||
#define EXTI_LINE_5 ((uint16_t)0x0020) /* EXTI Line index 5 */
|
||||
#define EXTI_LINE_6 ((uint16_t)0x0040) /* EXTI Line index 6 */
|
||||
#define EXTI_LINE_7 ((uint16_t)0x0080) /* EXTI Line index 7 */
|
||||
#define EXTI_LINE_8 ((uint16_t)0x0100) /* EXTI Line index 8 */
|
||||
#define EXTI_LINE_9 ((uint16_t)0x0200) /* EXTI Line index 9 */
|
||||
#define EXTI_LINE_10 ((uint16_t)0x0400) /* EXTI Line index 10 */
|
||||
#define EXTI_LINE_11 ((uint16_t)0x0800) /* EXTI Line index 11 */
|
||||
#define EXTI_LINE_12 ((uint16_t)0x1000) /* EXTI Line index 12 */
|
||||
#define EXTI_LINE_13 ((uint16_t)0x2000) /* EXTI Line index 13 */
|
||||
#define EXTI_LINE_14 ((uint16_t)0x4000) /* EXTI Line index 14 */
|
||||
#define EXTI_LINE_15 ((uint16_t)0x8000) /* EXTI Line index 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* GPIO mode */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MODE_INPUT = 0x1000u, /*!< Input Floating Mode */
|
||||
GPIO_MODE_INPUT_HRS = 0x1001u, /*!< Input High Resistance Mode */
|
||||
GPIO_MODE_OUTPUT_PP = 0x1002u, /*!< Output Push Pull Mode */
|
||||
GPIO_MODE_AF_PP = 0x0002u, /*!< Alternate Function Push Pull Mode */
|
||||
GPIO_MODE_EXTI_IT_LOW_LEVEL = 0x1100u, /*!< External Interrupt Mode with low level trigger detection */
|
||||
GPIO_MODE_EXTI_IT_HIGH_LEVEL = 0x1101u, /*!< External Interrupt Mode with high level trigger detection */
|
||||
GPIO_MODE_EXTI_IT_FALLING = 0x1102u, /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
GPIO_MODE_EXTI_IT_RISING = 0x1103u, /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
|
||||
GPIO_MODE_IO_MASK = 0x1000, /*!< GPIO Function Mask */
|
||||
GPIO_MODE_IT_MASK = 0x0100, /*!< EXTI Function Mask */
|
||||
}enum_GPIO_MODE_t;
|
||||
|
||||
/* GPIO pull */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_NOPULL, /*!< No Pull-up or Pull-down activation */
|
||||
GPIO_PULLUP, /*!< Pull-up activation */
|
||||
GPIO_PULLDOWN, /*!< Pull-down activation */
|
||||
}enum_Pull_t;
|
||||
|
||||
/* function selection */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_FUNCTION_0,
|
||||
GPIO_FUNCTION_1,
|
||||
GPIO_FUNCTION_2,
|
||||
GPIO_FUNCTION_3,
|
||||
GPIO_FUNCTION_4,
|
||||
GPIO_FUNCTION_5,
|
||||
GPIO_FUNCTION_6,
|
||||
GPIO_FUNCTION_7,
|
||||
GPIO_FUNCTION_8,
|
||||
GPIO_FUNCTION_9,
|
||||
GPIO_FUNCTION_A,
|
||||
GPIO_FUNCTION_B,
|
||||
GPIO_FUNCTION_C,
|
||||
GPIO_FUNCTION_D,
|
||||
GPIO_FUNCTION_E,
|
||||
GPIO_FUNCTION_F,
|
||||
}enum_Function_t;
|
||||
|
||||
/* GPIO Bit SET and Bit RESET enumeration */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_CLEAR = 0u,
|
||||
GPIO_PIN_SET = 1u,
|
||||
}enum_PinStatus_t;
|
||||
|
||||
/* GPIO Drive Current Index */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_DRIVE_1mA,
|
||||
GPIO_DRIVE_2mA,
|
||||
GPIO_DRIVE_3mA,
|
||||
GPIO_DRIVE_4mA,
|
||||
}enum_GPIO_Drive_Current_t;
|
||||
|
||||
/*
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref enum_GPIO_MODE_t */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref enum_Pull_t */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref enum_Function_t */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* gpio_init */
|
||||
void gpio_init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
|
||||
/* gpio_set_portpull */
|
||||
void gpio_set_portpull(GPIO_TypeDef *GPIOx, uint16_t fu16_Pin, enum_Pull_t fe_Pull);
|
||||
|
||||
/* gpio_write_group */
|
||||
/* gpio_write_pin */
|
||||
void gpio_write_group(GPIO_TypeDef *GPIOx, uint16_t fu16_GroupStatus);
|
||||
void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t fu16_Pin, enum_PinStatus_t fe_PinStatus);
|
||||
|
||||
/* gpio_read_group */
|
||||
/* gpio_read_pin */
|
||||
uint16_t gpio_read_group(GPIO_TypeDef *GPIOx);
|
||||
enum_PinStatus_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t fu16_Pin);
|
||||
|
||||
/* gpio_drive_current_config */
|
||||
/* input schmitt enable/disable */
|
||||
void gpio_drive_current_config(GPIO_TypeDef *GPIOx, uint16_t fu16_Pin, enum_GPIO_Drive_Current_t fe_GPIO_Drive);
|
||||
|
||||
/* exti_interrupt_enable */
|
||||
/* exti_interrupt_disable */
|
||||
void exti_interrupt_enable(GPIO_TypeDef *GPIOx, uint16_t fu16_EXTI_Line);
|
||||
void exti_interrupt_disable(GPIO_TypeDef *GPIOx, uint16_t fu16_EXTI_Line);
|
||||
|
||||
/* exti_get_LineStatus */
|
||||
/* exti_clear_LineStatus */
|
||||
bool exti_get_LineStatus(GPIO_TypeDef *GPIOx, uint16_t fu16_EXTI_Line);
|
||||
void exti_clear_LineStatus(GPIO_TypeDef *GPIOx, uint16_t fu16_EXTI_Line);
|
||||
|
||||
/* exti_set_FilterCNT */
|
||||
void exti_set_Filter(GPIO_TypeDef *GPIOx, uint16_t fu16_EXTI_Line, uint8_t fu8_DIV, uint16_t fu16_CNT);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
370
fr3092_mcu/components/drivers/peripheral/Inc/driver_i2c.h
Normal file
370
fr3092_mcu/components/drivers/peripheral/Inc/driver_i2c.h
Normal file
@ -0,0 +1,370 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_i2c.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_I2C_H__
|
||||
#define __DRIVER_I2C_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup I2C_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* I2C control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t MASTER_MODE : 1;
|
||||
uint32_t SPEED : 2;
|
||||
uint32_t ADDR_SLAVE_10BIT : 1;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t RESTART_EN : 1;
|
||||
uint32_t SLAVE_DISABLE : 1;
|
||||
uint32_t STOP_DET_IF_ADDR_ESSED : 1;
|
||||
uint32_t TX_EMPTY_CTRL : 1;
|
||||
uint32_t RX_FIFO_FULL_HLD_CTRL : 1;
|
||||
uint32_t STOP_DET_IF_MASTER_ACTIVE : 1;
|
||||
uint32_t BUS_DETEC_FEATURE_CTRL : 1;
|
||||
uint32_t rsv_1 : 20;
|
||||
}REG_I2C_CTRL_t;
|
||||
|
||||
/* target address Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TAR : 10;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t SPECIAL : 1;
|
||||
uint32_t ADDR_MASTER_10BIT : 1;
|
||||
uint32_t DEVICE_ID : 1;
|
||||
uint32_t rsv_1 : 18;
|
||||
}REG_TAR_t;
|
||||
|
||||
/* DATA CMD Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAT : 8;
|
||||
uint32_t CMD : 1;
|
||||
uint32_t STOP : 1;
|
||||
uint32_t RESTART : 1;
|
||||
uint32_t FIRST_DATA_BYTE : 1;
|
||||
uint32_t rsv_0 : 20;
|
||||
}REG_DATA_CMD_t;
|
||||
|
||||
/* enable Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ENABLE : 1;
|
||||
uint32_t ABORT : 1;
|
||||
uint32_t TX_CMD_BLOCK : 1;
|
||||
uint32_t SDA_STUCK_RECOVERY : 1;
|
||||
uint32_t rsv_0 : 28;
|
||||
}REG_ENABLE_t;
|
||||
|
||||
/* Status Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ACTIVITY : 1;
|
||||
uint32_t TFNF : 1;
|
||||
uint32_t TFE : 1;
|
||||
uint32_t RFNE : 1;
|
||||
uint32_t RFF : 1;
|
||||
uint32_t MST_ACTIVITY : 1;
|
||||
uint32_t SLV_ACTIVITY : 1;
|
||||
uint32_t MST_HOLD_TX_FIFO_EMPTY : 1;
|
||||
uint32_t MST_HOLD_RX_FIFO_FULL : 1;
|
||||
uint32_t SLV_HOLD_TX_FIFO_EMPTY : 1;
|
||||
uint32_t SLV_HOLD_RX_FIFO_FULL : 1;
|
||||
uint32_t SDA_STUCK_NOT_RECOVERED : 1;
|
||||
uint32_t rsv_0 : 20;
|
||||
}REG_STATUS_t;
|
||||
|
||||
/* SDA hold Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDA_TX_HOLD : 16;
|
||||
uint32_t SDA_RX_HOLD : 8;
|
||||
uint32_t rsv_0 : 8;
|
||||
}REG_SDA_HOLD_t;
|
||||
|
||||
/* TX ABRT SOURCE Register */
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ABRT_7ADDR_NOACK : 1;
|
||||
uint32_t ABRT_10ADDR1_NOACK : 1;
|
||||
uint32_t ABRT_10ADDR2_NOACK : 1;
|
||||
uint32_t ABRT_TXDATA_NOACK : 1;
|
||||
uint32_t rsv_0 : 2;
|
||||
uint32_t ABRT_SBYTE_ACKDET : 1;
|
||||
uint32_t rsv_1 : 1;
|
||||
uint32_t ABRT_HS_NORSTRT : 1;
|
||||
uint32_t rsv_2 : 1;
|
||||
uint32_t ABRT_10B_RD_NORSTRT : 1;
|
||||
uint32_t ABRT_MASTER_DIS : 1;
|
||||
uint32_t ARB_LOST : 1;
|
||||
uint32_t ABRT_SLVFLUSH_TXFIFO : 1;
|
||||
uint32_t ABRT_SLV_ARBLOST : 1;
|
||||
uint32_t ABRT_SLVRD_INTX : 1;
|
||||
uint32_t ABRT_USER_ABRT : 1;
|
||||
uint32_t ABRT_SDA_STUCK_AT_LOW : 1;
|
||||
uint32_t rsv_3 : 1;
|
||||
uint32_t ABRT_DEVICE_SLVADDR_NOACK : 1;
|
||||
uint32_t ABRT_DEVICE_WRITE : 1;
|
||||
uint32_t rsv_4 : 2;
|
||||
uint32_t TX_FLUSH_CNT : 9;
|
||||
}TX_ABRT_SOURCE_BIT;
|
||||
|
||||
uint32_t TX_ABRT_SOURCE_DWORD;
|
||||
|
||||
}REG_TX_ABRT_SOURCE_t;
|
||||
|
||||
/* DMA control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RDMAE : 1;
|
||||
uint32_t TDMAE : 1;
|
||||
uint32_t rsv_0 : 30;
|
||||
}REG_DMA_CR_t;
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* I2C Register */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_I2C_CTRL_t CTRL; /* Offset 0x00 */
|
||||
volatile REG_TAR_t TAR; /* Offset 0x04 */
|
||||
volatile uint32_t SAR; /* Offset 0x08 */
|
||||
volatile uint32_t HS_MADDR; /* Offset 0x0C */
|
||||
volatile uint32_t DATA_CMD; /* Offset 0x10 */
|
||||
volatile uint32_t rsv_0[2];
|
||||
volatile uint32_t FS_SCL_HCNT; /* Offset 0x1C */
|
||||
volatile uint32_t FS_SCL_LCNT; /* Offset 0x20 */
|
||||
volatile uint32_t rsv_1[2];
|
||||
volatile uint32_t INT_STAT; /* Offest 0x2C */
|
||||
volatile uint32_t INT_MASK; /* Offest 0x30 */
|
||||
volatile uint32_t RAW_INT_STAT; /* Offest 0x34 */
|
||||
volatile uint32_t RX_TL; /* Offest 0x38 */
|
||||
volatile uint32_t TX_TL; /* Offest 0x3C */
|
||||
volatile uint32_t CLR_INTR; /* Offest 0x40 */
|
||||
volatile uint32_t CLR_RX_UNDER; /* Offest 0x44 */
|
||||
volatile uint32_t CLR_RX_OVER; /* Offest 0x48 */
|
||||
volatile uint32_t CLR_TX_OVER; /* Offest 0x4C */
|
||||
volatile uint32_t CLR_RD_REQ; /* Offest 0x50 */
|
||||
volatile uint32_t CLR_TX_ABRT; /* Offest 0x54 */
|
||||
volatile uint32_t CLR_RX_DONE; /* Offest 0x58 */
|
||||
volatile uint32_t CLR_ACTIVITY; /* Offest 0x5C */
|
||||
volatile uint32_t CLR_STOP_DET; /* Offest 0x60 */
|
||||
volatile uint32_t CLR_START_DET; /* Offest 0x64 */
|
||||
volatile uint32_t rsv_2;
|
||||
volatile REG_ENABLE_t ENABLE; /* Offest 0x6C */
|
||||
volatile REG_STATUS_t STATUS; /* Offest 0x70 */
|
||||
volatile uint32_t TXFLR; /* Offest 0x74 */
|
||||
volatile uint32_t RXFLR; /* Offest 0x78 */
|
||||
volatile REG_SDA_HOLD_t SDA_HOLD; /* Offest 0x7C */
|
||||
volatile REG_TX_ABRT_SOURCE_t TX_ABRT_SOURCE; /* Offest 0x80 */
|
||||
volatile uint32_t SLV_DATA_NACK; /* Offest 0x84 */
|
||||
volatile REG_DMA_CR_t DMA_CTRL; /* Offest 0x88 */
|
||||
volatile uint32_t DMATDL; /* Offest 0x8C */
|
||||
volatile uint32_t DMARDL; /* Offest 0x90 */
|
||||
volatile uint32_t SDA_SETUP; /* Offest 0x94 */
|
||||
volatile uint32_t rsv_3[2];
|
||||
volatile uint32_t FS_SPKLEN; /* Offest 0xA0 */
|
||||
volatile uint32_t rsv_4;
|
||||
volatile uint32_t CLR_RESTART_DET; /* Offest 0xA8 */
|
||||
volatile uint32_t SCL_STUCK_LOW_TIMEOUT; /* Offest 0xAC */
|
||||
volatile uint32_t SDA_STUCK_LOW_TIMEOUT; /* Offest 0xB0 */
|
||||
volatile uint32_t CLR_SCL_STUCK_DET; /* Offest 0xB4 */
|
||||
}struct_I2C_t;
|
||||
|
||||
#define I2C0 ((struct_I2C_t *)I2C0_BASE)
|
||||
#define I2C1 ((struct_I2C_t *)I2C1_BASE)
|
||||
#define I2C2 ((struct_I2C_t *)I2C2_BASE)
|
||||
#define I2C3 ((struct_I2C_t *)I2C3_BASE)
|
||||
#define I2C4 ((struct_I2C_t *)I2C4_BASE)
|
||||
#define I2C5 ((struct_I2C_t *)I2C5_BASE)
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup I2C_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/* interrupt index */
|
||||
typedef enum
|
||||
{
|
||||
INT_RX_UNDER = 0x00000001,
|
||||
INT_RX_OVER = 0x00000002,
|
||||
INT_RX_FULL = 0x00000004,
|
||||
INT_TX_OVER = 0x00000008,
|
||||
INT_TX_EMPTY = 0x00000010,
|
||||
INT_RD_REQ = 0x00000020,
|
||||
INT_TX_ABRT = 0x00000040,
|
||||
INT_RX_DONE = 0x00000080,
|
||||
INT_ACTIVITY = 0x00000100,
|
||||
INT_STOP_DET = 0x00000200,
|
||||
INT_START_DET = 0x00000400,
|
||||
INT_RESTART_DET = 0x00001000,
|
||||
INT_MASTER_ON_HOLD = 0x00002000,
|
||||
INT_SCL_STUCK_AT_LOW = 0x00004000,
|
||||
}enum_INT_Index_t;
|
||||
|
||||
/* interrupt index */
|
||||
typedef enum
|
||||
{
|
||||
CMD_WRITE = 0x0000,
|
||||
CMD_READ = 0x0100,
|
||||
CMD_STOP = 0x0200,
|
||||
CMD_RESTART = 0x0400,
|
||||
}enum_CMD_t;
|
||||
|
||||
/* I2C Mode */
|
||||
typedef enum
|
||||
{
|
||||
I2C_MODE_MASTER_7BIT = 0x01,
|
||||
I2C_MODE_MASTER_10BIT = 0x11,
|
||||
I2C_MODE_SLAVE_7BIT = 0x00,
|
||||
I2C_MODE_SLAVE_10BIT = 0x10,
|
||||
|
||||
I2C_MASK_MASTER = 0x01,
|
||||
I2C_MASK_10BIT = 0x10,
|
||||
}enum_I2C_MODE_t;
|
||||
|
||||
|
||||
/*
|
||||
* @brief I2C Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_Mode; /* This parameter can be a value of @ref enum_I2C_MODE_t */
|
||||
|
||||
uint32_t SCL_HCNT; /* This parameter can be a 16-bit value. The minimum limit is 6 */
|
||||
uint32_t SCL_LCNT; /* SCL high/low level hold time. The minimum limit is 8 */
|
||||
|
||||
uint32_t Slave_Address; /* This parameter can be a 7-bit or 10-bit address */
|
||||
}struct_I2CInit_t;
|
||||
|
||||
|
||||
/*
|
||||
* @brief I2C handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
struct_I2C_t *I2Cx; /*!< I2C registers base address */
|
||||
|
||||
struct_I2CInit_t Init; /*!< I2C communication parameters */
|
||||
|
||||
volatile uint32_t u32_TxSize; /*!< I2C Transmit parameters in interrupt */
|
||||
volatile uint32_t u32_TxCount;
|
||||
volatile uint8_t *p_TxData;
|
||||
volatile bool b_TxBusy;
|
||||
|
||||
volatile uint32_t u32_RxSize; /*!< I2C Receive parameters in interrupt */
|
||||
volatile uint32_t u32_RxCount;
|
||||
volatile uint8_t *p_RxData;
|
||||
volatile bool b_RxBusy;
|
||||
}I2C_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define __I2C_ENABLE(__I2Cx__) (__I2Cx__->ENABLE.ENABLE = 1)
|
||||
#define __I2C_DISABLE(__I2Cx__) (__I2Cx__->ENABLE.ENABLE = 0)
|
||||
|
||||
/* master transfe abort */
|
||||
#define __I2C_MASTER_TRAN_ABORT(__I2Cx__) (__I2Cx__->ENABLE.ABORT = 1)
|
||||
|
||||
/* master Block/start the transmission */
|
||||
#define __I2C_MASTER_BLOCK_TRAN(__I2Cx__) (__I2Cx__->ENABLE.TX_CMD_BLOCK = 1)
|
||||
#define __I2C_MASTER_START_TRAN(__I2Cx__) (__I2Cx__->ENABLE.TX_CMD_BLOCK = 0)
|
||||
|
||||
/* get the number of valid data in RxFIFO/TxFIFO */
|
||||
#define __I2C_GET_TxFIFO_VALID_NUM(__I2Cx__) (__I2Cx__->TXFLR)
|
||||
#define __I2C_GET_RxFIFO_VALID_NUM(__I2Cx__) (__I2Cx__->RXFLR)
|
||||
|
||||
/* Get Tx abort source */
|
||||
#define __I2C_GET_TX_ABRT_SOURCE(__I2Cx__) (__I2Cx__->TX_ABRT_SOURCE.TX_ABRT_SOURCE_DWORD)
|
||||
#define __I2C_IS_TX_ABRT(__I2Cx__) (__I2Cx__->RAW_INT_STAT & INT_TX_ABRT)
|
||||
|
||||
/* get I2C Status */
|
||||
#define __I2C_IS_BUSY(__I2Cx__) (__I2Cx__->STATUS.ACTIVITY)
|
||||
#define __I2C_IS_MASTER_BUSY(__I2Cx__) (__I2Cx__->STATUS.MST_ACTIVITY)
|
||||
#define __I2C_IS_SLAVE_BUSY(__I2Cx__) (__I2Cx__->STATUS.SLV_ACTIVITY)
|
||||
#define __I2C_IS_TxFIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.TFNF == 0)
|
||||
#define __I2C_IS_TxFIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.TFE)
|
||||
#define __I2C_IS_RxFIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.RFF)
|
||||
#define __I2C_IS_RxFIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.RFNE == 0)
|
||||
#define __I2C_IS_MST_HOLD_TX_FIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.MST_HOLD_TX_FIFO_EMPTY)
|
||||
#define __I2C_IS_MST_HOLD_RX_FIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.MST_HOLD_RX_FIFO_FULL)
|
||||
#define __I2C_IS_SLV_HOLD_TX_FIFO_EMPTY(__I2Cx__) (__I2Cx__->STATUS.SLV_HOLD_TX_FIFO_EMPTY)
|
||||
#define __I2C_IS_SLV_HOLD_RX_FIFO_FULL(__I2Cx__) (__I2Cx__->STATUS.SLV_HOLD_RX_FIFO_FULL)
|
||||
#define __I2C_IS_SDA_STUCK_NOT_RECOVERED(__I2Cx__) (__I2Cx__->STATUS.SDA_STUCK_NOT_RECOVERED)
|
||||
|
||||
/* RxFIFO/TxFIFO Threshold level */
|
||||
#define __I2C_RxFIFO_THRESHOLD_LEVEL(__I2Cx__, __LEVEL__) (__I2Cx__->RX_TL = __LEVEL__)
|
||||
#define __I2C_TxFIFO_THRESHOLD_LEVEL(__I2Cx__, __LEVEL__) (__I2Cx__->TX_TL = __LEVEL__)
|
||||
|
||||
/* SCL High/Low count, */
|
||||
#define __I2C_SCL_HIGH_COUNT(__I2Cx__, __COUNT__) (__I2Cx__->FS_SCL_HCNT = __COUNT__)
|
||||
#define __I2C_SCL_LOW_COUNT(__I2Cx__, __COUNT__) (__I2Cx__->FS_SCL_LCNT = __COUNT__)
|
||||
#define __I2C_SDA_HOLD(__I2Cx__, __COUNT__) (__I2Cx__->SDA_HOLD.SDA_TX_HOLD = __COUNT__)
|
||||
#define __I2C_SDA_SETUP(__I2Cx__, __COUNT__) (__I2Cx__->SDA_SETUP = __COUNT__)
|
||||
|
||||
/* Slave send ACK/NACK */
|
||||
#define __I2C_SLAVE_SEND_NACK(__I2Cx__) (__I2Cx__->SLV_DATA_NACK = 1)
|
||||
#define __I2C_SLAVE_SEND_ACK(__I2Cx__) (__I2Cx__->SLV_DATA_NACK = 0)
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/* i2c_IRQHandler */
|
||||
void i2c_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* i2c_init */
|
||||
void i2c_init(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Master transmit/receive */
|
||||
bool i2c_master_transmit(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_master_receive(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_master_transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_master_receive_IT(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_slave_transmit(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_slave_receive(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_slave_transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_slave_receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
|
||||
/* memory write/read */
|
||||
bool i2c_memory_write(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint16_t fu16_MemAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_memory_read(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint16_t fu16_MemAddress, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_memory_is_busy(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress);
|
||||
|
||||
/* interrupt function */
|
||||
void i2c_int_enable(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
||||
void i2c_int_disable(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
||||
bool i2c_is_int_enable(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
||||
bool i2c_get_int_status(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
||||
void i2c_clear_int_status(I2C_HandleTypeDef *hi2c, enum_INT_Index_t fe_INT_Index);
|
||||
|
||||
/* sensor write/read */
|
||||
bool i2c_sensor_write(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint32_t fu32_RegAddress, uint8_t fu8_AddressLength, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
bool i2c_sensor_read(I2C_HandleTypeDef *hi2c, uint16_t fu16_DevAddress, uint32_t fu32_RegAddress, uint8_t fu8_AddressLength, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
#endif
|
||||
409
fr3092_mcu/components/drivers/peripheral/Inc/driver_i2s.h
Normal file
409
fr3092_mcu/components/drivers/peripheral/Inc/driver_i2s.h
Normal file
@ -0,0 +1,409 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_i2s.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_I2S_H__
|
||||
#define __DRIVER_I2S_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup I2S_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* I2S control 0 Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t MSTSLV : 1;
|
||||
uint32_t LR_WD_EN : 1;
|
||||
uint32_t INTEN : 1;
|
||||
uint32_t LR_WD_SWAP : 1;
|
||||
uint32_t RXFF_R_EN : 1;
|
||||
uint32_t RXFF_L_EN : 1;
|
||||
uint32_t TXFF_R_EN : 1;
|
||||
uint32_t TXFF_L_EN : 1;
|
||||
uint32_t RXFF_R_CLR : 1;
|
||||
uint32_t RXFF_L_CLR : 1;
|
||||
uint32_t TXFF_R_CLR : 1;
|
||||
uint32_t TXFF_L_CLR : 1;
|
||||
uint32_t rsv_0 : 4;
|
||||
uint32_t SBC_ACCESS : 1;
|
||||
uint32_t rsv_1 : 15;
|
||||
}REG_I2S_CTRL0_t;
|
||||
|
||||
/* frame divder Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BCLKDIV : 16;
|
||||
uint32_t FRMDIV : 16;
|
||||
}REG_FRM_DIV_t;
|
||||
|
||||
/* I2S control 1 Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2S_EN : 1;
|
||||
uint32_t I2S_FRMINV : 1;
|
||||
uint32_t I2S_BCLKINV : 1;
|
||||
uint32_t I2S_LP : 1;
|
||||
uint32_t I2S_HLSEL : 1;
|
||||
uint32_t A2DP_SYNC_DISABLE : 1;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t I2S_NORMAL : 1;
|
||||
uint32_t I2S_ADJUST : 1;
|
||||
uint32_t I2S_LSB1ST : 1;
|
||||
uint32_t rsv_1 : 2;
|
||||
uint32_t I2S_DATA_LENGTH : 3;
|
||||
uint32_t rsv_2 : 1;
|
||||
uint32_t I2SFBOFF : 16;
|
||||
}REG_I2S_CTRL1_t;
|
||||
|
||||
/* FIFO config right Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TXFF_AEMPTY : 8;
|
||||
uint32_t TXFF_AFULL : 8;
|
||||
uint32_t RXFF_AEMPTY : 8;
|
||||
uint32_t RXFF_AFULL : 8;
|
||||
}REG_FIFO_CFG_t;
|
||||
|
||||
/* DMA config Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMACR_L_TX : 1;
|
||||
uint32_t DMACR_R_TX : 1;
|
||||
uint32_t DMACR_L_RX : 1;
|
||||
uint32_t DMACR_R_RX : 1;
|
||||
uint32_t rsv_0 : 4;
|
||||
uint32_t DMARDLR : 5;
|
||||
uint32_t rsv_1 : 3;
|
||||
uint32_t DMATDLR : 5;
|
||||
uint32_t rsv_2 : 11;
|
||||
}REG_I2S_DMA_CFG_t;
|
||||
|
||||
/* PCM general Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PCM_EN : 1;
|
||||
uint32_t PCM_LRSWAP : 1;
|
||||
uint32_t PCM_BYTESWAP : 1;
|
||||
uint32_t PCM_PLL_EN : 1;
|
||||
uint32_t PCM_MONO_STEREO : 1;
|
||||
uint32_t PCM_MONO_LR_SEL : 1;
|
||||
uint32_t PCM_LOOPBACK : 1;
|
||||
uint32_t PCM_CLKINV : 1;
|
||||
uint32_t PCM_SLVBFMST : 1;
|
||||
uint32_t PCM_SET_FRAME : 1;
|
||||
uint32_t rsv_0 : 22;
|
||||
}REG_PCM_GENCTRL_t;
|
||||
|
||||
/* PCM PHY CTRL Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PCM_FSYNCSHP : 3;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t PCM_DOUTCFG : 2;
|
||||
uint32_t rsv_1 : 2;
|
||||
uint32_t PCM_LRCHPOL : 1;
|
||||
uint32_t PCM_IOM : 1;
|
||||
uint32_t PCM_LSB1ST : 1;
|
||||
uint32_t rsv_2 : 1;
|
||||
uint32_t PCM_SAMPSZ : 1;
|
||||
uint32_t PCM_SAMPTYPE : 1;
|
||||
uint32_t rsv_3 : 2;
|
||||
uint32_t PCM_SLOTNB : 3;
|
||||
uint32_t rsv_4 : 1;
|
||||
uint32_t PCM_FIRSTACTSLOT : 2;
|
||||
uint32_t rsv_5 : 10;
|
||||
}REG_PCM_PHYCTRL_t;
|
||||
|
||||
/* PCM PHY CTRL Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PCM_LSAMPPAD : 16;
|
||||
uint32_t PCM_RSAMPPAD : 16;
|
||||
}REG_PCM_PADDING_t;
|
||||
|
||||
/* PCM MUTE Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PCM_MUTE_PATT : 16;
|
||||
uint32_t rsv_0 : 15;
|
||||
uint32_t PCM_MUTE_EN : 1;
|
||||
}REG_PCM_MUTE_t;
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* I2S Register */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_I2S_CTRL0_t CTRL0; /* Offset 0x00 */
|
||||
volatile REG_FRM_DIV_t FrmDiv; /* Offset 0x04 */
|
||||
volatile REG_I2S_CTRL1_t CTRL1; /* Offset 0x08 */
|
||||
volatile uint32_t DATA_L; /* Offset 0x0C */
|
||||
volatile uint32_t DATA_R; /* Offset 0x10 */
|
||||
volatile uint32_t INT_STATUS; /* Offset 0x14 */
|
||||
volatile uint32_t INT_STATUS_EN; /* Offset 0x18 */
|
||||
volatile REG_FIFO_CFG_t FIFO_CFG_L; /* Offset 0x1C */
|
||||
volatile REG_FIFO_CFG_t FIFO_CFG_R; /* Offset 0x20 */
|
||||
volatile REG_I2S_DMA_CFG_t DMA_CFG; /* Offset 0x24 */
|
||||
volatile REG_PCM_GENCTRL_t PCM_GENCTRL; /* Offset 0x28 */
|
||||
volatile REG_PCM_PHYCTRL_t PCM_RHYCTRL; /* Offset 0x2C */
|
||||
volatile REG_PCM_PADDING_t PCM_PADDING; /* Offset 0x30 */
|
||||
volatile REG_PCM_MUTE_t PCM_MUTE; /* Offset 0x34 */
|
||||
}struct_I2S_t;
|
||||
|
||||
#define I2S0 ((struct_I2S_t *)I2S0_BASE)
|
||||
#define I2S1 ((struct_I2S_t *)I2S1_BASE)
|
||||
#define I2S2 ((struct_I2S_t *)I2S2_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup I2S_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
#define I2S_FIFO_DEPTH (32)
|
||||
#define I2S_FIFO_HALF_DEPTH (I2S_FIFO_DEPTH >> 1)
|
||||
|
||||
/* FIFO Status start */
|
||||
#define I2S_RX_FIFOS_FULL (0x00001)
|
||||
#define I2S_RX_FIFOS_HALF_FULL (0x00002)
|
||||
#define I2S_RX_FIFOS_EMPTY (0x00004)
|
||||
#define I2S_RX_L_FIFO_FULL (0x00008)
|
||||
#define I2S_RX_L_FIFO_HALF_FULL (0x00010)
|
||||
#define I2S_RX_L_FIFO_EMPTY (0x00020)
|
||||
#define I2S_RX_R_FIFO_FULL (0x00040)
|
||||
#define I2S_RX_R_FIFO_HALF_FULL (0x00080)
|
||||
#define I2S_RX_R_FIFO_EMPTY (0x00100)
|
||||
#define I2S_TX_FIFOS_FULL (0x00200)
|
||||
#define I2S_TX_FIFOS_ALMOST_EMPTY (0x00400)
|
||||
#define I2S_TX_FIFOS_EMPTY (0x00800)
|
||||
#define I2S_TX_L_FIFO_FULL (0x01000)
|
||||
#define I2S_TX_L_FIFO_ALMOST_EMPTY (0x02000)
|
||||
#define I2S_TX_L_FIFO_EMPTY (0x04000)
|
||||
#define I2S_TX_R_FIFO_FULL (0x08000)
|
||||
#define I2S_TX_R_FIFO_ALMOST_EMPTY (0x10000)
|
||||
#define I2S_TX_R_FIFO_EMPTY (0x20000)
|
||||
#define I2S_ALL_FIFO_STATUS (0x3FFFF)
|
||||
/* FIFO Status end */
|
||||
|
||||
/* I2S Mode */
|
||||
typedef enum
|
||||
{
|
||||
I2S_MODE_MASTER,
|
||||
I2S_MODE_SLAVE,
|
||||
}enum_I2S_Mode_t;
|
||||
|
||||
/* I2S Standard */
|
||||
typedef enum
|
||||
{
|
||||
I2S_STANDARD_PHILIPS,
|
||||
I2S_STANDARD_MSB,
|
||||
I2S_STANDARD_LSB,
|
||||
I2S_STANDARD_PCM,
|
||||
}enum_I2S_Standard_t;
|
||||
|
||||
/* I2S Data Format */
|
||||
typedef enum
|
||||
{
|
||||
I2S_DATA_FORMAT_8BIT,
|
||||
I2S_DATA_FORMAT_16BIT,
|
||||
I2S_DATA_FORMAT_20BIT,
|
||||
I2S_DATA_FORMAT_24BIT,
|
||||
I2S_DATA_FORMAT_32BIT,
|
||||
}enum_I2S_DataFormat_t;
|
||||
|
||||
/* I2S Audio Frequency */
|
||||
typedef enum
|
||||
{
|
||||
I2S_AUDIOFREQ_192000,
|
||||
I2S_AUDIOFREQ_96000,
|
||||
I2S_AUDIOFREQ_48000,
|
||||
I2S_AUDIOFREQ_44100,
|
||||
I2S_AUDIOFREQ_32000,
|
||||
I2S_AUDIOFREQ_22050,
|
||||
I2S_AUDIOFREQ_16000,
|
||||
I2S_AUDIOFREQ_11025,
|
||||
I2S_AUDIOFREQ_8000,
|
||||
}enum_I2S_Audio_Frequency_t;
|
||||
|
||||
/*
|
||||
* @brief I2S Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref enum_I2S_Mode_t */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the communication standard.
|
||||
This parameter can be a value of @ref enum_I2S_Standard_t */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format.
|
||||
This parameter can be a value of @ref enum_I2S_DataFormat_t */
|
||||
|
||||
uint32_t BCLKDIV; /*!< Specifies the clock dividor used to generate bclk.
|
||||
This parameter can be a even value of between 0x000 ~ 0xFFF. */
|
||||
|
||||
uint32_t ChannelLength; /*!< Specifies the channel length.
|
||||
This parameter can be a even value of between 0x000 ~ 0xFFF. */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
}struct_I2SInit_t;
|
||||
|
||||
/*
|
||||
* @brief PCM Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
#if defined(__ICCARM__)
|
||||
uint32_t dummy; /* used to avoid compile error in IAR */
|
||||
#endif
|
||||
}struct_PCMInit_t;
|
||||
|
||||
/*
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
typedef struct __I2S_HandleTypeDef
|
||||
{
|
||||
struct_I2S_t *I2Sx; /*!< I2S registers base address */
|
||||
|
||||
struct_I2SInit_t Init; /*!< I2S communication parameters */
|
||||
|
||||
struct_PCMInit_t PCM_Init; /*!< PCM communication parameters */
|
||||
|
||||
volatile bool b_TxBusy;
|
||||
void (*TxIntCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< Tx Interrupt Callback */
|
||||
|
||||
volatile bool b_RxBusy;
|
||||
void (*RxIntCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< Rx Interrupt Callback */
|
||||
|
||||
}I2S_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* I2s and PCM Enable/Disable */
|
||||
#define __I2S_ENABLE(__I2Sx__) (__I2Sx__->CTRL1.I2S_EN = 1)
|
||||
#define __I2S_DISABLE(__I2Sx__) (__I2Sx__->CTRL1.I2S_EN = 0)
|
||||
|
||||
#define __I2S_PCM_ENABLE(__I2Sx__) do{ __I2Sx__->PCM_GENCTRL.PCM_PLL_EN = 1; \
|
||||
__I2Sx__->PCM_GENCTRL.PCM_EN = 1;}while(0)
|
||||
|
||||
#define __I2S_PCM_DISABLE(__I2Sx__) do{ __I2Sx__->PCM_GENCTRL.PCM_PLL_EN = 0; \
|
||||
__I2Sx__->PCM_GENCTRL.PCM_EN = 0;}while(0)
|
||||
|
||||
/* RxFIFO/TxFIFO clear */
|
||||
#define __I2S_TxFIFO_CLR(__I2Sx__) do{ __I2Sx__->CTRL0.TXFF_R_CLR = 1; \
|
||||
__I2Sx__->CTRL0.TXFF_L_CLR = 1;}while(0)
|
||||
|
||||
#define __I2S_RxFIFO_CLR(__I2Sx__) do{ __I2Sx__->CTRL0.RXFF_R_CLR = 1; \
|
||||
__I2Sx__->CTRL0.RXFF_L_CLR = 1;}while(0)
|
||||
|
||||
/* TxFIFO/RxFIFO enable */
|
||||
#define __I2S_TxFIFO_EN(__I2Sx__) do{ __I2Sx__->CTRL0.TXFF_L_EN = 1; \
|
||||
__I2Sx__->CTRL0.TXFF_R_EN = 1; }while(0)
|
||||
|
||||
#define __I2S_RxFIFO_EN(__I2Sx__) do{ __I2Sx__->CTRL0.RXFF_L_EN = 1; \
|
||||
__I2Sx__->CTRL0.RXFF_R_EN = 1;}while(0)
|
||||
|
||||
/* TxFIFO Data from sbcdecode or cpu*/
|
||||
#define __I2S_TXFIFO_SOURCE_SBC_DECODE(__I2Sx__) (__I2Sx__->CTRL0.SBC_ACCESS = 1)
|
||||
#define __I2S_TXFIFO_SOURCE_CPU(__I2Sx__) (__I2Sx__->CTRL0.SBC_ACCESS = 0)
|
||||
|
||||
/* enable channels Operate Simultaneously*/
|
||||
#define __I2S_LR_WD_ENABLE(__I2Sx__) (__I2Sx__->CTRL0.LR_WD_EN = 1)
|
||||
#define __I2S_LR_WD_DISABLE(__I2Sx__) (__I2Sx__->CTRL0.LR_WD_EN = 0)
|
||||
|
||||
#define __I2S_WD_SWAP_HIGH16SIZE_RIGHT(__I2Sx__) (__I2Sx__->CTRL0.LR_WD_SWAP = 1)
|
||||
#define __I2S_WD_SWAP_HIGH16SIZE_LEFT(__I2Sx__) (__I2Sx__->CTRL0.LR_WD_SWAP = 0)
|
||||
|
||||
/* Status interrupt enable and disable */
|
||||
#define __I2S_INT_ENABLE(__I2Sx__, __STATUS__) do{ __I2Sx__->CTRL0.INTEN = 1; \
|
||||
__I2Sx__->INT_STATUS_EN |= __STATUS__;}while(0)
|
||||
|
||||
#define __I2S_INT_DISABLE(__I2Sx__, __STATUS__) do{ __I2Sx__->CTRL0.INTEN = 0; \
|
||||
__I2Sx__->INT_STATUS_EN &= ~__STATUS__;}while(0)
|
||||
|
||||
#define __I2S_INT_IS_ENANLE(__I2Sx__, __STATUS__) (__I2Sx__->INT_STATUS_EN & __STATUS__)
|
||||
|
||||
/* Get interrupt status */
|
||||
#define __I2S_GET_INT_STATUS(__I2Sx__) (__I2Sx__->INT_STATUS)
|
||||
|
||||
/* Left/Right Rxfifo txfifo full/empty level */
|
||||
#define __I2S_L_RxFIFO_FULL_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_L.RXFF_AFULL = __LEVEL__)
|
||||
#define __I2S_L_RxFIFO_EMPTY_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_L.RXFF_AEMPTY = __LEVEL__)
|
||||
#define __I2S_L_TxFIFO_FULL_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_L.TXFF_AFULL = __LEVEL__)
|
||||
#define __I2S_L_TxFIFO_EMPTY_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_L.TXFF_AEMPTY = __LEVEL__)
|
||||
|
||||
#define __I2S_R_RxFIFO_FULL_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_R.RXFF_AFULL = __LEVEL__)
|
||||
#define __I2S_R_RxFIFO_EMPTY_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_R.RXFF_AEMPTY = __LEVEL__)
|
||||
#define __I2S_R_TxFIFO_FULL_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_R.TXFF_AFULL = __LEVEL__)
|
||||
#define __I2S_R_TxFIFO_EMPTY_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->FIFO_CFG_R.TXFF_AEMPTY = __LEVEL__)
|
||||
|
||||
/* BCLK Inverted Output */
|
||||
#define __I2S_BCLK_INV_ENABLE(__I2Sx__) (__I2Sx__->CTRL1.I2S_BCLKINV = 1)
|
||||
#define __I2S_BCLK_INV_DISABLE(__I2Sx__) (__I2Sx__->CTRL1.I2S_BCLKINV = 0)
|
||||
|
||||
/* Frame Inverted Output */
|
||||
#define __I2S_FRAME_INV_ENABLE(__I2Sx__) (__I2Sx__->CTRL1.I2S_FRMINV = 1)
|
||||
#define __I2S_FRAME_INV_DISABLE(__I2Sx__) (__I2Sx__->CTRL1.I2S_FRMINV = 0)
|
||||
|
||||
/* PCMCLK Inverted Output */
|
||||
#define __I2S_PCMCLK_INV_ENABLE(__I2Sx__) (__I2Sx__->PCM_GENCTRL.PCM_CLKINV = 1)
|
||||
#define __I2S_PCMCLK_INV_DISABLE(__I2Sx__) (__I2Sx__->PCM_GENCTRL.PCM_CLKINV = 0)
|
||||
|
||||
/* PCM SLOTS SET */
|
||||
#define __I2S_PCM_SLOTS_SET(__I2Sx__, __LEVEL__) (__I2Sx__->PCM_RHYCTRL.PCM_SLOTNB = __LEVEL__)
|
||||
#define __I2S_PCM_FIRSTSLOTS_SET(__I2Sx__, __CONFIGURE__) (__I2Sx__->PCM_RHYCTRL.PCM_FIRSTACTSLOT = __CONFIGURE__)
|
||||
|
||||
/* PCM SAMPLE SIZE SELECT */
|
||||
#define __I2S_PCM_SAMPLESIZE_8BIT(__I2Sx__) (__I2Sx__->PCM_RHYCTRL.PCM_SAMPSZ = 0)
|
||||
#define __I2S_PCM_SAMPLESIZE_16BIT(__I2Sx__) (__I2Sx__->PCM_RHYCTRL.PCM_SAMPSZ = 1)
|
||||
|
||||
/* DMA Request Level */
|
||||
#define __I2S_TX_DMA_EMPTY_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->DMA_CFG.DMATDLR = __LEVEL__)
|
||||
#define __I2S_RX_DMA_EMPTY_LEVEL(__I2Sx__, __LEVEL__) (__I2Sx__->DMA_CFG.DMARDLR = __LEVEL__)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* i2s_init */
|
||||
void i2s_init(I2S_HandleTypeDef *hi2s);
|
||||
/* i2s_init */
|
||||
void i2s_deinit(I2S_HandleTypeDef *hi2s);
|
||||
/* i2s_transmit_IT */
|
||||
bool i2s_transmit_IT(I2S_HandleTypeDef *hi2s);
|
||||
/* i2s_receive_IT */
|
||||
bool i2s_receive_IT(I2S_HandleTypeDef *hi2s);
|
||||
/* i2s_IRQHandler */
|
||||
void i2s_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
/* i2s_read_data */
|
||||
uint32_t i2s_read_data(I2S_HandleTypeDef *hi2s, uint32_t *buffer, uint32_t samples);
|
||||
/* i2s_send_data */
|
||||
uint32_t i2s_send_data(I2S_HandleTypeDef *hi2s, uint32_t *buffer, uint32_t samples);
|
||||
/* i2s_transmit_DMA */
|
||||
void i2s_transmit_DMA(I2S_HandleTypeDef *hi2s);
|
||||
/* i2s_receive_DMA */
|
||||
void i2s_receive_DMA(I2S_HandleTypeDef *hi2s);
|
||||
#endif
|
||||
152
fr3092_mcu/components/drivers/peripheral/Inc/driver_iir.h
Normal file
152
fr3092_mcu/components/drivers/peripheral/Inc/driver_iir.h
Normal file
@ -0,0 +1,152 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_iir.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of IIR module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_IIR_H__
|
||||
#define __DRIVER_IIR_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup IIR_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* IIR CTRL */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t N_DIV : 7;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t ORDER_SEL : 2;
|
||||
uint32_t rsv_1 : 6;
|
||||
uint32_t NODE_SEL : 2;
|
||||
uint32_t rsv_2 : 6;
|
||||
uint32_t NBYTE_SEL : 2;
|
||||
uint32_t ESV4 : 6;
|
||||
} REG_IIR_CTRL_t;
|
||||
|
||||
|
||||
/* IIR THR FIFO */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t THR_TX_FIFO : 6;
|
||||
uint32_t rsv_0 : 10;
|
||||
uint32_t THR_RX_FIFO : 6;
|
||||
uint32_t rsv_1 : 10;
|
||||
} REG_IIR_THR_FIFO_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t IIR_COEF[20]; /* Offser 0x00-0x4c*/
|
||||
volatile REG_IIR_CTRL_t IIR_CTRL; /* Offset 0x50*/
|
||||
volatile REG_IIR_THR_FIFO_t IIR_THR_FIFO; /* Offset 0x54*/
|
||||
volatile uint32_t rsv_0;
|
||||
volatile uint32_t rsv_1;
|
||||
volatile uint32_t IIR_SOFTRST; /* Offset 0x60*/
|
||||
volatile uint32_t rsv_2[5];
|
||||
volatile uint32_t IIR_STATUS; /* Offset 0x78*/
|
||||
volatile uint32_t rsv_3;
|
||||
volatile uint32_t IIR_FIFO; /* Offset 0x80*/
|
||||
}struct_IIR_t;
|
||||
|
||||
#define IIR_FILTER ((struct_IIR_t *)IIR_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IIR_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization_Config Section Start ################################ */
|
||||
|
||||
/* FIFO Status */
|
||||
typedef enum
|
||||
{
|
||||
TX_FIFO_FULL = 0x01,
|
||||
TX_FIFO_EMPTY = 0x02,
|
||||
TX_FIFO_AL_EMPTY = 0x04,
|
||||
RX_FIFO_FULL = 0x08,
|
||||
RX_FIFO_EMPTY = 0x10,
|
||||
RX_FIFO_AL_FULL = 0x20,
|
||||
}enum_IIR_INT_Index_t;
|
||||
|
||||
/* Nbytes Select */
|
||||
typedef enum{
|
||||
IIR_BYTE_1,
|
||||
IIR_BYTE_2,
|
||||
IIR_BYTE_3,
|
||||
IIR_BYTE_ALL,
|
||||
}enum_Nbytes_sel_t;
|
||||
|
||||
/* Node Select */
|
||||
typedef enum{
|
||||
THE_FIRST_STAGE_OUTPUT,
|
||||
THE_SENCOND_STAGE_OUTPUT,
|
||||
THE_THIRD_STAGE_OUTPUT,
|
||||
THE_FOURTH_STAGE_OUTPUT,
|
||||
}enum_Node_Sel_t;
|
||||
|
||||
/* Order Select */
|
||||
typedef enum{
|
||||
ORDER_2,
|
||||
ORDER_4,
|
||||
ORDER_6,
|
||||
ORDER_8,
|
||||
}enum_Order_Sel_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IIRCoef[20]; /*!< Specifies the internal Feedback coefficient.
|
||||
This parameter The value can be a value 0~0xFFFFFF*/
|
||||
|
||||
uint8_t N_Div; /*!< Specifies the internal read/write tx and rx FIFO is relative The frequency division factor of the system clock.
|
||||
This parameter The value should be greater than 2*(order_sel + 1)*5 */
|
||||
|
||||
uint8_t Order_Sel; /*!< Specifies the internal Filter order configuration.
|
||||
This parameter can be a value of @ref enum_Order_Sel_t */
|
||||
|
||||
uint8_t Node_Sel; /*!< Specifies the internal Filter order configuration.
|
||||
This parameter can be a value of @ref enum_Node_Sel_t */
|
||||
|
||||
uint8_t Nbytes_Sel; /*!< Specifies the internal Filter order configuration.
|
||||
This parameter can be a value of @ref enum_Nbytes_sel_t */
|
||||
|
||||
}IIR_InitTypeDef;
|
||||
|
||||
/* ################################ Initialization_Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* RxFIFO/TxFIFO Threshold level */
|
||||
#define __IIR_RxFIFO_THRESHOLD_LEVEL(__LEVEL__) (IIR_FILTER->IIR_THR_FIFO.THR_RX_FIFO = __LEVEL__)
|
||||
#define __IIR_TxFIFO_THRESHOLD_LEVEL(__LEVEL__) (IIR_FILTER->IIR_THR_FIFO.THR_TX_FIFO = __LEVEL__)
|
||||
|
||||
/* SOFTRST Set and Clear */
|
||||
#define __IIR_SOFTRST_SET() (IIR_FILTER->IIR_SOFTRST = 0)
|
||||
#define __IIR_SOFTRST_CLEAR() (IIR_FILTER->IIR_SOFTRST = 1)
|
||||
|
||||
/* Get FIFO status */
|
||||
#define __IIR_GET_FIFO_STATUS(__STATUS__) (IIR_FILTER->IIR_STATUS & __STATUS__)
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/* iir_init */
|
||||
void iir_init(IIR_InitTypeDef *hiir);
|
||||
/* iir_filter_start */
|
||||
void iir_filter_start(uint32_t *fp_Data_In, uint32_t *fp_Data_Out, uint32_t fu32_Size);
|
||||
|
||||
#endif
|
||||
936
fr3092_mcu/components/drivers/peripheral/Inc/driver_iomux.h
Normal file
936
fr3092_mcu/components/drivers/peripheral/Inc/driver_iomux.h
Normal file
@ -0,0 +1,936 @@
|
||||
/**
|
||||
* Copyright (c) 2019, Freqchip
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
*/
|
||||
#ifndef DRIVER_IOMUX_H
|
||||
#define DRIVER_IOMUX_H
|
||||
|
||||
/**********************************************************************************************************************************
|
||||
PX/MUX 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'ha
|
||||
PORTA0 gpio_a0 I2C0_CLK I2S_CLK PWM0 SSP0_CLK UART0_RXD UART1_RXD CLK_OUT PDM_CLK
|
||||
PORTA1 gpio_a1 I2C0_DAT I2S_FRM PWM1 SSP0_CSN UART0_TXD UART1_TXD ant_ctl[0] PDM_DATA
|
||||
PORTA2 gpio_a2 I2C1_CLK I2S_DOUT PWM2 SSP0_DOUT UART0_RXD UART1_RXD ant_ctl[0] PDM_CLK
|
||||
PORTA3 gpio_a3 I2C1_DAT I2S_DIN PWM3 SSP0_DIN UART0_TXD UART1_TXD ant_ctl[1] PDM_DATA
|
||||
PORTA4 gpio_a4 I2C0_CLK I2S_CLK PWM4 SSP0_CLK UART0_RXD UART1_RXD CLK_OUT PDM_CLK
|
||||
PORTA5 gpio_a5 I2C0_DAT I2S_FRM PWM5 SSP0_CSN UART0_TXD UART1_TXD ant_ctl[1] PDM_DATA
|
||||
PORTA6 gpio_a6 I2C1_CLK I2S_DOUT PWM0 SSP0_DOUT UART0_RXD UART1_RXD CLK_OUT PDM_CLK
|
||||
PORTA7 gpio_a7 I2C1_DAT I2S_DIN PWM1 SSP0_DIN UART0_TXD UART1_TXD ant_ctl[0] PDM_DATA
|
||||
|
||||
PORTB0 gpio_b0 I2C0_CLK I2S_CLK PWM0 SSP0_CLK UART0_RXD UART1_RXD ble_tx PDM_CLK
|
||||
PORTB1 gpio_b1 I2C0_DAT I2S_FRM PWM1 SSP0_CSN UART0_TXD UART1_TXD ble_rx PDM_DATA
|
||||
PORTB2 gpio_b2 I2C1_CLK I2S_DOUT PWM2 SSP0_DOUT UART0_RXD UART1_RXD wlan_tx/in PDM_CLK
|
||||
PORTB3 gpio_b3 I2C1_DAT I2S_DIN PWM3 SSP0_DIN UART0_TXD UART1_TXD wlan_rx/in PDM_DATA
|
||||
PORTB4 gpio_b4 I2C0_CLK I2S_CLK PWM4 SSP0_CLK UART0_RXD UART1_RXD CLK_OUT PDM_CLK
|
||||
PORTB5 gpio_b5 I2C0_DAT I2S_FRM PWM5 SSP0_CSN UART0_TXD UART1_TXD ant_ctl[0] PDM_DATA
|
||||
PORTB6 gpio_b6 I2C1_CLK I2S_DOUT PWM2 SSP0_DOUT UART0_RXD UART1_RXD ant_ctl[1] PDM_CLK
|
||||
PORTB7 gpio_b7 I2C1_DAT I2S_DIN PWM3 SSP0_DIN UART0_TXD UART1_TXD CLK_OUT PDM_DATA
|
||||
|
||||
PORTC0 gpio_c0 I2C0_CLK I2S_CLK PWM0 SSP0_CLK UART0_RXD UART1_RXD SWV PDM_CLK
|
||||
PORTC1 gpio_c1 I2C0_DAT I2S_FRM PWM1 SSP0_CSN UART0_TXD UART1_TXD SWV PDM_DATA
|
||||
PORTC2 gpio_c2 I2C1_CLK I2S_DOUT PWM2 SSP0_DOUT UART0_RXD UART1_RXD SWV PDM_CLK
|
||||
PORTC3 gpio_c3 I2C1_DAT I2S_DIN PWM3 SSP0_DIN UART0_TXD UART1_TXD SWV PDM_DATA
|
||||
PORTC4 gpio_c4 I2C0_CLK I2S_CLK PWM4 SSP0_CLK UART0_RXD UART1_RXD ant_ctl[1] PDM_CLK
|
||||
PORTC5 gpio_c5 I2C0_DAT I2S_FRM PWM5 SSP0_CSN UART0_TXD UART1_TXD SWV PDM_DATA
|
||||
PORTC6 gpio_c6 I2C1_CLK I2S_DOUT PWM4 SSP0_DOUT UART0_RXD UART1_RXD SW_TCK PDM_CLK
|
||||
PORTC7 gpio_c7 I2C1_DAT I2S_DIN PWM5 SSP0_DIN UART0_TXD UART1_TXD SW_DIO PDM_DATA
|
||||
|
||||
PORTD0 gpio_d0 I2C0_CLK I2S_CLK PWM0 SSP0_CLK UART0_RXD UART1_RXD ble_tx PDM_CLK
|
||||
PORTD1 gpio_d1 I2C0_DAT I2S_FRM PWM1 SSP0_CSN UART0_TXD UART1_TXD ble_rx PDM_DATA
|
||||
PORTD2 gpio_d2 I2C1_CLK I2S_DOUT PWM2 SSP0_DOUT UART0_RXD UART1_RXD wlan_tx/in PDM_CLK
|
||||
PORTD3 gpio_d3 I2C1_DAT I2S_DIN PWM3 SSP0_DIN UART0_TXD UART1_TXD wlan_rx/in PDM_DATA
|
||||
PORTD4 gpio_d4 I2C0_CLK I2S_CLK PWM4 SSP0_CLK UART0_RXD UART1_RXD ant_ctl[0] PDM_CLK ADC0
|
||||
PORTD5 gpio_d5 I2C0_DAT I2S_FRM PWM5 SSP0_CSN UART0_TXD UART1_TXD ant_ctl[0] PDM_DATA ADC1
|
||||
PORTD6 gpio_d6 I2C1_CLK I2S_DOUT PWM0 SSP0_DOUT UART0_RXD UART1_RXD CLK_OUT PDM_CLK ADC2
|
||||
PORTD7 gpio_d7 I2C1_DAT I2S_DIN PWM1 SSP0_DIN UART0_TXD UART1_TXD ant_ctl[1] PDM_DATA ADC3
|
||||
|
||||
*************************************************************************************************************************************/
|
||||
#if 1
|
||||
#define PORTA0_FUNC_A0 0x00
|
||||
#define PORTA0_FUNC_CM0_A0 0x01
|
||||
#define PORTA0_FUNC_CM0_UART_RXD 0x02
|
||||
#define PORTA0_FUNC_UART0_RXD 0x03
|
||||
#define PORTA0_FUNC_SPIM0_CLK 0x04
|
||||
#define PORTA0_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTA0_FUNC_PDM0_CLK 0x06
|
||||
#define PORTA0_FUNC_I2C0_CLK 0x07
|
||||
#define PORTA0_FUNC_PWM0 0x08
|
||||
#define PORTA0_FUNC_TIM0_PAUSE 0x09
|
||||
|
||||
#define PORTA1_FUNC_A1 0x00
|
||||
#define PORTA1_FUNC_CM0_A1 0x01
|
||||
#define PORTA1_FUNC_CM0_UART_TXD 0x02
|
||||
#define PORTA1_FUNC_UART0_TXD 0x03
|
||||
#define PORTA1_FUNC_SPIM0_CSN 0x04
|
||||
#define PORTA1_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTA1_FUNC_PDM0_SDA 0x06
|
||||
#define PORTA1_FUNC_I2C0_SDA 0x07
|
||||
#define PORTA1_FUNC_PWM1 0x08
|
||||
#define PORTA1_FUNC_TIM1_PAUSE 0x09
|
||||
|
||||
#define PORTA2_FUNC_A2 0x00
|
||||
#define PORTA2_FUNC_CM0_A2 0x01
|
||||
#define PORTA2_FUNC_CM0_I2C_CLK 0x02
|
||||
#define PORTA2_FUNC_UART2_RXD 0x03
|
||||
#define PORTA2_FUNC_SPIM0_MOSI 0x04
|
||||
#define PORTA2_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTA2_FUNC_PDM1_CLK 0x06
|
||||
#define PORTA2_FUNC_I2C1_CLK 0x07
|
||||
#define PORTA2_FUNC_PWM2 0x08
|
||||
#define PORTA2_FUNC_TIM0_TOG 0x09
|
||||
#define PORTA2_FUNC_SPIM8_0_IO0 0x0A
|
||||
|
||||
#define PORTA3_FUNC_A3 0x00
|
||||
#define PORTA3_FUNC_CM0_A3 0x01
|
||||
#define PORTA3_FUNC_CM0_I2C_SDA 0x02
|
||||
#define PORTA3_FUNC_UART2_TXD 0x03
|
||||
#define PORTA3_FUNC_SPIM0_MISO 0x04
|
||||
#define PORTA3_FUNC_SPIS0_MISO 0x05
|
||||
#define PORTA3_FUNC_PDM1_SDA 0x06
|
||||
#define PORTA3_FUNC_I2C1_SDA 0x07
|
||||
#define PORTA3_FUNC_PWM3 0x08
|
||||
#define PORTA3_FUNC_TIM1_TOG 0x09
|
||||
#define PORTA3_FUNC_SPIM8_0_IO1 0x0A
|
||||
|
||||
#define PORTA4_FUNC_A4 0x00
|
||||
#define PORTA4_FUNC_CM0_A0 0x01
|
||||
#define PORTA4_FUNC_CM0_SPI_CLK 0x02
|
||||
#define PORTA4_FUNC_UART2_CTS 0x03
|
||||
#define PORTA4_FUNC_SPIM1_CLK 0x04
|
||||
#define PORTA4_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTA4_FUNC_PDM0_CLK 0x06
|
||||
#define PORTA4_FUNC_I2C0_CLK 0x07
|
||||
#define PORTA4_FUNC_PWM4 0x08
|
||||
#define PORTA4_FUNC_TIM0_PAUSE 0x09
|
||||
#define PORTA4_FUNC_SPIM8_0_IO2 0x0A
|
||||
|
||||
#define PORTA5_FUNC_A5 0x00
|
||||
#define PORTA5_FUNC_CM0_A1 0x01
|
||||
#define PORTA5_FUNC_CM0_SPI_CSN 0x02
|
||||
#define PORTA5_FUNC_UART2_RTS 0x03
|
||||
#define PORTA5_FUNC_SPIM1_CSN 0x04
|
||||
#define PORTA5_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTA5_FUNC_PDM0_SDA 0x06
|
||||
#define PORTA5_FUNC_I2C0_SDA 0x07
|
||||
#define PORTA5_FUNC_PWM5 0x08
|
||||
#define PORTA5_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTA5_FUNC_SPIM8_0_IO3 0x0A
|
||||
|
||||
#define PORTA6_FUNC_A6 0x00
|
||||
#define PORTA6_FUNC_CM0_A2 0x01
|
||||
#define PORTA6_FUNC_CM0_SPI_MOSI 0x02
|
||||
#define PORTA6_FUNC_UART0_RXD 0x03
|
||||
#define PORTA6_FUNC_SPIM1_MOSI 0x04
|
||||
#define PORTA6_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTA6_FUNC_PDM1_CLK 0x06
|
||||
#define PORTA6_FUNC_I2C1_CLK 0x07
|
||||
#define PORTA6_FUNC_PWM6 0x08
|
||||
#define PORTA6_FUNC_TIM0_TOG 0x09
|
||||
#define PORTA6_FUNC_SPIM8_0_CLK 0x0A
|
||||
|
||||
#define PORTA7_FUNC_A7 0x00
|
||||
#define PORTA7_FUNC_CM0_A3 0x01
|
||||
#define PORTA7_FUNC_CM0_SPI_MIS0 0x02
|
||||
#define PORTA7_FUNC_UART0_TXD 0x03
|
||||
#define PORTA7_FUNC_SPIM1_MISO 0x04
|
||||
#define PORTA7_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTA7_FUNC_PDM1_SDA 0x06
|
||||
#define PORTA7_FUNC_I2C1_SDA 0x07
|
||||
#define PORTA7_FUNC_PWM7 0x08
|
||||
#define PORTA7_FUNC_TIM1_TOG 0x09
|
||||
#define PORTA7_FUNC_SPIM8_0_CSN 0x0A
|
||||
|
||||
#define PORTB0_FUNC_B0 0x00
|
||||
#define PORTB0_FUNC_CM0_A0 0x01
|
||||
#define PORTB0_FUNC_CM0_UART_RXD 0x02
|
||||
#define PORTB0_FUNC_UART0_RXD 0x03
|
||||
#define PORTB0_FUNC_SPIM1_CLK 0x04
|
||||
#define PORTB0_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTB0_FUNC_PDM0_CLK 0x06
|
||||
#define PORTB0_FUNC_I2C0_CLK 0x07
|
||||
#define PORTB0_FUNC_PWM0 0x08
|
||||
#define PORTB0_FUNC_TIM0_PAUSE 0x09
|
||||
#define PORTB0_FUNC_SPIM8_0_IO0 0x0A
|
||||
#define PORTB0_FUNC_PSRAM_QSPI_MIO0 0x0B
|
||||
|
||||
#define PORTB1_FUNC_B1 0x00
|
||||
#define PORTB1_FUNC_CM0_A1 0x01
|
||||
#define PORTB1_FUNC_CM0_UART_TXD 0x02
|
||||
#define PORTB1_FUNC_UART0_TXD 0x03
|
||||
#define PORTB1_FUNC_SPIM1_CSN 0x04
|
||||
#define PORTB1_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTB1_FUNC_PDM0_SDA 0x06
|
||||
#define PORTB1_FUNC_I2C0_SDA 0x07
|
||||
#define PORTB1_FUNC_PWM1 0x08
|
||||
#define PORTB1_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTB1_FUNC_SPIM8_0_IO1 0x0A
|
||||
#define PORTB1_FUNC_PSRAM_QSPI_MIO1 0x0B
|
||||
|
||||
#define PORTB2_FUNC_B2 0x00
|
||||
#define PORTB2_FUNC_CM0_A2 0x01
|
||||
#define PORTB2_FUNC_CM0_I2C_CLK 0x02
|
||||
#define PORTB2_FUNC_UART2_RXD 0x03
|
||||
#define PORTB2_FUNC_SPIM1_MOSI 0x04
|
||||
#define PORTB2_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTB2_FUNC_PDM1_CLK 0x06
|
||||
#define PORTB2_FUNC_I2C1_CLK 0x07
|
||||
#define PORTB2_FUNC_PWM2 0x08
|
||||
#define PORTB2_FUNC_TIM0_TOG 0x09
|
||||
#define PORTB2_FUNC_SPIM8_0_IO2 0x0A
|
||||
#define PORTB2_FUNC_PSRAM_QSPI_MIO2 0x0B
|
||||
|
||||
#define PORTB3_FUNC_B3 0x00
|
||||
#define PORTB3_FUNC_CM0_A3 0x01
|
||||
#define PORTB3_FUNC_CM0_I2C_SDA 0x02
|
||||
#define PORTB3_FUNC_UART2_TXD 0x03
|
||||
#define PORTB3_FUNC_SPIM1_MISO 0x04
|
||||
#define PORTB3_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTB3_FUNC_PDM1_SDA 0x06
|
||||
#define PORTB3_FUNC_I2C1_SDA 0x07
|
||||
#define PORTB3_FUNC_PWM3 0x08
|
||||
#define PORTB3_FUNC_TIM1_TOG 0x09
|
||||
#define PORTB3_FUNC_SPIM8_0_IO3 0x0A
|
||||
#define PORTB3_FUNC_PSRAM_QSPI_MIO3 0x0B
|
||||
|
||||
#define PORTB4_FUNC_B4 0x00
|
||||
#define PORTB4_FUNC_CM0_A0 0x01
|
||||
#define PORTB4_FUNC_CM0_SPI_CLK 0x02
|
||||
#define PORTB4_FUNC_UART2_CTS 0x03
|
||||
#define PORTB4_FUNC_SPIM0_CLK 0x04
|
||||
#define PORTB4_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTB4_FUNC_PDM0_CLK 0x06
|
||||
#define PORTB4_FUNC_I2C0_CLK 0x07
|
||||
#define PORTB4_FUNC_PWM4 0x08
|
||||
#define PORTB4_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTB4_FUNC_SPIM8_0_IO4 0x0A
|
||||
#define PORTB4_FUNC_PSRAM_QSPI_MIO4 0x0B
|
||||
|
||||
#define PORTB5_FUNC_B5 0x00
|
||||
#define PORTB5_FUNC_CM0_A1 0x01
|
||||
#define PORTB5_FUNC_CM0_SPI_CSN 0x02
|
||||
#define PORTB5_FUNC_UART2_RTS 0x03
|
||||
#define PORTB5_FUNC_SPIM0_CSN 0x04
|
||||
#define PORTB5_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTB5_FUNC_PDM0_SDA 0x06
|
||||
#define PORTB5_FUNC_I2C0_SDA 0x07
|
||||
#define PORTB5_FUNC_PWM5 0x08
|
||||
#define PORTB5_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTB5_FUNC_SPIM8_0_IO5 0x0A
|
||||
#define PORTB5_FUNC_PSRAM_QSPI_MIO5 0x0B
|
||||
|
||||
#define PORTB6_FUNC_B6 0x00
|
||||
#define PORTB6_FUNC_CM0_A2 0x01
|
||||
#define PORTB6_FUNC_CM0_SPI_MOSI 0x02
|
||||
#define PORTB6_FUNC_UART0_RXD 0x03
|
||||
#define PORTB6_FUNC_SPIM0_MOSI 0x04
|
||||
#define PORTB6_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTB6_FUNC_PDM1_CLK 0x06
|
||||
#define PORTB6_FUNC_I2C1_CLK 0x07
|
||||
#define PORTB6_FUNC_PWM6 0x08
|
||||
#define PORTB6_FUNC_TIM0_TOG 0x09
|
||||
#define PORTB6_FUNC_SPIM8_0_IO6 0x0A
|
||||
#define PORTB6_FUNC_PSRAM_QSPI_MIO6 0x0B
|
||||
|
||||
#define PORTB7_FUNC_B7 0x00
|
||||
#define PORTB7_FUNC_CM0_A3 0x01
|
||||
#define PORTB7_FUNC_CM0_SPI_MISO 0x02
|
||||
#define PORTB7_FUNC_UART0_TXD 0x03
|
||||
#define PORTB7_FUNC_SPIM0_MISO 0x04
|
||||
#define PORTB7_FUNC_SPIS0_MISO 0x05
|
||||
#define PORTB7_FUNC_PDM1_SDA 0x06
|
||||
#define PORTB7_FUNC_I2C1_SDA 0x07
|
||||
#define PORTB7_FUNC_PWM7 0x08
|
||||
#define PORTB7_FUNC_TIM1_TOG 0x09
|
||||
#define PORTB7_FUNC_SPIM8_0_IO7 0x0A
|
||||
#define PORTB7_FUNC_PSRAM_QSPI_MIO7 0x0B
|
||||
|
||||
#define PORTC0_FUNC_C0 0x00
|
||||
#define PORTC0_FUNC_CM0_A0 0x01
|
||||
#define PORTC0_FUNC_CM0_SWCK 0x02
|
||||
#define PORTC0_FUNC_UART0_RXD 0x03
|
||||
#define PORTC0_FUNC_SPIM0_CLK 0x04
|
||||
#define PORTC0_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTC0_FUNC_PDM0_CLK 0x06
|
||||
#define PORTC0_FUNC_I2C0_CLK 0x07
|
||||
#define PORTC0_FUNC_PWM0 0x08
|
||||
#define PORTC0_FUNC_TIM0_PAUSE 0x09
|
||||
#define PORTC0_FUNC_SPIM8_0_CLK 0x0A
|
||||
#define PORTC0_FUNC_PSRAM_QSPI_CLK 0x0B
|
||||
|
||||
#define PORTC1_FUNC_C1 0x00
|
||||
#define PORTC1_FUNC_CM0_A1 0x01
|
||||
#define PORTC1_FUNC_CM0_SWIO 0x02
|
||||
#define PORTC1_FUNC_UART0_TXD 0x03
|
||||
#define PORTC1_FUNC_SPIM0_CSN 0x04
|
||||
#define PORTC1_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTC1_FUNC_PDM0_SDA 0x06
|
||||
#define PORTC1_FUNC_I2C0_SDA 0x07
|
||||
#define PORTC1_FUNC_PWM1 0x08
|
||||
#define PORTC1_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTC1_FUNC_SPIM8_0_CSN 0x0A
|
||||
#define PORTC1_FUNC_PSRAM_QSPI_N_SS 0x0B
|
||||
|
||||
#define PORTC2_FUNC_C2 0x00
|
||||
#define PORTC2_FUNC_CM0_A2 0x01
|
||||
#define PORTC2_FUNC_CM0_SWCK 0x02
|
||||
#define PORTC2_FUNC_UART2_RXD 0x03
|
||||
#define PORTC2_FUNC_SPIM0_MOSI 0x04
|
||||
#define PORTC2_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTC2_FUNC_PDM1_CLK 0x06
|
||||
#define PORTC2_FUNC_I2C1_CLK 0x07
|
||||
#define PORTC2_FUNC_PWM2 0x08
|
||||
#define PORTC2_FUNC_TIM0_TOG 0x09
|
||||
#define PORTC2_FUNC_SPIM8_0_IO0 0x0A
|
||||
#define PORTC2_FUNC_PSRAM_QSPI_MIO0 0x0B
|
||||
|
||||
#define PORTC3_FUNC_C3 0x00
|
||||
#define PORTC3_FUNC_CM0_A3 0x01
|
||||
#define PORTC3_FUNC_CM0_SWIO 0x02
|
||||
#define PORTC3_FUNC_UART2_TXD 0x03
|
||||
#define PORTC3_FUNC_SPIM0_MISO 0x04
|
||||
#define PORTC3_FUNC_SPIS0_MISO 0x05
|
||||
#define PORTC3_FUNC_PDM1_SDA 0x06
|
||||
#define PORTC3_FUNC_I2C1_SDA 0x07
|
||||
#define PORTC3_FUNC_PWM3 0x08
|
||||
#define PORTC3_FUNC_TIM1_TOG 0x09
|
||||
#define PORTC3_FUNC_SPIM8_0_IO1 0x0A
|
||||
#define PORTC3_FUNC_PSRAM_QSPI_MIO1 0x0B
|
||||
|
||||
#define PORTC4_FUNC_C4 0x00
|
||||
#define PORTC4_FUNC_CM0_A0 0x01
|
||||
#define PORTC4_FUNC_CM33_1_SWCK 0x02
|
||||
#define PORTC4_FUNC_UART2_CTS 0x03
|
||||
#define PORTC4_FUNC_SPIM1_CLK 0x04
|
||||
#define PORTC4_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTC4_FUNC_PDM0_CLK 0x06
|
||||
#define PORTC4_FUNC_I2C0_CLK 0x07
|
||||
#define PORTC4_FUNC_PWM4 0x08
|
||||
#define PORTC4_FUNC_TIM0_PAUSE 0x09
|
||||
#define PORTC4_FUNC_SPIM8_0_IO2 0x0A
|
||||
#define PORTC4_FUNC_PSRAM_QSPI_MIO2 0x0B
|
||||
|
||||
#define PORTC5_FUNC_C5 0x00
|
||||
#define PORTC5_FUNC_CM0_A1 0x01
|
||||
#define PORTC5_FUNC_CM33_1_SWIO 0x02
|
||||
#define PORTC5_FUNC_UART2_RTS 0x03
|
||||
#define PORTC5_FUNC_SPIM1_CSN 0x04
|
||||
#define PORTC5_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTC5_FUNC_PDM0_SDA 0x06
|
||||
#define PORTC5_FUNC_I2C0_SDA 0x07
|
||||
#define PORTC5_FUNC_PWM5 0x08
|
||||
#define PORTC5_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTC5_FUNC_SPIM8_0_IO3 0x0A
|
||||
#define PORTC5_FUNC_PSRAM_QSPI_MIO3 0x0B
|
||||
|
||||
#define PORTC6_FUNC_C6 0x00
|
||||
#define PORTC6_FUNC_CM0_A2 0x01
|
||||
#define PORTC6_FUNC_CM33_0_SWCK 0x02
|
||||
#define PORTC6_FUNC_UART0_RXD 0x03
|
||||
#define PORTC6_FUNC_SPIM1_MOSI 0x04
|
||||
#define PORTC6_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTC6_FUNC_PDM1_CLK 0x06
|
||||
#define PORTC6_FUNC_I2C1_CLK 0x07
|
||||
#define PORTC6_FUNC_PWM6 0x08
|
||||
#define PORTC6_FUNC_TIM0_TOG 0x09
|
||||
#define PORTC6_FUNC_SPIM8_0_CLK 0x0A
|
||||
#define PORTC6_FUNC_PSRAM_QSPI_CLK 0x0B
|
||||
|
||||
#define PORTC7_FUNC_C7 0x00
|
||||
#define PORTC7_FUNC_CM0_A3 0x01
|
||||
#define PORTC7_FUNC_CM33_0_SWIO 0x02
|
||||
#define PORTC7_FUNC_UART0_TXD 0x03
|
||||
#define PORTC7_FUNC_SPIM1_MISO 0x04
|
||||
#define PORTC7_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTC7_FUNC_PDM1_SDA 0x06
|
||||
#define PORTC7_FUNC_I2C1_SDA 0x07
|
||||
#define PORTC7_FUNC_PWM7 0x08
|
||||
#define PORTC7_FUNC_TIM1_TOG 0x09
|
||||
#define PORTC7_FUNC_SPIM8_0_CSN 0x0A
|
||||
#define PORTC7_FUNC_PSRAM_QSPI_N_SS 0x0B
|
||||
|
||||
#define PORTD0_FUNC_D0 0x00
|
||||
#define PORTD0_FUNC_CM0_A0 0x01
|
||||
#define PORTD0_FUNC_CM0_UART_RXD 0x02
|
||||
#define PORTD0_FUNC_UART0_RXD 0x03
|
||||
#define PORTD0_FUNC_SPIM1_CLK 0x04
|
||||
#define PORTD0_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTD0_FUNC_PDM0_CLK 0x06
|
||||
#define PORTD0_FUNC_I2C0_CLK 0x07
|
||||
#define PORTD0_FUNC_PWM0 0x08
|
||||
#define PORTD0_FUNC_TIM0_PAUSE 0x09
|
||||
#define PORTD0_FUNC_SPIM8_0_IO4 0x0A
|
||||
#define PORTD0_FUNC_PSRAM_QSPI_MIO0 0x0B
|
||||
|
||||
#define PORTD1_FUNC_D1 0x00
|
||||
#define PORTD1_FUNC_CM0_A1 0x01
|
||||
#define PORTD1_FUNC_CM0_UART_TXD 0x02
|
||||
#define PORTD1_FUNC_UART0_TXD 0x03
|
||||
#define PORTD1_FUNC_SPIM1_CSN 0x04
|
||||
#define PORTD1_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTD1_FUNC_PDM0_SDA 0x06
|
||||
#define PORTD1_FUNC_I2C0_SDA 0x07
|
||||
#define PORTD1_FUNC_PWM1 0x08
|
||||
#define PORTD1_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTD1_FUNC_SPIM8_0_IO5 0x0A
|
||||
#define PORTD1_FUNC_PSRAM_QSPI_MIO1 0x0B
|
||||
|
||||
#define PORTD2_FUNC_D2 0x00
|
||||
#define PORTD2_FUNC_CM0_A2 0x01
|
||||
#define PORTD2_FUNC_CM0_I2C_CLK 0x02
|
||||
#define PORTD2_FUNC_UART2_RXD 0x03
|
||||
#define PORTD2_FUNC_SPIM1_MOSI 0x04
|
||||
#define PORTD2_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTD2_FUNC_PDM1_CLK 0x06
|
||||
#define PORTD2_FUNC_I2C1_CLK 0x07
|
||||
#define PORTD2_FUNC_PWM2 0x08
|
||||
#define PORTD2_FUNC_TIM0_TOG 0x09
|
||||
#define PORTD2_FUNC_SPIM8_0_IO6 0x0A
|
||||
#define PORTD2_FUNC_PSRAM_QSPI_MIO2 0x0B
|
||||
|
||||
#define PORTD3_FUNC_D3 0x00
|
||||
#define PORTD3_FUNC_CM0_A3 0x01
|
||||
#define PORTD3_FUNC_CM0_I2C_SDA 0x02
|
||||
#define PORTD3_FUNC_UART2_TXD 0x03
|
||||
#define PORTD3_FUNC_SPIM1_MISO 0x04
|
||||
#define PORTD3_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTD3_FUNC_PDM1_SDA 0x06
|
||||
#define PORTD3_FUNC_I2C1_SDA 0x07
|
||||
#define PORTD3_FUNC_PWM3 0x08
|
||||
#define PORTD3_FUNC_TIM1_TOG 0x09
|
||||
#define PORTD3_FUNC_SPIM8_0_IO7 0x0A
|
||||
#define PORTD3_FUNC_PSRAM_QSPI_MIO3 0x0B
|
||||
|
||||
#define PORTD4_FUNC_D4 0x00
|
||||
#define PORTD4_FUNC_CM0_A0 0x01
|
||||
#define PORTD4_FUNC_CM0_SPI_CLK 0x02
|
||||
#define PORTD4_FUNC_UART2_CTS 0x03
|
||||
#define PORTD4_FUNC_SPIM0_CLK 0x04
|
||||
#define PORTD4_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTD4_FUNC_PDM0_CLK 0x06
|
||||
#define PORTD4_FUNC_I2C2_CLK 0x07
|
||||
#define PORTD4_FUNC_PWM4 0x08
|
||||
#define PORTD4_FUNC_TIM0_PAUSE 0x09
|
||||
#define PORTD4_FUNC_PSRAM_QSPI_MIO4 0x0B
|
||||
|
||||
#define PORTD5_FUNC_D5 0x00
|
||||
#define PORTD5_FUNC_CM0_A1 0x01
|
||||
#define PORTD5_FUNC_CM0_SPI_CSN 0x02
|
||||
#define PORTD5_FUNC_UART2_RTS 0x03
|
||||
#define PORTD5_FUNC_SPIM0_CSN 0x04
|
||||
#define PORTD5_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTD5_FUNC_PDM0_SDA 0x06
|
||||
#define PORTD5_FUNC_I2C2_SDA 0x07
|
||||
#define PORTD5_FUNC_PWM5 0x08
|
||||
#define PORTD5_FUNC_TIM1_PAUSE 0x09
|
||||
#define PORTD5_FUNC_PSRAM_QSPI_MIO5 0x0B
|
||||
|
||||
#define PORTD6_FUNC_D6 0x00
|
||||
#define PORTD6_FUNC_CM0_A2 0x01
|
||||
#define PORTD6_FUNC_CM0_SPI_MOSI 0x02
|
||||
#define PORTD6_FUNC_UART0_RXD 0x03
|
||||
#define PORTD6_FUNC_SPIM0_MOSI 0x04
|
||||
#define PORTD6_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTD6_FUNC_PDM1_CLK 0x06
|
||||
#define PORTD6_FUNC_I2C3_CLK 0x07
|
||||
#define PORTD6_FUNC_PWM6 0x08
|
||||
#define PORTD6_FUNC_TIM0_TOG 0x09
|
||||
#define PORTD6_FUNC_PSRAM_QSPI_MIO6 0x0B
|
||||
|
||||
#define PORTD7_FUNC_D7 0x00
|
||||
#define PORTD7_FUNC_CM0_A3 0x01
|
||||
#define PORTD7_FUNC_CM0_SPI_MISO 0x02
|
||||
#define PORTD7_FUNC_UART0_TXD 0x03
|
||||
#define PORTD7_FUNC_SPIM0_MISO 0x04
|
||||
#define PORTD7_FUNC_SPIS0_MISO 0x05
|
||||
#define PORTD7_FUNC_PDM1_SDA 0x06
|
||||
#define PORTD7_FUNC_I2C3_SDA 0x07
|
||||
#define PORTD7_FUNC_PWM7 0x08
|
||||
#define PORTD7_FUNC_TIM1_TOG 0x09
|
||||
#define PORTD7_FUNC_PSRAM_QSPI_MIO7 0x0B
|
||||
|
||||
#define PORTE0_FUNC_E0 0x00
|
||||
#define PORTE0_FUNC_CM0_A4 0x01
|
||||
#define PORTE0_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTE0_FUNC_UART1_RXD 0x03
|
||||
#define PORTE0_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTE0_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTE0_FUNC_PDM2_CLK 0x06
|
||||
#define PORTE0_FUNC_I2C2_CLK 0x07
|
||||
#define PORTE0_FUNC_PWM8 0x08
|
||||
#define PORTE0_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTE0_FUNC_SPIM8_1_IO0 0x0A
|
||||
|
||||
#define PORTE1_FUNC_E1 0x00
|
||||
#define PORTE1_FUNC_CM0_A5 0x01
|
||||
#define PORTE1_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTE1_FUNC_UART1_TXD 0x03
|
||||
#define PORTE1_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTE1_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTE1_FUNC_PDM2_SDA 0x06
|
||||
#define PORTE1_FUNC_I2C2_SDA 0x07
|
||||
#define PORTE1_FUNC_PWM9 0x08
|
||||
#define PORTE1_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTE1_FUNC_SPIM8_1_IO1 0x0A
|
||||
|
||||
#define PORTE2_FUNC_E2 0x00
|
||||
#define PORTE2_FUNC_CM0_A6 0x01
|
||||
#define PORTE2_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTE2_FUNC_UART3_RXD 0x03
|
||||
#define PORTE2_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTE2_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTE2_FUNC_PDM3_CLK 0x06
|
||||
#define PORTE2_FUNC_I2C3_CLK 0x07
|
||||
#define PORTE2_FUNC_PWM10 0x08
|
||||
#define PORTE2_FUNC_TIM2_TOG 0x09
|
||||
#define PORTE2_FUNC_SPIM8_1_IO2 0x0A
|
||||
|
||||
#define PORTE3_FUNC_E3 0x00
|
||||
#define PORTE3_FUNC_CM0_A7 0x01
|
||||
#define PORTE3_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTE3_FUNC_UART3_TXD 0x03
|
||||
#define PORTE3_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTE3_FUNC_SPIS0_MISO 0x05
|
||||
#define PORTE3_FUNC_PDM3_SDA 0x06
|
||||
#define PORTE3_FUNC_I2C3_SDA 0x07
|
||||
#define PORTE3_FUNC_PWM11 0x08
|
||||
#define PORTE3_FUNC_TIM3_TOG 0x09
|
||||
#define PORTE3_FUNC_SPIM8_1_IO3 0x0A
|
||||
|
||||
#define PORTE4_FUNC_E4 0x00
|
||||
#define PORTE4_FUNC_CM0_A4 0x01
|
||||
#define PORTE4_FUNC_CM0_SPI_CLK 0x02
|
||||
#define PORTE4_FUNC_UART3_CTS 0x03
|
||||
#define PORTE4_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTE4_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTE4_FUNC_PDM2_CLK 0x06
|
||||
#define PORTE4_FUNC_I2C2_CLK 0x07
|
||||
#define PORTE4_FUNC_PWM12 0x08
|
||||
#define PORTE4_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTE4_FUNC_SPIM8_1_IO4 0x0A
|
||||
|
||||
#define PORTE5_FUNC_E5 0x00
|
||||
#define PORTE5_FUNC_CM0_A5 0x01
|
||||
#define PORTE5_FUNC_CM0_SPI_CSN 0x02
|
||||
#define PORTE5_FUNC_UART3_RTS 0x03
|
||||
#define PORTE5_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTE5_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTE5_FUNC_PDM2_SDA 0x06
|
||||
#define PORTE5_FUNC_I2C2_SDA 0x07
|
||||
#define PORTE5_FUNC_PWM13 0x08
|
||||
#define PORTE5_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTE5_FUNC_SPIM8_1_IO5 0x0A
|
||||
|
||||
#define PORTE6_FUNC_E6 0x00
|
||||
#define PORTE6_FUNC_CM0_A6 0x01
|
||||
#define PORTE6_FUNC_CM0_SPI_MOSI 0x02
|
||||
#define PORTE6_FUNC_UART1_RXD 0x03
|
||||
#define PORTE6_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTE6_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTE6_FUNC_PDM3_CLK 0x06
|
||||
#define PORTE6_FUNC_I2C3_CLK 0x07
|
||||
#define PORTE6_FUNC_PWM14 0x08
|
||||
#define PORTE6_FUNC_TIM2_TOG 0x09
|
||||
#define PORTE6_FUNC_SPIM8_1_IO6 0x0A
|
||||
|
||||
#define PORTE7_FUNC_E7 0x00
|
||||
#define PORTE7_FUNC_CM0_A7 0x01
|
||||
#define PORTE7_FUNC_CM0_SPI_MISO 0x02
|
||||
#define PORTE7_FUNC_UART1_TXD 0x03
|
||||
#define PORTE7_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTE7_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTE7_FUNC_PDM3_SDA 0x06
|
||||
#define PORTE7_FUNC_I2C3_SDA 0x07
|
||||
#define PORTE7_FUNC_PWM15 0x08
|
||||
#define PORTE7_FUNC_TIM3_TOG 0x09
|
||||
#define PORTE7_FUNC_SPIM8_1_IO7 0x0A
|
||||
|
||||
#define PORTF0_FUNC_F0 0x00
|
||||
#define PORTF0_FUNC_CM0_A4 0x01
|
||||
#define PORTF0_FUNC_CM0_SPI_CLK 0x02
|
||||
#define PORTF0_FUNC_UART1_RXD 0x03
|
||||
#define PORTF0_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTF0_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTF0_FUNC_PDM2_CLK 0x06
|
||||
#define PORTF0_FUNC_I2C2_CLK 0x07
|
||||
#define PORTF0_FUNC_PWM8 0x08
|
||||
#define PORTF0_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTF0_FUNC_SPIM8_1_CLK 0x0A
|
||||
|
||||
#define PORTF1_FUNC_F1 0x00
|
||||
#define PORTF1_FUNC_CM0_A5 0x01
|
||||
#define PORTF1_FUNC_CM0_SPI_CSN 0x02
|
||||
#define PORTF1_FUNC_UART1_TXD 0x03
|
||||
#define PORTF1_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTF1_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTF1_FUNC_PDM2_SDA 0x06
|
||||
#define PORTF1_FUNC_I2C2_SDA 0x07
|
||||
#define PORTF1_FUNC_PWM9 0x08
|
||||
#define PORTF1_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTF1_FUNC_SPIM8_1_CSN 0x0A
|
||||
|
||||
#define PORTF2_FUNC_F2 0x00
|
||||
#define PORTF2_FUNC_CM0_A6 0x01
|
||||
#define PORTF2_FUNC_CM0_SPI_MOSI 0x02
|
||||
#define PORTF2_FUNC_UART3_RXD 0x03
|
||||
#define PORTF2_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTF2_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTF2_FUNC_PDM3_CLK 0x06
|
||||
#define PORTF2_FUNC_I2C3_CLK 0x07
|
||||
#define PORTF2_FUNC_PWM10 0x08
|
||||
#define PORTF2_FUNC_TIM2_TOG 0x09
|
||||
#define PORTF2_FUNC_SPIM8_1_IO0 0x0A
|
||||
|
||||
#define PORTF3_FUNC_F3 0x00
|
||||
#define PORTF3_FUNC_CM0_A7 0x01
|
||||
#define PORTF3_FUNC_CM0_SPI_MISO 0x02
|
||||
#define PORTF3_FUNC_UART3_TXD 0x03
|
||||
#define PORTF3_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTF3_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTF3_FUNC_PDM3_SDA 0x06
|
||||
#define PORTF3_FUNC_I2C3_SDA 0x07
|
||||
#define PORTF3_FUNC_PWM11 0x08
|
||||
#define PORTF3_FUNC_TIM3_TOG 0x09
|
||||
#define PORTF3_FUNC_SPIM8_1_IO1 0x0A
|
||||
|
||||
#define PORTF4_FUNC_F4 0x00
|
||||
#define PORTF4_FUNC_CM0_A4 0x01
|
||||
#define PORTF4_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTF4_FUNC_UART3_CTS 0x03
|
||||
#define PORTF4_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTF4_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTF4_FUNC_PDM2_CLK 0x06
|
||||
#define PORTF4_FUNC_I2C4_CLK 0x07
|
||||
#define PORTF4_FUNC_PWM12 0x08
|
||||
#define PORTF4_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTF4_FUNC_SPIM8_1_IO2 0x0A
|
||||
|
||||
#define PORTF5_FUNC_F5 0x00
|
||||
#define PORTF5_FUNC_CM0_A5 0x01
|
||||
#define PORTF5_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTF5_FUNC_UART3_RTS 0x03
|
||||
#define PORTF5_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTF5_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTF5_FUNC_PDM2_SDA 0x06
|
||||
#define PORTF5_FUNC_I2C4_SDA 0x07
|
||||
#define PORTF5_FUNC_PWM13 0x08
|
||||
#define PORTF5_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTF5_FUNC_SPIM8_1_IO3 0x0A
|
||||
|
||||
#define PORTF6_FUNC_F6 0x00
|
||||
#define PORTF6_FUNC_CM0_A6 0x01
|
||||
#define PORTF6_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTF6_FUNC_UART1_RXD 0x03
|
||||
#define PORTF6_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTF6_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTF6_FUNC_PDM3_CLK 0x06
|
||||
#define PORTF6_FUNC_I2C2_CLK 0x07
|
||||
#define PORTF6_FUNC_PWM14 0x08
|
||||
#define PORTF6_FUNC_TIM2_TOG 0x09
|
||||
#define PORTF6_FUNC_SPIM8_1_CLK 0x0A
|
||||
|
||||
#define PORTF7_FUNC_F7 0x00
|
||||
#define PORTF7_FUNC_CM0_A7 0x01
|
||||
#define PORTF7_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTF7_FUNC_UART1_TXD 0x03
|
||||
#define PORTF7_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTF7_FUNC_SPIS0_MISO 0x05
|
||||
#define PORTF7_FUNC_PDM3_SDA 0x06
|
||||
#define PORTF7_FUNC_I2C2_SDA 0x07
|
||||
#define PORTF7_FUNC_PWM15 0x08
|
||||
#define PORTF7_FUNC_TIM3_TOG 0x09
|
||||
#define PORTF7_FUNC_SPIM8_1_CSN 0x0A
|
||||
|
||||
#define PORTG0_FUNC_G0 0x00
|
||||
#define PORTG0_FUNC_CM0_A4 0x01
|
||||
#define PORTG0_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTG0_FUNC_UART1_RXD 0x03
|
||||
#define PORTG0_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTG0_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTG0_FUNC_PDM2_CLK 0x06
|
||||
#define PORTG0_FUNC_I2C3_CLK 0x07
|
||||
#define PORTG0_FUNC_PWM8 0x08
|
||||
#define PORTG0_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTG0_FUNC_SPIM8_1_IO4 0x0A
|
||||
|
||||
#define PORTG1_FUNC_G1 0x00
|
||||
#define PORTG1_FUNC_CM0_A5 0x01
|
||||
#define PORTG1_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTG1_FUNC_UART1_TXD 0x03
|
||||
#define PORTG1_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTG1_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTG1_FUNC_PDM2_SDA 0x06
|
||||
#define PORTG1_FUNC_I2C3_SDA 0x07
|
||||
#define PORTG1_FUNC_PWM9 0x08
|
||||
#define PORTG1_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTG1_FUNC_SPIM8_1_IO5 0x0A
|
||||
|
||||
#define PORTG2_FUNC_G2 0x00
|
||||
#define PORTG2_FUNC_CM0_A6 0x01
|
||||
#define PORTG2_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTG2_FUNC_UART3_RXD 0x03
|
||||
#define PORTG2_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTG2_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTG2_FUNC_PDM3_CLK 0x06
|
||||
#define PORTG2_FUNC_I2C4_CLK 0x07
|
||||
#define PORTG2_FUNC_PWM10 0x08
|
||||
#define PORTG2_FUNC_TIM2_TOG 0x09
|
||||
#define PORTG2_FUNC_SPIM8_1_IO6 0x0A
|
||||
|
||||
#define PORTG3_FUNC_G3 0x00
|
||||
#define PORTG3_FUNC_CM0_A7 0x01
|
||||
#define PORTG3_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTG3_FUNC_UART3_TXD 0x03
|
||||
#define PORTG3_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTG3_FUNC_SPIS0_MISO 0x05
|
||||
#define PORTG3_FUNC_PDM3_SDA 0x06
|
||||
#define PORTG3_FUNC_I2C4_SDA 0x07
|
||||
#define PORTG3_FUNC_PWM11 0x08
|
||||
#define PORTG3_FUNC_TIM3_TOG 0x09
|
||||
#define PORTG3_FUNC_SPIM8_1_IO7 0x0A
|
||||
|
||||
#define PORTG4_FUNC_G4 0x00
|
||||
#define PORTG4_FUNC_CM0_A4 0x01
|
||||
#define PORTG4_FUNC_CM0_SPI_CLK 0x02
|
||||
#define PORTG4_FUNC_UART3_CTS 0x03
|
||||
#define PORTG4_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTG4_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTG4_FUNC_PDM2_CLK 0x06
|
||||
#define PORTG4_FUNC_I2C3_CLK 0x07
|
||||
#define PORTG4_FUNC_PWM12 0x08
|
||||
#define PORTG4_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTG4_FUNC_SPIM8_1_IO0 0x0A
|
||||
|
||||
#define PORTG5_FUNC_G5 0x00
|
||||
#define PORTG5_FUNC_CM0_A5 0x01
|
||||
#define PORTG5_FUNC_CM0_SPI_CSN 0x02
|
||||
#define PORTG5_FUNC_UART3_RTS 0x03
|
||||
#define PORTG5_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTG5_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTG5_FUNC_PDM2_SDA 0x06
|
||||
#define PORTG5_FUNC_I2C3_SDA 0x07
|
||||
#define PORTG5_FUNC_PWM13 0x08
|
||||
#define PORTG5_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTG5_FUNC_SPIM8_1_IO1 0x0A
|
||||
|
||||
#define PORTG6_FUNC_G6 0x00
|
||||
#define PORTG6_FUNC_CM0_A6 0x01
|
||||
#define PORTG6_FUNC_CM0_SPI_MOSI 0x02
|
||||
#define PORTG6_FUNC_UART1_RXD 0x03
|
||||
#define PORTG6_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTG6_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTG6_FUNC_PDM3_CLK 0x06
|
||||
#define PORTG6_FUNC_I2C4_CLK 0x07
|
||||
#define PORTG6_FUNC_PWM14 0x08
|
||||
#define PORTG6_FUNC_TIM2_TOG 0x09
|
||||
#define PORTG6_FUNC_SPIM8_1_IO2 0x0A
|
||||
|
||||
#define PORTG7_FUNC_G7 0x00
|
||||
#define PORTG7_FUNC_CM0_A7 0x01
|
||||
#define PORTG7_FUNC_CM0_SPI_MISO 0x02
|
||||
#define PORTG7_FUNC_UART1_TXD 0x03
|
||||
#define PORTG7_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTG7_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTG7_FUNC_PDM3_SDA 0x06
|
||||
#define PORTG7_FUNC_I2C4_SDA 0x07
|
||||
#define PORTG7_FUNC_PWM15 0x08
|
||||
#define PORTG7_FUNC_TIM3_TOG 0x09
|
||||
#define PORTG7_FUNC_SPIM8_1_IO3 0x0A
|
||||
|
||||
#define PORTH0_FUNC_H0 0x00
|
||||
#define PORTH0_FUNC_CM0_A4 0x01
|
||||
#define PORTH0_FUNC_CM0_SPI_CLK 0x02
|
||||
#define PORTH0_FUNC_UART1_RXD 0x03
|
||||
#define PORTH0_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTH0_FUNC_SPIS1_CLK 0x05
|
||||
#define PORTH0_FUNC_PDM2_CLK 0x06
|
||||
#define PORTH0_FUNC_I2C3_CLK 0x07
|
||||
#define PORTH0_FUNC_PWM8 0x08
|
||||
#define PORTH0_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTH0_FUNC_SPIM8_1_CLK 0x0A
|
||||
|
||||
#define PORTH1_FUNC_H1 0x00
|
||||
#define PORTH1_FUNC_CM0_A5 0x01
|
||||
#define PORTH1_FUNC_CM0_SPI_CSN 0x02
|
||||
#define PORTH1_FUNC_UART1_TXD 0x03
|
||||
#define PORTH1_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTH1_FUNC_SPIS1_FRM 0x05
|
||||
#define PORTH1_FUNC_PDM2_SDA 0x06
|
||||
#define PORTH1_FUNC_I2C3_SDA 0x07
|
||||
#define PORTH1_FUNC_PWM9 0x08
|
||||
#define PORTH1_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTH1_FUNC_SPIM8_1_CSN 0x0A
|
||||
|
||||
#define PORTH2_FUNC_H2 0x00
|
||||
#define PORTH2_FUNC_CM0_A6 0x01
|
||||
#define PORTH2_FUNC_CM0_SPI_MOSI 0x02
|
||||
#define PORTH2_FUNC_UART3_RXD 0x03
|
||||
#define PORTH2_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTH2_FUNC_SPIS1_MOSI 0x05
|
||||
#define PORTH2_FUNC_PDM3_CLK 0x06
|
||||
#define PORTH2_FUNC_I2C4_CLK 0x07
|
||||
#define PORTH2_FUNC_PWM10 0x08
|
||||
#define PORTH2_FUNC_TIM2_TOG 0x09
|
||||
#define PORTH2_FUNC_SPIM8_1_IO0 0x0A
|
||||
|
||||
#define PORTH3_FUNC_H3 0x00
|
||||
#define PORTH3_FUNC_CM0_A7 0x01
|
||||
#define PORTH3_FUNC_CM0_SPI_MISO 0x02
|
||||
#define PORTH3_FUNC_UART3_TXD 0x03
|
||||
#define PORTH3_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTH3_FUNC_SPIS1_MISO 0x05
|
||||
#define PORTH3_FUNC_PDM3_SDA 0x06
|
||||
#define PORTH3_FUNC_I2C4_SDA 0x07
|
||||
#define PORTH3_FUNC_PWM11 0x08
|
||||
#define PORTH3_FUNC_TIM3_TOG 0x09
|
||||
#define PORTH3_FUNC_SPIM8_1_IO1 0x0A
|
||||
|
||||
#define PORTH4_FUNC_H4 0x00
|
||||
#define PORTH4_FUNC_CM0_A4 0x01
|
||||
#define PORTH4_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTH4_FUNC_UART3_CTS 0x03
|
||||
#define PORTH4_FUNC_SPIM2_CLK 0x04
|
||||
#define PORTH4_FUNC_SPIS0_CLK 0x05
|
||||
#define PORTH4_FUNC_PDM2_CLK 0x06
|
||||
#define PORTH4_FUNC_I2C3_CLK 0x07
|
||||
#define PORTH4_FUNC_PWM12 0x08
|
||||
#define PORTH4_FUNC_TIM2_PAUSE 0x09
|
||||
#define PORTH4_FUNC_SPIM8_1_IO2 0x0A
|
||||
|
||||
#define PORTH5_FUNC_H5 0x00
|
||||
#define PORTH5_FUNC_CM0_A5 0x01
|
||||
#define PORTH5_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTH5_FUNC_UART3_RTS 0x03
|
||||
#define PORTH5_FUNC_SPIM2_CSN 0x04
|
||||
#define PORTH5_FUNC_SPIS0_CSN 0x05
|
||||
#define PORTH5_FUNC_PDM2_SDA 0x06
|
||||
#define PORTH5_FUNC_I2C3_SDA 0x07
|
||||
#define PORTH5_FUNC_PWM13 0x08
|
||||
#define PORTH5_FUNC_TIM3_PAUSE 0x09
|
||||
#define PORTH5_FUNC_SPIM8_1_IO3 0x0A
|
||||
|
||||
#define PORTH6_FUNC_H6 0x00
|
||||
#define PORTH6_FUNC_CM0_A6 0x01
|
||||
#define PORTH6_FUNC_CM1_UART_RXD 0x02
|
||||
#define PORTH6_FUNC_UART1_RXD 0x03
|
||||
#define PORTH6_FUNC_SPIM2_MOSI 0x04
|
||||
#define PORTH6_FUNC_SPIS0_MOSI 0x05
|
||||
#define PORTH6_FUNC_PDM3_CLK 0x06
|
||||
#define PORTH6_FUNC_I2C4_CLK 0x07
|
||||
#define PORTH6_FUNC_PWM14 0x08
|
||||
#define PORTH6_FUNC_TIM2_TOG 0x09
|
||||
|
||||
#define PORTH7_FUNC_H7 0x00
|
||||
#define PORTH7_FUNC_CM0_A7 0x01
|
||||
#define PORTH7_FUNC_CM1_UART_TXD 0x02
|
||||
#define PORTH7_FUNC_UART1_TXD 0x03
|
||||
#define PORTH7_FUNC_SPIM2_MISO 0x04
|
||||
#define PORTH7_FUNC_SPIS0_MISOI 0x05
|
||||
#define PORTH7_FUNC_PDM3_SDA 0x06
|
||||
#define PORTH7_FUNC_I2C4_SDA 0x07
|
||||
#define PORTH7_FUNC_PWM15 0x08
|
||||
#define PORTH7_FUNC_TIM3_TOG 0x09
|
||||
|
||||
|
||||
#define GPIO_PA0 (1<<0)
|
||||
#define GPIO_PA1 (1<<1)
|
||||
#define GPIO_PA2 (1<<2)
|
||||
#define GPIO_PA3 (1<<3)
|
||||
#define GPIO_PA4 (1<<4)
|
||||
#define GPIO_PA5 (1<<5)
|
||||
#define GPIO_PA6 (1<<6)
|
||||
#define GPIO_PA7 (1<<7)
|
||||
|
||||
#define GPIO_PB0 (1<<8)
|
||||
#define GPIO_PB1 (1<<9)
|
||||
#define GPIO_PB2 (1<<10)
|
||||
#define GPIO_PB3 (1<<11)
|
||||
#define GPIO_PB4 (1<<12)
|
||||
#define GPIO_PB5 (1<<13)
|
||||
#define GPIO_PB6 (1<<14)
|
||||
#define GPIO_PB7 (1<<15)
|
||||
|
||||
#define GPIO_PC0 (1<<16)
|
||||
#define GPIO_PC1 (1<<17)
|
||||
#define GPIO_PC2 (1<<18)
|
||||
#define GPIO_PC3 (1<<19)
|
||||
#define GPIO_PC4 (1<<20)
|
||||
#define GPIO_PC5 (1<<21)
|
||||
#define GPIO_PC6 (1<<22)
|
||||
#define GPIO_PC7 (1<<23)
|
||||
|
||||
#define GPIO_PD0 (1<<24)
|
||||
#define GPIO_PD1 (1<<25)
|
||||
#define GPIO_PD2 (1<<26)
|
||||
#define GPIO_PD3 (1<<27)
|
||||
#define GPIO_PD4 (1<<28)
|
||||
#define GPIO_PD5 (1<<29)
|
||||
#define GPIO_PD6 (1<<30)
|
||||
#define GPIO_PD7 ((uint32_t)1<<31)
|
||||
|
||||
#define GPIO_PE0 (1<<0)
|
||||
#define GPIO_PE1 (1<<1)
|
||||
#define GPIO_PE2 (1<<2)
|
||||
#define GPIO_PE3 (1<<3)
|
||||
#define GPIO_PE4 (1<<4)
|
||||
#define GPIO_PE5 (1<<5)
|
||||
#define GPIO_PE6 (1<<6)
|
||||
#define GPIO_PE7 (1<<7)
|
||||
|
||||
#define GPIO_PF0 (1<<8)
|
||||
#define GPIO_PF1 (1<<9)
|
||||
#define GPIO_PF2 (1<<10)
|
||||
#define GPIO_PF3 (1<<11)
|
||||
#define GPIO_PF4 (1<<12)
|
||||
#define GPIO_PF5 (1<<13)
|
||||
#define GPIO_PF6 (1<<14)
|
||||
#define GPIO_PF7 (1<<15)
|
||||
|
||||
#define GPIO_PG0 (1<<16)
|
||||
#define GPIO_PG1 (1<<17)
|
||||
#define GPIO_PG2 (1<<18)
|
||||
#define GPIO_PG3 (1<<19)
|
||||
#define GPIO_PG4 (1<<20)
|
||||
#define GPIO_PG5 (1<<21)
|
||||
#define GPIO_PG6 (1<<22)
|
||||
#define GPIO_PG7 (1<<23)
|
||||
|
||||
#define GPIO_PH0 (1<<24)
|
||||
#define GPIO_PH1 (1<<25)
|
||||
#define GPIO_PH2 (1<<26)
|
||||
#define GPIO_PH3 (1<<27)
|
||||
#define GPIO_PH4 (1<<28)
|
||||
#define GPIO_PH5 (1<<29)
|
||||
#define GPIO_PH6 (1<<30)
|
||||
#define GPIO_PH7 ((uint32_t)1<<31)
|
||||
|
||||
#endif
|
||||
|
||||
enum system_port_t
|
||||
{
|
||||
GPIO_PORT_A,
|
||||
GPIO_PORT_B,
|
||||
GPIO_PORT_C,
|
||||
GPIO_PORT_D,
|
||||
GPIO_PORT_E,
|
||||
GPIO_PORT_F,
|
||||
GPIO_PORT_G,
|
||||
GPIO_PORT_H,
|
||||
};
|
||||
|
||||
enum system_port_bit_t
|
||||
{
|
||||
GPIO_BIT_0,
|
||||
GPIO_BIT_1,
|
||||
GPIO_BIT_2,
|
||||
GPIO_BIT_3,
|
||||
GPIO_BIT_4,
|
||||
GPIO_BIT_5,
|
||||
GPIO_BIT_6,
|
||||
GPIO_BIT_7,
|
||||
};
|
||||
#define SET_FEILD(reg,field,pos,value) (reg) = ( (reg) & ~(field<<(pos)) | (value<<(pos)))
|
||||
|
||||
#endif // DRIVER_IOMUX_H
|
||||
|
||||
173
fr3092_mcu/components/drivers/peripheral/Inc/driver_ipc.h
Normal file
173
fr3092_mcu/components/drivers/peripheral/Inc/driver_ipc.h
Normal file
@ -0,0 +1,173 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_ipc.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of IPC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_IPC_H__
|
||||
#define __DRIVER_IPC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/*IPC CTRL REG 0x00*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t CH0_IN_EN : 1; //Channel 0 input message enable
|
||||
uint32_t CH1_IN_EN : 1; //Channel 1 input message enable
|
||||
uint32_t CH2_IN_EN : 1; //Channel 2 input message enable
|
||||
uint32_t CH3_IN_EN : 1; //Channel 3 input message enable
|
||||
uint32_t CH0_OUT_EN : 1; //Channel 0 output message enable
|
||||
uint32_t CH1_OUT_EN : 1; //Channel 1 output message enable
|
||||
uint32_t CH2_OUT_EN : 1; //Channel 2 output message enable
|
||||
uint32_t CH3_OUT_EN : 1; //Channel 3 output message enable
|
||||
uint32_t RSV : 24;
|
||||
} Bits;
|
||||
} REG_IPC_CTRL_t;
|
||||
|
||||
/*IPC Message Pending REG 0x04*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t CH0_IN : 1;//Channel 0 input message pending
|
||||
uint32_t CH1_IN : 1;//Channel 1 input message pending
|
||||
uint32_t CH2_IN : 1;//Channel 2 input message pending
|
||||
uint32_t CH3_IN : 1;//Channel 3 input message pending
|
||||
uint32_t CH0_OUT : 1;//Channel 0 output message pending
|
||||
uint32_t CH1_OUT : 1;//Channel 1 output message pending
|
||||
uint32_t CH2_OUT : 1;//Channel 2 output message pending
|
||||
uint32_t CH3_OUT : 1;//Channel 3 output message pending
|
||||
uint32_t RSV : 24;
|
||||
} Bits;
|
||||
} REG_IPC_MSG_PENDING_t;
|
||||
|
||||
/*IPC Message IN Clear REG 0x28*/
|
||||
typedef volatile struct
|
||||
{
|
||||
uint32_t CH0_IN : 1;//write 1 to clear Channel 0 input message interrupt
|
||||
uint32_t CH1_IN : 1;//write 1 to clear Channel 1 input message interrupt
|
||||
uint32_t CH2_IN : 1;//write 1 to clear Channel 2 input message interrupt
|
||||
uint32_t CH3_IN : 1;//write 1 to clear Channel 3 input message interrupt
|
||||
uint32_t RSV : 28;
|
||||
} REG_IPC_MSG_CLR_t;
|
||||
|
||||
/*IPC ISR Interrupt Enable REG 0x2C*/
|
||||
typedef volatile union
|
||||
{
|
||||
uint32_t Word;
|
||||
struct {
|
||||
uint32_t CH0_IN : 1;//Channel 0 input enable
|
||||
uint32_t CH1_IN : 1;//Channel 1 input enable
|
||||
uint32_t CH2_IN : 1;//Channel 2 input enable
|
||||
uint32_t CH3_IN : 1;//Channel 3 input enable
|
||||
uint32_t CH0_OUT : 1;//Channel 0 output enable
|
||||
uint32_t CH1_OUT : 1;//Channel 1 output enable
|
||||
uint32_t CH2_OUT : 1;//Channel 2 output enable
|
||||
uint32_t CH3_OUT : 1;//Channel 3 output enable
|
||||
uint32_t RSV1 : 24;
|
||||
} Bits;
|
||||
} REG_IPC_ISR_EN_t;
|
||||
|
||||
/*IPC MSG Interrupt Status REG 0x30*/
|
||||
typedef volatile union
|
||||
{
|
||||
uint32_t Word;
|
||||
struct {
|
||||
uint32_t CH0_IN : 1;//Channel 0 input interrupt status
|
||||
uint32_t CH1_IN : 1;//Channel 1 input interrupt status
|
||||
uint32_t CH2_IN : 1;//Channel 2 input interrupt status
|
||||
uint32_t CH3_IN : 1;//Channel 3 input interrupt status
|
||||
uint32_t CH0_OUT : 1;//Channel 0 output interrupt status
|
||||
uint32_t CH1_OUT : 1;//Channel 1 output interrupt status
|
||||
uint32_t CH2_OUT : 1;//Channel 2 output interrupt status
|
||||
uint32_t CH3_OUT : 1;//Channel 3 output interrupt status
|
||||
uint32_t RSV1 : 24;
|
||||
} Bits;
|
||||
} REG_IPC_ISR_STA_t;
|
||||
|
||||
/*IPC MSG Interrupt Raw Status REG 0x34*/
|
||||
typedef volatile union
|
||||
{
|
||||
uint32_t Word;
|
||||
struct {
|
||||
uint32_t CH0_IN : 1;//Channel 0 input raw interrupt status
|
||||
uint32_t CH1_IN : 1;//Channel 1 input raw interrupt status
|
||||
uint32_t CH2_IN : 1;//Channel 2 input raw interrupt status
|
||||
uint32_t CH3_IN : 1;//Channel 3 input raw interrupt status
|
||||
uint32_t CH0_OUT : 1;//Channel 0 output raw interrupt status
|
||||
uint32_t CH1_OUT : 1;//Channel 1 output raw interrupt status
|
||||
uint32_t CH2_OUT : 1;//Channel 2 output raw interrupt status
|
||||
uint32_t CH3_OUT : 1;//Channel 3 output raw interrupt status
|
||||
uint32_t RSV1 : 24;
|
||||
} Bits;
|
||||
} REG_IPC_ISR_RAW_STA_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_IPC_CTRL_t IPC_CTRL; /* Offset 0x00 */
|
||||
volatile REG_IPC_MSG_PENDING_t IPC_PENDING; /* Offset 0x04 */
|
||||
volatile uint32_t IPC_MSG_IN0; /* Offset 0x08 */
|
||||
volatile uint32_t IPC_MSG_IN1; /* Offset 0x0C */
|
||||
volatile uint32_t IPC_MSG_IN2; /* Offset 0x10 */
|
||||
volatile uint32_t IPC_MSG_IN3; /* Offset 0x14 */
|
||||
volatile uint32_t IPC_MSG_OUT0; /* Offset 0x18 */
|
||||
volatile uint32_t IPC_MSG_OUT1; /* Offset 0x1C */
|
||||
volatile uint32_t IPC_MSG_OUT2; /* Offset 0x20 */
|
||||
volatile uint32_t IPC_MSG_OUT3; /* Offset 0x24 */
|
||||
volatile REG_IPC_MSG_CLR_t IPC_MSG_CLR; /* Offset 0x28 */
|
||||
volatile REG_IPC_ISR_EN_t IPC_ISR_EN; /* Offset 0x2C */
|
||||
volatile REG_IPC_ISR_STA_t IPC_ISR_STA; /* Offset 0x30 */
|
||||
volatile REG_IPC_ISR_RAW_STA_t IPC_ISR_RAW_STA; /* Offset 0x34 */
|
||||
}struct_IPC_t;
|
||||
|
||||
#define IPC_MCU ((struct_IPC_t *)IPC_BASE)
|
||||
#define IPC_DSP ((struct_IPC_t *)DSP_IPC_BASE)
|
||||
|
||||
#define IPC_INT_STATUS_CH0_IN (1<<0)
|
||||
#define IPC_INT_STATUS_CH1_IN (1<<1)
|
||||
#define IPC_INT_STATUS_CH2_IN (1<<2)
|
||||
#define IPC_INT_STATUS_CH3_IN (1<<3)
|
||||
#define IPC_INT_STATUS_CH0_OUT (1<<4)
|
||||
#define IPC_INT_STATUS_CH1_OUT (1<<5)
|
||||
#define IPC_INT_STATUS_CH2_OUT (1<<6)
|
||||
#define IPC_INT_STATUS_CH3_OUT (1<<7)
|
||||
|
||||
typedef enum{
|
||||
IPC_CH_0 = (1<<0),
|
||||
IPC_CH_1 = (1<<1),
|
||||
IPC_CH_2 = (1<<2),
|
||||
IPC_CH_3 = (1<<3),
|
||||
}enum_IPC_Chl_Sel_t;
|
||||
|
||||
typedef struct __IPC_HandleTypeDef
|
||||
{
|
||||
struct_IPC_t *IPCx;
|
||||
|
||||
uint8_t TxEnableChannels;
|
||||
uint8_t RxEnableChannels;
|
||||
|
||||
uint8_t TxOngoingChannels;
|
||||
|
||||
void (*TxCallback)(struct __IPC_HandleTypeDef *hipc, enum_IPC_Chl_Sel_t ch); /*!< Tx Callback */
|
||||
void (*RxCallback)(struct __IPC_HandleTypeDef *hipc, enum_IPC_Chl_Sel_t ch, uint32_t msg); /*!< Rx Callback */
|
||||
|
||||
}IPC_HandleTypeDef;
|
||||
|
||||
void ipc_IRQHandler(IPC_HandleTypeDef *hipc);
|
||||
|
||||
void ipc_init(IPC_HandleTypeDef *hipc);
|
||||
void ipc_msg_send(IPC_HandleTypeDef *hipc, enum_IPC_Chl_Sel_t ch, uint32_t msg);
|
||||
|
||||
#endif
|
||||
243
fr3092_mcu/components/drivers/peripheral/Inc/driver_mp3_dec.h
Normal file
243
fr3092_mcu/components/drivers/peripheral/Inc/driver_mp3_dec.h
Normal file
@ -0,0 +1,243 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_mp3_dec.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of MP3 DECODER module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_MP3_DEC_H__
|
||||
#define __DRIVER_MP3_DEC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup MP3_DEC_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* MP3 DECODER CTRL REG 0x00*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t OPERA_EN : 1;//this bit enables the mp3d 0->no effect 1->operation enable
|
||||
uint32_t OPERA_START : 1;//this bit enables to start the mp3d 0->no effect 1->start mp3 decoder
|
||||
uint32_t ISR_EN : 1;//this bit enables the interrupt request 0->disable interrupt requeset 1->enable...
|
||||
uint32_t RESTART_DEC : 1;//this bit enables to restart the mp3d
|
||||
uint32_t RESET_PCM_FIFO : 1;//this bit enables to reset the pcm fifo
|
||||
uint32_t DAI_EN : 1;//this bit enables direct audio interface
|
||||
uint32_t ISSUE_NEW_FILE : 1;//this bit enables to issue new mp3 file
|
||||
uint32_t RSV : 24;//
|
||||
uint32_t MP3D_SOFTRST : 1;//this bit enable to reset the mp3d controller
|
||||
} Bits;
|
||||
} REG_MP3D_CTRL_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t SOURCE_CMPLETION_ISR_EN : 1;//this bit enables source complete interrupt
|
||||
uint32_t PCM_BUFFER_UNDERRUN_ISR_EN : 1;//this bit enables pcm buffer underrun interrupt
|
||||
uint32_t PCM_BUFFER_FULL_ISR_EN : 1;//this bit enables pcm buffer full interrupt
|
||||
uint32_t MP3_FRAME_LOCKED_ISR_EN : 1;//this bit enables mp3 frame locked interrupt
|
||||
uint32_t RSV : 28;//
|
||||
} Bits;
|
||||
} REG_MP3D_INTMASK_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t SOURCE_CMPLETION_ISR : 1;//this bit indicates the source decoding is complete 0->no effect 1->decode complete
|
||||
uint32_t PCM_BUFFER_UNDERRUN_ISR : 1;//this bit indicates the pcm buffer is underrun 0->no effect 1->pcm buffer is underrun
|
||||
uint32_t PCM_BUFFER_FULL_ISR : 1;//this bit indicates the pcm buffer is full
|
||||
uint32_t MP3_FRAME_LOCKED_ISR : 1;//this bit indicates the mp3 frame is locked
|
||||
uint32_t RSV : 28;//
|
||||
} Bits;
|
||||
} REG_MP3D_INTSTA_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t VOLUME : 5;//volume control range from 0 to 31,0->no volume gain,31->maximum volume gain
|
||||
uint32_t RSV : 27;//
|
||||
} Bits;
|
||||
} REG_MP3D_VOL_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t EQ_60HZ_BAND : 6;//equalizer coefficients,60Hz band
|
||||
uint32_t EQ_170HZ_BAND : 6;//equalizer coefficients,170Hz band
|
||||
uint32_t EQ_310HZ_BAND : 6;//equalizer coefficients,310Hz band
|
||||
uint32_t EQ_600HZ_BAND : 6;//equalizer coefficients,600Hz band
|
||||
uint32_t EQ_1KHZ_BAND : 6;//equalizer coefficients,1KHz band
|
||||
uint32_t RSV : 2;//
|
||||
} Bits;
|
||||
} REG_MP3D_EQ0_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t EQ_3kHZ_BAND : 6;//equalizer coefficients,3KHz band
|
||||
uint32_t EQ_6kHZ_BAND : 6;//equalizer coefficients,6KHz band
|
||||
uint32_t EQ_12kHZ_BAND : 6;//equalizer coefficients,12KHz band
|
||||
uint32_t EQ_14kHZ_BAND : 6;//equalizer coefficients,14KHz band
|
||||
uint32_t EQ_16KHZ_BAND : 6;//equalizer coefficients,16KHz band
|
||||
uint32_t RSV : 2;//
|
||||
} Bits;
|
||||
} REG_MP3D_EQ1_t;
|
||||
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t MP3_STREAM_AUDIO_VER : 2;//MP3 stream audio version 11172 or 13818
|
||||
uint32_t MP3_STREAM_ERROR_PROTECT : 1;//mp3 stream error protection
|
||||
uint32_t MP3_STREAM_BIT_RATE : 4;//mp3 stream bit rate
|
||||
uint32_t MP3_STREAM_SAMPLE_RATE : 2;//mp3 stream sample rate
|
||||
uint32_t MP3_STREAM_AUDIO_MODE : 2;//mp3 stream audio mode
|
||||
uint32_t MP3_STREAM_AUDIO_MODE_EXTEN : 2;//mp3 stream audio mode extension
|
||||
uint32_t MP3_STREAM_COPYRIGHT : 1;//mp3 stream copyright
|
||||
uint32_t MP3_STREAM_ORIGINAL : 1;//mp3 stream original
|
||||
uint32_t MP3_STREAM_AUDIO_EMPHASIS : 2;//mp3 stream emphasis
|
||||
uint32_t MP3_FRAME_LOCKED : 1;//mp3 frame locked bit[16:0] valid only when frame locked
|
||||
uint32_t MP3_MAIN_DONE : 1;//mp3 huffman main done
|
||||
uint32_t MP3_MAIN_EXHAUST : 1;//mp3 huffman main exhaust
|
||||
uint32_t RSV : 12;//
|
||||
} Bits;
|
||||
} REG_MP3D_INFO_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t MP3_DATA_SOURCE_SIZE : 16;//mp3 data source buffer size
|
||||
uint32_t RSV : 16;//
|
||||
} Bits;
|
||||
} REG_MP3D_SSIZE_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t MP3_PCM_BUFFER_SIZE : 16;//mp3 pcm buffer size (32 bit align)
|
||||
uint32_t RSV : 16;//
|
||||
} Bits;
|
||||
} REG_MP3D_PSIZE_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_MP3D_CTRL_t MP3D_CTRL; /* Offset 0x00 */
|
||||
volatile REG_MP3D_INTMASK_t MP3D_INTMASK; /* Offset 0x04 */
|
||||
volatile REG_MP3D_INTSTA_t MP3D_INTSTA; /* Offset 0x08 */
|
||||
volatile REG_MP3D_VOL_t MP3D_VOL; /* Offset 0x0C */
|
||||
volatile REG_MP3D_EQ0_t MP3D_EQ0; /* Offset 0x10*/
|
||||
volatile REG_MP3D_EQ1_t MP3D_EQ1; /* Offset 0x14 */
|
||||
volatile REG_MP3D_INFO_t MP3D_INFO; /* Offser 0x18*/
|
||||
volatile uint32_t MP3D_SADDR; /* Offser 0x1C*/
|
||||
volatile REG_MP3D_SSIZE_t MP3D_SSIZE; /* Offser 0x20*/
|
||||
volatile uint32_t MP3D_PADDR; /* Offser 0x24*/
|
||||
volatile REG_MP3D_PSIZE_t MP3D_PSIZE; /* Offser 0x28*/
|
||||
volatile uint32_t RSV[3]; /*Offser 0x2C-0x34*/
|
||||
volatile uint32_t MP3D_FRMCNT; /* Offser 0x38*/
|
||||
}struct_MP3D_t;
|
||||
|
||||
typedef struct{
|
||||
volatile uint32_t audio_ver;
|
||||
volatile uint32_t error_protection;
|
||||
volatile uint32_t bit_rate;
|
||||
volatile uint32_t sample_rate;
|
||||
volatile uint32_t audio_mode;
|
||||
volatile uint32_t mode_extension;
|
||||
volatile uint32_t copyright;
|
||||
volatile uint32_t original;
|
||||
volatile uint32_t audio_emphasis;
|
||||
volatile uint32_t frame_locked;
|
||||
volatile uint32_t main_done;
|
||||
volatile uint32_t main_exhaust;
|
||||
}struct_MP3D_stream_info_t;
|
||||
|
||||
typedef enum{
|
||||
SOURCE_COMPLETE_ISR = 0,
|
||||
PCM_BUF_UNDERRUN_ISR,
|
||||
PCM_BUF_FULL_ISR,
|
||||
MP3_FRAME_LOCKED_ISR,
|
||||
}enum_mp3d_isr_t;
|
||||
|
||||
#define MP3D ((struct_MP3D_t *)MP3_DEC_BASE)
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t DAI_EN : 1;
|
||||
uint32_t ISR_EN : 1;
|
||||
uint32_t VOL : 5;
|
||||
} Bits;
|
||||
} struct_MP3Dec_Init_t;
|
||||
|
||||
|
||||
typedef struct __MP3_DEC_HandleTypeDef
|
||||
{
|
||||
struct_MP3Dec_Init_t mp3dec_ctrl_Init;
|
||||
REG_MP3D_EQ0_t mp3dec_eq0_Init;
|
||||
REG_MP3D_EQ1_t mp3dec_eq1_Init;
|
||||
uint8_t *MP3Enced_Data;
|
||||
uint32_t MP3Enced_Index;
|
||||
uint32_t FrameLen;
|
||||
uint32_t LeftLen;
|
||||
void (*Callback)(struct __MP3_DEC_HandleTypeDef *hSbcDec); /*!< MP3 decode finish Callback */
|
||||
}MP3_DEC_HandleTypeDef;
|
||||
|
||||
#define __MP3D_SOFTRST() (MP3D->MP3D_CTRL.Bits.MP3D_SOFTRST = 1)
|
||||
#define __MP3D_PCM_FIFO_RESET() (MP3D->MP3D_CTRL.Bits.RESET_PCM_FIFO = 1)
|
||||
#define __MP3D_ISSUE_NEW_FILE() (MP3D->MP3D_CTRL.Bits.ISSUE_NEW_FILE = 1)
|
||||
#define __MP3D_OPERA_ENABLE() (MP3D->MP3D_CTRL.Bits.OPERA_EN = 1)
|
||||
#define __MP3D_SET_FRMCNT(frmcnt) (MP3D->MP3D_FRMCNT = frmcnt)
|
||||
#define __MP3D_GET_FRMCNT (MP3D->MP3D_FRMCNT)
|
||||
#define __MP3D_GET_INTSTA (MP3D->MP3D_INTSTA.Word)
|
||||
#define __MP3D_CHECK_NEED_SEC() (MP3D->MP3D_INTSTA.Bits.SOURCE_CMPLETION_ISR == 1)
|
||||
#define __MP3D_RESTART() (MP3D->MP3D_CTRL.Bits.RESTART_DEC = 1)
|
||||
|
||||
#define __MP3D_PCM_BUFF_FULL_ISR_IS_SET() (MP3D->MP3D_INTSTA.Bits.PCM_BUFFER_FULL_ISR == 1)
|
||||
#define __MP3D_SRC_COMPLETE_ISR_IS_SET() (MP3D->MP3D_INTSTA.Bits.SOURCE_CMPLETION_ISR == 1)
|
||||
|
||||
#define __MP3D_COMPLETE_ISR_DISABLE() (MP3D->MP3D_INTMASK.Bits.SOURCE_CMPLETION_ISR_EN = 0)
|
||||
#define __MP3D_COMPLETE_ISR_ENABLE() (MP3D->MP3D_INTMASK.Bits.SOURCE_CMPLETION_ISR_EN = 1)
|
||||
|
||||
/* mp3 decoder init */
|
||||
void mp3_dec_init(MP3_DEC_HandleTypeDef *hmp3dec, uint32_t *pcm_buff, uint32_t pcm_buf_size);
|
||||
/* mp3 decoder play data without isr */
|
||||
void mp3_dec_playdata(MP3_DEC_HandleTypeDef *hmp3dec, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
/* mp3 decoder get stream information */
|
||||
void mp3d_get_stream_info(struct_MP3D_stream_info_t *info);
|
||||
/* mp3 decoder failed */
|
||||
int mp3d_check_dec_failed(void);
|
||||
/* mp3 decoder handle function in mp3 decoder isr */
|
||||
void mp3dec_IRQHandler(MP3_DEC_HandleTypeDef *hmp3dec);
|
||||
/* mp3 decoder play data with isr */
|
||||
void mp3_dec_playdata_IT(MP3_DEC_HandleTypeDef *hmp3dec, uint8_t *fp_Data, uint32_t fu32_Size);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,263 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_parallel_interface.H
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of parallel_interface HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_PARALLEL_INTERFACE_H__
|
||||
#define __DRIVER_PARALLEL_INTERFACE_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup Parallel_Interface_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* parallel interface config */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DC_POLARITY : 1;
|
||||
uint32_t CS_POLARITY : 1;
|
||||
uint32_t MODE : 1;
|
||||
uint32_t PARA_WIDTH : 1;
|
||||
uint32_t rsv_0 : 28;
|
||||
}REG_INTERFACE_CFG_t;
|
||||
|
||||
/* Write/Read clock Config */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WRITE_CLK_CFG : 3;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t READ_CLK_CFG : 4;
|
||||
uint32_t WR_L_LEN : 3;
|
||||
uint32_t rsv_1 : 1;
|
||||
uint32_t WR_H_LEN : 3;
|
||||
uint32_t rsv_2 : 17;
|
||||
}REG_WR_CLK_t;
|
||||
|
||||
/* Data transmission Configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DATA_TRANS_SEQ_0 : 2;
|
||||
uint32_t DATA_TRANS_SEQ_1 : 2;
|
||||
uint32_t DATA_TRANS_SEQ_2 : 2;
|
||||
uint32_t DATA_TRANS_SEQ_3 : 2;
|
||||
uint32_t rsv_1 :24;
|
||||
}REG_DATA_CFG_t;
|
||||
|
||||
/* DMA Configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_TX_LEVEL : 5;
|
||||
uint32_t DMA_ENABLE : 1;
|
||||
uint32_t rsv_0 : 26;
|
||||
}REG_DMA_t;
|
||||
|
||||
/* -------------------------------------------*/
|
||||
/* parallel Register */
|
||||
/* -------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_INTERFACE_CFG_t INTF_CFG; /* offset 0x00 */
|
||||
volatile uint32_t CSX; /* offset 0x04 */
|
||||
volatile REG_WR_CLK_t CRM; /* offset 0x08 */
|
||||
volatile uint32_t BUS_STATUS; /* offset 0x0C */
|
||||
volatile uint32_t CFG; /* offset 0x10 */
|
||||
volatile uint32_t DATA_WR_LEN; /* offset 0x14 */
|
||||
volatile REG_DATA_CFG_t DATA_CFG; /* offset 0x18 */
|
||||
volatile uint32_t TX_FIFO; /* offset 0x1C */
|
||||
volatile uint32_t RD_REQ; /* offset 0x20 */
|
||||
volatile uint32_t DAT_RD; /* offset 0x24 */
|
||||
volatile uint32_t TXFF_AEMP_LV; /* offset 0x28 */
|
||||
volatile uint32_t TXFF_CLR; /* offset 0x2C */
|
||||
volatile uint32_t INT_CONTROL; /* offset 0x30 */
|
||||
volatile uint32_t INT_STATUS; /* offset 0x34 */
|
||||
volatile REG_DMA_t DMA; /* offset 0x38 */
|
||||
}struct_Parallel_t;
|
||||
|
||||
#define PARALLEL0 ((struct_Parallel_t *)PARALLEL_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup Parallel_Interface_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization_Config Section Start ################################ */
|
||||
|
||||
/** @defgroup PARALLEL_FIFO PARALLEL FIFO
|
||||
* @{
|
||||
*/
|
||||
#define PARALLEL_FIFO_DEPTH 32
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* mode select */
|
||||
typedef enum
|
||||
{
|
||||
MODE_8080,
|
||||
MODE_6800,
|
||||
}enum_Parallel_MODE_t;
|
||||
|
||||
/* data bus width */
|
||||
typedef enum
|
||||
{
|
||||
DATA_BUS_8_BIT,
|
||||
DATA_BUS_16_BIT,
|
||||
}enum_DATA_BUS_t;
|
||||
|
||||
/* read clock division */
|
||||
typedef enum
|
||||
{
|
||||
RDCLK_DIV_1,
|
||||
RDCLK_DIV_2,
|
||||
RDCLK_DIV_3,
|
||||
RDCLK_DIV_4,
|
||||
RDCLK_DIV_6,
|
||||
RDCLK_DIV_8,
|
||||
RDCLK_DIV_16,
|
||||
RDCLK_DIV_32,
|
||||
RDCLK_DIV_64,
|
||||
}enum_RDCLK_DIV_t;
|
||||
|
||||
/* write clock division */
|
||||
typedef enum
|
||||
{
|
||||
WDCLK_DIV_1,
|
||||
WDCLK_DIV_2,
|
||||
WDCLK_DIV_3,
|
||||
WDCLK_DIV_4,
|
||||
WDCLK_DIV_6,
|
||||
WDCLK_DIV_8,
|
||||
}enum_WDCLK_DIV_t;
|
||||
|
||||
/* interrupt index */
|
||||
typedef enum
|
||||
{
|
||||
INT_TXFIFO_FULL = 0x00000001,
|
||||
INT_TXFIFO_EMPTY = 0x00000002,
|
||||
INT_TXFIFO_LEVEMPT = 0x00000004,
|
||||
}enum_INT_t;
|
||||
|
||||
/**
|
||||
* @brief parallel Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ParallelMode; /* This parameter can be a value of @ref enum_Parallel_MODE_t */
|
||||
|
||||
uint32_t DataBusSelect; /* This parameter can be a value of @ref enum_DATA_BUS_t */
|
||||
|
||||
uint32_t ReadClock; /* This parameter can be a value of @ref enum_RDCLK_DIV_t */
|
||||
|
||||
uint32_t WriteClock; /* This parameter can be a value of @ref enum_WDCLK_DIV_t */
|
||||
}str_ParallelInit_t;
|
||||
|
||||
/**
|
||||
* @brief parallel handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
struct_Parallel_t *PARALLELx; /*!< PARALLEL registers base address */
|
||||
|
||||
str_ParallelInit_t Init; /*!< PARALLEL communication parameters */
|
||||
}PARALLEL_HandTypeDef;
|
||||
|
||||
/* ################################ Initialization_Config Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Parallel tx fifo level */ /* fu8_level: 0 ~ 31 */
|
||||
#define __PARALLEL_TX_FIFO_ALMOST_EMPTY_LEVEL(__PARALLELx__, __LEVEL__) (__PARALLELx__->TXFF_AEMP_LV = __LEVEL__)
|
||||
|
||||
/* Parallel tx fifo reset */
|
||||
/* Parallel tx fifo release */
|
||||
#define __PARALLEL_TX_FIFO_RESET(__PARALLELx__) (__PARALLELx__->TXFF_CLR = 0x07)
|
||||
#define __PARALLEL_TX_FIFO_RELEASE(__PARALLELx__) (__PARALLELx__->TXFF_CLR = 0x00)
|
||||
|
||||
/* Parallel writer CMD */
|
||||
#define __PARALLEL_WR_CMD(__PARALLELx__ , __CMD__) (__PARALLELx__->CFG = __CMD__)
|
||||
#define __PARALLEL_WR_PARAM(__PARALLELx__ , __DATA__) (__PARALLELx__->CFG = 0x10000 | __DATA__)
|
||||
|
||||
/* Parallel get interrupt status */
|
||||
#define __PARALLEL_INT_STATUS(__PARALLELx__) (__PARALLELx__->INT_STATUS)
|
||||
/* Parallel interrupt Status enable/disable */
|
||||
#define __PARALLEL_INT_STATUS_ENABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL |= (__STATUS__))
|
||||
#define __PARALLEL_INT_STATUS_DISABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL &= ~(__STATUS__))
|
||||
#define __PARALLEL_INT_STATUS_ALL_ENABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL = 0x0F)
|
||||
#define __PARALLEL_INT_STATUS_ALL_DISABLE(__PARALLELx__, __STATUS__) (__PARALLELx__->INT_CONTROL = 0x00)
|
||||
|
||||
/* Parallel bus status */
|
||||
#define __PARALLEL_IS_BUS_BUSY(__PARALLELx__) (__PARALLELx__->BUS_STATUS)
|
||||
/* Parallel bus status */
|
||||
#define __PARALLEL_RD_REQ(__PARALLELx__) (__PARALLELx__->RD_REQ = 0x1)
|
||||
|
||||
/* Parallel_dma_requset_level */ /* fu8_level: 0 ~ 31 */
|
||||
#define __PARALLEL_DMA_TX_LEVEL(__PARALLELx__, __LEVEL__) (__PARALLELx__->DMA.DMA_TX_LEVEL = __LEVEL__)
|
||||
/* Parallel_dma ENABLE and DISABLE */
|
||||
#define __PARALLEL_DMA_ENABLE(__PARALLELx__) (__PARALLELx__->DMA.DMA_ENABLE = 1)
|
||||
#define __PARALLEL_DMA_DISABLE(__PARALLELx__) (__PARALLELx__->DMA.DMA_ENABLE = 0)
|
||||
|
||||
/* Parallel_cs_set */
|
||||
/* Parallel_cs_release */
|
||||
#define __PARALLEL_CS_SET(__PARALLELx__) (__PARALLELx__->CSX = 0)
|
||||
#define __PARALLEL_CS_RELEASE(__PARALLELx__) (__PARALLELx__->CSX = 1)
|
||||
|
||||
/* Parallel_set_bus_8bit */
|
||||
/* Parallel_set_bus_16bit */
|
||||
#define __PARALLEL_SET_BUS_8BIT(__PARALLELx__) (__PARALLELx__->INTF_CFG.PARA_WIDTH = DATA_BUS_8_BIT)
|
||||
#define __PARALLEL_SET_BUS_16BIT(__PARALLELx__) (__PARALLELx__->INTF_CFG.PARA_WIDTH = DATA_BUS_16_BIT)
|
||||
|
||||
/* Parallel_wrclk_div */
|
||||
/* Parallel_rdclk_div */
|
||||
#define __PARALLEL_WRCLK_DIV(__PARALLELx__, __WDCLK_DIV__) (__PARALLELx__->CRM.WRITE_CLK_CFG = __WDCLK_DIV__)
|
||||
#define __PARALLEL_RDCLK_DIV(__PARALLELx__, __RDCLK_DIV__) (__PARALLELx__->CRM.READ_CLK_CFG = __RDCLK_DIV__)
|
||||
|
||||
/* Parallel_wrclk_HighLength */
|
||||
/* Parallel_wrclk_LowLength */
|
||||
#define __PARALLEL_WRCLK_HIGHLENGTH(__PARALLELx__, __LENGTH__) (__PARALLELx__->CRM.WR_H_LEN = __LENGTH__)
|
||||
#define __PARALLEL_WRCLK_LOWLENGTH(__PARALLELx__, __LENGTH__) (__PARALLELx__->CRM.WR_L_LEN = __LENGTH__)
|
||||
|
||||
/* Parallel_CS_Polarity */ /* fb_Polarity: 1: high active */
|
||||
/* Parallel_DC_Polarity */ /* 0: low active */
|
||||
#define __PARALLEL_CS_POLARITY(__PARALLELx__, __POLARITY__) (__PARALLELx__->INTF_CFG.CS_POLARITY = __POLARITY__)
|
||||
#define __PARALLEL_DC_POLARITY(__PARALLELx__, __FB_POLARITY__) (__PARALLELx__->INTF_CFG.DC_POLARITY = __POLARITY__)
|
||||
|
||||
/* __PARALLEL_Set_WR_LEN */
|
||||
#define __PARALLEL_SET_WR_LEN(__PARALLELx__, __LEVEL__) (__PARALLELx__->DATA_WR_LEN = __LEVEL__)
|
||||
|
||||
|
||||
/* Exported functions ---------------------------------------------------------------*/
|
||||
|
||||
/* parallel_init */
|
||||
void parallel_init(PARALLEL_HandTypeDef *hparallel);
|
||||
|
||||
/* Parallel_write_cmd */
|
||||
/* Parallel_write_param */
|
||||
/* Parallel_write_data */
|
||||
void Parallel_write_cmd(PARALLEL_HandTypeDef *hparallel, uint8_t fp8_CMD);
|
||||
void Parallel_write_param(PARALLEL_HandTypeDef *hparallel, uint16_t fu16_Data);
|
||||
void Parallel_write_data(PARALLEL_HandTypeDef *hparallel, uint32_t *fp32_WriteBuffer, uint32_t fu32_WriteNum);
|
||||
|
||||
/* Parallel_read_data_8bit */
|
||||
/* Parallel_read_data_16bit */
|
||||
void Parallel_read_data_8bit(PARALLEL_HandTypeDef *hparallel, uint8_t fu8_Param, uint8_t *fp8_ReadBuffer, uint32_t fu32_ReadNum);
|
||||
void Parallel_read_data_16bit(PARALLEL_HandTypeDef *hparallel, uint8_t fu8_Param, uint16_t *fp16_ReadBuffer, uint32_t fu32_ReadNum);
|
||||
|
||||
#endif
|
||||
255
fr3092_mcu/components/drivers/peripheral/Inc/driver_pdm.h
Normal file
255
fr3092_mcu/components/drivers/peripheral/Inc/driver_pdm.h
Normal file
@ -0,0 +1,255 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_pdm.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of pdm HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_PDM_H__
|
||||
#define __DRIVER_PDM_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
#include <math.h>
|
||||
|
||||
/** @addtogroup PDM_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* PDM config register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EN : 1;
|
||||
uint32_t CLK_EN : 1;
|
||||
uint32_t RST : 1;
|
||||
uint32_t DAT_INV : 1;
|
||||
uint32_t CLK_INV : 1;
|
||||
uint32_t USB_MODE : 1;
|
||||
uint32_t SAMPLE_RATE : 4;
|
||||
uint32_t OSR_MODE : 2;
|
||||
uint32_t MONO : 1;
|
||||
uint32_t CH_SEL : 1;
|
||||
uint32_t LR_SWAP : 1;
|
||||
uint32_t HPF_EN : 1;
|
||||
uint32_t rsv_0 : 16;
|
||||
}REG_PDMConfig_t;
|
||||
|
||||
/* PDM FIFO Reset Register */
|
||||
typedef union{
|
||||
struct {
|
||||
uint32_t PUSH_RST : 1;
|
||||
uint32_t POP_RST : 1;
|
||||
uint32_t RST : 1;
|
||||
uint32_t rsv : 29;
|
||||
} s;
|
||||
uint32_t rst;
|
||||
}REG_PDMFFReset_t;
|
||||
|
||||
/* PDM interrupt Register */
|
||||
typedef struct{
|
||||
uint32_t FF_FULL : 1;
|
||||
uint32_t FF_AFULL : 1;
|
||||
uint32_t FF_EMPTY : 1;
|
||||
uint32_t rsv : 29;
|
||||
}REG_PDMFFInt_t;
|
||||
|
||||
/* PDM interrupt Register */
|
||||
typedef struct{
|
||||
uint32_t TRIG_LVL : 6;
|
||||
uint32_t EN : 1;
|
||||
uint32_t rsv : 25;
|
||||
}REG_PDMDMA_t;
|
||||
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* PDM Register */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_PDMConfig_t Config; /* Offset 0x00 */
|
||||
volatile uint32_t FF_AFLL_LVL; /* Offset 0x04 */
|
||||
volatile REG_PDMFFReset_t FF_RST; /* Offset 0x08 */
|
||||
volatile REG_PDMFFInt_t INT_EN; /* Offset 0x0C */
|
||||
volatile REG_PDMFFInt_t INT_STA; /* Offset 0x10 */
|
||||
volatile REG_PDMFFInt_t INT_RAW_STA; /* Offset 0x14 */
|
||||
volatile uint32_t VOL_L; /* Offset 0x18 */
|
||||
volatile uint32_t VOL_R; /* Offset 0x1C */
|
||||
volatile uint32_t rsv1; /* Offset 0x20 */
|
||||
volatile uint32_t DATA; /* Offset 0x24 */
|
||||
volatile REG_PDMDMA_t DMA_CFG; /* Offset 0x28 */
|
||||
}struct_PDM_t;
|
||||
|
||||
#define PDM0 ((struct_PDM_t *)PDM0_BASE)
|
||||
#define PDM1 ((struct_PDM_t *)PDM1_BASE)
|
||||
#define PDM2 ((struct_PDM_t *)PDM2_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PDM_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization Config Section Start ################################ */
|
||||
|
||||
/* PDM Sample Rate */
|
||||
typedef enum
|
||||
{
|
||||
PDM_SAMPLE_RATE_8000 = 0x00,
|
||||
PDM_SAMPLE_RATE_12000 = 0x01,
|
||||
PDM_SAMPLE_RATE_16000 = 0x02,
|
||||
PDM_SAMPLE_RATE_24000 = 0x03,
|
||||
PDM_SAMPLE_RATE_32000 = 0x04,
|
||||
PDM_SAMPLE_RATE_48000 = 0x05,
|
||||
PDM_SAMPLE_RATE_96000 = 0x06,
|
||||
PDM_SAMPLE_RATE_192000 = 0x07,
|
||||
PDM_SAMPLE_RATE_8012 = 0x08,
|
||||
PDM_SAMPLE_RATE_11025 = 0x09,
|
||||
PDM_SAMPLE_RATE_22050 = 0x0A,
|
||||
PDM_SAMPLE_RATE_44100 = 0x0B,
|
||||
PDM_SAMPLE_RATE_88200 = 0x0C,
|
||||
PDM_SAMPLE_RATE_176400 = 0x0D,
|
||||
PDM_SAMPLE_RATE_44_1K_SET = 0x08,
|
||||
}enum_PDM_SampleRate_t;
|
||||
|
||||
/* PDM Clock Mode Selection */
|
||||
typedef enum{
|
||||
PDM_CLOCK_MODE_NORMAL, /* clock from AUPLL2 */
|
||||
PDM_CLOCK_MODE_USB, /* clock is 24MHz */
|
||||
}enum_PDM_ClockMode_t;
|
||||
|
||||
/* PDM Over Sample Mode */
|
||||
typedef enum{
|
||||
PDM_OSM_0, // oversampling low level support to all SampleRate.
|
||||
PDM_OSM_1, // oversampling middle level support up to 96K.
|
||||
PDM_OSM_2, // oversampling high level support up to 48K.
|
||||
}enum_PDM_OverSampleMode_t;
|
||||
|
||||
/* PDM Channel Selection in Mono mode */
|
||||
typedef enum{
|
||||
PDM_MONO_LEFT, /* Mono selcet left */
|
||||
PDM_MONO_RIGHT, /* Mono selcet right */
|
||||
PDM_STEREO, /* stereo */
|
||||
}enum_PDM_ChannelMode_t;
|
||||
|
||||
/* PDM Volume */
|
||||
typedef enum{
|
||||
PDM_VOL_0,
|
||||
PDM_VOL_1,
|
||||
PDM_VOL_2,
|
||||
PDM_VOL_3,
|
||||
PDM_VOL_4,
|
||||
PDM_VOL_5,
|
||||
PDM_VOL_6,
|
||||
PDM_VOL_7,
|
||||
PDM_VOL_8,
|
||||
PDM_VOL_9,
|
||||
PDM_VOL_10,
|
||||
PDM_VOL_11,
|
||||
PDM_VOL_12,
|
||||
PDM_VOL_13,
|
||||
PDM_VOL_14,
|
||||
PDM_VOL_15,
|
||||
PDM_VOL_MAX
|
||||
}enum_PDM_Volume_t;
|
||||
|
||||
/*
|
||||
* @brief PDM Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t SampleRate; /* This parameter can be a value of @ref enum_PDM_SampleRate_t */
|
||||
|
||||
uint8_t OverSampleMode; /* This parameter can be a value of @ref enum_PDM_OverSampleMode_t */
|
||||
|
||||
uint8_t ChannelMode; /* This parameter can be a value of @ref enum_PDM_ChannelMode_t */
|
||||
|
||||
int8_t Volume; /* This parameter can be a value with dB as unit */
|
||||
|
||||
uint8_t FIFO_FullThreshold; /* This parameter can be a 5 bit value */
|
||||
}struct_PDMInit_t;
|
||||
|
||||
/*
|
||||
* @brief PDM handle Structure definition
|
||||
*/
|
||||
typedef struct __PDM_HandleTypeDef
|
||||
{
|
||||
struct_PDM_t *PDMx; /*!< PDM registers base address */
|
||||
|
||||
struct_PDMInit_t Init; /*!< PDM communication parameters */
|
||||
|
||||
void (*RxCallback)(struct __PDM_HandleTypeDef *hpdm);
|
||||
|
||||
bool b_RxBusy;
|
||||
void *p_RxData;
|
||||
}PDM_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define PDM_FIFO_DEPTH 64
|
||||
#define PDM_FIFO_H_FULL (PDM_FIFO_DEPTH / 2)
|
||||
#define PDM_VOL_dB(x) (uint32_t)(pow(10.0, (x)/20.0) * 0x2000)
|
||||
|
||||
/* PDM enable/disable */
|
||||
#define __PDM_ENABLE(__PDMx__) (__PDMx__->Config.EN = 1)
|
||||
#define __PDM_DISABLE(__PDMx__) (__PDMx__->Config.EN = 0)
|
||||
/* PDM clock enable/disable */
|
||||
#define __PDM_CLK_ENABLE(__PDMx__) (__PDMx__->Config.CLK_EN = 1)
|
||||
#define __PDM_CLK_DISABLE(__PDMx__) (__PDMx__->Config.CLK_EN = 0)
|
||||
|
||||
#define __PDM_SWAP_ENABLE(__PDMx__) (__PDMx__->Config.LR_SWAP = 1)
|
||||
#define __PDM_SWAP_DISABLE(__PDMx__) (__PDMx__->Config.LR_SWAP = 0)
|
||||
|
||||
/* PDM clock mode. 0: from AUPLL. 1: from 24M */
|
||||
#define __PDM_CLK_MODE(__PDMx__, __MODE__) (__PDMx__->Config.USB_MODE = __MODE__)
|
||||
|
||||
/* PDM FIFO interrupt enable/disable */
|
||||
#define __PDM_FIFO_FULL_INT_ENABLE(__PDMx__) (__PDMx__->INT_EN.FF_FULL = 1)
|
||||
#define __PDM_FIFO_EMPTY_INT_ENABLE(__PDMx__) (__PDMx__->INT_EN.FF_EMPTY = 1)
|
||||
#define __PDM_FIFO_ALMOST_FULL_INT_ENABLE(__PDMx__) (__PDMx__->INT_EN.FF_AFULL = 1)
|
||||
|
||||
#define __PDM_FIFO_FULL_INT_DISABLE(__PDMx__) (__PDMx__->INT_EN.FF_FULL = 0)
|
||||
#define __PDM_FIFO_EMPTY_INT_DISABLE(__PDMx__) (__PDMx__->INT_EN.FF_EMPTY = 0)
|
||||
#define __PDM_FIFO_ALMOST_FULL_INT_DISABLE(__PDMx__) (__PDMx__->INT_EN.FF_AFULL = 0)
|
||||
|
||||
/* PDM FIFO status */
|
||||
#define __PDM_IS_FIFO_FULL(__PDMx__) (__PDMx__->INT_RAW_STA.FF_FULL)
|
||||
#define __PDM_IS_FIFO_EMPTY(__PDMx__) (__PDMx__->INT_RAW_STA.FF_EMPTY)
|
||||
#define __PDM_IS_FIFO_ALMOST_FULL(__PDMx__) (__PDMx__->INT_RAW_STA.FF_AFULL)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void pdm_IRQHandler(PDM_HandleTypeDef *hpdm);
|
||||
|
||||
/* pdm_init */
|
||||
void pdm_init(PDM_HandleTypeDef *hpdm);
|
||||
|
||||
/* pdm_start/stio */
|
||||
void pdm_start(PDM_HandleTypeDef *hpdm);
|
||||
void pdm_stop(PDM_HandleTypeDef *hpdm);
|
||||
|
||||
/* pdm_start_IT */
|
||||
void pdm_start_IT(PDM_HandleTypeDef *hpdm, void *fp_Data);
|
||||
|
||||
/* pdm_vol_set */
|
||||
void pdm_vol_set(PDM_HandleTypeDef *hpdm, int8_t vol);
|
||||
|
||||
/* pdm_read_data */
|
||||
void pdm_read_data(PDM_HandleTypeDef *hpdm, void *fp_Data);
|
||||
|
||||
#endif
|
||||
598
fr3092_mcu/components/drivers/peripheral/Inc/driver_pmu.h
Normal file
598
fr3092_mcu/components/drivers/peripheral/Inc/driver_pmu.h
Normal file
@ -0,0 +1,598 @@
|
||||
#ifndef _DRIVER_PMU_H
|
||||
#define _DRIVER_PMU_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/// PMU module clock source
|
||||
#define PMU_REG_CLK 0x00
|
||||
/// 1: external XTAL32768, 0: internal 62K RC
|
||||
#define PMU_SYSCLK_SEL_POS 0
|
||||
#define PMU_SYSCLK_SEL_BIT 0x01
|
||||
|
||||
/// configure PMU on-off base timing dividor
|
||||
#define PMU_REG_FSM_TIMER 0x01
|
||||
#define PMU_FSM_OFF_DIV_LSB 5
|
||||
#define PMU_FSM_OFF_DIV_MSK 0xE0
|
||||
#define PMU_FSM_ON_DIV_LSB 0
|
||||
#define PMU_FSM_ON_DIV_MSK 0x1F
|
||||
|
||||
/// configure debounce module dividor
|
||||
#define PMU_REG_DEB_CLK_DIV 0x02
|
||||
|
||||
/// configure PMU reset source
|
||||
#define PMU_REG_RST_SRC_EN 0x03
|
||||
#define PMU_LOW_BAT_RST_POS 2
|
||||
#define PMU_LOW_BAT_RST_BIT (1<<2)
|
||||
#define PMU_WDT_RST_POS 1
|
||||
#define PMU_WDT_RST_BIT (1<<1)
|
||||
#define PMU_PIN_RST_POS 0
|
||||
#define PMU_PIN_RST_BIT (1<<0)
|
||||
|
||||
/// configure module clock enalbe
|
||||
#define PMU_REG_CLK_EN 0x04
|
||||
#define PMU_EFUSE_CLK_EN_POS 7
|
||||
#define PMU_EFUSE_CLK_EN_BIT (1<<7)
|
||||
#define PMU_FILTER_CLK_EN_POS 6
|
||||
#define PMU_FILTER_CLK_EN_BIT (1<<6)
|
||||
#define PMU_QDEC_CLK_EN_POS 5
|
||||
#define PMU_QDEC_CLK_EN_BIT (1<<5)
|
||||
#define PMU_KEYSCAN_CLK_EN_POS 4
|
||||
#define PMU_KEYSCAN_CLK_EN_BIT (1<<4)
|
||||
#define PMU_DEB_CLK_EN_POS 3
|
||||
#define PMU_DEB_CLK_EN_BIT (1<<3)
|
||||
#define PMU_RTC_CLK_EN_POS 2
|
||||
#define PMU_RTC_CLK_EN_BIT (1<<2)
|
||||
#define PMU_WDT_CLK_EN_POS 1
|
||||
#define PMU_WDT_CLK_EN_BIT (1<<1)
|
||||
#define PMU_LP_TICK_CLK_EN_POS 0
|
||||
#define PMU_LP_TICK_CLK_EN_BIT (1<<0)
|
||||
|
||||
/// reset modules inside PMU
|
||||
#define PMU_REG_RST 0x05
|
||||
#define PMU_EFUSE_SFT_RST_POS 7
|
||||
#define PMU_EFUSE_SFT_RST_BIT (1<<7)
|
||||
#define PMU_FILTER_SFT_RST_POS 6
|
||||
#define PMU_FILTER_SFT_RST_BIT (1<<6)
|
||||
#define PMU_QDEC_SFT_RST_POS 5
|
||||
#define PMU_QDEC_SFT_RST_BIT (1<<5)
|
||||
#define PMU_KEYSCAN_SFT_RST_POS 4
|
||||
#define PMU_KEYSCAN_SFT_RST_BIT (1<<4)
|
||||
#define PMU_DEB_SFT_RST_POS 3
|
||||
#define PMU_DEB_SFT_RST_BIT (1<<3)
|
||||
#define PMU_RTC_SFT_RST_POS 2
|
||||
#define PMU_RTC_SFT_RST_BIT (1<<2)
|
||||
#define PMU_WDT_SFT_RST_POS 1
|
||||
#define PMU_WDT_SFT_RST_BIT (1<<1)
|
||||
#define PMU_LP_TICK_SFT_RST_POS 0
|
||||
#define PMU_LP_TICK_SFT_RST_BIT (1<<0)
|
||||
|
||||
/// indicate which module could put PMU into sleep mode or wake up PMU
|
||||
#define PMU_REG_SLP_WK_SRC 0x06
|
||||
#define PMU_WK_IRQ_EN_POS 5
|
||||
#define PMU_WK_IRQ_EN_BIT (1<<5)
|
||||
#define PMU_WK_TICK_EN_POS 4
|
||||
#define PMU_WK_TICK_EN_BIT (1<<4)
|
||||
#define PMU_SLP_CPU_EN_POS 1
|
||||
#define PMU_SLP_CPU_EN_BIT (1<<1)
|
||||
#define PMU_SLP_TICK_EN_POS 0
|
||||
#define PMU_SLP_TICK_EN_BIT (1<<0)
|
||||
|
||||
/// control PMU wakeup or enter sleep by software
|
||||
#define PMU_REG_SW_OP 0x07
|
||||
#define PMU_SW_WK_TICK_POS 1
|
||||
#define PMU_SW_WK_TICK_BIT (1<<1)
|
||||
#define PMU_SW_EN_SLP_POS 0
|
||||
#define PMU_SW_EN_SLP_BIT (1<<0)
|
||||
|
||||
/// default value is 0xAD
|
||||
#define PMU_REG_STATUS 0x08
|
||||
#define PMU_STATUS_DEEP_SLEEP 0xC3
|
||||
#define PMU_STATUS_NORAML 0xAD
|
||||
|
||||
/// indicate which module could wake up TICK
|
||||
#define PMU_REG_TICK_CTRL 0x09
|
||||
#define PMU_IRQ_WK_TICK_EN_POS 3
|
||||
#define PMU_IRQ_WK_TICK_EN_BIT (1<<3)
|
||||
/// this bit has to be set when PMU_IRQ_WK_TICK_EN_BIT is set
|
||||
#define PMU_EXT_WK_TICK_EN_POS 1
|
||||
#define PMU_EXT_WK_TICK_EN_BIT (1<<1)
|
||||
#define PMU_TICK_SLP_PMU_EN_POS 0
|
||||
#define PMU_TICK_SLP_PMU_EN_BIT (1<<0)
|
||||
|
||||
/// counter from start PMU wakeup procedure to generate BTDM sleep interrupt
|
||||
#define PMU_REG_TW_WKUP_L 0x0a
|
||||
#define PMU_REG_TW_WKUP_H 0x0b
|
||||
|
||||
/// write: expect sleep duration, read: actual sleep duration
|
||||
#define PMU_REG_TICK_COUNTER_0 0x0c
|
||||
#define PMU_REG_TICK_COUNTER_1 0x0d
|
||||
#define PMU_REG_TICK_COUNTER_2 0x0e
|
||||
#define PMU_REG_TICK_COUNTER_3 0x0f
|
||||
|
||||
#define PMU_REG_WDT_CTRL 0x10
|
||||
#define PMU_WDT_CLR_EN_POS 6
|
||||
#define PMU_WDT_CLR_EN_BIT (1<<6)
|
||||
#define PMU_WDT_CLR_POS 4
|
||||
#define PMU_WDT_CLR_BIT (1<<4)
|
||||
#define PMU_WDT_IRQ_EN_POS 3
|
||||
#define PMU_WDT_IRQ_EN_BIT (1<<3)
|
||||
#define PMU_WDT_RST_CPU_POS 2
|
||||
#define PMU_WDT_RST_CPU_BIT (1<<2)
|
||||
#define PMU_WDT_RST_CHIP_POS 1
|
||||
#define PMU_WDT_RST_CHIP_BIT (1<<1)
|
||||
#define PMU_WDT_EN_POS 0
|
||||
#define PMU_WDT_EN_BIT (1<<0)
|
||||
|
||||
/// timeout counter between wdt interrupt is triggered to reset operation is executed
|
||||
#define PMU_REG_WDT_TOUT_COUNTER_0 0x11
|
||||
#define PMU_REG_WDT_TOUT_COUNTER_1 0x12
|
||||
|
||||
/// watchdog length
|
||||
#define PMU_REG_WDT_LEN_0 0x13
|
||||
#define PMU_REG_WDT_LEN_1 0x14
|
||||
#define PMU_REG_WDT_LEN_2 0x15
|
||||
#define PMU_REG_WDT_LEN_3 0x16
|
||||
|
||||
#define PMU_REG_RTC_CTRL 0x17
|
||||
#define PMU_RTC_ALARM_B_EN_POS 5
|
||||
#define PMU_RTC_ALARM_B_EN_BIT (1<<5)
|
||||
#define PMU_RTC_ALARM_A_EN_POS 4
|
||||
#define PMU_RTC_ALARM_A_EN_BIT (1<<4)
|
||||
#define PMU_RTC_ALARM_B_CLR_POS 3
|
||||
#define PMU_RTC_ALARM_B_CLR_BIT (1<<3)
|
||||
#define PMU_RTC_ALARM_A_CLR_POS 2
|
||||
#define PMU_RTC_ALARM_A_CLR_BIT (1<<2)
|
||||
#define PMU_RTC_SAMPLE_POS 1
|
||||
#define PMU_RTC_SAMPLE_BIT (1<<1)
|
||||
/// reload RTC counter with value set in PMU_REG_RTC_COUNTER_x
|
||||
#define PMU_RTC_UPD_EN_POS 0
|
||||
#define PMU_RTC_UPD_EN_BIT (1<<0)
|
||||
|
||||
/// write: set RTC counter, read: current RTC counter
|
||||
#define PMU_REG_RTC_COUNTER_0 0x18
|
||||
#define PMU_REG_RTC_COUNTER_1 0x19
|
||||
#define PMU_REG_RTC_COUNTER_2 0x1a
|
||||
#define PMU_REG_RTC_COUNTER_3 0x1b
|
||||
|
||||
/// RTC alarm A target value
|
||||
#define PMU_REG_ALARM_A_COUNTER_0 0x1c
|
||||
#define PMU_REG_ALARM_A_COUNTER_1 0x1d
|
||||
#define PMU_REG_ALARM_A_COUNTER_2 0x1e
|
||||
#define PMU_REG_ALARM_A_COUNTER_3 0x1f
|
||||
|
||||
/// RTC alarm B target value
|
||||
#define PMU_REG_ALARM_B_COUNTER_0 0x20
|
||||
#define PMU_REG_ALARM_B_COUNTER_1 0x21
|
||||
#define PMU_REG_ALARM_B_COUNTER_2 0x22
|
||||
#define PMU_REG_ALARM_B_COUNTER_3 0x23
|
||||
|
||||
#define PMU_REG_QDEC_CTRL 0x24
|
||||
#define PMU_QDEC_SMP_EN_POS 6
|
||||
#define PMU_QDEC_SMP_EN_BIT (1<<6)
|
||||
#define PMU_QDEC_DEB_EN_POS 4
|
||||
#define PMU_QDEC_DEB_EN_MSK (0x3<<4)
|
||||
#define PMU_QDEC_RST_PROC_POS 3
|
||||
#define PMU_QDEC_RST_PROC_MSK (0x1<<3)
|
||||
#define PMU_QDEC_3x_EN_POS 2
|
||||
#define PMU_QDEC_3x_EN_BIT (0x1<<2)
|
||||
#define PMU_QDEC_CNT_MODE_POS 0
|
||||
#define PMU_QDEC_CNT_MODE_MSK (0x3<<0)
|
||||
|
||||
#define PMU_REG_QDEC_CLR 0x25
|
||||
#define PMU_QDEC_INT_CLR_POS 4
|
||||
#define PMU_QDEC_INT_CLR_BIT (1<<4)
|
||||
#define PMU_QDEC_INT_EN_POS 0
|
||||
#define PMU_QDEC_INT_EN_MSK (0x3<<0)
|
||||
|
||||
#define PMU_REG_QDEC_CNT_LEN 0x26
|
||||
|
||||
#define PMU_REG_QDEC_DEB_LEN 0x27
|
||||
|
||||
#define PMU_REG_QDEC_DINAB_MUX 0x28
|
||||
|
||||
#define PMU_REG_QDEC_CNTA_VAL 0x29
|
||||
#define PMU_REG_QDEC_CNTB_VAL 0x2a
|
||||
|
||||
#define PMU_REG_INT_MASK 0x32
|
||||
#define PMU_OTD_INT_MASK_POS 15
|
||||
#define PMU_OTD_INT_MASK_BIT (1<<15)
|
||||
#define PMU_BATFULL_INT_MASK_POS 12
|
||||
#define PMU_BATFULL_INT_MASK_BIT (1<<12)
|
||||
#define PMU_CHG_ACOK_INT_MASK_POS 11
|
||||
#define PMU_CHG_ACOK_INT_MASK_BIT (1<<11)
|
||||
#define PMU_LVD_INT_MASK_POS 10
|
||||
#define PMU_LVD_INT_MASK_BIT (1<<10)
|
||||
#define PMU_ADKEY1_INT_MASK_POS 9
|
||||
#define PMU_ADKEY1_INT_MASK_BIT (1<<9)
|
||||
#define PMU_ADKEY0_INT_MASK_POS 8
|
||||
#define PMU_ADKEY0_INT_MASK_BIT (1<<8)
|
||||
#define PMU_GPIO_PMU_INT_MSK_POS 7
|
||||
#define PMU_GPIO_PMU_INT_MSK_BIT (1<<7)
|
||||
#define PMU_GPIO_GROUPL_INT_MSK_POS 6
|
||||
#define PMU_GPIO_GROUPL_INT_MSK_BIT (1<<6)
|
||||
#define PMU_GPIO_GROUPH_INT_MSK_POS 5
|
||||
#define PMU_GPIO_GROUPH_INT_MSK_BIT (1<<5)
|
||||
#define PMU_KEYSCAN_INT_MSK_POS 3
|
||||
#define PMU_KEYSCAN_INT_MSK_BIT (1<<3)
|
||||
#define PMU_RTC_B_INT_MSK_POS 2
|
||||
#define PMU_RTC_B_INT_MSK_BIT (1<<2)
|
||||
#define PMU_RTC_A_INT_MSK_POS 1
|
||||
#define PMU_RTC_A_INT_MSK_BIT (1<<1)
|
||||
#define PMU_WDT_INT_MSK_POS 0
|
||||
#define PMU_WDT_INT_MSK_BIT (1<<0)
|
||||
|
||||
#define PMU_REG_INT_RAW 0x34
|
||||
#define PMU_OTD_INT_RAW_POS 15
|
||||
#define PMU_OTD_INT_RAW_BIT (1<<15)
|
||||
#define PMU_BATFULL_INT_RAW_POS 12
|
||||
#define PMU_BATFULL_INT_RAW_BIT (1<<12)
|
||||
#define PMU_CHG_ACOK_INT_RAW_POS 11
|
||||
#define PMU_CHG_ACOK_INT_RAW_BIT (1<<11)
|
||||
#define PMU_LVD_INT_RAW_POS 10
|
||||
#define PMU_LVD_INT_RAW_BIT (1<<10)
|
||||
#define PMU_ADKEY1_INT_RAW_POS 9
|
||||
#define PMU_ADKEY1_INT_RAW_BIT (1<<9)
|
||||
#define PMU_ADKEY0_INT_RAW_POS 8
|
||||
#define PMU_ADKEY0_INT_RAW_BIT (1<<8)
|
||||
#define PMU_GPIO_PMU_INT_RAW_POS 7
|
||||
#define PMU_GPIO_PMU_INT_RAW_BIT (1<<7)
|
||||
#define PMU_GPIO_GROUPB_INT_RAW_POS 6
|
||||
#define PMU_GPIO_GROUPB_INT_RAW_BIT (1<<6)
|
||||
#define PMU_GPIO_GROUPA_INT_RAW_POS 5
|
||||
#define PMU_GPIO_GROUPA_INT_RAW_BIT (1<<5)
|
||||
#define PMU_KEYSCAN_INT_RAW_POS 3
|
||||
#define PMU_KEYSCAN_INT_RAW_BIT (1<<3)
|
||||
#define PMU_RTC_B_INT_RAW_POS 2
|
||||
#define PMU_RTC_B_INT_RAW_BIT (1<<2)
|
||||
#define PMU_RTC_A_INT_RAW_POS 1
|
||||
#define PMU_RTC_A_INT_RAW_BIT (1<<1)
|
||||
#define PMU_WDT_INT_RAW_POS 0
|
||||
#define PMU_WDT_INT_RAW_BIT (1<<0)
|
||||
|
||||
#define PMU_REG_INT_STATUS 0x36
|
||||
#define PMU_OTD_INT_STATUS_POS 15
|
||||
#define PMU_OTD_INT_STATUS_BIT (1<<15)
|
||||
#define PMU_BATFULL_INT_STATUS_POS 12
|
||||
#define PMU_BATFULL_INT_STATUS_BIT (1<<12)
|
||||
#define PMU_CHG_ACOK_INT_STATUS_POS 11
|
||||
#define PMU_CHG_ACOK_INT_STATUS_BIT (1<<11)
|
||||
#define PMU_LVD_INT_STATUS_POS 10
|
||||
#define PMU_LVD_INT_STATUS_BIT (1<<10)
|
||||
#define PMU_ADKEY1_INT_STATUS_POS 9
|
||||
#define PMU_ADKEY1_INT_STATUS_BIT (1<<9)
|
||||
#define PMU_ADKEY0_INT_STATUS_POS 8
|
||||
#define PMU_ADKEY0_INT_STATUS_BIT (1<<8)
|
||||
#define PMU_GPIO_PMU_INT_STATUS_POS 7
|
||||
#define PMU_GPIO_PMU_INT_STATUS_BIT (1<<7)
|
||||
#define PMU_GPIO_GROUPL_INT_STATUS_POS 6
|
||||
#define PMU_GPIO_GROUPL_INT_STATUS_BIT (1<<6)
|
||||
#define PMU_GPIO_GROUPH_INT_STATUS_POS 5
|
||||
#define PMU_GPIO_GROUPH_INT_STATUS_BIT (1<<5)
|
||||
#define PMU_KEYSCAN_INT_STATUS_POS 3
|
||||
#define PMU_KEYSCAN_INT_STATUS_BIT (1<<3)
|
||||
#define PMU_RTC_B_INT_STATUS_POS 2
|
||||
#define PMU_RTC_B_INT_STATUS_BIT (1<<2)
|
||||
#define PMU_RTC_A_INT_STATUS_POS 1
|
||||
#define PMU_RTC_A_INT_STATUS_BIT (1<<1)
|
||||
#define PMU_WDT_INT_STATUS_POS 0
|
||||
#define PMU_WDT_INT_STATUS_BIT (1<<0)
|
||||
|
||||
#define PMU_REG_ANA_STATUS 0x38
|
||||
#define PMU_OTD_STATUS_POS 7
|
||||
#define PMU_OTD_STATUS_BIT (1<<7)
|
||||
#define PMU_BATFULL_STATUS_POS 4
|
||||
#define PMU_BATFULL_STATUS_BIT (1<<4)
|
||||
#define PMU_CHG_ACOK_STATUS_POS 3
|
||||
#define PMU_CHG_ACOK_STATUS_BIT (1<<3)
|
||||
#define PMU_LVD_STATUS_POS 2
|
||||
#define PMU_LVD_STATUS_BIT (1<<2)
|
||||
#define PMU_ADKEY1_STATUS_POS 1
|
||||
#define PMU_ADKEY1_STATUS_BIT (1<<1)
|
||||
#define PMU_ADKEY0_STATUS_POS 0
|
||||
#define PMU_ADKEY0_STATUS_BIT (1<<0)
|
||||
|
||||
#define PMU_REG_ANA_LEVEL 0x39
|
||||
#define PMU_OTD_LEVEL_POS 7
|
||||
#define PMU_OTD_LEVEL_BIT (1<<7)
|
||||
#define PMU_BATFULL_LEVEL_POS 4
|
||||
#define PMU_BATFULL_LEVEL_BIT (1<<4)
|
||||
#define PMU_CHG_ACOK_LEVEL_POS 3
|
||||
#define PMU_CHG_ACOK_LEVEL_BIT (1<<3)
|
||||
#define PMU_LVD_LEVEL_POS 2
|
||||
#define PMU_LVD_LEVEL_BIT (1<<2)
|
||||
#define PMU_ADKEY1_LEVEL_POS 1
|
||||
#define PMU_ADKEY1_LEVEL_BIT (1<<1)
|
||||
#define PMU_ADKEY0_LEVEL_POS 0
|
||||
#define PMU_ADKEY0_LEVEL_BIT (1<<0)
|
||||
|
||||
#define PMU_REG_CHG_ACOK_FILTER 0x3C
|
||||
#define PMU_REG_BAT_FULL_FILTER 0x3D
|
||||
#define PMU_REG_OTD_FILTER 0x3F
|
||||
|
||||
#define PMU_REG_ANA_INT_EN 0x40
|
||||
#define PMU_OTD_INT_EN_POS 7
|
||||
#define PMU_OTD_INT_EN_BIT (1<<7)
|
||||
#define PMU_BATFULL_INT_EN_POS 4
|
||||
#define PMU_BATFULL_INT_EN_BIT (1<<4)
|
||||
#define PMU_CHG_ACOK_INT_EN_POS 3
|
||||
#define PMU_CHG_ACOK_INT_EN_BIT (1<<3)
|
||||
#define PMU_LVD_INT_EN_POS 2
|
||||
#define PMU_LVD_INT_EN_BIT (1<<2)
|
||||
#define PMU_ADKEY1_INT_EN_POS 1
|
||||
#define PMU_ADKEY1_INT_EN_BIT (1<<1)
|
||||
#define PMU_ADKEY0_INT_EN_POS 0
|
||||
#define PMU_ADKEY0_INT_EN_BIT (1<<0)
|
||||
|
||||
#define PMU_REG_ANA_INT_CLR 0x41
|
||||
#define PMU_OTD_INT_CLR_POS 7
|
||||
#define PMU_OTD_INT_CLR_BIT (1<<7)
|
||||
#define PMU_BATFULL_INT_CLR_POS 4
|
||||
#define PMU_BATFULL_INT_CLR_BIT (1<<4)
|
||||
#define PMU_CHG_ACOK_INT_CLR_POS 3
|
||||
#define PMU_CHG_ACOK_INT_CLR_BIT (1<<3)
|
||||
#define PMU_LVD_INT_CLR_POS 2
|
||||
#define PMU_LVD_INT_CLR_BIT (1<<2)
|
||||
#define PMU_ADKEY1_INT_CLR_POS 1
|
||||
#define PMU_ADKEY1_INT_CLR_BIT (1<<1)
|
||||
#define PMU_ADKEY0_INT_CLR_POS 0
|
||||
#define PMU_ADKEY0_INT_CLR_BIT (1<<0)
|
||||
|
||||
#define PMU_REG_PIN_INPUT_EN 0x42
|
||||
#define PMU_REG_PIN_PULL_EN 0x44
|
||||
#define PMU_REG_PIN_PULL_SEL 0x46
|
||||
#define PMU_REG_PIN_DATA 0x48
|
||||
#define PMU_REG_PIN_OUTPUT_EN 0x4a
|
||||
#define PMU_REG_PIN_XOR_EN 0x4c
|
||||
#define PMU_REG_PIN_LAST_V 0x4e
|
||||
#define PMU_REG_PIN_XOR_RESULT 0x50
|
||||
#define PMU_REG_PIN_XOR_CLR 0x52
|
||||
#define PMU_REG_PIN_INT_EN 0x54
|
||||
#define PMU_REG_WKUP_INT_EN 0x57
|
||||
#define PMU_REG_WKUP_INT_CLR 0x58
|
||||
|
||||
#define PMU_REG_PIN_IOMUX_L 0x59
|
||||
#define PMU_REG_PIN_IOMUX_M 0x5a
|
||||
#define PMU_REG_PIN_IOMUX_H 0x5b
|
||||
|
||||
// CPU reset vector = {1'b0, PMU_REG_CPU_RESET_VECTOR, 7'b0}
|
||||
#define PMU_REG_CPU_RESET_VECTOR 0x5c
|
||||
|
||||
#define PMU_REG_PMU_GATE_L 0x60
|
||||
#define PMU_REG_PMU_GATE_M 0x61
|
||||
#define PMU_REG_PMU_GATE_H 0x62
|
||||
|
||||
#define PMU_REG_PKSRAM_MASK 0x6a
|
||||
#define PMU_REG_PKSRAM_GATE 0x6e
|
||||
|
||||
#define PMU_REG_PMU_ONOFF_CNT 0x70
|
||||
#define PMU_REG_BBG_ONOFF_CNT 0x71
|
||||
#define PMU_REG_SYSBUCK_ONOFF_CNT 0x72
|
||||
#define PMU_REG_IOBUCK_ONOFF_CNT 0x73
|
||||
#define PMU_REG_IOLDO1_ONOFF_CNT 0x74
|
||||
#define PMU_REG_IOLDO2_ONOFF_CNT 0x75
|
||||
#define PMU_REG_APPDLDO_ONOFF_CNT 0x76
|
||||
#define PMU_REG_DSPDLDO_ONOFF_CNT 0x77
|
||||
#define PMU_REG_PKSTPD_ONOFF_CNT 0x78
|
||||
#define PMU_REG_MEMPK_ONOFF_CNT 0x79
|
||||
#define PMU_REG_MEMPD_ONOFF_CNT 0x7a
|
||||
#define PMU_REG_OSCLDO_ONOFF_CNT 0x7b
|
||||
#define PMU_REG_OSC_ONOFF_CNT 0x7c
|
||||
#define PMU_REG_RC24PD_ONOFF_CNT 0x7d
|
||||
#define PMU_REG_RAMPK_ONOFF_CNT 0x7e
|
||||
#define PMU_REG_PMUISO_ONOFF_CNT 0x7f
|
||||
#define PMU_REG_IOISO_ONOFF_CNT 0x80
|
||||
#define PMU_REG_IORTON_ONOFF_CNT 0x81
|
||||
#define PMU_REG_IOSNS_ONOFF_CNT 0x82
|
||||
#define PMU_REG_RSTN_ONOFF_CNT 0x83
|
||||
|
||||
#define PMU_REG_DIAG_CTRL 0x8f
|
||||
#define PMU_DIAG_EN_POS 7
|
||||
#define PMU_DIAG_EN_BIT (1<<7)
|
||||
#define PMU_DIAG_SEL_LSB 0
|
||||
#define PMU_DIAG_SEL_MSK 0x0f
|
||||
|
||||
#define PMU_REG_APP_DLDO_CTRL 0xc2
|
||||
|
||||
#define PMU_REG_AULDO_CTL 0xc3
|
||||
#define PMU_AULDO_CTL_PD_POS 7
|
||||
#define PMU_AULDO_CTL_PD_BIT (1<<7)
|
||||
|
||||
#define PMU_REG_BBG_CTL 0xc6
|
||||
#define PMU_BBG_CTL_VBE_EN_POS 3
|
||||
#define PMU_BBG_CTL_VBE_EN_BIT (1<<3)
|
||||
|
||||
#define PMU_REG_CHG_CFG_C8 0xc8
|
||||
#define PMU_CHG_CFG_CUR_POS 0
|
||||
#define PMU_CHG_CFG_CUR_MASK 0x3F
|
||||
|
||||
#define PMU_REG_CHG_CFG_CB 0xcb
|
||||
#define PMU_CHG_CFG_END_VOL_POS 4
|
||||
#define PMU_CHG_CFG_END_VOL_MASK 0x7
|
||||
|
||||
#define PMU_REG_CHG_CFG_CD 0xcd
|
||||
#define PMU_CHG_CFG_ENABLE_POS 3
|
||||
#define PMU_CHG_CFG_ENABLE_BIT (1<<3)
|
||||
#define PMU_CHG_CFG_REF_SEL_POS 1
|
||||
#define PMU_CHG_CFG_REF_SEL_BIT (1<<1)
|
||||
|
||||
#define PMU_REG_DSP_DLDO_CTRL 0xd0
|
||||
|
||||
#define PMU_REG_IOBUCK_CTRL_0 0xd2
|
||||
#define PMU_REG_IOBUCK_CTRL_1 0xd3
|
||||
#define PMU_REG_IOBUCK_CTRL_2 0xd4
|
||||
#define PMU_REG_IOBUCK_CTRL_3 0xd5
|
||||
#define PMU_REG_IOBUCK_CTRL_4 0xd6
|
||||
#define PMU_REG_IOBUCK_CTRL_5 0xd7
|
||||
#define PMU_REG_IOBUCK_CTRL_6 0xd8
|
||||
#define PMU_REG_IOBUCK_CTRL_7 0xd9
|
||||
#define PMU_REG_IOBUCK_CTRL_8 0xda
|
||||
|
||||
#define PMU_REG_SYSBUCK_CTRL_0 0xdb
|
||||
#define PMU_REG_SYSBUCK_CTRL_1 0xdc
|
||||
#define PMU_REG_SYSBUCK_CTRL_2 0xdd
|
||||
#define PMU_REG_SYSBUCK_CTRL_3 0xde
|
||||
#define PMU_REG_SYSBUCK_CTRL_4 0xdf
|
||||
#define PMU_REG_SYSBUCK_CTRL_5 0xe0
|
||||
#define PMU_REG_SYSBUCK_CTRL_6 0xe1
|
||||
#define PMU_REG_SYSBUCK_CTRL_7 0xe2
|
||||
#define PMU_REG_SYSBUCK_CTRL_8 0xe3
|
||||
|
||||
#define PMU_REG_IOLDO1_CTRL_0 0xe4
|
||||
#define PMU_REG_IOLDO1_CTRL_1 0xe5
|
||||
#define PMU_REG_IOLDO2_CTRL_0 0xe6
|
||||
#define PMU_REG_IOLDO2_CTRL_1 0xe7
|
||||
|
||||
#define PMU_REG_OSC_CTRL_0 0xe9
|
||||
#define PMU_REG_OSC_CTRL_1 0xea
|
||||
#define PMU_REG_OSC_CTRL_2 0xeb
|
||||
#define PMU_REG_OSC_CTRL_3 0xec
|
||||
#define PMU_REG_OSC_CTRL_4 0xed
|
||||
#define PMU_REG_OSC_CTRL_5 0xee
|
||||
|
||||
#define PMU_REG_PKVDD_CTRL 0xef
|
||||
|
||||
#define PMU_REG_PKVDDH_CTRL_0 0xf0
|
||||
#define PMU_REG_PKVDDH_CTRL_1 0xf1
|
||||
#define PMU_REG_SBG_CFG 0xf3
|
||||
|
||||
#define PMU_REG_ADC_CTL 0xf8
|
||||
#define PMU_ADC_CTL_POWER_POS 2
|
||||
#define PMU_ADC_CTL_POWER_BIT (1<<2)
|
||||
|
||||
/** @addtogroup PMU_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization Config Section Start ################################ */
|
||||
|
||||
/* PMU PIN index */
|
||||
typedef enum
|
||||
{
|
||||
PMU_PIN_0 = 0x0001,
|
||||
PMU_PIN_1 = 0x0002,
|
||||
PMU_PIN_2 = 0x0004,
|
||||
PMU_PIN_3 = 0x0008,
|
||||
PMU_PIN_4 = 0x0010,
|
||||
PMU_PIN_5 = 0x0020,
|
||||
PMU_PIN_6 = 0x0040,
|
||||
PMU_PIN_7 = 0x0080,
|
||||
PMU_PIN_8 = 0x0100,
|
||||
PMU_PIN_9 = 0x0200,
|
||||
}enum_PMU_PINx_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_GPIO_NO_PULL,
|
||||
PMU_GPIO_PULL_UP,
|
||||
PMU_GPIO_PULL_DOWN,
|
||||
}enum_PMU_GPIO_PULL_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_GPIO_MODE_INPUT,
|
||||
PMU_GPIO_MODE_OUTPUT,
|
||||
}enum_PMU_GPIO_MODE_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_LVD_THD_1_9,
|
||||
PMU_LVD_THD_2_0,
|
||||
PMU_LVD_THD_2_1,
|
||||
PMU_LVD_THD_2_2,
|
||||
PMU_LVD_THD_2_8,
|
||||
PMU_LVD_THD_3_0,
|
||||
PMU_LVD_THD_3_2,
|
||||
PMU_LVD_THD_3_4,
|
||||
}enum_PMU_LVD_THD_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_WDT_IRQ,
|
||||
PMU_WDT_RST_CHIP,
|
||||
}enum_PMU_WDT_MODE_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_CHG_END_VOL_4_1, /* charge end voltage select 4.1V */
|
||||
PMU_CHG_END_VOL_4_1_5, /* charge end voltage select 4.15V */
|
||||
PMU_CHG_END_VOL_4_2, /* charge end voltage select 4.2V */
|
||||
PMU_CHG_END_VOL_4_2_5, /* charge end voltage select 4.25V */
|
||||
PMU_CHG_END_VOL_4_3, /* charge end voltage select 4.3V */
|
||||
PMU_CHG_END_VOL_4_3_5, /* charge end voltage select 4.35V */
|
||||
PMU_CHG_END_VOL_4_4, /* charge end voltage select 4.4V */
|
||||
}enum_PMU_charge_end_vol_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_CHG_CUR_2mA = 0x00, /* charge current select 2mA */
|
||||
PMU_CHG_CUR_7mA = 0x01, /* charge current select 7mA */
|
||||
PMU_CHG_CUR_12mA = 0x02, /* charge current select 12mA */
|
||||
PMU_CHG_CUR_17mA = 0x03, /* charge current select 17mA */
|
||||
PMU_CHG_CUR_23mA = 0x04, /* charge current select 23mA */
|
||||
PMU_CHG_CUR_28mA = 0x05, /* charge current select 28mA */
|
||||
PMU_CHG_CUR_38mA = 0x07, /* charge current select 38mA */
|
||||
PMU_CHG_CUR_48mA = 0x09, /* charge current select 48mA */
|
||||
PMU_CHG_CUR_58mA = 0x0B, /* charge current select 58mA */
|
||||
PMU_CHG_CUR_68mA = 0x0D, /* charge current select 68mA */
|
||||
PMU_CHG_CUR_78mA = 0x0F, /* charge current select 78mA */
|
||||
PMU_CHG_CUR_88mA = 0x11, /* charge current select 88mA */
|
||||
PMU_CHG_CUR_103mA = 0x14, /* charge current select 103mA */
|
||||
PMU_CHG_CUR_123mA = 0x18, /* charge current select 123mA */
|
||||
PMU_CHG_CUR_143mA = 0x1C, /* charge current select 143mA */
|
||||
PMU_CHG_CUR_160mA = 0x20, /* charge current select 160mA */
|
||||
PMU_CHG_CUR_180mA = 0x24, /* charge current select 180mA */
|
||||
PMU_CHG_CUR_204mA = 0x29, /* charge current select 204mA */
|
||||
PMU_CHG_CUR_237mA = 0x30, /* charge current select 237mA */
|
||||
PMU_CHG_CUR_255mA = 0x34, /* charge current select 255mA */
|
||||
PMU_CHG_CUR_280mA = 0x39, /* charge current select 280mA */
|
||||
PMU_CHG_CUR_300mA = 0x3F, /* charge current select 300mA */
|
||||
}enum_PMU_charge_current_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_CHARGING_IN,
|
||||
PMU_CHARGING_OUT,
|
||||
}enum_PMU_charge_type_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PMU_BATTERY_FULL,
|
||||
PMU_BATTERY_NOT_FULL,
|
||||
}enum_PMU_battery_type_t;
|
||||
|
||||
/* ################################ Initialization Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
void pmu_init(void);
|
||||
|
||||
void pmu_set_pin_pull(enum_PMU_PINx_t bits, enum_PMU_GPIO_PULL_t type);
|
||||
void pmu_set_pin_dir(enum_PMU_PINx_t bits, enum_PMU_GPIO_MODE_t dir);
|
||||
void pmu_set_pin_value(enum_PMU_PINx_t bits, uint8_t value);
|
||||
uint8_t pmu_get_pin_value(enum_PMU_PINx_t bit);
|
||||
void pmu_port_wakeup_func_set(enum_PMU_PINx_t bits);
|
||||
void pmu_port_wakeup_func_clear(enum_PMU_PINx_t bits);
|
||||
void pmu_gpio_int_init(enum_PMU_PINx_t bits, enum_PMU_GPIO_PULL_t pull, uint8_t init_value);
|
||||
|
||||
void pmu_enable_isr(uint16_t isr_map);
|
||||
void pmu_disable_isr(uint16_t isr_map);
|
||||
uint16_t pmu_get_isr_state(void);
|
||||
void pmu_clear_isr_state(uint16_t state_map);
|
||||
|
||||
void pmu_lp_rc_calib(uint32_t lp_rc_counter, uint32_t hp_osc_counter);
|
||||
extern uint32_t pmu_lp_rc_get(void);
|
||||
|
||||
void pmu_lvd_enable(enum_PMU_LVD_THD_t thd);
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
void pmu_adc_power_ctrl(bool enable);
|
||||
void pmu_vbe_power_ctrl(bool enable);
|
||||
void pmu_auldo_power_ctrl(bool enable);
|
||||
|
||||
void pmu_charge_enable(enum_PMU_charge_current_t cur, enum_PMU_charge_end_vol_t vol);
|
||||
void pmu_charge_disable(void);
|
||||
void pmu_charge_monitor_en(enum_PMU_charge_type_t charge_type);
|
||||
void pmu_battery_full_monitor_en(enum_PMU_battery_type_t battery_type);
|
||||
|
||||
#endif // _DRIVER_PMU_H
|
||||
@ -0,0 +1,81 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_pmu_iwdt.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Header file of PMU IWDT HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_PMU_IWDT_H__
|
||||
#define __DRIVER_PMU_IWDT_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup IWDT_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization/config Section Start ################################ */
|
||||
|
||||
enum IWDT_INT_t
|
||||
{
|
||||
WDT_INT_ENABLE = 0x08,
|
||||
WDT_INT_DISABLE = 0x00,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iwdt Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t iwdt_Count; /* The watchdog initializes the count value.
|
||||
An interrupt can be generated when the count value is reached.
|
||||
This parameter can be a 32-bit Size. */
|
||||
|
||||
uint16_t iwdt_Timeout; /* The watchdog Timeout reset count value.
|
||||
When the count value is reached, the timeout counter is starting.
|
||||
Timeout triggers the system reset.
|
||||
Attention: Timeout Set to 0 the system will not reset.
|
||||
This parameter can be a 16-bit Size */
|
||||
|
||||
uint32_t iwdt_int_Enable; /* This parameter can be a value of @ref IWDT_INT_t */
|
||||
}iwdt_Init_t;
|
||||
|
||||
/* ################################ Initialization/config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* iwdt_init */
|
||||
void iwdt_init(iwdt_Init_t Init);
|
||||
|
||||
/* iwdt_Enable */
|
||||
/* iwdt_Disable */
|
||||
void iwdt_Enable(void);
|
||||
void iwdt_Disable(void);
|
||||
|
||||
/* iwdt_Refresh */
|
||||
void iwdt_Refresh(void);
|
||||
|
||||
/* iwdt_Interrupt_Enable */
|
||||
/* iwdt_Interrupt_Disable */
|
||||
void iwdt_Interrupt_Enable(void);
|
||||
void iwdt_Interrupt_Disable(void);
|
||||
|
||||
/* iwdt_Set_Count */
|
||||
void iwdt_Set_Count(uint32_t iwdtCount);
|
||||
|
||||
/* iwdt_Set_Timeout */
|
||||
void iwdt_Set_Timeout(uint16_t iwdtTimeout);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -0,0 +1,80 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_pmu_rtc.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Header file of pmu rtc HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_PMU_RTC_H__
|
||||
#define __DRIVER_PMU_RTC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup RTC_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t UnitBackup;
|
||||
}str_Time_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AlARM_A = 0x10,
|
||||
AlARM_B = 0x20,
|
||||
}enum_Alarm_t;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* rtc_AlarmA_Handler */
|
||||
/* rtc_AlarmB_Handler */
|
||||
void rtc_AlarmA_Handler(void);
|
||||
void rtc_AlarmB_Handler(void);
|
||||
|
||||
/* rtc_init */
|
||||
void rtc_init(uint32_t InitValue);
|
||||
|
||||
/* rtc_CountEnable */
|
||||
/* rtc_CountDisable */
|
||||
void rtc_CountEnable(void);
|
||||
void rtc_CountDisable(void);
|
||||
|
||||
/* rtc_AlarmConfig */
|
||||
void rtc_AlarmConfig(enum_Alarm_t fe_Alarm, uint32_t fu32_hour, uint32_t fu32_Minute, uint32_t fu32_Second);
|
||||
|
||||
/* rtc_GetCount */
|
||||
uint32_t rtc_GetCount(void);
|
||||
|
||||
/* rtc_CountUpdate */
|
||||
void rtc_CountUpdate(uint32_t fu32_CountValue);
|
||||
|
||||
/* rtc_AlarmUpdate */
|
||||
void rtc_AlarmUpdate(enum_Alarm_t fe_Alarm);
|
||||
|
||||
/* rtc_AlarmEnable */
|
||||
/* rtc_AlarmDisable */
|
||||
void rtc_AlarmEnable(enum_Alarm_t fe_Alarm);
|
||||
void rtc_AlarmDisable(enum_Alarm_t fe_Alarm);
|
||||
|
||||
/* rtc_AlarmRead */
|
||||
/* rtc_AlarmSet */
|
||||
uint32_t rtc_AlarmRead(enum_Alarm_t fe_Alarm);
|
||||
void rtc_AlarmSet(enum_Alarm_t fe_Alarm, uint32_t fu32_CountValue);
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
248
fr3092_mcu/components/drivers/peripheral/Inc/driver_pwm.h
Normal file
248
fr3092_mcu/components/drivers/peripheral/Inc/driver_pwm.h
Normal file
@ -0,0 +1,248 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_pwm.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of PWM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_PWM_H__
|
||||
#define __DRIVER_PWM_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup PWM_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* PWM Output ctrl register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OutputEN : 16;
|
||||
uint32_t Output_ctrl : 16;
|
||||
}REG_PWMOutput_t;
|
||||
|
||||
/* Posedge<67><65>Negedeg register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Posedge;
|
||||
uint32_t Negedeg;
|
||||
}REG_PWMedge_t;
|
||||
|
||||
/* capture control register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Capture_Mode : 8;
|
||||
uint32_t Capture_EN : 8;
|
||||
uint32_t rsv_0 : 16;
|
||||
}REG_CaptureCtrl_t;
|
||||
|
||||
/* PWM Update control register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PWM_Update : 16;
|
||||
uint32_t PWM_Status : 16;
|
||||
}REG_PWMUpdate_t;
|
||||
|
||||
/* Prescale<6C><65>Period register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescale;
|
||||
uint32_t Period;
|
||||
}REG_PWMFrequency_t;
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* PWM Register */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t rsv_0;
|
||||
volatile REG_PWMOutput_t OutputEN; /* Offset 0x04 */
|
||||
volatile uint32_t ChannelEN; /* Offset 0x08 */
|
||||
volatile uint32_t rsv_1;
|
||||
volatile REG_PWMedge_t Edge[16]; /* Offset 0x10 ~ 0x8C */
|
||||
volatile uint32_t OutputSelect; /* Offset 0x90 */
|
||||
volatile uint32_t CapturePrescale; /* Offset 0x94 */
|
||||
volatile uint32_t CaptureStatus; /* Offset 0x98 */
|
||||
volatile uint32_t CaptureINTEN; /* Offset 0x9C */
|
||||
volatile REG_CaptureCtrl_t CaptureCtrl; /* Offset 0xA0 */
|
||||
volatile uint32_t CaptureValue[8]; /* Offset 0xA4 ~ 0xE0 */
|
||||
volatile uint32_t rsv_2[8];
|
||||
volatile REG_PWMUpdate_t Update; /* Offset 0xE4 */
|
||||
volatile uint32_t DACMode; /* Offset 0xE8 */
|
||||
volatile uint32_t rsv_3;
|
||||
volatile uint32_t OutputValue; /* Offset 0xF0 */
|
||||
volatile uint32_t rsv_4;
|
||||
volatile uint32_t InverterEN; /* Offset 0xF8 */
|
||||
volatile uint32_t CNT_EN; /* Offset 0xFC */
|
||||
volatile REG_PWMFrequency_t Frequency[16]; /* Offset 0x100 ~ 0x17C */
|
||||
}struct_PWM_t;
|
||||
|
||||
#define PWM0 ((struct_PWM_t *)PWM0_BASE)
|
||||
#define PWM1 ((struct_PWM_t *)PWM1_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWM_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/* PWM Channel */
|
||||
typedef enum
|
||||
{
|
||||
PWM_CHANNEL_0 = 0x0001,
|
||||
PWM_CHANNEL_1 = 0x0002,
|
||||
PWM_CHANNEL_2 = 0x0004,
|
||||
PWM_CHANNEL_3 = 0x0008,
|
||||
PWM_CHANNEL_4 = 0x0010,
|
||||
PWM_CHANNEL_5 = 0x0020,
|
||||
PWM_CHANNEL_6 = 0x0040,
|
||||
PWM_CHANNEL_7 = 0x0080,
|
||||
PWM_CHANNEL_8 = 0x0100,
|
||||
PWM_CHANNEL_9 = 0x0200,
|
||||
PWM_CHANNEL_10 = 0x0400,
|
||||
PWM_CHANNEL_11 = 0x0800,
|
||||
PWM_CHANNEL_12 = 0x1000,
|
||||
PWM_CHANNEL_13 = 0x2000,
|
||||
PWM_CHANNEL_14 = 0x4000,
|
||||
PWM_CHANNEL_15 = 0x8000,
|
||||
}enum_PWMChannel_t;
|
||||
|
||||
/* Inverter Enable */
|
||||
typedef enum
|
||||
{
|
||||
Inverter_Enable, /* output Inverter enable */
|
||||
Inverter_Disable, /* output Inverter disable */
|
||||
}enum_InverterEN_t;
|
||||
|
||||
/* Capture_Prescale */
|
||||
typedef enum
|
||||
{
|
||||
CAPTURE_DIV_1,
|
||||
CAPTURE_DIV_2,
|
||||
CAPTURE_DIV_4,
|
||||
CAPTURE_DIV_8,
|
||||
CAPTURE_DIV_16,
|
||||
CAPTURE_DIV_32,
|
||||
CAPTURE_DIV_64,
|
||||
CAPTURE_DIV_128,
|
||||
CAPTURE_DIV_256,
|
||||
CAPTURE_DIV_512,
|
||||
CAPTURE_DIV_1024,
|
||||
CAPTURE_DIV_2048,
|
||||
}enum_CapturePrescale_t;
|
||||
|
||||
/* Capture Mode */
|
||||
typedef enum
|
||||
{
|
||||
MODE_LOOP, /* Loop trigger */
|
||||
MODE_SINGLE, /* Single trigger */
|
||||
}enum_CaptureMode_t;
|
||||
|
||||
/*
|
||||
* @brief PWM mode config parameter
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Prescale; /* Clock = APB_Clock / Prescale */
|
||||
uint16_t Period; /* Period = Clock * PWM_Period */
|
||||
|
||||
uint16_t Posedge; /* The position of the rising edge in the period */
|
||||
uint16_t Negedge; /* The position of the falling edge in the period */
|
||||
}struct_PWM_Config_t;
|
||||
|
||||
/*
|
||||
* @brief PWM complementary config parameter
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Prescale; /* Clock = APB_Clock / Prescale */
|
||||
uint16_t Period; /* Period = Clock * PWM_Period */
|
||||
|
||||
uint16_t DutyCycle; /* Low level hold time in one period */
|
||||
|
||||
uint16_t MianDeadTime; /* Mian Channel dead-time */
|
||||
uint16_t CompDeadTime; /* complementary Channel dead-time */
|
||||
}struct_PWM_Complementary_Config_t;
|
||||
|
||||
/*
|
||||
* @brief Capture mode config parameter
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CapturePrescale; /* This parameter can be a value of @ref enum_CapturePrescale_t */
|
||||
uint32_t CaptureMode; /* This parameter can be a value of @ref enum_CaptureMode_t */
|
||||
}struct_Capture_Config_t;
|
||||
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* PWM mode. output inverter Enable/Disable */
|
||||
#define __PWM_INVERTER_ENABLE(__PWMx__, __CHANNEL__) (__PWMx__->InverterEN |= (__CHANNEL__))
|
||||
#define __PWM_INVERTER_DISABLE(__PWMx__, __CHANNEL__) (__PWMx__->InverterEN &= ~(__CHANNEL__))
|
||||
|
||||
/* Capture mode. Capture interrupt Enable/Disable/Clear */
|
||||
#define __PWM_CAPTURE_INT_ENABLE(__PWMx__, __CHANNEL__) (__PWMx__->CaptureINTEN |= (__CHANNEL__))
|
||||
#define __PWM_CAPTURE_INT_DISABLE(__PWMx__, __CHANNEL__) (__PWMx__->CaptureINTEN &= ~(__CHANNEL__))
|
||||
#define __PWM_CAPTURE_INT_CLEAR(__PWMx__, __CHANNEL__) (__PWMx__->CaptureStatus |= (__CHANNEL__))
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------*/
|
||||
/*------------------ PWM Mode functions ------------------*/
|
||||
/*------------------ PWM_DAC Mode functions ------------------*/
|
||||
/*------------------------------------------------------------*/
|
||||
/* pwm_config */
|
||||
void pwm_config(struct_PWM_t *PWMx, uint16_t fu16_channel, struct_PWM_Config_t fstr_Config);
|
||||
|
||||
/* pwm_complementary_config */
|
||||
bool pwm_complementary_config(struct_PWM_t *PWMx, uint16_t fu16_MainChannel, uint16_t ComplementaryChannel, struct_PWM_Complementary_Config_t fstr_Config);
|
||||
|
||||
/* pwm_output_enable/disable */
|
||||
void pwm_output_enable(struct_PWM_t *PWMx, uint16_t fu16_channel);
|
||||
void pwm_output_disable(struct_PWM_t *PWMx, uint16_t fu16_channel);
|
||||
|
||||
/* pwm_output_status */
|
||||
bool pwm_output_status(struct_PWM_t *PWMx, enum_PWMChannel_t fe_channel);
|
||||
|
||||
/* pwm_output_updata */
|
||||
void pwm_output_updata(struct_PWM_t *PWMx, uint16_t fu16_channel);
|
||||
|
||||
/*------------------------------------------------------------*/
|
||||
/*------------------ Capture Mode functions ------------------*/
|
||||
/*------------------------------------------------------------*/
|
||||
/* pwm_capture_config */
|
||||
void pwm_capture_config(struct_PWM_t *PWMx, uint16_t fu16_channel, struct_Capture_Config_t fstr_Config);
|
||||
|
||||
/* capture_enable/disable */
|
||||
void pwm_capture_enable(struct_PWM_t *PWMx, uint16_t fu16_channel);
|
||||
void pwm_capture_disable(struct_PWM_t *PWMx, uint16_t fu16_channel);
|
||||
|
||||
/* pwm_capture_status */
|
||||
bool pwm_capture_status(struct_PWM_t *PWMx, enum_PWMChannel_t fe_channel);
|
||||
|
||||
/* pwm_capture_status_clear */
|
||||
void pwm_capture_status_clear(struct_PWM_t *PWMx, enum_PWMChannel_t fe_channel);
|
||||
|
||||
/* pwm_capture_value */
|
||||
uint32_t pwm_capture_value(struct_PWM_t *PWMx, enum_PWMChannel_t fe_channel);
|
||||
|
||||
#endif
|
||||
458
fr3092_mcu/components/drivers/peripheral/Inc/driver_qspi.h
Normal file
458
fr3092_mcu/components/drivers/peripheral/Inc/driver_qspi.h
Normal file
@ -0,0 +1,458 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_qspi.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of QSPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_QSPI_H__
|
||||
#define __DRIVER_QSPI_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup QSPI_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
struct qspi_config_reg_t { //@0x00
|
||||
uint32_t enable:1;
|
||||
uint32_t cpol:1;
|
||||
uint32_t cpha:1;
|
||||
uint32_t reserved0:1;
|
||||
uint32_t octal_xccela:1;
|
||||
uint32_t octal_opi:1;
|
||||
uint32_t octal_div2:1;
|
||||
uint32_t enable_DAC:1; //direct access controller
|
||||
uint32_t enable_legacy:1;
|
||||
uint32_t peri_sel:1;
|
||||
uint32_t peri_sel_line:4; //<2F><>peri_sel<65><6C><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
|
||||
uint32_t write_en_pin:1;
|
||||
uint32_t enable_DMA:1;
|
||||
uint32_t enable_AHB_remap:1;
|
||||
uint32_t enable_XIP_next_R:1; //enter XIP Mode on next READ
|
||||
uint32_t enalbe_XIP:1; //enter XIP Mode immediately
|
||||
uint32_t baud_rate:4;
|
||||
uint32_t enable_AHB_decoder:1;
|
||||
uint32_t enable_DTR_prot:1;
|
||||
uint32_t reserved1:6;
|
||||
uint32_t status:1;
|
||||
};
|
||||
|
||||
struct qspi_read_ins_reg_t { //@0x04
|
||||
uint32_t opcode:8;
|
||||
uint32_t instruction_type:2;
|
||||
uint32_t enable_DDR:1;
|
||||
uint32_t reserved0:1;
|
||||
uint32_t addr_type:2;
|
||||
uint32_t reserved1:2;
|
||||
uint32_t data_type:2;
|
||||
uint32_t reserved2:2;
|
||||
uint32_t enable_mode:1;
|
||||
uint32_t reserved3:3;
|
||||
uint32_t dummy_cycles:5;
|
||||
uint32_t reserved4:3;
|
||||
};
|
||||
|
||||
struct qspi_write_ins_reg_t { //@0x08
|
||||
uint32_t opcode:8;
|
||||
uint32_t disable_WEL:1;
|
||||
uint32_t reserved0:3;
|
||||
uint32_t addr_type:2;
|
||||
uint32_t reserved1:2;
|
||||
uint32_t data_type:2;
|
||||
uint32_t reserved2:6;
|
||||
uint32_t dummy_cycles:5;
|
||||
uint32_t reserved3:3;
|
||||
};
|
||||
|
||||
struct qspi_device_delay_reg_t { //@0x0c
|
||||
uint32_t sel_start_offset:8;
|
||||
uint32_t sel_end_offset:8;
|
||||
uint32_t sel_dessert_diff:8;
|
||||
uint32_t sel_dessert:8;
|
||||
};
|
||||
|
||||
struct qspi_read_cap_reg_t { //@0x10
|
||||
uint32_t enable_loopback_clk:1;
|
||||
uint32_t delay_capture:4;
|
||||
uint32_t sample_edge:1;
|
||||
uint32_t reserved0:10;
|
||||
uint32_t delay_trans:4;
|
||||
uint32_t reserved1:12;
|
||||
};
|
||||
|
||||
struct qspi_device_size_cfg_t { //@0x14
|
||||
uint32_t addr_bytes:4; //number of address bytes. 0=1byte
|
||||
uint32_t page_bytes:12; //number of bytes per device page
|
||||
uint32_t block_bytes:5; //number of bytes per block. bytes = 2^block_bytes
|
||||
uint32_t CS0_size:2;
|
||||
uint32_t CS1_size:2;
|
||||
uint32_t CS2_size:2;
|
||||
uint32_t CS3_size:2;
|
||||
uint32_t reserved0:3;
|
||||
};
|
||||
|
||||
struct qspi_dma_peri_cfg_t { //@0x20
|
||||
uint32_t bytes_per_req:4; //2^bytes_per_req
|
||||
uint32_t reserved0:4;
|
||||
uint32_t bytes_per_burst:4; //2^bytes_per_burst
|
||||
uint32_t reserved1:20;
|
||||
};
|
||||
|
||||
struct qspi_sram_level_reg_t { //@0x2c
|
||||
uint32_t read_part:16;
|
||||
uint32_t write_part:16;
|
||||
};
|
||||
|
||||
struct qspi_write_comp_ctrl_reg_t { //@0x38
|
||||
uint32_t opcode_poll:8;
|
||||
uint32_t poll_bit_index:3; //the bit index that should be polled
|
||||
uint32_t reserved0:2;
|
||||
uint32_t poll_polarity:1;
|
||||
uint32_t disable_poll:1;
|
||||
uint32_t enable_expiration:1;
|
||||
uint32_t poll_count:8;
|
||||
uint32_t poll_repetition_delay:8;
|
||||
};
|
||||
|
||||
struct qspi_write_protect_reg_t {
|
||||
uint32_t inversion:1;
|
||||
uint32_t enable:1;
|
||||
uint32_t reserved0:30;
|
||||
};
|
||||
|
||||
struct qspi_ind_read_crtl_reg_t { //@0x60
|
||||
uint32_t start:1;
|
||||
uint32_t cancel:1;
|
||||
uint32_t progress_status:1;
|
||||
uint32_t sram_status:1;
|
||||
uint32_t queue_status:1;
|
||||
uint32_t comp_status:1;
|
||||
uint32_t num_operation_comp:2;
|
||||
uint32_t reserved0:24;
|
||||
};
|
||||
|
||||
struct qspi_ind_write_crtl_reg_t { //@0x70
|
||||
uint32_t start:1;
|
||||
uint32_t cancel:1;
|
||||
uint32_t progress_status:1;
|
||||
uint32_t reserved0:1;
|
||||
uint32_t queue_status:1;
|
||||
uint32_t comp_status:1;
|
||||
uint32_t num_operation_comp:2;
|
||||
uint32_t reserved1:24;
|
||||
};
|
||||
|
||||
struct qspi_stig_mem_reg_t {
|
||||
uint32_t mem_bank_req:1;
|
||||
uint32_t mem_bank_status:1;
|
||||
uint32_t reserved0:6;
|
||||
uint32_t mem_bank_data:8;
|
||||
uint32_t mem_bank_req_bytes:3;
|
||||
uint32_t reserved1:1;
|
||||
uint32_t mem_bank_addr:9;
|
||||
uint32_t reserved2:3;
|
||||
};
|
||||
|
||||
struct qspi_stig_reg_t {
|
||||
uint32_t execute:1;
|
||||
uint32_t progress_status:1;
|
||||
uint32_t enable_bank:1;
|
||||
uint32_t reserved0:4;
|
||||
uint32_t dummy_cycles:5;
|
||||
uint32_t write_bytes:3; //0~1bytes
|
||||
uint32_t enable_write:1;
|
||||
uint32_t addr_bytes:2; //0~1bytes
|
||||
uint32_t enable_mode:1;
|
||||
uint32_t enable_cmd_addr:1;
|
||||
uint32_t read_bytes:3;
|
||||
uint32_t enable_read:1;
|
||||
uint32_t opcode:8;
|
||||
};
|
||||
|
||||
struct qspi_poll_flash_status_t {
|
||||
uint32_t status:8;
|
||||
uint32_t valid:1;
|
||||
uint32_t reserved0:7;
|
||||
uint32_t dummy_cycles:4;
|
||||
uint32_t reserved1:12;
|
||||
};
|
||||
struct qspi_cs_ctrl_t{
|
||||
uint32_t rd_brk_en:1;
|
||||
uint32_t page_boundary_protect_en:1;
|
||||
uint32_t disable_cs_after_first_byte:1;
|
||||
uint32_t resv0:13;
|
||||
uint32_t page_boundary:12;
|
||||
uint32_t resv1:4;
|
||||
};
|
||||
|
||||
struct qspi_regs_t {
|
||||
volatile struct qspi_config_reg_t config; //@0x00
|
||||
volatile struct qspi_read_ins_reg_t read_conf;
|
||||
volatile struct qspi_write_ins_reg_t write_conf;
|
||||
volatile struct qspi_device_delay_reg_t delay;
|
||||
volatile struct qspi_read_cap_reg_t read_cap; //@0x10
|
||||
volatile struct qspi_device_size_cfg_t size_cfg;
|
||||
volatile uint32_t sram_part_cfg;
|
||||
volatile uint32_t AHB_trigger_address;
|
||||
volatile struct qspi_dma_peri_cfg_t dma_cfg; //@0x20
|
||||
volatile uint32_t remap_address;
|
||||
volatile uint32_t mode_bits;
|
||||
volatile struct qspi_sram_level_reg_t sram_level;
|
||||
volatile uint32_t tx_threshold; //@0x30
|
||||
volatile uint32_t rx_threshold;
|
||||
volatile struct qspi_write_comp_ctrl_reg_t poll_cfg;
|
||||
volatile uint32_t poll_expiration;
|
||||
volatile uint32_t int_status; //@0x40
|
||||
volatile uint32_t int_mask;
|
||||
uint32_t reserved0[2];
|
||||
volatile uint32_t lower_write_protect; //@0x50
|
||||
volatile uint32_t upper_write_protect;
|
||||
volatile struct qspi_write_protect_reg_t write_protect;
|
||||
uint32_t reserved1;
|
||||
volatile struct qspi_ind_read_crtl_reg_t ind_read_ctrl; //@0x60
|
||||
volatile uint32_t ind_read_watermark;
|
||||
volatile uint32_t ind_read_start_addr;
|
||||
volatile uint32_t ind_read_bytes;
|
||||
volatile struct qspi_ind_write_crtl_reg_t ind_write_ctrl; //@0x70
|
||||
volatile uint32_t ind_write_watermark;
|
||||
volatile uint32_t ind_write_start_addr;
|
||||
volatile uint32_t ind_write_bytes;
|
||||
volatile uint32_t ind_range_width; //@0x80
|
||||
uint32_t reserved2[2];
|
||||
volatile struct qspi_stig_mem_reg_t cmd_ctrl_mem;
|
||||
volatile struct qspi_stig_reg_t cmd_ctrl; //@0x90
|
||||
volatile uint32_t cmd_address;
|
||||
uint32_t reserved3[2];
|
||||
volatile uint32_t read_data_L; //@0xa0
|
||||
volatile uint32_t read_data_H;
|
||||
volatile uint32_t write_data_L;
|
||||
volatile uint32_t write_data_H;
|
||||
volatile struct qspi_poll_flash_status_t poll_status; //@0xb0
|
||||
volatile struct qspi_cs_ctrl_t cs_ctrl;
|
||||
uint32_t reserved4[17];
|
||||
volatile uint32_t module_id; //@0xfc
|
||||
};
|
||||
|
||||
#define QSPI0 ((struct qspi_regs_t *)FLASH_QSPI_BASE)
|
||||
#define QSPI1 ((struct qspi_regs_t *)DSP_QSPI_BASE)
|
||||
#define OSPI ((struct qspi_regs_t *)PSRAM_OSPI_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
#define QSPI_INT_MODE_FAIL 0x00000001
|
||||
#define QSPI_INT_UNDERFLOW 0x00000002
|
||||
#define QSPI_INT_COMP_INDIRECT 0x00000004
|
||||
#define QSPI_INT_FAIL_INDIRECT 0x00000008
|
||||
#define QSPI_INT_FAIL_WR_PROTECT 0x00000010
|
||||
#define QSPI_INT_ILLEGAL_AHB 0x00000020
|
||||
#define QSPI_INT_INDIRECT_WATER 0x00000040
|
||||
#define QSPI_INT_OVERFLOW 0x00000080
|
||||
#define QSPI_INT_TXFF_NOFULL 0x00000100
|
||||
#define QSPI_INT_TXFF_FULL 0x00000200
|
||||
#define QSPI_INT_RXFF_NOEMPTY 0x00000400
|
||||
#define QSPI_INT_RXFF_FULL 0x00000800
|
||||
#define QSPI_INT_RD_PART_FULL 0x00001000
|
||||
#define QSPI_INT_POLL_EXPIRED 0x00002000
|
||||
#define QSPI_INT_COMP_STIG 0x00004000
|
||||
|
||||
enum qspi_flash_size_t {
|
||||
QSPI_FLASH_SIZE_512Mb,
|
||||
QSPI_FLASH_SIZE_1Gb,
|
||||
QSPI_FLASH_SIZE_2Gb,
|
||||
QSPI_FLASH_SIZE_4Gb,
|
||||
};
|
||||
|
||||
enum qspi_mem_bank_bytes_t {
|
||||
QSPI_MEM_BANK_BYTES_16,
|
||||
QSPI_MEM_BANK_BYTES_32,
|
||||
QSPI_MEM_BANK_BYTES_64,
|
||||
QSPI_MEM_BANK_BYTES_128,
|
||||
QSPI_MEM_BANK_BYTES_256,
|
||||
QSPI_MEM_BANK_BYTES_512,
|
||||
};
|
||||
|
||||
enum qspi_wire_type_t {
|
||||
QSPI_WIRE_TYPE_STAND,
|
||||
QSPI_WIRE_TYPE_DIO,
|
||||
QSPI_WIRE_TYPE_QIO,
|
||||
QSPI_WIRE_TYPE_OIO,
|
||||
};
|
||||
|
||||
enum qspi_baud_rate_t {
|
||||
QSPI_BAUDRATE_DIV_2,
|
||||
QSPI_BAUDRATE_DIV_4,
|
||||
QSPI_BAUDRATE_DIV_6,
|
||||
QSPI_BAUDRATE_DIV_8,
|
||||
QSPI_BAUDRATE_DIV_10,
|
||||
QSPI_BAUDRATE_DIV_12,
|
||||
QSPI_BAUDRATE_DIV_14,
|
||||
QSPI_BAUDRATE_DIV_16,
|
||||
QSPI_BAUDRATE_DIV_18,
|
||||
QSPI_BAUDRATE_DIV_20,
|
||||
QSPI_BAUDRATE_DIV_22,
|
||||
QSPI_BAUDRATE_DIV_24,
|
||||
QSPI_BAUDRATE_DIV_26,
|
||||
QSPI_BAUDRATE_DIV_28,
|
||||
QSPI_BAUDRATE_DIV_30,
|
||||
QSPI_BAUDRATE_DIV_32,
|
||||
};
|
||||
|
||||
enum qspi_stig_cmd_type_t {
|
||||
QSPI_STIG_CMD_READ,
|
||||
QSPI_STIG_CMD_BANK_READ,
|
||||
QSPI_STIG_CMD_WRITE,
|
||||
QSPI_STIG_CMD_EXE,
|
||||
};
|
||||
|
||||
enum qspi_stig_addr_bytes_t {
|
||||
QSPI_STIG_ADDR_BYTES_1,
|
||||
QSPI_STIG_ADDR_BYTES_2,
|
||||
QSPI_STIG_ADDR_BYTES_3,
|
||||
QSPI_STIG_ADDR_BYTES_4,
|
||||
};
|
||||
|
||||
enum qspi_device_addr_bytes_t {
|
||||
QSPI_DEVICE_ADDR_BYTES_1,
|
||||
QSPI_DEVICE_ADDR_BYTES_2,
|
||||
QSPI_DEVICE_ADDR_BYTES_3,
|
||||
QSPI_DEVICE_ADDR_BYTES_4,
|
||||
};
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* QSPI Enable/Disable */
|
||||
#define __QSPI_ENABLE(__QSPIx__) (__QSPIx__->config.enable = 1)
|
||||
#define __QSPI_DISABLE(__QSPIx__) (__QSPIx__->config.enable = 0)
|
||||
|
||||
#define __QSPI_CFG_CPOL_SET(__QSPIx__, __VAULE__) (__QSPIx__->config.cpol = __VAULE__)
|
||||
#define __QSPI_CFG_CPHA_SET(__QSPIx__, __VAULE__) (__QSPIx__->config.cpha = __VAULE__)
|
||||
#define __QSPI_CFG_OCTAL_XCCELA_ENABLE(__QSPIx__) (__QSPIx__->config.octal_xccela = 1)
|
||||
#define __QSPI_CFG_OCTAL_XCCELA_DISABLE(__QSPIx__) (__QSPIx__->config.octal_xccela = 0)
|
||||
#define __QSPI_CFG_OCTAL_OPI_ENABLE(__QSPIx__) (__QSPIx__->config.octal_opi = 1)
|
||||
#define __QSPI_CFG_OCTAL_OPI_DISABLE(__QSPIx__) (__QSPIx__->config.octal_opi = 0)
|
||||
|
||||
#define __QSPI_CFG_DAC_ENABLE(__QSPIx__) (__QSPIx__->config.enable_DAC = 1)
|
||||
#define __QSPI_CFG_DAC_DISABLE(__QSPIx__) (__QSPIx__->config.enable_DAC = 0)
|
||||
|
||||
#define __QSPI_CFG_LEGACY_ENABLE(__QSPIx__) (__QSPIx__->config.enable_legacy = 1)
|
||||
#define __QSPI_CFG_LEGACY_DISABLE(__QSPIx__) (__QSPIx__->config.enable_legacy = 0)
|
||||
|
||||
#define __QSPI_CFG_WRITE_PROTECT_ENABLE(__QSPIx__) (__QSPIx__->config.write_en_pin = 1)
|
||||
#define __QSPI_CFG_WRITE_PROTECT_DISABLE(__QSPIx__) (__QSPIx__->config.write_en_pin = 0)
|
||||
|
||||
#define __QSPI_CFG_REMAP_ENABLE(__QSPIx__) (__QSPIx__->config.enable_AHB_remap = 1)
|
||||
#define __QSPI_CFG_REMAP_DISABLE(__QSPIx__) (__QSPIx__->config.enable_AHB_remap = 0)
|
||||
|
||||
#define __QSPI_CFG_AHB_DECODER_ENABLE(__QSPIx__) (__QSPIx__->config.enable_AHB_decoder = 1)
|
||||
#define __QSPI_CFG_AHB_DECODER_DISABLE(__QSPIx__) (__QSPIx__->config.enable_AHB_decoder = 0)
|
||||
|
||||
#define __QSPI_CFG_DTR_ENABLE(__QSPIx__) (__QSPIx__->config.enable_DTR_prot = 1)
|
||||
#define __QSPI_CFG_DTR_DISABLE(__QSPIx__) (__QSPIx__->config.enable_DTR_prot = 0)
|
||||
|
||||
#define __QSPI_CFG_BAUDRATE_SET(__QSPIx__, baudrate) (__QSPIx__->config.baud_rate = baudrate)
|
||||
|
||||
#define __QSPI_IS_BUSY(__QSPIx__) (__QSPIx__->config.status == 0)
|
||||
|
||||
#define __QSPI_READ_OPCODE_SET(__QSPIx__, _opcode) (__QSPIx__->read_conf.opcode = _opcode)
|
||||
#define __QSPI_READ_INSTRUCTION_TYPE_SET(__QSPIx__, type) (__QSPIx__->read_conf.instruction_type = type)
|
||||
#define __QSPI_READ_ADDRESS_TYPE_SET(__QSPIx__, type) (__QSPIx__->read_conf.addr_type = type)
|
||||
#define __QSPI_READ_DATA_TYPE_SET(__QSPIx__, type) (__QSPIx__->read_conf.data_type = type)
|
||||
#define __QSPI_READ_MODE_ENABLE_SET(__QSPIx__, en) (__QSPIx__->read_conf.enable_mode = en)
|
||||
#define __QSPI_READ_DUMMY_CYCLES_SET(__QSPIx__, cycles) (__QSPIx__->read_conf.dummy_cycles = cycles)
|
||||
#define __QSPI_READ_DDR_ENABLE(__QSPIx__) (__QSPIx__->read_conf.enable_DDR = 1)
|
||||
#define __QSPI_READ_DDR_DISABLE(__QSPIx__) (__QSPIx__->read_conf.enable_DDR = 0)
|
||||
#define __QSPI_READ_DDR_GET(__QSPIx__) (__QSPIx__->read_conf.enable_DDR)
|
||||
|
||||
#define __QSPI_WRITE_OPCODE_SET(__QSPIx__, _opcode) (__QSPIx__->write_conf.opcode = _opcode)
|
||||
#define __QSPI_WRITE_WEL_ENABLE(__QSPIx__) (__QSPIx__->write_conf.disable_WEL = 0)
|
||||
#define __QSPI_WRITE_WEL_DISABLE(__QSPIx__) (__QSPIx__->write_conf.disable_WEL = 1)
|
||||
#define __QSPI_WRITE_ADDRESS_TYPE_SET(__QSPIx__, type) (__QSPIx__->write_conf.addr_type = type)
|
||||
#define __QSPI_WRITE_DATA_TYPE_SET(__QSPIx__, type) (__QSPIx__->write_conf.data_type = type)
|
||||
#define __QSPI_WRITE_DUMMY_CYCLES_SET(__QSPIx__, cycles) (__QSPIx__->write_conf.dummy_cycles = cycles)
|
||||
|
||||
#define __QSPI_DEVICE_PAGE_SIZE_SET(__QSPIx__, page_size) (__QSPIx__->size_cfg.page_bytes = page_size)
|
||||
#define __QSPI_DEVICE_CS0_SIZE_SET(__QSPIx__, cs_size) (__QSPIx__->size_cfg.CS0_size = cs_size)
|
||||
|
||||
#define __QSPI_DELAY_CS_END_SET(__QSPIx__, _delay) (__QSPIx__->delay.sel_end_offset = _delay)
|
||||
#define __QSPI_DELAY_CS_START_SET(__QSPIx__, _delay) (__QSPIx__->delay.sel_start_offset = _delay)
|
||||
#define __QSPI_DELAY_CS_DESSERT_SET(__QSPIx__, __dessert) (__QSPIx__->delay.sel_dessert = __dessert)
|
||||
|
||||
#define __QSPI_READ_CAPTURE_LP_CLK_EN(__QSPIx__) (__QSPIx__->read_cap.enable_loopback_clk = 1)
|
||||
#define __QSPI_READ_CAPTURE_DELAY_SET(__QSPIx__, delay) (__QSPIx__->read_cap.delay_capture = delay)
|
||||
|
||||
#define __QSPI_DEVICE_ADDR_BYTES_SET(__QSPIx__, bytes) (__QSPIx__->size_cfg.addr_bytes = bytes)
|
||||
|
||||
#define __QSPI_REMAP_ADDRESS_SET(__QSPIx__, address) (__QSPIx__->remap_address = address)
|
||||
|
||||
#define __QSPI_MODE_BIT_SET(__QSPIx__, mode) (__QSPIx__->mode_bits = mode)
|
||||
|
||||
#define __QSPI_POLL_OPCODE_SET(__QSPIx__, opcode) (__QSPIx__->poll_cfg.opcode_poll = opcode)
|
||||
#define __QSPI_POLL_BIT_INDEX_SET(__QSPIx__, index) (__QSPIx__->poll_cfg.poll_bit_index = index)
|
||||
#define __QSPI_POLL_POLARITY_SET(__QSPIx__, pol) (__QSPIx__->poll_cfg.poll_polarity = pol)
|
||||
#define __QSPI_POLL_ENABLE(__QSPIx__) (__QSPIx__->poll_cfg.disable_poll = 0)
|
||||
#define __QSPI_POLL_DISABLE(__QSPIx__) (__QSPIx__->poll_cfg.disable_poll = 1)
|
||||
#define __QSPI_POLL_EXPIRE_ENABLE(__QSPIx__) (__QSPIx__->poll_cfg.enable_expiration = 1)
|
||||
#define __QSPI_POLL_EXPIRE_DISABLE(__QSPIx__) (__QSPIx__->poll_cfg.enable_expiration = 0)
|
||||
#define __QSPI_POLL_COUNT_SET(__QSPIx__, count) (__QSPIx__->poll_cfg.poll_count = count)
|
||||
#define __QSPI_POLL_DELAY_SET(__QSPIx__, delay) (__QSPIx__->poll_cfg.poll_repetition_delay = delay)
|
||||
|
||||
#define __QSPI_POLL_EXPIRATION_SET(__QSPIx__, duration) (__QSPIx__->poll_expiration = duration)
|
||||
|
||||
#define __QSPI_CMD_ADDRESS_SET(__QSPIx__, address) (__QSPIx__->cmd_address = address)
|
||||
|
||||
#define __QSPI_STIG_CMD_SET(__QSPIx__, cmd) (__QSPIx__->cmd_ctrl = cmd)
|
||||
#define __QSPI_STIG_OPCODE_SET(__QSPIx__, opcode) (__QSPIx__->cmd_ctrl.opcode = opcode)
|
||||
#define __QSPI_STIG_READ_ENABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_read = 1)
|
||||
#define __QSPI_STIG_READ_DISABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_read = 0)
|
||||
#define __QSPI_STIG_READ_BYTES_SET(__QSPIx__, bytes) (__QSPIx__->cmd_ctrl.read_bytes = (bytes)-1)
|
||||
#define __QSPI_STIG_CMD_ADDRESS_ENABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_cmd_addr = 0)
|
||||
#define __QSPI_STIG_CMD_ADDRESS_DISABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_cmd_addr = 1)
|
||||
#define __QSPI_STIG_CMD_ADDRESS_BYTES_SET(__QSPIx__, bytes) (__QSPIx__->cmd_ctrl.addr_bytes = (bytes)-1)
|
||||
#define __QSPI_STIG_MODE_ENABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_mode = 1)
|
||||
#define __QSPI_STIG_MODE_DISABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_mode = 0)
|
||||
#define __QSPI_STIG_WRITE_ENABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_write = 1)
|
||||
#define __QSPI_STIG_WRITE_DISABLE(__QSPIx__) (__QSPIx__->cmd_ctrl.enable_write = 0)
|
||||
#define __QSPI_STIG_WRITE_BYTES_SET(__QSPIx__, bytes) (__QSPIx__->cmd_ctrl.write_bytes = (bytes)-1)
|
||||
#define __QSPI_STIG_DUMMY_CYCLES_SET(__QSPIx__, cycles) (__QSPIx__->cmd_ctrl.dummy_cycles = cycles)
|
||||
#define __QSPI_STIG_EXECUTE(__QSPIx__) (__QSPIx__->cmd_ctrl.execute = 1)
|
||||
#define __QSPI_STIG_ON_GOING(__QSPIx__) (__QSPIx__->cmd_ctrl.progress_status == 1)
|
||||
|
||||
#define __QSPI_STIG_DATA_L_SET(__QSPIx__, data_l) (__QSPIx__->write_data_L = data_l)
|
||||
#define __QSPI_STIG_DATA_H_SET(__QSPIx__, data_h) (__QSPIx__->write_data_H = data_h)
|
||||
#define __QSPI_STIG_DATA_L_GET(__QSPIx__) (__QSPIx__->read_data_L)
|
||||
#define __QSPI_STIG_DATA_H_GET(__QSPIx__) (__QSPIx__->read_data_H)
|
||||
|
||||
#define __QSPI_CS_CTRL_RD_BRK_ENABLE(__QSPIx__) (__QSPIx__->cs_ctrl.rd_brk_en = 1)
|
||||
#define __QSPI_CS_CTRL_RD_BRK_DISABLE(__QSPIx__) (__QSPIx__->cs_ctrl.rd_brk_en = 0)
|
||||
#define __QSPI_CS_CTRL_DIS_CS_AFT_FIRST_BYTE_SET(__QSPIx__) (__QSPIx__->cs_ctrl.disable_cs_after_first_byte = 1)
|
||||
#define __QSPI_CS_CTRL_DIS_CS_AFT_FIRST_BYTE_CLR(__QSPIx__) (__QSPIx__->cs_ctrl.disable_cs_after_first_byte = 0)
|
||||
#define __QSPI_CS_PAGE_BOUNDARY_PROTECT_ENABLE(__QSPIx__) (__QSPIx__->cs_ctrl.page_boundary_protect_en = 1)
|
||||
#define __QSPI_CS_PAGE_BOUNDARY_PROTECT_DISABLE(__QSPIx__) (__QSPIx__->cs_ctrl.page_boundary_protect_en = 0)
|
||||
#define __QSPI_CS_PAGE_BOUNDARY_SET(__QSPIx__, _v) (__QSPIx__->cs_ctrl.page_boundary = _v)
|
||||
|
||||
int qspi_stig_cmd(struct qspi_regs_t *QSPI, const struct qspi_stig_reg_t cmd, enum qspi_stig_cmd_type_t type, int len, uint8_t *buffer);
|
||||
|
||||
#endif /* _DRIVER_QSPI_H_ */
|
||||
|
||||
31
fr3092_mcu/components/drivers/peripheral/Inc/driver_rtc.h
Normal file
31
fr3092_mcu/components/drivers/peripheral/Inc/driver_rtc.h
Normal file
@ -0,0 +1,31 @@
|
||||
#ifndef _DRIVER_RTC_H_
|
||||
#define _DRIVER_RTC_H_
|
||||
#include <stdint.h>
|
||||
|
||||
#define CO_BIT(pos) (1UL<<(pos))
|
||||
|
||||
#define PMU_RTC_CRL 0x37
|
||||
#define PMU_UPDATE_EN CO_BIT(0)
|
||||
#define PMU_VAL_RD CO_BIT(1)
|
||||
#define ALAMA_CLR CO_BIT(2)
|
||||
#define ALAMB_CLR CO_BIT(3)
|
||||
#define ALAMA_EN CO_BIT(4)
|
||||
#define ALAMB_EN CO_BIT(5)
|
||||
|
||||
#define PMU_REG_RST_CTRL 0x02
|
||||
|
||||
#define PMU_REG_CLK_CTRL 0x01
|
||||
|
||||
|
||||
|
||||
enum rtc_idx_t
|
||||
{
|
||||
RTC_A,
|
||||
RTC_B,
|
||||
};
|
||||
|
||||
void rtc_test(void);
|
||||
void rtc_stop(void);
|
||||
void rtc_isr_ram(uint8_t rtc_idx);
|
||||
|
||||
#endif
|
||||
288
fr3092_mcu/components/drivers/peripheral/Inc/driver_sbc_dec.h
Normal file
288
fr3092_mcu/components/drivers/peripheral/Inc/driver_sbc_dec.h
Normal file
@ -0,0 +1,288 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_sbc_dec.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of SBC DEC module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SBC_DEC_H__
|
||||
#define __DRIVER_SBC_DEC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
#define SBCD_INFIFO_DEEPTH 128
|
||||
#define SBCD_OUTLFIFO_DEEPTH 256
|
||||
#define SBCD_OUTRFIFO_DEEPTH 256
|
||||
|
||||
|
||||
/** @addtogroup SBC_CODEC_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
/* SBC DEC CTRL REGISTER 0x00*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t DEC_EN : 1;//sbc decoder enable
|
||||
uint32_t DEC_LR_SWAP : 1;//swap decoder left and rignt channel enable
|
||||
uint32_t DEC_OUTL_FLOW_CTRL : 1;//whether use the left outfifo almost full status to control whether to read the infifo
|
||||
uint32_t DEC_OUTR_FLOW_CTRL : 1;//whether use the right outfifo almost full status to control whether to read the infifo
|
||||
uint32_t DEC_RESET : 1;//decoder reset
|
||||
uint32_t DEC_IN_FIFO_RESET : 1;//decoder infifo reset
|
||||
uint32_t DEC_OUTL_FIFO_RESET : 1;//decoder left outfifo reset
|
||||
uint32_t DEC_OUTR_FIFO_RESET : 1;//decoder right outfifo reset
|
||||
uint32_t IN_DMA_EN : 1;//infifo dma enable
|
||||
uint32_t OUT_DMA_EN : 1;//outfifo dma enable
|
||||
uint32_t OUTL_FIFO_EN : 1;//outfifo status select left fifo
|
||||
uint32_t OUTR_FIFO_EN : 1;//outfifo status select right fifo
|
||||
uint32_t RSV : 20;
|
||||
} Bits;
|
||||
} REG_SBCD_CTRL_t;
|
||||
|
||||
|
||||
/* SBC DEC IN FIFO REG REGISTER 0x04*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t SBC_IN : 8;//sbc encoded data in
|
||||
uint32_t RSV : 24;
|
||||
} Bits;
|
||||
} REG_SBCD_INFIFO_REG_t;
|
||||
|
||||
/* SBC DEC OUT FIFO REG REGISTER 0x08*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t PCM_RIGHT_DATA : 16;//sbc encoded data in
|
||||
uint32_t PCM_LEFT_DATA : 16;
|
||||
} Bits;
|
||||
} REG_SBCD_OUTFIFO_REG_t;
|
||||
|
||||
/* SBC DEC INT EN REGISTER 0x0C*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INFF_FULL_INT_EN : 1;//input fifo full interrupt enbale
|
||||
uint32_t INFF_EMPTY_INT_EN : 1;//input fifo empty interrupt enbale
|
||||
uint32_t INFF_ALEMPTY_INT_EN : 1;//input fifo almost empty interrupt enbale
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t OUTLFF_FULL_INT_EN : 1;//output left fifo full interrupt enbale
|
||||
uint32_t OUTLFF_EMPTY_INT_EN : 1;//output left fifo empty interrupt enbale
|
||||
uint32_t OUTLFF_ALFULL_INT_EN : 1;//output left fifo almost full interrupt enbale
|
||||
uint32_t RSV2 : 1;
|
||||
uint32_t OUTRFF_FULL_INT_EN : 1;//output right fifo full interrupt enbale
|
||||
uint32_t OUTRFF_EMPTY_INT_EN : 1;//output right fifo empty interrupt enbale
|
||||
uint32_t OUTRFF_ALFULL_INT_EN : 1;//output right fifo amlost full interrupt enbale
|
||||
uint32_t RSV3 : 1;
|
||||
uint32_t CRC_ERR_INT_EN : 1;//crc error flag interrupt enable
|
||||
uint32_t RSV4 : 19;
|
||||
} Bits;
|
||||
} REG_SBCD_INTEN_REG_t;
|
||||
|
||||
/* SBC DEC INT STATUS REGISTER 0x10*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INFF_FULL_INT_STS : 1;//input fifo full interrupt status
|
||||
uint32_t INFF_EMPTY_INT_STS : 1;//input fifo empty interrupt status
|
||||
uint32_t INFF_ALEMPTY_INT_STS : 1;//input fifo almost empty interrupt status
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t OUTLFF_FULL_INT_STS : 1;//output left fifo full interrupt status
|
||||
uint32_t OUTLFF_EMPTY_INT_STS : 1;//output left fifo empty interrupt status
|
||||
uint32_t OUTLFF_ALFULL_INT_STS : 1;//output left fifo almost full interrupt status
|
||||
uint32_t RSV2 : 1;
|
||||
uint32_t OUTRFF_FULL_INT_STS : 1;//output right fifo full interrupt status
|
||||
uint32_t OUTRFF_EMPTY_INT_STS : 1;//output right fifo empty interrupt status
|
||||
uint32_t OUTRFF_ALFULL_INT_STS : 1;//output right fifo almost full interrupt status
|
||||
uint32_t RSV3 : 1;
|
||||
uint32_t CRC_ERR_INT_STS : 1;//crc interrupt status ,write 1 to cleat this bit
|
||||
uint32_t RSV4 : 19;
|
||||
} Bits;
|
||||
} REG_SBCD_INTS_REG_t;
|
||||
|
||||
|
||||
/* SBC DEC FIFO STATE REGISTER 0x14 */
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INFIFO_FULL : 1;//infifo full flag
|
||||
uint32_t INFIFO_EMPTY : 1;//infifo empty flag
|
||||
uint32_t INFIFO_ALEMPTY : 1;//infifo almost empty flag
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t OUTLFIFO_FULL : 1;//outlfifo full flag
|
||||
uint32_t OUTLFIFO_EMPTY : 1;//outlfifo empty flag
|
||||
uint32_t OUTLFIFO_ALFULL : 1;//outlfifo almost full flag
|
||||
uint32_t RSV2 : 1;
|
||||
uint32_t OUTRFIFO_FULL : 1;//outrfifo full flag
|
||||
uint32_t OUTRFIFO_EMPTY : 1;//outrfifo empty flag
|
||||
uint32_t OUTRFIFO_ALFULL : 1;//outrfifo almost full flag
|
||||
uint32_t RSV : 21;
|
||||
} Bits;
|
||||
} REG_SBCD_FIFO_STATE_t;
|
||||
|
||||
/* SBC DEC FIFO INWDS 0x18*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INFIFO_WC : 8;//input fifo words count
|
||||
uint32_t RSV : 24;//
|
||||
} Bits;
|
||||
} REG_SBCD_FIFO_INWDS_t;
|
||||
|
||||
/* SBC DEC FIFO OUTWDS 0x1C*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t OUTLFIFO_WC : 8;//output left fifo words pointer
|
||||
uint32_t RSV1 : 8;
|
||||
uint32_t OUTRFIFO_WC : 8;//output right fifo words pointer
|
||||
uint32_t RSV2 : 8;
|
||||
} Bits;
|
||||
} REG_SBCD_FIFO_OUTWDS_t;
|
||||
|
||||
/*SBC FIFO LEVEL 0x20*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INFIFO_ALEMPTY_LEVEL : 7;//output left fifo words pointer
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t OUTLFIFO_ALFULL_LEVEL : 8;//output right fifo words pointer
|
||||
uint32_t OUTRFIFO_ALFULL_LEVEL : 8;//output right fifo words pointer
|
||||
uint32_t RSV2 : 8;
|
||||
} Bits;
|
||||
} REG_SBCD_FIFO_LEVEL_t;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_SBCD_CTRL_t SBCD_CTRL; /* Offset 0x00 */
|
||||
volatile REG_SBCD_INFIFO_REG_t SBCD_INFIFO; /* Offset 0x04 */
|
||||
volatile REG_SBCD_OUTFIFO_REG_t SBCD_OUTFIFO; /* Offset 0x08 */
|
||||
volatile REG_SBCD_INTEN_REG_t SBCD_INTEN; /* Offset 0x0C */
|
||||
volatile REG_SBCD_INTS_REG_t SBCD_INTS; /* Offset 0x10 */
|
||||
volatile REG_SBCD_FIFO_STATE_t SBCD_FIFO_STATE; /* Offset 0x14 */
|
||||
volatile REG_SBCD_FIFO_INWDS_t SBCD_FIFO_INWDS; /* Offset 0x18 */
|
||||
volatile REG_SBCD_FIFO_OUTWDS_t SBCD_FIFO_OUTWDS; /* Offset 0x1C */
|
||||
volatile REG_SBCD_FIFO_LEVEL_t SBCD_FIFO_LEVEL; /* Offset 0x20 */
|
||||
}struct_SBCD_t;
|
||||
|
||||
#define SBC_DEC ((struct_SBCD_t *)SBC_DEC_BASE)
|
||||
|
||||
typedef enum{
|
||||
SBCD_MONO = 0,
|
||||
SBCD_STEREO,
|
||||
}enum_Ch_Mode_t ;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t infifo_alempty_lvl : 7;
|
||||
uint32_t outlfifo_alfull_lvl : 8;
|
||||
uint32_t outrlfifo_alfull_lvl : 8;
|
||||
uint32_t input_dma_en : 1;
|
||||
uint32_t output_dma_en : 1;
|
||||
uint32_t outlfifo_en : 1;
|
||||
uint32_t outrfifo_en : 1;
|
||||
uint32_t ch_mode : 1;
|
||||
uint32_t RSV : 4;
|
||||
}Bits;
|
||||
}struct_SBCDec_Init_t;
|
||||
|
||||
|
||||
typedef struct __SBC_DEC_HandleTypeDef
|
||||
{
|
||||
struct_SBCDec_Init_t sbc_init;
|
||||
uint8_t *EncodeData;
|
||||
uint32_t DataSize;
|
||||
uint16_t *OrignData;
|
||||
uint32_t InputIndex;
|
||||
uint32_t OutIndex;
|
||||
|
||||
void (*Callback)(struct __SBC_DEC_HandleTypeDef *hSbcDec); /*!< SBC decode finish Callback */
|
||||
}SBC_DEC_HandleTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
INFF_FULL_INT = (1 << 0),
|
||||
INFF_EMPTY_INT = (1 << 1),
|
||||
INFF_ALEMPTY_INT = (1 << 2),
|
||||
OUTLF_FULL_INT = (1 << 4),
|
||||
OUTLF_EMPTY_INT = (1 << 5),
|
||||
OUTLF_ALFULL_INT = (1 << 6),
|
||||
OUTRF_FULL_INT = (1 << 8),
|
||||
OUTRF_EMPTY_INT = (1 << 9),
|
||||
OUTRF_ALFULL_INT = (1 << 10),
|
||||
CRC_ERR_INT = (1 << 12),
|
||||
}enum_isr_status_t ;
|
||||
|
||||
typedef struct{
|
||||
uint8_t frequency;
|
||||
uint8_t block_mode;
|
||||
uint8_t block_len;
|
||||
uint8_t channels;
|
||||
uint8_t bit_pool;
|
||||
enum {
|
||||
MONO = 0,
|
||||
DUAL_CHANNEL = 1,
|
||||
STEREO = 2,
|
||||
JOINT_STEREO = 3
|
||||
} mode;
|
||||
enum {
|
||||
LOUDNESS = 0,
|
||||
SNR = 1
|
||||
} allocation;
|
||||
uint8_t subband_mode;
|
||||
uint8_t subbands;
|
||||
}struct_frame_info_t;
|
||||
|
||||
#define __SBCD_INFIFO_IS_FULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.INFIFO_FULL == 1)
|
||||
#define __SBCD_INFIFO_IS_EMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.INFIFO_EMPTY == 1)
|
||||
#define __SBCD_INFIFO_IS_ALEMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.INFIFO_ALEMPTY == 1)
|
||||
#define __SBCD_OUTLFIFO_IS_FULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTLFIFO_FULL == 1)
|
||||
#define __SBCD_OUTLFIFO_IS_EMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTLFIFO_EMPTY == 1)
|
||||
#define __SBCD_OUTLFIFO_IS_ALFULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTLFIFO_ALFULL == 1)
|
||||
#define __SBCD_OUTRFIFO_IS_FULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTRFIFO_FULL == 1)
|
||||
#define __SBCD_OUTRFIFO_IS_EMPTY() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTRFIFO_EMPTY == 1)
|
||||
#define __SBCD_OUTRFIFO_IS_ALFULL() (SBC_DEC->SBCD_FIFO_STATE.Bits.OUTRFIFO_ALFULL == 1)
|
||||
|
||||
#define __SBCD_GET_ISR_STS() (SBC_DEC->SBCD_INTS.Word)
|
||||
|
||||
#define __SBCD_INFIFO_EMPTY_DISABLE() (SBC_DEC->SBCD_INTEN.Bits.INFF_EMPTY_INT_EN = 0)
|
||||
|
||||
/* sbc decoder initialize */
|
||||
void sbc_dec_init(SBC_DEC_HandleTypeDef *hSbcDec);
|
||||
/* sbc decoder get packed frame info */
|
||||
int sbc_dec_get_packed_frame_info(uint8_t *data, struct_frame_info_t frame_info);
|
||||
/* sbc decoder handle function in sbc decoder isr */
|
||||
void sbcdec_IRQHandler(SBC_DEC_HandleTypeDef *hSbcDec);
|
||||
/* sbc decoder play data with isr */
|
||||
void sbc_dec_playdata_IT(SBC_DEC_HandleTypeDef *hSbcDec, uint8_t *fp_Data, uint32_t fu32_Size, uint16_t *fp_Data_Out);
|
||||
|
||||
#endif
|
||||
306
fr3092_mcu/components/drivers/peripheral/Inc/driver_sbc_enc.h
Normal file
306
fr3092_mcu/components/drivers/peripheral/Inc/driver_sbc_enc.h
Normal file
@ -0,0 +1,306 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_sbc_enc.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of SBC ENC module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SBC_ENC_H__
|
||||
#define __DRIVER_SBC_ENC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
#define SBCE_INFIFO_DEEPTH 256
|
||||
#define SBCE_OUTFIFO_DEEPTH 128
|
||||
|
||||
|
||||
/** @addtogroup SBC_ENC_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
/* SBC ENC CTRL REGISTER 0x00*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t ENC_EN : 1;//sbc encoder enable
|
||||
uint32_t ENC_LR_SWAP : 1;//swap encoder left and rignt channel enable
|
||||
uint32_t ENC_INL_FLOW_CTRL : 1;//bypass in left fifo status
|
||||
uint32_t ENC_INR_FLOW_CTRL : 1;//bypass in right fifo status
|
||||
uint32_t ENC_RESET : 1;//encoder reset
|
||||
uint32_t ENC_OUT_FIFO_RESET : 1;//encoder outfifo reset
|
||||
uint32_t ENC_INL_FIFO_RESET : 1;//encoder left infifo reset
|
||||
uint32_t ENC_INR_FIFO_RESET : 1;//encoder right infifo reset
|
||||
uint32_t IN_DMA_EN : 1;//infifo dma enable
|
||||
uint32_t OUT_DMA_EN : 1;//outfifo dma enable
|
||||
uint32_t INL_FIFO_EN : 1;//infifo status select left fifo
|
||||
uint32_t INR_FIFO_EN : 1;//infifo status select right fifo
|
||||
uint32_t RSV : 20;
|
||||
} Bits;
|
||||
} REG_SBCE_CTRL_t;
|
||||
|
||||
/* SBC ENC CONFIG REGISTER 0x04*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t SMP_FRQ : 2;//sbc encoder sample frequncy 00->16KHz, 01->32KHz, 10->44.1KHz, 11->48KHz
|
||||
uint32_t BLK_LEN : 2;//block length 00->4 01->8 10->12 11->16
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t CH_MODE : 1;//0->mono 1->dual
|
||||
uint32_t RSV2 : 26;
|
||||
} Bits;
|
||||
} REG_SBCE_CFG_t;
|
||||
|
||||
/* SBC ENC IN FIFO REG REGISTER 0x08*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t ENC_FFL : 16;//left channel input data
|
||||
uint32_t ENC_FFR : 16;//right channel input data
|
||||
} Bits;
|
||||
} REG_SBCE_INFIFO_REG_t;
|
||||
|
||||
/* SBC ENC OUT FIFO REG REGISTER 0x0C*/
|
||||
|
||||
|
||||
/* SBC ENC INT EN REGISTER 0x10*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t OUTFF_FULL_INT_EN : 1;//output fifo full interrupt enbale
|
||||
uint32_t OUTFF_EMPTY_INT_EN : 1;//output fifo empty interrupt enbale
|
||||
uint32_t OUTFF_ALFULL_INT_EN : 1;//output fifo almost full interrupt enbale
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t INLFF_FULL_INT_EN : 1;//input left fifo full interrupt enbale
|
||||
uint32_t INLFF_EMPTY_INT_EN : 1;//input left fifo empty interrupt enbale
|
||||
uint32_t INLFF_ALEMPTY_INT_EN : 1;//input left fifo almost empty interrupt enbale
|
||||
uint32_t RSV2 : 1;
|
||||
uint32_t INRFF_FULL_INT_EN : 1;//input right fifo full interrupt enbale
|
||||
uint32_t INRFF_EMPTY_INT_EN : 1;//input right fifo empty interrupt enbale
|
||||
uint32_t INRFF_ALEMPTY_INT_EN : 1;//input right fifo amlost empty interrupt enbale
|
||||
uint32_t RSV3 : 21;
|
||||
} Bits;
|
||||
} REG_SBCE_INTEN_REG_t;
|
||||
|
||||
/* SBC ENC INT STATUS REGISTER 0x14*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t OUTFF_FULL_INT_STS : 1;//output fifo full interrupt status
|
||||
uint32_t OUTFF_EMPTY_INT_STS : 1;//output fifo empty interrupt status
|
||||
uint32_t OUTFF_ALFULL_INT_STS : 1;//output fifo almost full interrupt status
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t INLFF_FULL_INT_STS : 1;//input left fifo full interrupt status
|
||||
uint32_t INLFF_EMPTY_INT_STS : 1;//input left fifo empty interrupt status
|
||||
uint32_t INLFF_ALEMPTY_INT_STS : 1;//input left fifo almost empty interrupt status
|
||||
uint32_t RSV2 : 1;
|
||||
uint32_t INRFF_FULL_INT_STS : 1;//input right fifo full interrupt status
|
||||
uint32_t INRFF_EMPTY_INT_STS : 1;//input right fifo empty interrupt status
|
||||
uint32_t INRFF_ALEMPTY_INT_STS : 1;//input right fifo almost empty interrupt status
|
||||
uint32_t RSV3 : 21;
|
||||
} Bits;
|
||||
} REG_SBCE_INTS_REG_t;
|
||||
|
||||
|
||||
/* SBC ENC FIFO STATE REGISTER 0x18 */
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t OUTFIFO_FULL : 1;//outfifo full flag
|
||||
uint32_t OUTFIFO_EMPTY : 1;//outfifo empty flag
|
||||
uint32_t OUTFIFO_ALFULL : 1;//outfifo almost empty flag
|
||||
uint32_t RSV1 : 1;
|
||||
uint32_t INLFIFO_FULL : 1;//inlfifo full flag
|
||||
uint32_t INLFIFO_EMPTY : 1;//inlfifo empty flag
|
||||
uint32_t INLFIFO_ALEMPTY : 1;//inlfifo almost full flag
|
||||
uint32_t RSV2 : 1;
|
||||
uint32_t INRFIFO_FULL : 1;//inrfifo full flag
|
||||
uint32_t INRFIFO_EMPTY : 1;//inrfifo empty flag
|
||||
uint32_t INRFIFO_ALEMPTY : 1;//inrfifo almost full flag
|
||||
uint32_t RSV : 21;
|
||||
} Bits;
|
||||
} REG_SBCE_FIFO_STATE_t;
|
||||
|
||||
/* SBC ENC FIFO INWDS 0x1C*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t ENC_INLFFWDS_CNT : 9;//input left fifo words count
|
||||
uint32_t RSV1 : 7;
|
||||
uint32_t ENC_INRFFWDS_CNT : 9;//input right fifo words count
|
||||
uint32_t RSV2 : 7;
|
||||
} Bits;
|
||||
} REG_SBCE_FIFO_INWDS_t;
|
||||
|
||||
/* SBC ENC FIFO OUTWDS 0x20*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t ENC_OUTFFWDS_CNT : 8;//output fifo words pointer
|
||||
uint32_t RSV1 : 24;
|
||||
} Bits;
|
||||
} REG_SBCE_FIFO_OUTWDS_t;
|
||||
|
||||
/*SBC ENC INPUT FIFO LEVEL 0x24*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INLFIFO_ALEMPTY_LEVEL : 8;//output left fifo words pointer
|
||||
uint32_t RSV1 : 8;
|
||||
uint32_t INRFIFO_ALEMPTY_LEVEL : 8;//output left fifo words pointer
|
||||
uint32_t RSV2 : 8;
|
||||
} Bits;
|
||||
} REG_SBCE_INFIFO_LEVEL_t;
|
||||
|
||||
/*SBC ENC OUTPUT FIFO LEVEL 0x28*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t OUTFIFO_ALFULL_LEVEL : 8;//output fifo almost full level
|
||||
uint32_t RSV : 24;
|
||||
} Bits;
|
||||
} REG_SBCE_OUTFIFO_LEVEL_t;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_SBCE_CTRL_t SBCE_CTRL; /* Offset 0x00 */
|
||||
volatile REG_SBCE_CFG_t SBCE_CFG; /* Offset 0x04 */
|
||||
volatile REG_SBCE_INFIFO_REG_t SBCE_INFIFO; /* Offset 0x08 */
|
||||
volatile uint32_t SBCE_OUTFIFO; /* Offset 0x0C */
|
||||
volatile REG_SBCE_INTEN_REG_t SBCE_INTEN; /* Offset 0x10 */
|
||||
volatile REG_SBCE_INTS_REG_t SBCE_INTS; /* Offset 0x14 */
|
||||
volatile REG_SBCE_FIFO_STATE_t SBCE_FIFO_STATE; /* Offset 0x18 */
|
||||
volatile REG_SBCE_FIFO_INWDS_t SBCE_FIFO_INWDS; /* Offset 0x1C */
|
||||
volatile REG_SBCE_FIFO_OUTWDS_t SBCE_FIFO_OUTWDS; /* Offset 0x20 */
|
||||
volatile REG_SBCE_INFIFO_LEVEL_t SBCE_INFIFO_LVL; /* Offset 0x24 */
|
||||
volatile REG_SBCE_OUTFIFO_LEVEL_t SBCE_OUTFF_LVL; /* Offset 0x28 */
|
||||
}struct_SBCE_t;
|
||||
|
||||
#define SBC_ENC ((struct_SBCE_t *)SBC_ENC_BASE)
|
||||
|
||||
typedef enum{
|
||||
SBCE_MONO = 0,
|
||||
SBCE_STEREO = 1,
|
||||
}enum_pcm_channel_mode_t ;
|
||||
|
||||
typedef enum{
|
||||
BLOCK_4 = 0,
|
||||
BLOCK_8 = 1,
|
||||
BLOCK_12 = 2,
|
||||
BLOCK_16 = 3,
|
||||
}enum_pcm_block_length_t ;
|
||||
|
||||
typedef enum{
|
||||
SP_16KHz = 0,
|
||||
SP_32KHz = 1,
|
||||
SP_44_1KHz = 2,
|
||||
SP_48KHz = 3,
|
||||
}enum_pcm_sample_freq_t ;
|
||||
|
||||
typedef struct{
|
||||
uint32_t input_dma_en;
|
||||
uint32_t output_dma_en;
|
||||
uint32_t inlfifo_dma_en;
|
||||
uint32_t inrfifo_dma_en;
|
||||
}struct_SBCE_DMA_cfg_t;
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t inlfifo_alempty_lvl : 8;
|
||||
uint32_t inrfifo_alempty_lvl : 8;
|
||||
uint32_t outlfifo_alfull_lvl : 8;
|
||||
uint32_t output_dma_en : 1;
|
||||
uint32_t input_dma_en : 1;
|
||||
uint32_t sample_freq : 2;
|
||||
uint32_t ch_mode : 1;
|
||||
uint32_t blk_len : 2;
|
||||
uint32_t RSV : 1;
|
||||
}Bits;
|
||||
}struct_SBCENC_Init_t;
|
||||
|
||||
typedef struct{
|
||||
uint32_t outfifo_full_int_en;
|
||||
uint32_t outfifo_empty_int_en;
|
||||
uint32_t outfifo_alfull_int_en;
|
||||
uint32_t inlff_full_int_en;
|
||||
uint32_t inlff_empty_int_en;
|
||||
uint32_t inlff_alempty_int_en;
|
||||
uint32_t inrff_full_int_en;
|
||||
uint32_t inrff_empty_int_en;
|
||||
uint32_t inrff_alempty_int_en;
|
||||
}struct_SBCE_ISR_cfg_t;
|
||||
|
||||
typedef struct __SBC_ENC_HandleTypeDef
|
||||
{
|
||||
struct_SBCENC_Init_t SbcEncInit;
|
||||
uint16_t *OrignlData;
|
||||
uint32_t gDataInIndex;
|
||||
uint8_t *EncodedData;
|
||||
uint32_t gDataOutIndex;
|
||||
uint32_t OrignlDataSize;
|
||||
void (*Callback)(struct __SBC_ENC_HandleTypeDef *hSbcEnc); /*!< SBC encode finish Callback */
|
||||
}SBC_ENC_HandleTypeDef ;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
OUTFF_FULL_INT = (1 << 0),
|
||||
OUTFF_EMPTY_INT = (1 << 1),
|
||||
OUTFF_ALFULL_INT = (1 << 2),
|
||||
INLF_FULL_INT = (1 << 4),
|
||||
INLF_EMPTY_INT = (1 << 5),
|
||||
INLF_ALEMPTY_INT = (1 << 6),
|
||||
INRF_FULL_INT = (1 << 8),
|
||||
INRF_EMPTY_INT = (1 << 9),
|
||||
INRF_ALEMPTY_INT = (1 << 10),
|
||||
}enum_sbce_isr_status_t ;
|
||||
|
||||
#define __SBCE_OUTFIFO_IS_FULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.OUTFIFO_FULL == 1)
|
||||
#define __SBCE_OUTFIFO_IS_EMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.OUTFIFO_EMPTY == 1)
|
||||
#define __SBCE_OUTFIFO_IS_ALFULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.OUTFIFO_ALFULL == 1)
|
||||
#define __SBCE_INLFIFO_IS_FULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.INLFIFO_FULL == 1)
|
||||
#define __SBCE_INLFIFO_IS_EMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INLFIFO_EMPTY == 1)
|
||||
#define __SBCE_INLFIFO_IS_ALEMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INLFIFO_ALEMPTY == 1)
|
||||
#define __SBCE_INRFIFO_IS_FULL() (SBC_ENC->SBCE_FIFO_STATE.Bits.INRFIFO_FULL == 1)
|
||||
#define __SBCE_INRFIFO_IS_EMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INRFIFO_EMPTY == 1)
|
||||
#define __SBCE_INRFIFO_IS_ALEMPTY() (SBC_ENC->SBCE_FIFO_STATE.Bits.INRFIFO_ALEMPTY == 1)
|
||||
|
||||
#define __SBCE_GET_ISR_STS() (SBC_ENC->SBCE_INTS.Word)
|
||||
#define __SBCE_GET_OUT_RESULT_WORD() (SBC_ENC->SBCE_OUTFIFO)
|
||||
|
||||
#define __SBCE_INLFF_EMPTY_INT_DISABLE() (SBC_ENC->SBCE_INTEN.Bits.INLFF_EMPTY_INT_EN = 0)
|
||||
|
||||
void sbc_enc_init(SBC_ENC_HandleTypeDef *hSbcEnc);
|
||||
void sbc_encoder_enc_IT(SBC_ENC_HandleTypeDef *hSbcEnc, uint16_t *fp_Data_In, uint32_t fu32_size, uint8_t *fp_Data_Out);
|
||||
void sbcenc_IRQHandler(SBC_ENC_HandleTypeDef *hSbcEnc);
|
||||
|
||||
#endif
|
||||
764
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd.h
Normal file
764
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd.h
Normal file
@ -0,0 +1,764 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_sd.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of SD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SD_H__
|
||||
#define __DRIVER_SD_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup SD_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Transfer Block control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BlockSize : 12;
|
||||
uint32_t HostSDMABuffer : 3;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t BlockCount : 16;
|
||||
}REG_TransferBlock_t;
|
||||
|
||||
/* Transfer mode Register */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t DMAEnable : 1;
|
||||
uint16_t BlockCountEnable : 1;
|
||||
uint16_t AutoCMDEnable : 2;
|
||||
uint16_t DataDirection : 1;
|
||||
uint16_t MultiBlockEnable : 1;
|
||||
uint16_t rsv_0 : 5;
|
||||
uint16_t StreamModeEnable : 1;
|
||||
uint16_t SPIModeEnable : 1;
|
||||
uint16_t BootAckEnable : 1;
|
||||
uint16_t AlternateBootOperation : 1;
|
||||
uint16_t BootOperation : 1;
|
||||
}REG_TransferConfig_t;
|
||||
|
||||
/* Transfer Block control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CMDInhibit : 1;
|
||||
uint32_t DATInhibit : 1;
|
||||
uint32_t DATLineActive : 1;
|
||||
uint32_t Re_TuningRequset : 1;
|
||||
uint32_t rsv_0 : 4;
|
||||
uint32_t WriteTransferActive : 1;
|
||||
uint32_t ReadTransferActive : 1;
|
||||
uint32_t BufferWriteEnable : 1;
|
||||
uint32_t BUfferReadEnable : 1;
|
||||
uint32_t rsv_1 : 4;
|
||||
uint32_t CradInserted : 1;
|
||||
uint32_t CradStateStable : 1;
|
||||
uint32_t CredDetctPin : 1;
|
||||
uint32_t WriteProtectPin : 1;
|
||||
uint32_t DATLineSignal : 4;
|
||||
uint32_t CMDLineSignal : 1;
|
||||
uint32_t rsv_2 : 7;
|
||||
}REG_PresentState_t;
|
||||
|
||||
/* control 0 Register */
|
||||
typedef struct
|
||||
{
|
||||
/* host control 1 */
|
||||
uint32_t LEDControl : 1;
|
||||
uint32_t DataTransferWidth : 1;
|
||||
uint32_t HighSpeedEnable : 1;
|
||||
uint32_t DMASelect : 2;
|
||||
uint32_t ExtendDataTransferWidth : 1;
|
||||
uint32_t CardDetectTestLevel : 1;
|
||||
uint32_t CardDetectSignalSelection : 1;
|
||||
/* Power control */
|
||||
uint32_t SDBusPower : 1;
|
||||
uint32_t SDBusVoltageSelect : 3;
|
||||
uint32_t SMIH_OD_PP : 1;
|
||||
uint32_t SMIH_RST_N : 1;
|
||||
uint32_t rsv_0 : 2;
|
||||
/* Block gap control */
|
||||
uint32_t StopRequest : 1;
|
||||
uint32_t ContinueRequest : 1;
|
||||
uint32_t ReadWaitControl : 1;
|
||||
uint32_t BlockGapInt : 1;
|
||||
uint32_t rsv_1 : 4;
|
||||
/* wakeup control */
|
||||
uint32_t WEE_CardInterrupt : 1; /* WEE: Wakeup Event Enable */
|
||||
uint32_t WEE_SDCardInsertion : 1;
|
||||
uint32_t WEE_SDCardRemoval : 1;
|
||||
uint32_t rsv_2 : 5;
|
||||
}REG_SD_Control0_t;
|
||||
|
||||
/* control 1 Register */
|
||||
typedef struct
|
||||
{
|
||||
/* clock control */
|
||||
uint32_t InternalClockEnable : 1;
|
||||
uint32_t InternalClockStable : 1;
|
||||
uint32_t SDClockEnable : 1;
|
||||
uint32_t rsv_0 : 2;
|
||||
uint32_t ClockGeneratorSelect : 1;
|
||||
uint32_t SDCLKFrequencySelect1 : 2;
|
||||
uint32_t SDCLKFrequencySelect0 : 8;
|
||||
/* timeout control */
|
||||
uint32_t DATTimeoutValue : 4;
|
||||
uint32_t rsv_1 : 4;
|
||||
/* Software reset */
|
||||
uint32_t ResetAll : 1;
|
||||
uint32_t ResetCMDLine : 1;
|
||||
uint32_t ResetDATLine : 1;
|
||||
uint32_t rsv_2 : 5;
|
||||
}REG_SD_Control1_t;
|
||||
|
||||
/* control 2 Register */
|
||||
typedef struct
|
||||
{
|
||||
/* Auto CMD Error status */
|
||||
uint32_t AutoCMD12NotExecuted : 1;
|
||||
uint32_t AutoCMDTimeoutError : 1;
|
||||
uint32_t AutoCMDCRCError : 1;
|
||||
uint32_t AutoCMDEndBitError : 1;
|
||||
uint32_t AUtoCMDIndexError : 1;
|
||||
uint32_t rsv_0 : 2;
|
||||
uint32_t CommandNotIssuedByAutoCMD12Error : 1;
|
||||
uint32_t rsv_1 : 8;
|
||||
/* host control 2 */
|
||||
uint32_t UHSModeSelect : 3;
|
||||
uint32_t Signal1_8Enable : 1;
|
||||
uint32_t DriverStrengthSelect : 2;
|
||||
uint32_t ExcuteTuning : 1;
|
||||
uint32_t SamplingClockSelect : 1;
|
||||
uint32_t ConsecutiveSampling : 6;
|
||||
uint32_t AsynchronousInterruptEnable : 1;
|
||||
uint32_t SDCLK_IO_Operation : 1;
|
||||
}REG_SD_Control2_t;
|
||||
|
||||
/* Capability0 Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDR50_Support : 1;
|
||||
uint32_t SDR104_Support : 1;
|
||||
uint32_t DDR50_Support : 1;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t DriverTypeASupport : 1;
|
||||
uint32_t DriverTypeCSupport : 1;
|
||||
uint32_t DriverTypeDSupport : 1;
|
||||
uint32_t rsv_1 : 1;
|
||||
uint32_t ReTuningTimerCount : 4;
|
||||
uint32_t rsv_2 : 1;
|
||||
uint32_t SDR50_UseTuning : 1;
|
||||
uint32_t ReTuningMode : 2;
|
||||
uint32_t ClockMultiplier : 8;
|
||||
uint32_t rsv_3 : 8;
|
||||
}REG_Capability0_t;
|
||||
|
||||
/* ------------------------------------------------*/
|
||||
/* SD Register */
|
||||
/* ------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t Argument2; /* Offset 0x00 */
|
||||
volatile REG_TransferBlock_t Block; /* Offset 0x04 */
|
||||
volatile uint32_t Argument1; /* Offset 0x08 */
|
||||
volatile REG_TransferConfig_t TransferConfig; /* Offset 0x0C */
|
||||
volatile uint16_t Command; /* Offset 0x0E */
|
||||
volatile uint32_t Response0; /* Offset 0x10 */
|
||||
volatile uint32_t Response1; /* Offset 0x14 */
|
||||
volatile uint32_t Response2; /* Offset 0x18 */
|
||||
volatile uint32_t Response3; /* Offset 0x1C */
|
||||
volatile uint32_t BufferData; /* Offset 0x20 */
|
||||
volatile uint32_t PresentState; /* Offset 0x24 */
|
||||
volatile REG_SD_Control0_t Control0; /* Offset 0x28 */
|
||||
volatile REG_SD_Control1_t Control1; /* Offset 0x2C */
|
||||
volatile uint32_t StatusInt; /* Offset 0x30 */
|
||||
volatile uint32_t StatusIntEN; /* Offset 0x34 */
|
||||
volatile uint32_t SignalIntEN; /* Offset 0x38 */
|
||||
volatile REG_SD_Control2_t Control2; /* Offset 0x3C */
|
||||
volatile uint32_t Capability0; /* Offset 0x40 */
|
||||
volatile uint32_t Capability1; /* Offset 0x44 */
|
||||
volatile uint32_t MaxCurrent0; /* Offset 0x48 */
|
||||
volatile uint32_t MaxCurrent1; /* Offset 0x4C */
|
||||
volatile uint32_t ForceError; /* Offset 0x50 */
|
||||
volatile uint32_t AMDAError; /* Offset 0x54 */
|
||||
volatile uint32_t ADMA_Address0; /* Offset 0x58 */
|
||||
volatile uint32_t ADMA_Address1; /* Offset 0x5C */
|
||||
volatile uint32_t PresetValue0; /* Offset 0x60 */
|
||||
volatile uint32_t PresetValue1; /* Offset 0x64 */
|
||||
volatile uint32_t PresetValue2; /* Offset 0x68 */
|
||||
volatile uint32_t PresetValue3; /* Offset 0x6C */
|
||||
volatile uint32_t rsv_0[28];
|
||||
volatile uint32_t ShareBusCtl; /* Offset 0xE0 */
|
||||
volatile uint32_t rsv_1[2];
|
||||
volatile uint32_t BurstSize; /* Offset 0xEC */
|
||||
volatile uint32_t rsv_2[3];
|
||||
volatile uint32_t SoltIntStatus; /* Offset 0xFC */
|
||||
}struct_SD_t;
|
||||
|
||||
#define SDIO0 ((struct_SD_t *)SDIOH0_BASE)
|
||||
#define SDIO1 ((struct_SD_t *)SDIOH1_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup SD_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/* SD Bus Voltage Select */
|
||||
typedef enum
|
||||
{
|
||||
VOLTAGE_3_3 = 7,
|
||||
VOLTAGE_3_0 = 6,
|
||||
VOLTAGE_1_8 = 5,
|
||||
}enum_Voltage_Select_t;
|
||||
|
||||
/* command response type */
|
||||
typedef enum
|
||||
{
|
||||
CMD_TYPE_ABORT = 0xC0,
|
||||
CMD_TYPE_RESUME = 0x80,
|
||||
CMD_TYPE_SUSPEND = 0x40,
|
||||
CMD_TYPE_NORMAL = 0,
|
||||
|
||||
DATA_PRESENT = 0x20,
|
||||
NO_DATA_PRESENT = 0,
|
||||
|
||||
RES_NO = 0,
|
||||
RES_R2 = 0x09,
|
||||
RES_R3_R4 = 0x02,
|
||||
RES_R1_R5_R6_R7 = 0x1A,
|
||||
RES_R1b_R5b = 0x1B,
|
||||
}enum_CmdRes_Type_t;
|
||||
|
||||
/* present state mask */
|
||||
typedef enum
|
||||
{
|
||||
PreState_CMD_LINE_MASK = 0x00000001,
|
||||
PreState_DAT_LINE_MASK = 0x00000002,
|
||||
PreState_DAT_LINE_ACTIVE_MASK = 0x00000004,
|
||||
PreState_RE_TUNING_REQUEST_MASK = 0x00000008,
|
||||
PreState_WRITE_TRANDSFER_MASK = 0x00000100,
|
||||
PreState_READ_TRANDSFER_MASK = 0x00000200,
|
||||
PreState_BUFFER_WRITE_EN_MASK = 0x00000400,
|
||||
PreState_BUFFER_READ_EN_MASK = 0x00000800,
|
||||
PreState_CARD_INSERTED_MASK = 0x00010000,
|
||||
PreState_CARD_STABLE_MASK = 0x00020000,
|
||||
PreState_WRITE_PROTECT_MASK = 0x00080000,
|
||||
PreState_DAT0_SIGNAL_MASK = 0x00100000,
|
||||
PreState_DAT1_SIGNAL_MASK = 0x00200000,
|
||||
PreState_DAT2_SIGNAL_MASK = 0x00400000,
|
||||
PreState_DAT3_SIGNAL_MASK = 0x00800000,
|
||||
PreState_CMD_SIGNAL_MASK = 0x01000000,
|
||||
}enum_PresentState_t;
|
||||
|
||||
/* interrupt status mask */
|
||||
typedef enum
|
||||
{
|
||||
INT_CMD_COMPLETE = 0x00000001,
|
||||
INT_TRANSFER_COMPLETE = 0x00000002,
|
||||
INT_BLOCK_GAP_EVENT = 0x00000004,
|
||||
INT_DMA_INT = 0x00000008,
|
||||
INT_BUFFER_WRITE_READY = 0x00000010,
|
||||
INT_BUFFER_READ_READY = 0x00000020,
|
||||
INT_CARD_INSERTION = 0x00000040,
|
||||
INT_CARD_REMOVAL = 0x00000080,
|
||||
INT_CARD_INT = 0x00000100,
|
||||
INT_A = 0x00000200,
|
||||
INT_B = 0x00000400,
|
||||
INT_C = 0x00000800,
|
||||
INT_RE_RUNING_EVENT = 0x00001000,
|
||||
INT_BOOT_ACK_COMPLETE = 0x00002000,
|
||||
INT_BOOT_DONE = 0x00004000,
|
||||
INT_ERR = 0x00008000,
|
||||
|
||||
INT_ERR_CMD_TO = 0x00010000,
|
||||
INT_ERR_CMD_CRC = 0x00020000,
|
||||
INT_ERR_CMD_END_BIT = 0x00040000,
|
||||
INT_ERR_CMD_INDEX = 0x00080000,
|
||||
INT_ERR_DAT_TO = 0x00100000,
|
||||
INT_ERR_DAT_CRC = 0x00200000,
|
||||
INT_ERR_DAT_END_BIT = 0x00400000,
|
||||
INT_ERR_CURRENT_LIMIT = 0x00800000,
|
||||
INT_ERR_AUTO_CMD = 0x01000000,
|
||||
INT_ERR_ADMA = 0x02000000,
|
||||
INT_ERR_TUNING = 0x04000000,
|
||||
INT_ERR_MASK = 0x07FF0000,
|
||||
|
||||
INT_NO_ERR = 0,
|
||||
}enum_INT_Status_t;
|
||||
|
||||
/* Auto CMD error status mask */
|
||||
typedef enum
|
||||
{
|
||||
AUTO_CMD12_NOT_EXECUTED = 0x00000001,
|
||||
AUTO_CMD_ERR_TO = 0x00000002,
|
||||
AUTO_CMD_ERR_CRC = 0x00000004,
|
||||
AUTO_CMD_ERR_END_BIT = 0x00000008,
|
||||
AUTO_CMD_ERR_INDEX = 0x00000010,
|
||||
AUTO_CMD23_ERR = 0x00000080,
|
||||
}enum_AUTO_CMD_ERR_STATUS_t;
|
||||
|
||||
/**
|
||||
* @brief Masks for errors Card Status Response R1
|
||||
*/
|
||||
#define RESP1_ERR_ADDR_OUT_OF_RANGE (0x80000000U)
|
||||
#define RESP1_ERR_ADDR_MISALIGNED (0x40000000U)
|
||||
#define RESP1_ERR_BLOCK_LEN_ERR (0x20000000U)
|
||||
#define RESP1_ERR_ERASE_SEQ_ERR (0x10000000U)
|
||||
#define RESP1_ERR_BAD_ERASE_PARAM (0x08000000U)
|
||||
#define RESP1_ERR_WRITE_PROT_VIOLATION (0x04000000U)
|
||||
#define RESP1_ERR_LOCK_UNLOCK_FAILED (0x01000000U)
|
||||
#define RESP1_ERR_COM_CRC_FAILED (0x00800000U)
|
||||
#define RESP1_ERR_ILLEGAL_CMD (0x00400000U)
|
||||
#define RESP1_ERR_CARD_ECC_FAILED (0x00200000U)
|
||||
#define RESP1_ERR_CC_ERROR (0x00100000U)
|
||||
#define RESP1_ERR_GENERAL_UNKNOWN_ERROR (0x00080000U)
|
||||
#define RESP1_ERR_STREAM_READ_UNDERRUN (0x00040000U)
|
||||
#define RESP1_ERR_STREAM_WRITE_OVERRUN (0x00020000U)
|
||||
#define RESP1_ERR_CID_CSD_OVERWRITE (0x00010000U)
|
||||
#define RESP1_ERR_WP_ERASE_SKIP (0x00008000U)
|
||||
#define RESP1_ERR_CARD_ECC_DISABLED (0x00004000U)
|
||||
#define RESP1_ERR_ERASE_RESET (0x00002000U)
|
||||
#define RESP1_ERR_AKE_SEQ_ERROR (0x00000008U)
|
||||
#define RESP1_ERR_ERRORBITS (0xFDFFE008U)
|
||||
|
||||
#define RCA_ERR_AKE_SEQ_ERROR (0x00000008U)
|
||||
#define RCA_ERR_GENERAL_UNKNOWN_ERROR (0x00002000U)
|
||||
#define RCA_ERR_ILLEGAL_CMD (0x00004000U)
|
||||
#define RCA_ERR_COM_CRC_FAILED (0x00008000U)
|
||||
#define RCA_ERR_ERRORBITS (0x0000E008U)
|
||||
|
||||
/* SD Commands Index */
|
||||
typedef enum
|
||||
{
|
||||
SDMMC_CMD0_GO_IDLE_STATE = 0x000, // 0
|
||||
MMC_CMD1_SEND_OP_COND = 0x100, // 1
|
||||
SDMMC_CMD2_ALL_SEND_CID = 0x200, // 2
|
||||
SD_CMD3_SEND_RELATIVE_ADDR = 0x300, // 3
|
||||
MMC_CMD3_SET_RELATIVE_ADDR = 0x300, // 3
|
||||
SDMMC_CMD4_SET_DSR = 0x400, // 4
|
||||
SD_CMD6_SWITCH_FUNC = 0x600, // 6
|
||||
MMC_CMD6_SWITCH = 0x600, // 6
|
||||
SDMMC_CMD7_SEL_DESEL_CARD = 0x700, // 7
|
||||
SD_CMD8_SEND_IF_COND = 0x800, // 8
|
||||
MMC_CMD8_SEND_EXT_CSD = 0x800, // 8
|
||||
SDMMC_CMD9_SEND_CSD = 0x900, // 9
|
||||
SDMMC_CMD10_SEND_CID = 0xA00, // 10
|
||||
SD_CMD11_VOLTAGE_SWITCH = 0xB00, // 11
|
||||
SDMMC_CMD12_STOP_TRANSMISSION = 0xC00, // 12
|
||||
SDMMC_CMD13_SEND_STATUS = 0xD00, // 13
|
||||
SDMMC_CMD15_GO_INACTIVE_STATE = 0xF00, // 15
|
||||
SDMMC_CMD16_SET_BLOCKLEN = 0x1000, // 16
|
||||
SDMMC_CMD17_READ_SINGLI_BLOCK = 0x1100, // 17
|
||||
SDMMC_CMD18_READ_MULTIPLE_BLOCK = 0x1200, // 18
|
||||
SD_CMD19_SEND_TUNING_BLOCK = 0x1300, // 19
|
||||
SD_CMD20_SPEED_CLASS_CONTROL = 0x1400, // 20
|
||||
MMC_CMD21_SEND_TUNING_BLOCK = 0x1500, // 21
|
||||
SDMMC_CMD23_SET_BLOCK_COUNT = 0x1700, // 23
|
||||
SDMMC_CMD24_WRITE_BLOCK = 0x1800, // 24
|
||||
SDMMC_CMD25_WRITE_MULTIPLE_BLOCK = 0x1900, // 25
|
||||
MMC_CMD226_PROGRAM_CID = 0x1A00, // 26
|
||||
SDMMC_CMD27_PROGRAM_CSD = 0x1B00, // 27
|
||||
SDMMC_CMD28_SET_WRITE_PROT = 0x1C00, // 28
|
||||
SDMMC_CMD29_CLR_WRITE_PROT = 0x1D00, // 29
|
||||
SDMMC_CMD30_SEND_WRITE_PROT = 0x1E00, // 30
|
||||
MMC_CMD30_SEND_WRITE_PROT_TYPE = 0x1F00, // 31
|
||||
SD_CMD32_ERASE_WR_BLK_START = 0x2000, // 32
|
||||
SD_CMD33_ERASE_WR_BLK_END = 0x2100, // 33
|
||||
MMC_CMD35_ERASE_GROUP_START = 0x2300, // 35
|
||||
MMC_CMD36_ERASE_GROUP_END = 0x2400, // 36
|
||||
SDMMC_CMD38_ERASE = 0x2600, // 38
|
||||
SDMMC_CMD42_LOCK_UNLOCK = 0x2A00, // 42
|
||||
SDMMC_CMD55_APP_CMD = 0x3700, // 55
|
||||
SDMMC_CMD56_GEN_CMD = 0x3800, // 56
|
||||
}enum_SD_MMC_CMD_t;
|
||||
|
||||
/* SD APP Commands Index */
|
||||
typedef enum
|
||||
{
|
||||
SD_ACMD6_SET_BUS_WIDTH = 0x600, // 6
|
||||
SD_ACMD13_SD_STATUS = 0xD00, // 13
|
||||
SD_ACMD22_SEND_NUM_WR_BLOCKS = 0x1600, // 22
|
||||
SD_ACMD23_SET_WR_BLK_ERASE_COUNT = 0x1700, // 23
|
||||
SD_ACMD41_SD_SEND_OP_COND = 0x2900, // 41
|
||||
SD_ACMD42_SET_CLR_CARD_DETECT = 0x2A00, // 42
|
||||
SD_ACMD51_SEND_SCR = 0x3300, // 51
|
||||
}enum_SD_ACMD_t;
|
||||
|
||||
/* SD BUS Speed mode */
|
||||
typedef enum
|
||||
{
|
||||
SPEED_DS = 0x010, /* default Speed up to 25MHz 3.3V signaling */
|
||||
SPEED_HS = 0x011, /* High Speed up to 50MHz 3.3V signaling */
|
||||
SPEED_SDR12 = 0x100, /* SDR up to 25MHz 1.8V signaling */
|
||||
SPEED_SDR25 = 0x101, /* SDR up to 50MHz 1.8V signaling */
|
||||
SPEED_SDR50 = 0x102, /* SDR up to 100MHz 1.8V signaling */
|
||||
SPEED_SDR104 = 0x103, /* SDR up to 208MHz 1.8V signaling */
|
||||
SPEED_DDR50 = 0x104, /* DDR up to 50MHz 1.8V signaling */
|
||||
|
||||
SIGNALING_3_3V_MASK = 0x010,
|
||||
SIGNALING_1_8V_MASK = 0x100,
|
||||
}enum_SpeedMode_t;
|
||||
|
||||
/**
|
||||
* @brief SDIO Command Control structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Argument; /*!< Specifies the SDIO command argument which is sent to a card
|
||||
as part of a command message. */
|
||||
|
||||
uint32_t CmdIndex; /*!< Specifies the SDIO command index.
|
||||
This parameter can be a value of @ref enum_SD_CMD_t/enum_SD_ACMD_t */
|
||||
|
||||
uint32_t CmdType; /*!< Specifies the SDIO command type.
|
||||
This parameter can be a value of @ref enum_CmdRes_Type_t */
|
||||
|
||||
uint32_t DataType; /*!< Specifies the SDIO command type.
|
||||
This parameter can be a value of @ref enum_CmdRes_Type_t */
|
||||
|
||||
uint32_t ResponseType; /*!< Specifies the SDIO response type.
|
||||
This parameter can be a value of @ref enum_CmdRes_Type_t */
|
||||
}SDIO_CmdTypeDef;
|
||||
|
||||
/*
|
||||
* @brief SD Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||
This parameter can be a even number from 0 to 510 */
|
||||
|
||||
uint32_t SpeedMode; /*!< Specifies the bus speed mode of the SDIO controller.
|
||||
This parameter can be a value of @ref enum_SpeedMode_t */
|
||||
}struct_SDInit_t;
|
||||
|
||||
/*
|
||||
* @brief MMC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||
This parameter can be a even number from 0 to 510 */
|
||||
}struct_MMCInit_t;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* set SDMA system Address */
|
||||
#define __SD_SET_SDMA_SYSTEM_ADDR(__SDx__, __ADDR__) (__SDx__->Argument2 = __ADDR__)
|
||||
/* set argument value */
|
||||
#define __SD_SET_ARGUMENT1(__SDx__, __VALUE__) (__SDx__->Argument1 = __VALUE__)
|
||||
#define __SD_SET_ARGUMENT2(__SDx__, __VALUE__) (__SDx__->Argument2 = __VALUE__)
|
||||
|
||||
/* __SD_SET_BLOCK_SIZE */
|
||||
#define __SD_SET_BLOCK_SIZE(__SDx__, __SIZE__) (__SDx__->Block.BlockSize = __SIZE__)
|
||||
/* __SD_SET_SDMA_BUFF */
|
||||
#define __SD_SET_SDMA_BUFF(__SDx__, __BUFF__) (__SDx__->Block.HostSDMABuffer = __BUFF__)
|
||||
/* __SD_SET_BLOCK_COUNT */
|
||||
/* __SD_GET_BLOCK_COUNT */
|
||||
#define __SD_SET_BLOCK_COUNT(__SDx__, __COUNT__) (__SDx__->Block.BlockCount = __COUNT__)
|
||||
#define __SD_GET_BLOCK_COUNT(__SDx__) (__SDx__->Block.BlockCount)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Transfer Mode */
|
||||
/* ----------------------*/
|
||||
/* __SD_DMA_ENABLE */
|
||||
/* __SD_DMA_DISABLE */
|
||||
#define __SD_DMA_ENABLE(__SDx__) (__SDx__->TransferConfig.DMAEnable = 1)
|
||||
#define __SD_DMA_DISABLE(__SDx__) (__SDx__->TransferConfig.DMAEnable = 0)
|
||||
|
||||
/* Block Count register Enable */
|
||||
#define __SD_BLOCK_COUNT_ENABLE(__SDx__) (__SDx__->TransferConfig.BlockCountEnable = 1)
|
||||
#define __SD_BLOCK_COUNT_DISABLE(__SDx__) (__SDx__->TransferConfig.BlockCountEnable = 0)
|
||||
|
||||
/* 0x0: Auto command disable */
|
||||
/* 0x1: Auto CMD12 enable */
|
||||
/* 0x2: Auto CMD23 enable */
|
||||
#define __SD_AUTO_CMD_ENABLE(__SDx__, __INDEX__) (__SDx__->TransferConfig.AutoCMDEnable = __INDEX__)
|
||||
|
||||
/* data transfer direction */
|
||||
#define __SD_DATA_DIRECTION(__SDx__, __DIR__) (__SDx__->TransferConfig.DataDirection = __DIR__)
|
||||
|
||||
/* Multi / Single Block Select */
|
||||
#define __SD_MULTI_BLOCK_ENABLE(__SDx__) (__SDx__->TransferConfig.MultiBlockEnable = 1)
|
||||
#define __SD_MULTI_BLOCK_DISABLE(__SDx__) (__SDx__->TransferConfig.MultiBlockEnable = 0)
|
||||
|
||||
/* MMC mode CMD11 / CMD20 Stream Read/Write Operations */
|
||||
#define __SD_MMC_STREAM_MODE_ENABLE(__SDx__) (__SDx__->TransferConfig.StreamModeEnable = 1)
|
||||
#define __SD_MMC_STREAM_MODE_DISABLE(__SDx__) (__SDx__->TransferConfig.StreamModeEnable = 0)
|
||||
|
||||
/* SPI mode enable */
|
||||
#define __SD_SPI_MODE_ENABLE(__SDx__) (__SDx__->TransferConfig.SPIModeEnable = 1)
|
||||
#define __SD_SPI_MODE_DISABLE(__SDx__) (__SDx__->TransferConfig.SPIModeEnable = 0)
|
||||
|
||||
/* Boot Ack Enable */
|
||||
#define __SD_BOOT_ACK_ENABLE(__SDx__) (__SDx__->TransferConfig.BootAckEnable = 1)
|
||||
#define __SD_BOOT_ACK_DISABLE(__SDx__) (__SDx__->TransferConfig.BootAckEnable = 0)
|
||||
|
||||
/* Alternate Boot Operation */
|
||||
#define __SD_ALTERNATE_BOOT_START(__SDx__) (__SDx__->TransferConfig.AlternateBootOperation = 1)
|
||||
#define __SD_ALTERNATE_BOOT_STOP(__SDx__) (__SDx__->TransferConfig.AlternateBootOperation = 0)
|
||||
|
||||
/* Boot Operation */
|
||||
#define __SD_BOOT_START(__SDx__) (__SDx__->TransferConfig.BootOperation = 1)
|
||||
#define __SD_BOOT_STOP(__SDx__) (__SDx__->TransferConfig.BootOperation = 0)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Command */
|
||||
/* ----------------------*/
|
||||
#define __SD_SEND_COMMAND(__SDx__, __CMD__) (__SDx__->Command = __CMD__)
|
||||
|
||||
/* Get response value */
|
||||
#define __SD_GET_RESPONSE0(__SDx__) (__SDx__->Response0)
|
||||
#define __SD_GET_RESPONSE1(__SDx__) (__SDx__->Response1)
|
||||
#define __SD_GET_RESPONSE2(__SDx__) (__SDx__->Response2)
|
||||
#define __SD_GET_RESPONSE3(__SDx__) (__SDx__->Response3)
|
||||
|
||||
/* Set BufferData address */
|
||||
/* Get BufferData address */
|
||||
#define __SD_SET_BUFFERDATA(__SDx__, __DATA__) (__SDx__->BufferData = __DATA__)
|
||||
#define __SD_GET_BUFFERDATA(__SDx__) (__SDx__->BufferData)
|
||||
|
||||
/* Get present state */
|
||||
#define __SD_GET_PRESENT_STATE(__SDx__) (__SDx__->PresentState)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Host control 1 */
|
||||
/* ----------------------*/
|
||||
/* LED Control */
|
||||
#define __SD_LED_CONTROL(__SDx__, __EN__) (__SDx__->Control0.LEDControl = __EN__)
|
||||
/* Data Transfer Width */
|
||||
#define __SD_DATA_WIDTH_1BIT(__SDx__) (__SDx__->Control0.DataTransferWidth = 0)
|
||||
#define __SD_DATA_WIDTH_4BIT(__SDx__) (__SDx__->Control0.DataTransferWidth = 1)
|
||||
/* High Speed Enable */
|
||||
#define __SD_SPEED_MODE(__SDx__, __SPEED__) (__SDx__->Control0.HighSpeedEnable = __SPEED__)
|
||||
/* DMA Select */
|
||||
#define __SD_DMA_SELECT(__SDx__, __DMA__) (__SDx__->Control0.DMASelect = __DMA__)
|
||||
/* 8 bit width mode */
|
||||
#define __SD_8BIT_WIDTH_ENABLE(__SDx__) (__SDx__->Control0.ExtendDataTransferWidth = 1)
|
||||
#define __SD_8BIT_WIDTH_DISABLE(__SDx__) (__SDx__->Control0.ExtendDataTransferWidth = 0)
|
||||
/* Card Detect Test */
|
||||
#define __SD_CRAD_DETECT(__SDx__, __DETECT__) (__SDx__->Control0.CardDetectTestLevel = __DETECT__)
|
||||
/* Card Detect Signal Selection */
|
||||
#define __SD_CRAD_DETECT_SIGNAL(__SDx__, __SIGNAL__) (__SDx__->Control0.CardDetectSignalSelection = __SIGNAL__)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Power control 1 */
|
||||
/* ----------------------*/
|
||||
/* SD Bus Power */
|
||||
#define __SD_BUS_POWER_ON(__SDx__) (__SDx__->Control0.SDBusPower = 1)
|
||||
#define __SD_BUS_POWER_OFF(__SDx__) (__SDx__->Control0.SDBusPower = 0)
|
||||
/* SD Bus Voltage Select */
|
||||
#define __SD_BUS_VOLTAGE_SELECT(__SDx__, __VOLTAGE__) (__SDx__->Control0.SDBusVoltageSelect = __VOLTAGE__)
|
||||
/* Open drain/push-pull in MMC mode */
|
||||
#define __SD_MMC_OD_PP(__SDx__, __OD_PP__) (__SDx__->Control0.SMIH_OD_PP = __OD_PP__)
|
||||
/* External Hardware reset in MMC mode */
|
||||
#define __SD_MMC_EXT_RST(__SDx__, __RST__) (__SDx__->Control0.SMIH_RST_N = __RST__)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Block Gap control */
|
||||
/* ----------------------*/
|
||||
/* Stop At Block Gap request */
|
||||
#define __SD_STOP_AT_BLOCK_GAP(__SDx__, __STOP__) (__SDx__->Control0.StopRequest = __STOP__)
|
||||
/* Continue At Block Gap request */
|
||||
#define __SD_CONTINUE_AT_BLOCK_GAP(__SDx__, __CONTINUE__) (__SDx__->Control0.ContinueRequest = __CONTINUE__)
|
||||
/* Read Wait Control */
|
||||
#define __SD_READ_WAIT(__SDx__, __WAIT__) (__SDx__->Control0.ReadWaitControl = __WAIT__)
|
||||
/* Interrupt At Block Gap */
|
||||
#define __SD_INT_AT_BLOCK_GAP(__SDx__, __INT__) (__SDx__->Control0.BlockGapInt = __INT__)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Wakeup control */
|
||||
/* ----------------------*/
|
||||
/* Wakeup Event Enable On Card Interrupt */
|
||||
#define __SD_WAKEUP_ON_CARD_INT(__SDx__, __ON__) (__SDx__->Control0.WEE_CardInterrupt = __ON__)
|
||||
/* Wakeup Event Enable On SD Card Insertion */
|
||||
#define __SD_WAKEUP_ON_CARD_INSERTION(__SDx__, __ON__) (__SDx__->Control0.WEE_SDCardInsertion = __ON__)
|
||||
/* Wakeup Event Enable On SD Card Removal */
|
||||
#define __SD_WAKEUP_ON_CARD_REMOVAL(__SDx__, __ON__) (__SDx__->Control0.WEE_SDCardRemoval = __ON__)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Clock control */
|
||||
/* ----------------------*/
|
||||
/* Internal Clock Enable/Disable */
|
||||
#define __SD_INTERNAL_CLOCK_ENABLE(__SDx__) (__SDx__->Control1.InternalClockEnable = 1)
|
||||
#define __SD_INTERNAL_CLOCK_DISABLE(__SDx__) (__SDx__->Control1.InternalClockEnable = 0)
|
||||
/* Is Internal Clock Stable */
|
||||
#define __SD_IS_INTERNAL_CLOCK_STABLE(__SDx__) (__SDx__->Control1.InternalClockStable == 1)
|
||||
/* SD Clock Enable/Disable */
|
||||
#define __SD_SDCLK_ENABLE(__SDx__) (__SDx__->Control1.SDClockEnable = 1)
|
||||
#define __SD_SDCLK_DISABLE(__SDx__) (__SDx__->Control1.SDClockEnable = 0)
|
||||
/* Clock Generator Select */
|
||||
#define __SD_CLOCK_GENERATOR_SELECT(__SDx__, __SELECT__) (__SDx__->Control1.ClockGeneratorSelect = __SELECT__)
|
||||
/* SDCLK Frequency divide high 2bit */
|
||||
#define __SD_CLOCK_DIV_HIGH_2BIT(__SDx__, __DIV__) (__SDx__->Control1.SDCLKFrequencySelect1 = __DIV__)
|
||||
/* SDCLK Frequency divide low 8bit */
|
||||
#define __SD_CLOCK_DIV_LOW_8BIT(__SDx__, __DIV__) (__SDx__->Control1.SDCLKFrequencySelect0 = __DIV__)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Timeout control */
|
||||
/* ----------------------*/
|
||||
/* Data Timeout Counter Value */
|
||||
#define __SD_DATA_TIMEOUT_COUNT(__SDx__, __COUNT__) (__SDx__->Control1.DATTimeoutValue = __COUNT__)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Software control */
|
||||
/* ----------------------*/
|
||||
/* Software Reset For All */
|
||||
#define __SD_RST_SDIO_CONTROLLER(__SDx__) (__SDx__->Control1.ResetAll = 1)
|
||||
/* Software Reset For CMD Line */
|
||||
#define __SD_RST_CMD_LINE(__SDx__) (__SDx__->Control1.ResetCMDLine = 1)
|
||||
/* Software Reset For DAT Line */
|
||||
#define __SD_RST_DAT_LINE(__SDx__) (__SDx__->Control1.ResetDATLine = 1)
|
||||
|
||||
/* get interrupt status */
|
||||
#define __SD_GET_INT_STATUS(__SDx__) (__SDx__->StatusInt)
|
||||
/* clear interrupt status */
|
||||
#define __SD_CLR_INT_STATUS(__SDx__, __STATUS__) (__SDx__->StatusInt |= __STATUS__)
|
||||
#define __SD_CLR_ALL_INT_STATUS(__SDx__) (__SDx__->StatusInt = 0xFFFFFFFF)
|
||||
/* interrupt Status enable/disable */
|
||||
#define __SD_INT_STATUS_ENABLE(__SDx__, __STATUS__) (__SDx__->StatusIntEN |= (__STATUS__))
|
||||
#define __SD_INT_STATUS_DISABLE(__SDx__, __STATUS__) (__SDx__->StatusIntEN &= ~(__STATUS__))
|
||||
#define __SD_INT_STATUS_ALL_ENABLE(__SDx__) (__SDx__->StatusIntEN = 0xFFFFFFFF)
|
||||
#define __SD_INT_STATUS_ALL_DISABLE(__SDx__) (__SDx__->StatusIntEN = 0x00000000)
|
||||
/* interrupt Signal enable/disable */
|
||||
#define __SD_INT_ENABLE(__SDx__, __STATUS__) (__SDx__->SignalIntEN |= (__STATUS__))
|
||||
#define __SD_INT_DISABLE(__SDx__, __STATUS__) (__SDx__->SignalIntEN &= ~(__STATUS__))
|
||||
|
||||
/* get Auto CMD Error Status */
|
||||
#define __SD_GET_AUTO_CMD_ERR_STATUS(__SDx__) (__SDx__->Control2 & 0x0000FFFF)
|
||||
|
||||
/* ----------------------*/
|
||||
/* Host control 2 */
|
||||
/* ----------------------*/
|
||||
/* UHS Mode Select */
|
||||
#define __SD_UHS_MODE(__SDx__, __MODE__) (__SDx__->Control2.UHSModeSelect = __MODE__)
|
||||
/* 1.8V Signaling */
|
||||
#define __SD_1_8V_ENABLE(__SDx__, __EN__) (__SDx__->Control2.Signal1_8Enable = __EN__)
|
||||
/* Driver Strength Select */
|
||||
#define __SD_DRIVER_TYPE_SELECT(__SDx__, __TYPE__) (__SDx__->Control2.DriverStrengthSelect = __TYPE__)
|
||||
/* Execute Tuning */
|
||||
#define __SD_EXECUTE_TUNING(__SDx__) (__SDx__->Control2.ExcuteTuning = 1)
|
||||
/* Sampling Clock Select */
|
||||
#define __SD_SAMPLING_CLOCK_SELECT(__SDx__, _SELECT__) (__SDx__->Control2.SamplingClockSelect = _SELECT__)
|
||||
/* Consecutive Sampling */
|
||||
#define __SD_CONSECUTIVE_SAMPLING(__SDx__, __COUNT__) (__SDx__->Control2.ConsecutiveSampling = __COUNT__)
|
||||
/* Asynchronous Interrupt Enable */
|
||||
#define __SD_ASYN_INT_ENABLE(__SDx__, __EN__) (__SDx__->Control2.AsynchronousInterruptEnable = __EN__)
|
||||
/* Preset config Enabled */
|
||||
#define __SD_PRESET_ENABLE(__SDx__, __EN__) (__SDx__->Control2.SDCLK_IO_Operation = __EN__)
|
||||
|
||||
/* AHB Master Burst Size */
|
||||
#define __SD_AHB_BURST_SIZE(__SDx__, __BURST__) (__SDx__->BurstSize = __BURST__)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* SD_CMD_SetBlockCount */
|
||||
uint32_t SD_CMD_SetBlockCount(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
/* Read */
|
||||
uint32_t SD_CMD_ReadSingleBlock(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
uint32_t SD_CMD_ReadMultiBlock(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
uint32_t SD_CMD_ReadBlock_SDMA(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
/* Write */
|
||||
uint32_t SD_CMD_WriteSingleBlock(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
uint32_t SD_CMD_WriteMultiBlock(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
uint32_t SD_CMD_WriteBlock_SDMA(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
/* Erase */
|
||||
uint32_t SD_CMD_EraseStartAddr(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
uint32_t SD_CMD_EraseEndAddr(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
uint32_t SD_CMD_Erase(struct_SD_t *SDx);
|
||||
|
||||
/* SD_CMD_StopTransfer */
|
||||
uint32_t SD_CMD_StopTransfer(struct_SD_t *SDx);
|
||||
/* SD_CMD_BlockLength */
|
||||
uint32_t SD_CMD_BlockLength(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
/* SD_CMD_SelectCard / SD_CMD_DeselectCard */
|
||||
uint32_t SD_CMD_SelectCard(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
uint32_t SD_CMD_DeselectCard(struct_SD_t *SDx);
|
||||
/* SD_CMD_GoIdleState */
|
||||
uint32_t SD_CMD_GoIdleState(struct_SD_t *SDx);
|
||||
/* SD_CMD_VoltageSwitch */
|
||||
uint32_t SD_CMD_VoltageSwitch(struct_SD_t *SDx);
|
||||
/* SD_CMD_SwitchFunc */
|
||||
uint32_t SD_CMD_SwitchFunc(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
|
||||
/* SD_CMD_AllSendCID */
|
||||
/* SD_CMD_SendRelAddr */
|
||||
/* SD_CMD_SendCSD */
|
||||
/* SD_CMD_SendStatus */
|
||||
/* SD_CMD_SendInterfaceCondition */
|
||||
uint32_t SD_CMD_AllSendCID(struct_SD_t *SDx, uint32_t *fp32_Response);
|
||||
uint32_t SD_CMD_SendRelAddr(struct_SD_t *SDx, uint32_t *fp32_RCA);
|
||||
uint32_t SD_CMD_SendCSD(struct_SD_t *SDx, uint32_t fu32_Argument, uint32_t *fp32_Response);
|
||||
uint32_t SD_CMD_SendStatus(struct_SD_t *SDx, uint32_t fu32_Argument, uint32_t *fp_Resp);
|
||||
uint32_t SD_CMD_SendInterfaceCondition(struct_SD_t *SDx);
|
||||
|
||||
/* SD_CMD_AppCommand */
|
||||
uint32_t SD_CMD_AppCommand(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
/* SD_ACMD_SendOperCondition */
|
||||
/* SD_ACMD_SetBusWidth */
|
||||
uint32_t SD_ACMD_SendOperCondition(struct_SD_t *SDx, uint32_t fu32_Argument, uint32_t *fp32_Response);
|
||||
uint32_t SD_ACMD_SetBusWidth(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
|
||||
/* SD_SDCardClass_Init */
|
||||
/* SD_SDMMCClass_Init */
|
||||
void SD_SDCardClass_Init(struct_SD_t *SDx);
|
||||
void SD_SDMMCClass_Init(struct_SD_t *SDx);
|
||||
|
||||
/* MMC_CMD_GoIdleState */
|
||||
/* MMC_CMD_AllSendCID */
|
||||
/* MMC_CMD_SendCSD */
|
||||
/* MMC_CMD_SelectCard */
|
||||
/* MMC_CMD_DeselectCard */
|
||||
#define MMC_CMD_GoIdleState SD_CMD_GoIdleState
|
||||
#define MMC_CMD_AllSendCID SD_CMD_AllSendCID
|
||||
#define MMC_CMD_SendCSD SD_CMD_SendCSD
|
||||
#define MMC_CMD_SelectCard SD_CMD_SelectCard
|
||||
#define MMC_CMD_DeselectCard SD_CMD_DeselectCard
|
||||
#define MMC_CMD_SendStatus SD_CMD_SendStatus
|
||||
|
||||
/* SD_CMD_SetBlockCount */
|
||||
#define MMC_CMD_SetBlockCount SD_CMD_SetBlockCount
|
||||
/* MMC_CMD_ReadSingleBlock */
|
||||
/* MMC_CMD_ReadMultiBlock */
|
||||
/* MMC_CMD_ReadBlock_SDMA */
|
||||
#define MMC_CMD_ReadSingleBlock SD_CMD_ReadSingleBlock
|
||||
#define MMC_CMD_ReadMultiBlock SD_CMD_ReadMultiBlock
|
||||
#define MMC_CMD_ReadBlock_SDMA SD_CMD_ReadBlock_SDMA
|
||||
/* MMC_CMD_WriteSingleBlock */
|
||||
/* MMC_CMD_WriteMultiBlock */
|
||||
/* MMC_CMD_WriteBlock_SDMA */
|
||||
#define MMC_CMD_WriteSingleBlock SD_CMD_WriteSingleBlock
|
||||
#define MMC_CMD_WriteMultiBlock SD_CMD_WriteMultiBlock
|
||||
#define MMC_CMD_WriteBlock_SDMA SD_CMD_WriteBlock_SDMA
|
||||
|
||||
/* MMC_CMD_SendOperCondition */
|
||||
uint32_t MMC_CMD_SendOperCondition(struct_SD_t *SDx, uint32_t fu32_Argument, uint32_t *fp32_Response);
|
||||
/* MMC_CMD_SendExtendedCSD */
|
||||
uint32_t MMC_CMD_SendExtendedCSD(struct_SD_t *SDx);
|
||||
/* MMC_CMD_SetRelAddr */
|
||||
uint32_t MMC_CMD_SetRelAddr(struct_SD_t *SDx, uint32_t fu32_RCA);
|
||||
/* MMC_CMD_Switch */
|
||||
uint32_t MMC_CMD_Switch(struct_SD_t *SDx, uint32_t fu32_Argument);
|
||||
|
||||
#endif
|
||||
254
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd_card.h
Normal file
254
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd_card.h
Normal file
@ -0,0 +1,254 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_sd_card.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of SD card application HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SD_CARD_H__
|
||||
#define __DRIVER_SD_CARD_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup SD_Card_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
#define BLOCKSIZE (512U) /*!< Block size is 512 bytes */
|
||||
|
||||
#define SDMA_ADDR_ALIGN_MASK (0xFFF80000U) /*!< SDMA align 512K Bytes */
|
||||
#define SDMA_ADDR_UNIT (0x80000U)
|
||||
|
||||
#define CARD_STATUS_IDLE (0x0) /*!< Card status idle */
|
||||
#define CARD_STATUS_READ_BUSY (0x1) /*!< Card status read busy */
|
||||
#define CARD_STATUS_WIRTE_BUSY (0x2) /*!< Card status write busy */
|
||||
#define CARD_STATUS_ERASE_BUSY (0x3) /*!< Card status erase busy */
|
||||
#define CARD_STATUS_ERR (0x4) /*!< Card status error */
|
||||
|
||||
/* card version */
|
||||
#define CARD_VER_1_X (1U)
|
||||
#define CARD_VER_2_X (2U)
|
||||
|
||||
/* card type */
|
||||
#define CARD_TYPE_SDHC_SDXC (1U)
|
||||
#define CARD_TYPE_SDSC (2U)
|
||||
|
||||
/* SDIO bus width */
|
||||
#define SDIO_BUS_WIDTH_1BIT (0U)
|
||||
#define SDIO_BUS_WIDTH_4BIT (2U)
|
||||
|
||||
/* Card current state in R1 */
|
||||
#define CARD_CURRENT_STATE_IDLE (0x000)
|
||||
#define CARD_CURRENT_STATE_READY (0x200)
|
||||
#define CARD_CURRENT_STATE_IDENT (0x400)
|
||||
#define CARD_CURRENT_STATE_STBY (0x600)
|
||||
#define CARD_CURRENT_STATE_TRAN (0x800)
|
||||
#define CARD_CURRENT_STATE_DATA (0xA00)
|
||||
#define CARD_CURRENT_STATE_RCV (0xC00)
|
||||
#define CARD_CURRENT_STATE_PRG (0xE00)
|
||||
#define CARD_CURRENT_STATE_DIS (0x1000)
|
||||
#define CARD_CURRENT_STATE_MASK (0x1E00)
|
||||
|
||||
/* ACMD41 argument */
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_27_28 (0x00008000) // VDD Voltage Window 2.7V~2.8V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_28_29 (0x00010000) // VDD Voltage Window 2.8V~2.9V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_29_30 (0x00020000) // VDD Voltage Window 2.9V~3.0V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_30_31 (0x00040000) // VDD Voltage Window 3.0V~3.1V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_31_32 (0x00080000) // VDD Voltage Window 3.1V~3.2V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_32_33 (0x00100000) // VDD Voltage Window 3.2V~3.3V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_33_34 (0x00200000) // VDD Voltage Window 3.3V~3.4V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_34_35 (0x00400000) // VDD Voltage Window 3.4V~3.5V
|
||||
#define ACMD41_ARG_VOLTAGE_WINDOW_35_36 (0x00800000) // VDD Voltage Window 3.5V~3.6V
|
||||
#define ACMD41_ARG_S18R (0x01000000) // switch to 1.8V Accepted
|
||||
#define ACMD41_ARG_XPC (0x10000000) // 150mA(max) and speed class is supported
|
||||
#define ACMD41_ARG_HCS (0x40000000) // host capacity support information
|
||||
|
||||
/* OCR register fields definition */
|
||||
#define OCR_BUSY (0x80000000) // Card power up status bit
|
||||
#define OCR_CCS (0x40000000) // Card capacity status
|
||||
#define OCR_S18A (0x01000000) // switch to 1.8V Accepted
|
||||
|
||||
/* error code */
|
||||
#define E1_NUM_ERR (0x0001) // Number of SD blocks is 0.
|
||||
#define E2_1_8V_ERR (0x0002) // Card not support 1.8V.
|
||||
#define E3_SPEED_ERR (0x0004) // Card not support selected Speed.
|
||||
#define E4_CARD_BUSY (0x0005) // Card busy.
|
||||
|
||||
/*
|
||||
* @brief CSD register definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t rsv_0 : 2;
|
||||
uint32_t FILE_FORMAT : 2; /*!< file format */
|
||||
uint32_t TMP_WRITE_PROTECT : 1; /*!< temporary write protection */
|
||||
uint32_t PERM_WRITE_PROTECT : 1; /*!< permanent write protection */
|
||||
uint32_t COPY : 1; /*!< copy flag */
|
||||
uint32_t FILE_FORMAT_GRP : 1; /*!< file format group */
|
||||
uint32_t rsv_1 : 5;
|
||||
uint32_t WRITE_BL_PARTIAL : 1; /*!< partial blocks for write allowed */
|
||||
uint32_t WRITE_BL_LEN : 4; /*!< max. write data block length */
|
||||
uint32_t R2W_FACTOR : 3; /*!< write speed factor */
|
||||
uint32_t rsv_2 : 2;
|
||||
uint32_t WP_GRP_ENABLE : 1; /*!< write protect group enable */
|
||||
uint32_t WP_GRP_SIZE : 7; /*!< write protect group size */
|
||||
uint32_t SECTOR_SIZE_H : 1; /*!< erase sector seize */
|
||||
|
||||
uint32_t SECTOR_SIZE_L : 6; /*!< erase sector seize */
|
||||
uint32_t REASE_BLK_EN : 1; /*!< erase single block enable */
|
||||
uint32_t rsv_3 : 1;
|
||||
uint32_t C_SIZE : 22; /*!< device size. 22-bit */
|
||||
uint32_t rsv_4 : 2;
|
||||
|
||||
uint32_t rsv_5 : 4;
|
||||
uint32_t DSR_IMP : 1; /*!< DSR implemented */
|
||||
uint32_t READ_BLK_MISALIGN : 1; /*!< read block misalignment */
|
||||
uint32_t WRITE_BLK_MISALIGN : 1; /*!< write block misalignment */
|
||||
uint32_t READ_BL_PARTIAL : 1; /*!< partial blocks for read allowed */
|
||||
uint32_t READ_BL_LEN : 4; /*!< max. read data block length */
|
||||
uint32_t CCC : 12; /*!< crad command classes */
|
||||
uint32_t TRAN_SPEED : 8; /*!< max. data transfer rate */
|
||||
|
||||
uint32_t NSAC : 8; /*!< data read access in CLK cycles(NSAC*100) */
|
||||
uint32_t TAAC : 8; /*!< data read access time 1 */
|
||||
uint32_t rsv_6 : 6;
|
||||
uint32_t CSD_STRUCTURE : 2; /*!< CSD structure */
|
||||
uint32_t rsv_7 : 8;
|
||||
}SD_CardCSDTypeDef;
|
||||
|
||||
/*
|
||||
* @brief CID register definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||
uint16_t ProductSN_A; /*!< Product Serial Number */
|
||||
uint16_t ProductSN_B; /*!< Product Serial Number */
|
||||
uint8_t ProductRevision; /*!< Product Revision */
|
||||
uint8_t ProductName[5]; /*!< Product Name */
|
||||
uint16_t OEM_ApplicationID; /*!< OEM/Application ID */
|
||||
uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
uint8_t rsv_0;
|
||||
}SD_CardCIDTypeDef;
|
||||
|
||||
/*
|
||||
* @brief SCR register definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SCR_STRUCTURE : 4; /*!< SCR structure */
|
||||
uint32_t SD_SPEC : 4; /*!< SD Memory Card - spec version */
|
||||
uint32_t DATA_STAT_AFTER_ERASE : 1; /*!< data status after erases */
|
||||
uint32_t SD_SECURITY : 3; /*!< CPRM security support */
|
||||
uint32_t SD_BUS_WIDTHS : 4; /*!< dat bus widths support */
|
||||
uint32_t SD_SPEC3 : 1; /*!< spec version 3.00 or higher */
|
||||
uint32_t EX_SUPPORT : 4; /*!< extended security support */
|
||||
uint32_t rsv_0 : 9;
|
||||
uint32_t CMD_SUPPORT : 2; /*!< command support bit */
|
||||
uint32_t Manufacturer : 32; /*!< reserved for Manufacturer usage */
|
||||
}SD_CardSCRTypeDef;
|
||||
|
||||
/*
|
||||
* @brief SD Card Status definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
|
||||
uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
|
||||
uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
|
||||
uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
|
||||
uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
|
||||
uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
|
||||
uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
|
||||
uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
|
||||
uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
|
||||
uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
|
||||
uint8_t UHS_SPEED_GRADE; /*!< speed grade for UHS mode */
|
||||
uint8_t UHS_AU_SIZE; /*!< Size of AU for UHS mode */
|
||||
}SD_CardStatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SD Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t CardVersion; /*!< Specifies the card version */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t MemoryCapacity; /*!< Specifies Memory Capacity in KBytes */
|
||||
|
||||
uint32_t SpeedCapacity; /*!< Specifies speed Capacity */
|
||||
}SD_CardInfoTypeDef;
|
||||
|
||||
/*
|
||||
* @brief SD handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
struct_SD_t *SDx; /*!< SD registers base address */
|
||||
|
||||
struct_SDInit_t Init; /*!< SD communication parameters */
|
||||
|
||||
SD_CardInfoTypeDef CardInfo; /*!< SD Card information */
|
||||
|
||||
SD_CardCIDTypeDef *CIDInfo; /*!< CID information */
|
||||
SD_CardCSDTypeDef *CSDInfo; /*!< CSD information */
|
||||
|
||||
uint32_t CSD[4]; /*!< SD card CSD register */
|
||||
uint32_t CID[4]; /*!< SD card CID register */
|
||||
uint32_t SCR[2]; /*!< SD card SCR register */
|
||||
uint32_t OCR; /*!< SD card OCR register */
|
||||
uint32_t RCA; /*!< SD card RCA register */
|
||||
|
||||
volatile uint32_t CardStatus; /*!< SD card status */
|
||||
volatile uint32_t AddrAlign; /*!< SDMA address align */
|
||||
}SD_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* SDCard_Init */
|
||||
uint32_t SDCard_Init(SD_HandleTypeDef *hsd);
|
||||
/* SDCard_BusWidth_Select */
|
||||
uint32_t SDCard_BusWidth_Select(SD_HandleTypeDef *hsd, uint32_t fu32_BusWidth);
|
||||
|
||||
/* Read/Write Blocks */
|
||||
uint32_t SDCard_ReadBolcks(SD_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
uint32_t SDCard_WriteBolcks(SD_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
|
||||
/* Read/Write Blocks use SDMA */
|
||||
uint32_t SDCard_ReadBolcks_SDMA(SD_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
uint32_t SDCard_WriteBolcks_SDMA(SD_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
|
||||
/* Read/Write Blocks use SDMA with interrupt */
|
||||
uint32_t SDCard_ReadBolcks_SDMA_IT(SD_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
uint32_t SDCard_WriteBolcks_SDMA_IT(SD_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
|
||||
/* SDCard_Erase */
|
||||
uint32_t SDCard_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAddr, uint32_t BlockEndAddr);
|
||||
|
||||
/* SDCard_Get_Block_count */
|
||||
uint32_t SDCard_Get_Block_count(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* SDCard_IRQHandler */
|
||||
void SDCard_IRQHandler(SD_HandleTypeDef *hsd);
|
||||
|
||||
#endif
|
||||
234
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd_device.h
Normal file
234
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd_device.h
Normal file
@ -0,0 +1,234 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_sd_device.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of SD device HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SD_DEVICE_H__
|
||||
#define __DRIVER_SD_DEVICE_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup SD_device_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Capability0 Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ProgramDone : 1;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t CardInitDone : 1;
|
||||
uint32_t AddressOutRange : 1;
|
||||
uint32_t AddressMisalign : 1;
|
||||
uint32_t RpmbDisable : 1;
|
||||
uint32_t EraseParam : 1;
|
||||
uint32_t CardECCFailed : 1;
|
||||
uint32_t CCError : 1;
|
||||
uint32_t Error : 1;
|
||||
uint32_t MMC_IRQ_Trigger : 1;
|
||||
uint32_t CMDDataOutputEdge : 1;
|
||||
uint32_t CMD32_CMD33_Enable : 1;
|
||||
uint32_t BootSequenceSupport : 1;
|
||||
uint32_t SwitchError : 1;
|
||||
uint32_t SendBootACK : 1;
|
||||
uint32_t WP_Violation : 1;
|
||||
uint32_t WP_Erase_Skip : 1;
|
||||
uint32_t CID_CSD_Overwrite : 1;
|
||||
uint32_t AKE_Seq_Error : 1;
|
||||
uint32_t Card_ECC_Disabled : 1;
|
||||
uint32_t StreamThresholdSize : 3;
|
||||
uint32_t PermanentWriteProtect : 1;
|
||||
uint32_t TemporaryWriteProtect : 1;
|
||||
uint32_t WPCommandsEnabled : 1;
|
||||
uint32_t ALLOW_AKE : 1;
|
||||
uint32_t SECURED_MODE : 1;
|
||||
uint32_t AKE_SEQ_OK : 1;
|
||||
uint32_t ASSD_Disable : 1;
|
||||
uint32_t BootDataReady : 1;
|
||||
}REG_SDDevice_Control_t;
|
||||
|
||||
/* Command Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Application : 1;
|
||||
uint32_t BlockSize : 12;
|
||||
uint32_t CommandIndex : 6;
|
||||
uint32_t CurrentBusWidth : 2;
|
||||
uint32_t CurrentSpeed : 3;
|
||||
uint32_t CardState : 4;
|
||||
uint32_t EraseSequence : 1;
|
||||
uint32_t rsv_0 : 3;
|
||||
}REG_SDDevice_Command_t;
|
||||
|
||||
/* Password Length Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PWDS_LEN : 8;
|
||||
uint32_t LockUnlockEnable : 1;
|
||||
uint32_t rsv_0 : 23;
|
||||
}REG_PasswordLength_t;
|
||||
|
||||
/* -------------------------------------------------*/
|
||||
/* SD Device Register */
|
||||
/* -------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_SDDevice_Control_t Control; /* Offset 0x00 */
|
||||
volatile REG_SDDevice_Command_t Command; /* Offset 0x04 */
|
||||
volatile uint32_t Argument; /* Offset 0x08 */
|
||||
volatile uint32_t BlockCount; /* Offset 0x0C */
|
||||
volatile uint32_t DMA1Address; /* Offset 0x10 */
|
||||
volatile uint32_t DMA1Control; /* Offset 0x14 */
|
||||
volatile uint32_t DMA2Address; /* Offset 0x18 */
|
||||
volatile uint32_t DMA2Control; /* Offset 0x1C */
|
||||
volatile uint32_t EraseWriteBlockStart; /* Offset 0x20 */
|
||||
volatile uint32_t EraseWriteblockEnd; /* Offset 0x24 */
|
||||
volatile REG_PasswordLength_t PasswordLength; /* Offset 0x28 */
|
||||
volatile uint32_t SecureBlockCount; /* Offset 0x2C */
|
||||
volatile uint32_t rsv_0[3];
|
||||
volatile uint32_t IntStatus; /* Offset 0x3C */
|
||||
volatile uint32_t IntStatusEn; /* Offset 0x40 */
|
||||
volatile uint32_t IntSignalEn; /* Offset 0x44 */
|
||||
volatile uint32_t CardAddress; /* Offset 0x48 */
|
||||
volatile uint32_t CardData; /* Offset 0x4C */
|
||||
volatile uint32_t IOREADY; /* Offset 0x50 */
|
||||
volatile uint32_t Function1Control; /* Offset 0x54 */
|
||||
volatile uint32_t Function2Control; /* Offset 0x58 */
|
||||
volatile uint32_t SDIOCCCRControl; /* Offset 0x5C */
|
||||
volatile uint32_t SDIOFBRxControl[8]; /* Offset 0x60 ~ 0x7C */
|
||||
volatile uint32_t CardSize; /* Offset 0x80 */
|
||||
volatile uint32_t CardOCR; /* Offset 0x84 */
|
||||
volatile uint32_t Control2; /* Offset 0x88 */
|
||||
volatile uint32_t rsv_1;
|
||||
volatile uint32_t Function3Control; /* Offset 0x90 */
|
||||
volatile uint32_t Function4Control; /* Offset 0x94 */
|
||||
volatile uint32_t Function5Control; /* Offset 0x98 */
|
||||
volatile uint32_t IntStatus2; /* Offset 0x9C */
|
||||
volatile uint32_t IntStatusEn2; /* Offset 0xA0 */
|
||||
volatile uint32_t IntSignal2; /* Offset 0xA4 */
|
||||
volatile uint32_t Password_127_96; /* Offset 0xA8 */
|
||||
volatile uint32_t Password_95_64; /* Offset 0xAC */
|
||||
volatile uint32_t Password_63_32; /* Offset 0xB0 */
|
||||
volatile uint32_t Passowrd_31_0; /* Offset 0xB4 */
|
||||
volatile uint32_t ADMAErrorStatus; /* Offset 0xB8 */
|
||||
volatile uint32_t RCA; /* Offset 0xBC */
|
||||
volatile uint32_t Debug[7]; /* Offset 0xC0 ~ 0xD8 */
|
||||
volatile uint32_t AHBMasterBurstSize; /* Offset 0xDC */
|
||||
volatile uint32_t Argument2; /* Offset 0xE0 */
|
||||
}struct_SD_Device_t;
|
||||
|
||||
#define SD_DEVICE ((struct_SD_Device_t *)SDIOD0_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup SD_device_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/* SD device interrupt status mask */
|
||||
typedef enum
|
||||
{
|
||||
INT_TRANSFER_COMP = 0x00000001,
|
||||
INT_DMA1 = 0x00000002,
|
||||
INT_SLEEP_AWAKE = 0x00000004,
|
||||
INT_WRITE_START = 0x00000008,
|
||||
INT_READ_START = 0x00000010,
|
||||
INT_PASSWORD_SET = 0x00000020,
|
||||
INT_PASSWORD_RESET = 0x00000040,
|
||||
INT_LOCK_CARD = 0x00000080,
|
||||
INT_UNLOCK_CARD = 0x00000100,
|
||||
INT_FORCE_ERASE = 0x00000200,
|
||||
INT_ERASE = 0x00000400,
|
||||
INT_CMD11 = 0x00000800,
|
||||
INT_CMD0_CMD52 = 0x00001000,
|
||||
INT_CMD6_CHECK = 0x00002000,
|
||||
INT_CMD6_SWITCH = 0x00004000,
|
||||
INT_PROGRAM_CSD = 0x00008000,
|
||||
INT_ACMD23 = 0x00010000,
|
||||
INT_CMD20 = 0x00020000,
|
||||
/* 0x00040000 */
|
||||
INT_CMD4 = 0x00080000,
|
||||
INT_BOOT_START = 0x00100000,
|
||||
INT_FUNCTION1_RESET = 0x00200000,
|
||||
INT_FUNCTION2_RESET = 0x00400000,
|
||||
INT_CMD11_CLK_STOP = 0x00800000,
|
||||
INT_CMD11_CLK_START = 0x01000000,
|
||||
INT_PROGRAM_START = 0x02000000,
|
||||
INT_CMD40 = 0x04000000,
|
||||
INT_CMD_R1b = 0x08000000,
|
||||
INT_FUNCTIONX_ERROR = 0x10000000,
|
||||
INT_FUNCTIONX_ABORT = 0x20000000,
|
||||
INT_LRST = 0x40000000,
|
||||
INT_BOOT_COMPLETE = 0x80000000,
|
||||
}enum_SD_Device_Status_t;
|
||||
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* ----------------------*/
|
||||
/* Control control */
|
||||
/* ----------------------*/
|
||||
|
||||
/* Program Done */
|
||||
#define __SD_D_SET_PROGRAM_DONE(__SDx__) (__SDx__->Control.ProgramDone = 1)
|
||||
/* Card Init Done */
|
||||
#define __SD_D_CARD_INIT_DONE(__SDx__) (__SDx__->Control.CardInitDone = 1)
|
||||
/* Address Out of Range */
|
||||
#define __SD_D_ADDR_OUT_RANGE(__SDx__) (__SDx__->Control.AddressOutRange = 1)
|
||||
/* Address Misalign */
|
||||
#define __SD_D_ADDR_MISALIGN(__SDx__) (__SDx__->Control.AddressMisalign = 1)
|
||||
/* Command and Data Output at the falling edge */
|
||||
/* Command and Data Output at the Rising edge */
|
||||
#define __SD_D_FALLING_EDGE_OUTPUT(__SDx__) (__SDx__->Control.CMDDataOutputEdge = 0)
|
||||
#define __SD_D_RISING_EDGE_OUTPUT(__SDx__) (__SDx__->Control.CMDDataOutputEdge = 1)
|
||||
/* support/nonsupport CMD32 CMD33 */
|
||||
#define __SD_D_CMD32_CMD33_ENABLE(__SDx__) (__SDx__->Control.CMD32_CMD33_Enable = 0)
|
||||
#define __SD_D_CMD32_CMD33_DISABLE(__SDx__) (__SDx__->Control.CMD32_CMD33_Enable = 1)
|
||||
/* Stream Threshold Size */
|
||||
#define __SD_D_SET_STREAM_THRESHOLD_SIZE(__SDx__, __SIZE__) (__SDx__->Control.StreamThresholdSize = __SIZE__)
|
||||
|
||||
/* Set card address */
|
||||
/* Set card data */
|
||||
#define __SD_D_SET_CARD_ADDR(__SDx__, __ADDR__) (__SDx__->CardAddress = __ADDR__)
|
||||
#define __SD_D_SET_CARD_DATA(__SDx__, __DATA__) (__SDx__->CardData = __DATA__)
|
||||
|
||||
/* get interrupt status */
|
||||
#define __SD_D_GET_INT_STATUS(__SDx__) (__SDx__->IntStatus)
|
||||
/* clear interrupt status */
|
||||
#define __SD_D_CLR_INT_STATUS(__SDx__, __STATUS__) (__SDx__->IntStatus |= __STATUS__)
|
||||
/* interrupt Status enable/disable */
|
||||
#define __SD_D_INT_STATUS_ENABLE(__SDx__, __STATUS__) (__SDx__->IntStatusEn |= (__STATUS__))
|
||||
#define __SD_D_INT_STATUS_DISABLE(__SDx__, __STATUS__) (__SDx__->IntStatusEn &= ~(__STATUS__))
|
||||
#define __SD_D_INT_STATUS_ALL_ENABLE(__SDx__) (__SDx__->IntStatusEn = 0xFFFFFFFF)
|
||||
#define __SD_D_INT_STATUS_ALL_DISABLE(__SDx__) (__SDx__->IntStatusEn = 0x00000000)
|
||||
/* interrupt Signal enable/disable */
|
||||
#define __SD_D_INT_ENABLE(__SDx__, __STATUS__) (__SDx__->IntSignalEn |= (__STATUS__))
|
||||
#define __SD_D_INT_DISABLE(__SDx__, __STATUS__) (__SDx__->IntSignalEn &= ~(__STATUS__))
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
212
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd_mmc.h
Normal file
212
fr3092_mcu/components/drivers/peripheral/Inc/driver_sd_mmc.h
Normal file
@ -0,0 +1,212 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_sd_mmc.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of Multi-Media card application HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SD_MMC_H__
|
||||
#define __DRIVER_SD_MMC_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup eMMC_Card_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/* MMC Voltage mode */
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
|
||||
|
||||
/* MMC Memory Cards type */
|
||||
#define eMMC_DUAL_VOLTAGE_CARD 0x00000080U
|
||||
#define eMMC_CAPACITY_HIGHER_2G 0x40000000U
|
||||
|
||||
/*
|
||||
* @brief Extended CSD revisions
|
||||
*/
|
||||
#define MMC_REV_V4_0 (0)
|
||||
#define MMC_REV_V4_1 (1)
|
||||
#define MMC_REV_V4_2 (2)
|
||||
#define MMC_REV_V4_3 (3)
|
||||
#define MMC_REV_V4_41 (5)
|
||||
#define MMC_REV_V4_45 (6)
|
||||
|
||||
/*
|
||||
* @brief MMC speed supports in
|
||||
*/
|
||||
#define MMC_DEVICE_TPYE_HS200_1_2V (0x20)
|
||||
#define MMC_DEVICE_TPYE_HS200_1_8V (0x10)
|
||||
#define MMC_DEVICE_TPYE_HIGH_SPEED_DUAL_1_2V (0x08)
|
||||
#define MMC_DEVICE_TPYE_HIGH_SPEED_DUAL_1_8V_3V (0x04)
|
||||
#define MMC_DEVICE_TPYE_HIGH_SPEED_SINGLE_52MHz (0x02)
|
||||
#define MMC_DEVICE_TPYE_HIGH_SPEED_SINGLE_26MHz (0x01)
|
||||
|
||||
/* MMC bus width */
|
||||
#define MMC_BUS_WIDTH_1BIT (0U)
|
||||
#define MMC_BUS_WIDTH_4BIT (1U)
|
||||
#define MMC_BUS_WIDTH_8BIT (2U)
|
||||
|
||||
/* MMC CMD6 access mode */
|
||||
#define MMC_CMD6_ACCESS_CMD_SET (0x00000000)
|
||||
#define MMC_CMD6_ACCESS_SET_BITS (0x01000000)
|
||||
#define MMC_CMD6_ACCESS_CLR_BITS (0x02000000)
|
||||
#define MMC_CMD6_ACCESS_WRITE_BYTE (0x03000000)
|
||||
|
||||
/*
|
||||
* @brief The parameter index in the Extended CSD register.
|
||||
*/
|
||||
#define MMC_EX_CSD_INDEX_SEC_COUNT0 (212)
|
||||
#define MMC_EX_CSD_INDEX_SEC_COUNT1 (213)
|
||||
#define MMC_EX_CSD_INDEX_SEC_COUNT2 (214)
|
||||
#define MMC_EX_CSD_INDEX_SEC_COUNT3 (215)
|
||||
#define MMC_EX_CSD_INDEX_DEVICE_TYPE (196)
|
||||
#define MMC_EX_CSD_INDEX_EXT_CSD_REV (192)
|
||||
#define MMC_EX_CSD_INDEX_HS_TIMING (185)
|
||||
#define MMC_EX_CSD_INDEX_BUS_WIDTH (183)
|
||||
|
||||
/*
|
||||
* @brief MMC CSD register definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ECC : 2; /*!< ECC code */
|
||||
uint32_t FILE_FORMAT : 2; /*!< file format */
|
||||
uint32_t TMP_WRITE_PROTECT : 1; /*!< temporary write protection */
|
||||
uint32_t PERM_WRITE_PROTECT : 1; /*!< permanent write protection */
|
||||
uint32_t COPY : 1; /*!< copy flag */
|
||||
uint32_t FILE_FORMAT_GRP : 1; /*!< file format group */
|
||||
uint32_t CONTENT_PROT_APP : 1; /*!< content protection application */
|
||||
uint32_t rsv_0 : 4;
|
||||
uint32_t WRITE_BL_PARTIAL : 1; /*!< partial blocks for write allowed */
|
||||
uint32_t WRITE_BL_LEN : 4; /*!< max. write data block length */
|
||||
uint32_t R2W_FACTOR : 3; /*!< write speed factor */
|
||||
uint32_t DEFAULT_ECC : 2;
|
||||
uint32_t WP_GRP_ENABLE : 1; /*!< write protect group enable */
|
||||
uint32_t WP_GRP_SIZE : 5; /*!< write protect group size */
|
||||
uint32_t ERASE_GRP_MULT_L : 3;
|
||||
|
||||
uint32_t ERASE_GRP_MULT_H : 2; /*!< Erase group size multiplier */
|
||||
uint32_t ERASE_GRP_SIZE : 5; /*!< Erase group size */
|
||||
uint32_t C_SIZE_MULT : 3; /*!< Device size multiplier */
|
||||
uint32_t VDD_W_CURR_MAX : 3; /*!< Max. write current @ VDD max */
|
||||
uint32_t VDD_W_CURR_MIN : 3; /*!< Max. write current @ VDD min */
|
||||
uint32_t VDD_R_CURR_MAX : 3; /*!< Max. read current @ VDD max */
|
||||
uint32_t VDD_R_CURR_MIN : 3; /*!< Max. read current @ VDD min */
|
||||
uint32_t C_SIZE_L : 10;
|
||||
|
||||
uint32_t C_SIZE_H : 2; /*!< device size. 12-bit */
|
||||
uint32_t rsv_1 : 2;
|
||||
uint32_t DSR_IMP : 1; /*!< DSR implemented */
|
||||
uint32_t READ_BLK_MISALIGN : 1; /*!< read block misalignment */
|
||||
uint32_t WRITE_BLK_MISALIGN : 1; /*!< write block misalignment */
|
||||
uint32_t READ_BL_PARTIAL : 1; /*!< partial blocks for read allowed */
|
||||
uint32_t READ_BL_LEN : 4; /*!< max. read data block length */
|
||||
uint32_t CCC : 12; /*!< crad command classes */
|
||||
uint32_t TRAN_SPEED : 8; /*!< max. data transfer rate */
|
||||
|
||||
uint32_t NSAC : 8; /*!< data read access in CLK cycles(NSAC*100) */
|
||||
uint32_t TAAC : 8; /*!< data read access time 1 */
|
||||
uint32_t rsv_2 : 2;
|
||||
uint32_t SPEC_VERS : 4; /*!< System specification version */
|
||||
uint32_t CSD_STRUCTURE : 2; /*!< CSD structure */
|
||||
uint32_t rsv_3 : 8;
|
||||
}MMC_CardCSDTypeDef;
|
||||
|
||||
/*
|
||||
* @brief MMC CID register definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t ManufactDate; /*!< Manufacturing Date */
|
||||
uint8_t ProductSN_A; /*!< Product Serial Number */
|
||||
uint16_t ProductSN_B; /*!< Product Serial Number */
|
||||
uint8_t ProductSN_C; /*!< Product Serial Number */
|
||||
uint8_t ProductRevision; /*!< Product Revision */
|
||||
uint8_t ProductName[6]; /*!< Product Name */
|
||||
uint8_t OEM_ApplicationID; /*!< OEM/Application ID */
|
||||
uint8_t BGA; /*!< Device/BGA */
|
||||
uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
uint8_t rsv_0;
|
||||
}MMC_CardCIDTypeDef;
|
||||
|
||||
/*
|
||||
* @brief Extended CSD register definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SEC_COUNT; /*!< Sector Count */
|
||||
uint8_t DEVICE_TYPE; /*!< Device type */
|
||||
uint8_t EXT_CSD_REV; /*!< Extended CSD revision */
|
||||
uint8_t HS_TIMING; /*!< High-speed interface timing */
|
||||
uint8_t BUS_WIDTH; /*!< Bus width mode */
|
||||
}MMC_CardExCSDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief MMC Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t MemoryCapacity; /*!< Specifies Memory Capacity in KBytes */
|
||||
|
||||
uint32_t Revision; /*!< Specifies the Revision */
|
||||
}MMC_CardInfoTypeDef;
|
||||
|
||||
/*
|
||||
* @brief eMMC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
struct_SD_t *SDx; /*!< SD registers base address */
|
||||
|
||||
struct_MMCInit_t Init; /*!< SD communication parameters */
|
||||
|
||||
MMC_CardInfoTypeDef CardInfo; /*!< MMC Card information */
|
||||
|
||||
MMC_CardCIDTypeDef *CIDInfo; /*!< CID information */
|
||||
MMC_CardCSDTypeDef *CSDInfo; /*!< CSD information */
|
||||
MMC_CardExCSDTypeDef ExCSDInfo; /*!< Extended CSD information */
|
||||
|
||||
uint32_t CSD[4]; /*!< SD card CSD register */
|
||||
uint32_t CID[4]; /*!< SD card CID register */
|
||||
uint32_t OCR; /*!< SD card OCR register */
|
||||
uint32_t RCA; /*!< SD card RCA register */
|
||||
}MMC_HandleTypeDef;
|
||||
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* eMMC_Init */
|
||||
uint32_t eMMC_Init(MMC_HandleTypeDef *hmmc);
|
||||
/* eMMC_BusWidth_Select */
|
||||
uint32_t eMMC_BusWidth_Select(MMC_HandleTypeDef *hmmc, uint32_t fu32_BusWidth);
|
||||
|
||||
/* Read/Write Blocks */
|
||||
uint32_t eMMC_ReadBolcks(MMC_HandleTypeDef *hmmc, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
uint32_t eMMC_WriteBolcks(MMC_HandleTypeDef *hmmc, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
|
||||
/* Read/Write Blocks use SDMA */
|
||||
uint32_t eMMC_ReadBolcks_SDMA(MMC_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
uint32_t eMMC_WriteBolcks_SDMA(MMC_HandleTypeDef *hsd, uint32_t *fp_Data, uint32_t fu32_BlockAddr, uint16_t fu16_BlockNum);
|
||||
|
||||
#endif
|
||||
115
fr3092_mcu/components/drivers/peripheral/Inc/driver_sha.h
Normal file
115
fr3092_mcu/components/drivers/peripheral/Inc/driver_sha.h
Normal file
@ -0,0 +1,115 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_sha.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2022
|
||||
* @brief Header file of sha module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SHA_H__
|
||||
#define __DRIVER_SHA_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup SHA_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/*SHA CTRL REG 0x00*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t MODE : 3;//001->SHA-1;010->SHA-256;011->SHA-224;100->SHA-512;101->SHA-384;110->SHA-512/256;111->SHA-512/224
|
||||
uint32_t INIT_EN : 1;//set this bit to encode thhe messgae with the initial value of A-H(A-E when mask= 010)
|
||||
uint32_t ISR_EN : 1;//interrupt enable
|
||||
uint32_t ENDIAN_MODE : 1;//message endian mode 0->big endian 1->little endian
|
||||
uint32_t CALCULATE : 1;//cpu write this bit to enable calculate.read this bit to verify whether the encoding is complete
|
||||
uint32_t RSV : 25;
|
||||
} Bits;
|
||||
} REG_SHA_CTRL_t;
|
||||
|
||||
/*SHA INT STATE REG 0x04*/
|
||||
typedef volatile union
|
||||
{
|
||||
volatile uint32_t Word;
|
||||
struct
|
||||
{
|
||||
uint32_t INT_DONE : 1;//this bit is set by SHA finishing encoding the message and writing the digest to the base address
|
||||
uint32_t INT_ERROR : 1;//this bit is set by SHA select error mode
|
||||
uint32_t RSV : 30;
|
||||
} Bits;
|
||||
} REG_SHA_INT_STATE_t;
|
||||
|
||||
/* ----------------------------------------------*/
|
||||
/* SHA Registers */
|
||||
/* ----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_SHA_CTRL_t SHA_CTRL; /* Offset 0x00 */
|
||||
volatile REG_SHA_INT_STATE_t SHA_INT_STATE; /* Offset 0x04 */
|
||||
volatile uint32_t HASH_VAL_L[8]; /* Offset 0x08 - 0x24*/
|
||||
volatile uint32_t HASH_VAL_H[8]; /* Offset 0x28 - 0x44*/
|
||||
volatile uint32_t DATA_1[16]; /* Offset 0x48 -0x84 */
|
||||
volatile uint32_t DATA_2[16]; /* Offset 0x88-0xb4*/
|
||||
}struct_SEC_SHA_t;
|
||||
|
||||
#define SEC_SHA_OFFSET 0x1000
|
||||
#define SEC_SHA ((struct_SEC_SHA_t *)(SEC_BASE + SEC_SHA_OFFSET))
|
||||
|
||||
/* ################################ Register Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization, Config Section Start ################################ */
|
||||
typedef enum{
|
||||
SHA_1 = 1,
|
||||
SHA_256 = 2,
|
||||
SHA_224 = 3,
|
||||
SHA_512 = 4,
|
||||
SHA_384 = 5,
|
||||
SHA_512_OR_256 = 6,
|
||||
SHA_512_OR_224 = 7
|
||||
}enum_sha_mode_t;
|
||||
|
||||
typedef enum{
|
||||
SHA_BIG_ENDIAN = 0,
|
||||
SHA_LITTLE_ENDIAN = 1
|
||||
}enum_sha_endian_t;
|
||||
|
||||
#define SHA_256_BLOCK_SIZE (64)
|
||||
#define SHA_512_BLOCK_SIZE (128)
|
||||
|
||||
/* ################################ Initialization, Config Section END ################################ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define __SHA_GET_INT_DONE_FALG() (SEC_SHA->SHA_INT_STATE.Bits.INT_DONE)
|
||||
#define __SHA_INT_ERROR() (SEC_SHA->SHA_INT_STATE.Bits.INT_ERROR == 1)
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* sha init */
|
||||
void sha_init(uint8_t Mode);
|
||||
/* sha updata */
|
||||
void sha_update(uint8_t *fp8_Data, uint32_t fu32_Size);
|
||||
/* sha_final */
|
||||
void sha_final(uint8_t *DataOut);
|
||||
|
||||
#endif
|
||||
236
fr3092_mcu/components/drivers/peripheral/Inc/driver_spdif.h
Normal file
236
fr3092_mcu/components/drivers/peripheral/Inc/driver_spdif.h
Normal file
@ -0,0 +1,236 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_spdif.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2023
|
||||
* @brief Header file of SPDIF module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SPDIF_H__
|
||||
#define __DRIVER_SPDIF_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup SPDIF_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* SPDIF CTRL REG */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TSAMPLERATE : 8;
|
||||
uint32_t SFR_ENABLE : 1;
|
||||
uint32_t SPDIF_ENABLE : 1;
|
||||
uint32_t FIFO_ENABLE : 1;
|
||||
uint32_t CLK_ENABLE : 1;
|
||||
uint32_t TR_MODE : 1;
|
||||
uint32_t PARITY_CHECK : 1;
|
||||
uint32_t PARITYGEN : 1;
|
||||
uint32_t VALIDITY_CHECK : 1;
|
||||
uint32_t CHANNEL_MODE : 1;
|
||||
uint32_t DUPLICATE : 1;
|
||||
uint32_t SETPREAMBB : 1;
|
||||
uint32_t rsv_0 : 2;
|
||||
uint32_t PARITY_MASK : 1;
|
||||
uint32_t UNDERR_MASK : 1;
|
||||
uint32_t OVERR_MASK : 1;
|
||||
uint32_t EMPTY_MASK : 1;
|
||||
uint32_t ALEMPTY_MASK : 1;
|
||||
uint32_t FULL_MASK : 1;
|
||||
uint32_t ALFULL_MASK : 1;
|
||||
uint32_t SYNCERR_MASK : 1;
|
||||
uint32_t LOCK_MASK : 1;
|
||||
uint32_t BEGIN_MASK : 1;
|
||||
uint32_t INTREQ_MASK : 1;
|
||||
} REG_SPDIF_CTRL_t;
|
||||
|
||||
/* SPDIF INT REG */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RSAMPLERATE : 8;
|
||||
uint32_t PREAMBLEDEL : 4;
|
||||
uint32_t rsv_0 : 9;
|
||||
uint32_t PARITYO : 1;
|
||||
uint32_t TDATA_UNDERR : 1;
|
||||
uint32_t RDATA_OVERR : 1;
|
||||
uint32_t FIFO_EMPTY : 1;
|
||||
uint32_t FIFO_ALEMPTY : 1;
|
||||
uint32_t FIFO_FULL : 1;
|
||||
uint32_t FIFO_ALFULL : 1;
|
||||
uint32_t SYNC_ERR : 1;
|
||||
uint32_t LOCK : 1;
|
||||
uint32_t BLOCK_BEGIN : 1;
|
||||
uint32_t rsv_1 : 1;
|
||||
} REG_SPDIF_INT_t;
|
||||
|
||||
/* SPDIF FIFO CTRL REG */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ALEMPTY_THRESHOLD : 7;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t HALFULL_THRESHOLD : 7;
|
||||
uint32_t rsv_1 : 1;
|
||||
uint32_t PARITY_INT_TYPE : 1;
|
||||
uint32_t UNDERR_INT_TYPE : 1;
|
||||
uint32_t OVERR_INT_TYPE : 1;
|
||||
uint32_t FF_EMPTY_INT_TYPE : 1;
|
||||
uint32_t FF_ALEMPTY_INT_TYPE : 1;
|
||||
uint32_t FF_FULL_INT_TYPE : 1;
|
||||
uint32_t FF_ALFULL_INT_TYPE : 1;
|
||||
uint32_t SYNCERR_INT_TYPE : 1;
|
||||
uint32_t LOCK_INT_TYPE : 1;
|
||||
uint32_t BLOCK_BEGIN_INT_TYPE : 1;
|
||||
uint32_t rsv_2 : 6;
|
||||
} REG_SPDIF_FIFO_CTRL_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_SPDIF_CTRL_t SPDIF_CTRL; /* Offset 0x00 */
|
||||
volatile uint32_t SPDIF_INT_CLEAR; /* Offset 0x04 */
|
||||
volatile REG_SPDIF_FIFO_CTRL_t SPDIF_FIFO_CTRL; /* Offset 0x08 */
|
||||
volatile uint32_t SPDIF_INT_STS; /* Offset 0x0C */
|
||||
volatile uint32_t SPDIF_FIFO_DATA; /* Offset 0x10 */
|
||||
}struct_SPDIF_t;
|
||||
|
||||
#define SPDIF ((struct_SPDIF_t *)SPDIF_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPDIF_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization_Config Section Start ################################ */
|
||||
|
||||
/* Interrupt Status */
|
||||
typedef enum
|
||||
{
|
||||
PARITY_FLAG = 0x200000,
|
||||
UNDERR_FLAG = 0x400000,
|
||||
OVERR_FLAG = 0x800000,
|
||||
EMPTY_FLAG = 0x1000000,
|
||||
ALEMPTY_FLAG = 0x2000000,
|
||||
FULL_FLAG = 0x4000000,
|
||||
ALFULL_FLAG = 0x8000000,
|
||||
SYNCERR_FLAG = 0x10000000,
|
||||
LOCK_FLAG = 0x20000000,
|
||||
BEGIN_FLAG = 0x40000000,
|
||||
RIGHT_LEFT = 0x80000000,
|
||||
}enum_SPDIF_INT_Index_t;
|
||||
|
||||
|
||||
/* MonoStere Select */
|
||||
typedef enum
|
||||
{
|
||||
SPDIF_STEREO,
|
||||
SPDIF_MONO,
|
||||
}enum_SPDIF_MonoStere_Sel_t;
|
||||
|
||||
/*
|
||||
* @brief SPDIF Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t TxSampleRate; /*!< Specifies the internal Send sample rate.
|
||||
This parameter The value can be a value 0~0x7F*/
|
||||
|
||||
uint8_t CH_Mode; /*!< Specifies the internal Channel selection.
|
||||
This parameter can be a value of @ref enum_SPDIF_MonoStere_Sel_t*/
|
||||
|
||||
uint8_t RSAMPLERATE; /*!< Specifies the internal Send receive rate.
|
||||
This parameter The value can be a value 0~0x7F*/
|
||||
|
||||
uint8_t PREAMBLEDEL; /*!< Specifies the internal Leader B delay.
|
||||
This parameter The value can be a value 0~0xF*/
|
||||
|
||||
uint8_t ALFIFOEmpty_Threshold; /*!< Specifies the internal FIFO Almost EMPTY Level.
|
||||
This parameter The value can be a value 0~0x3F*/
|
||||
|
||||
uint8_t HALFIFOFull_Threshold; /*!< Specifies the internal FIFO Half FULL Level.
|
||||
This parameter The value can be a value 0~0x3F*/
|
||||
|
||||
}struct_SPDIF_Init_t;
|
||||
|
||||
/*
|
||||
* @brief SPDIF handle Structure definition
|
||||
*/
|
||||
typedef struct __SPDIF_HandleTypeDef
|
||||
{
|
||||
struct_SPDIF_Init_t Init; /*!< SPDIF communication parameters */
|
||||
|
||||
void (*TxCallback)(struct __SPDIF_HandleTypeDef *hspdif); /*!< Callback */
|
||||
void (*RxCallback)(struct __SPDIF_HandleTypeDef *hspdif); /*!< Callback */
|
||||
|
||||
volatile bool b_TxBusy; /*!< SPDIF Receive and Send parameters in interrupt */
|
||||
volatile bool b_RxBusy;
|
||||
|
||||
volatile uint32_t *p_TxData;
|
||||
volatile uint32_t u32_TxCount;
|
||||
volatile uint32_t u32_TxSize;
|
||||
|
||||
volatile uint32_t *p_RxData;
|
||||
volatile uint32_t u32_RxCount;
|
||||
}SPDIF_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization_Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* SPDIF Enable Diable */
|
||||
#define __SPDIF_ENABLE() (SPDIF->SPDIF_CTRL.SPDIF_ENABLE = 1)
|
||||
#define __SPDIF_DISABLE() (SPDIF->SPDIF_CTRL.SPDIF_ENABLE = 0)
|
||||
|
||||
/* FIFO/TxFIFO level */
|
||||
#define __SPDIF_FIFO_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_STS = __LEVEL__)
|
||||
|
||||
/* FIFO HALFULL and ALEMPTY Threshold level */
|
||||
#define __SPDIF_FIFO_HALF_FULL_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_CTRL.HALFULL_THRESHOLD = __LEVEL__)
|
||||
#define __SPDIF_FIFO_ALMOST_EMPTY_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_CTRL.ALEMPTY_THRESHOLD = __LEVEL__)
|
||||
|
||||
/* Get Interrupt Status */
|
||||
#define __SPDIF_GET_INT_STATUS() (SPDIF->SPDIF_INT_STS)
|
||||
|
||||
/* FIFO Interrupt ALEMPTY ALFULL Enable and Disable */
|
||||
#define __SPDIF_ENABLE_ALEMPTY_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 1; \
|
||||
SPDIF->SPDIF_CTRL.ALEMPTY_MASK = 1;}while(0)
|
||||
#define __SPDIF_DISABLE_ALEMPTY_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 0; \
|
||||
SPDIF->SPDIF_CTRL.ALEMPTY_MASK = 0;}while(0)
|
||||
|
||||
#define __SPDIF_ENABLE_ALFULL_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 1; \
|
||||
SPDIF->SPDIF_CTRL.SYNCERR_MASK = 1; \
|
||||
SPDIF->SPDIF_CTRL.ALFULL_MASK = 1;}while(0)
|
||||
|
||||
#define __SPDIF_DISABLE_ALFULL_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 0; \
|
||||
SPDIF->SPDIF_CTRL.SYNCERR_MASK = 0; \
|
||||
SPDIF->SPDIF_CTRL.ALFULL_MASK = 0;}while(0)
|
||||
/* Get FIFO Interrupt Enable */
|
||||
#define __SPDIF_IS_INT_ALEMPTY() (SPDIF->SPDIF_CTRL.ALEMPTY_MASK)
|
||||
#define __SPDIF_IS_INT_ALFULL() (SPDIF->SPDIF_CTRL.ALFULL_MASK)
|
||||
#define __SPDIF_IS_INT_SYNCERR() (SPDIF->SPDIF_CTRL.SYNCERR_MASK)
|
||||
|
||||
/* TR MODE */
|
||||
#define __SPDIF_Tx_MODE() (SPDIF->SPDIF_CTRL.TR_MODE = 1)
|
||||
#define __SPDIF_Rx_MODE() (SPDIF->SPDIF_CTRL.TR_MODE = 0)
|
||||
|
||||
/* Exported functions -------------------------------------------------------------------------*/
|
||||
|
||||
void spdif_init(SPDIF_HandleTypeDef *hspdif);
|
||||
bool spdif_msg_send(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data, uint32_t fu32_Size);
|
||||
bool spdif_msg_send_IT(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data, uint32_t fu32_Size);
|
||||
bool spdif_msg_receive(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data);
|
||||
bool spdif_msg_receive_IT(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data);
|
||||
void SPDIF_IRQHandler(SPDIF_HandleTypeDef *hspdif);
|
||||
|
||||
#endif
|
||||
557
fr3092_mcu/components/drivers/peripheral/Inc/driver_spi.h
Normal file
557
fr3092_mcu/components/drivers/peripheral/Inc/driver_spi.h
Normal file
@ -0,0 +1,557 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_spi.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of SPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_SPI_H__
|
||||
#define __DRIVER_SPI_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup SPI_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Control Register 0 */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t rsv_0 : 4;
|
||||
uint32_t FRF : 2;
|
||||
uint32_t SCPH : 1;
|
||||
uint32_t SCPOL : 1;
|
||||
uint32_t TMOD : 2;
|
||||
uint32_t SLV_OE : 1;
|
||||
uint32_t rsv_1 : 1;
|
||||
uint32_t CFS : 4;
|
||||
uint32_t DFS_32 : 5;
|
||||
uint32_t SPI_FRF : 2;
|
||||
uint32_t rsv_2 : 1;
|
||||
uint32_t SSTE : 1;
|
||||
uint32_t rsv_3 : 7;
|
||||
}REG_Control0_t;
|
||||
|
||||
/* Control Register 1 */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t NDF : 16;
|
||||
uint32_t rsv_0 : 16;
|
||||
}REG_Control1_t;
|
||||
|
||||
/* Microwire Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t MWMOD : 1;
|
||||
uint32_t DMM : 1;
|
||||
uint32_t MHS : 1;
|
||||
uint32_t rsv_0 : 29;
|
||||
}REG_MWCR_t;
|
||||
|
||||
/* Status Register */
|
||||
typedef union
|
||||
{
|
||||
volatile struct
|
||||
{
|
||||
uint32_t BUSY : 1;
|
||||
uint32_t TFNF : 1;
|
||||
uint32_t TFE : 1;
|
||||
uint32_t RFNE : 1;
|
||||
uint32_t RFF : 1;
|
||||
uint32_t TXE : 1;
|
||||
uint32_t DCOL : 1;
|
||||
uint32_t rsv_0 : 25;
|
||||
}SR_BIT;
|
||||
|
||||
uint32_t SR_DWORD;
|
||||
}REG_SR_t;
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TXEIM : 1;
|
||||
uint32_t TXOIM : 1;
|
||||
uint32_t RXUIM : 1;
|
||||
uint32_t RXOIM : 1;
|
||||
uint32_t RXFIM : 1;
|
||||
uint32_t MSTIM : 1;
|
||||
uint32_t rsv_0 : 26;
|
||||
}REG_IMR_t;
|
||||
|
||||
/* Interrupt Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t TXEIS : 1;
|
||||
uint32_t TXOIS : 1;
|
||||
uint32_t RXUIS : 1;
|
||||
uint32_t RXOIS : 1;
|
||||
uint32_t RXFIS : 1;
|
||||
uint32_t MSTIS : 1;
|
||||
uint32_t rsv_0 : 26;
|
||||
}ISR_BIT;
|
||||
|
||||
uint32_t ISR_DWORD;
|
||||
}REG_ISR_t;
|
||||
|
||||
/* Raw Interrupt Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t TXEIR : 1;
|
||||
uint32_t TXOIR : 1;
|
||||
uint32_t RXUIR : 1;
|
||||
uint32_t RXOIR : 1;
|
||||
uint32_t RXFIR : 1;
|
||||
uint32_t MSTIR : 1;
|
||||
uint32_t rsv_0 : 26;
|
||||
}RISR_BIT;
|
||||
|
||||
uint32_t RISR_DWORD;
|
||||
}REG_RISR_t;
|
||||
|
||||
/* DMA Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RDMAE : 1;
|
||||
uint32_t TDMAE : 1;
|
||||
uint32_t rsv_0 : 30;
|
||||
}REG_DMACR_t;
|
||||
|
||||
/* Control Register 2 */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TRANS_TYPE : 2;
|
||||
uint32_t ADDR_L : 4;
|
||||
uint32_t rsv_0 : 2;
|
||||
uint32_t INST_L : 2;
|
||||
uint32_t DUAL_DEVICE_ACCESS : 1;
|
||||
uint32_t WAIT_CYCLES : 5;
|
||||
uint32_t DDR_EN : 1;
|
||||
uint32_t rsv_1 : 3;
|
||||
uint32_t TX_ENDIAN : 2;
|
||||
uint32_t RX_ENDIAN : 2;
|
||||
uint32_t rsv_2 : 4;
|
||||
uint32_t SPI_CLOCK_FIX : 1;
|
||||
uint32_t SPI_RX_NO_INST_ADD : 1;
|
||||
uint32_t SLV_DUAL_MODE : 1;
|
||||
uint32_t SLV_QUAD_MODE : 1;
|
||||
}REG_Control2_t;
|
||||
|
||||
/* Flow Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RX_FLOW_LR : 7;
|
||||
uint32_t rsv_0 : 1;
|
||||
uint32_t RX_FLOW_EN : 1;
|
||||
uint32_t rsv_1 : 7;
|
||||
uint32_t TX_FLOW_LR : 7;
|
||||
uint32_t rsv_2 : 1;
|
||||
uint32_t TX_FLOW_EN : 1;
|
||||
uint32_t rsv_3 : 7;
|
||||
}
|
||||
REG_Flow_Control_t;
|
||||
|
||||
/* -----------------------------------------------*/
|
||||
/* SPI Register */
|
||||
/* -----------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_Control0_t CTRL0; /* Offset 0x00 */
|
||||
volatile REG_Control1_t CTRL1; /* Offset 0x04 */
|
||||
volatile uint32_t SSI_EN; /* Offset 0x08 */
|
||||
volatile REG_MWCR_t MWCR; /* Offset 0x0C */
|
||||
volatile uint32_t SER; /* Offset 0x10 */
|
||||
volatile uint32_t BAUDR; /* Offset 0x14 */
|
||||
volatile uint32_t TXFTLR; /* Offset 0x18 */
|
||||
volatile uint32_t RXFTLR; /* Offset 0x1C */
|
||||
volatile uint32_t TXFLR; /* Offset 0x20 */
|
||||
volatile uint32_t RXFLR; /* Offset 0x24 */
|
||||
volatile REG_SR_t SR; /* Offset 0x28 */
|
||||
volatile REG_IMR_t IMR; /* Offset 0x2C */
|
||||
volatile REG_ISR_t ISR; /* Offset 0x30 */
|
||||
volatile REG_RISR_t RISR; /* Offset 0x34 */
|
||||
volatile uint32_t TXOICR; /* Offset 0x38 */
|
||||
volatile uint32_t RXOICR; /* Offset 0x3C */
|
||||
volatile uint32_t RXUICR; /* Offset 0x40 */
|
||||
volatile uint32_t MSTICR; /* Offset 0x44 */
|
||||
volatile uint32_t ICR; /* Offset 0x48 */
|
||||
volatile REG_DMACR_t DMACR; /* Offset 0x4C */
|
||||
volatile uint32_t DMATDLR; /* Offset 0x50 */
|
||||
volatile uint32_t DMARDLR; /* Offset 0x54 */
|
||||
volatile uint32_t rsv_0[2];
|
||||
volatile uint32_t DR; /* Offset 0x60 */
|
||||
volatile uint32_t rsv_1[35];
|
||||
volatile uint32_t RX_SAMPLE_DLY; /* Offset 0xF0 */
|
||||
volatile REG_Control2_t CTRL2; /* Offset 0xF4 */
|
||||
volatile uint32_t TED; /* Offset 0xF8 */
|
||||
volatile REG_Flow_Control_t FLOW_CTRL; /* Offset 0xFC */
|
||||
}struct_SPI_t;
|
||||
|
||||
#define SPIM0 ((struct_SPI_t *)SPIM0_BASE)
|
||||
#define SPIM1 ((struct_SPI_t *)SPIM1_BASE)
|
||||
#define SPIM2 ((struct_SPI_t *)SPIM2_BASE)
|
||||
|
||||
#define SPIS0 ((struct_SPI_t *)SPIS0_BASE)
|
||||
#define SPIS1 ((struct_SPI_t *)SPIS1_BASE)
|
||||
|
||||
#define SPIMX8_0 ((struct_SPI_t *)SPIMX8_0_BASE)
|
||||
#define SPIMX8_1 ((struct_SPI_t *)SPIMX8_1_BASE)
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup SPI_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/* SPI Frame Size */
|
||||
typedef enum
|
||||
{
|
||||
SPI_FRAME_SIZE_4BIT = 3,
|
||||
SPI_FRAME_SIZE_5BIT,
|
||||
SPI_FRAME_SIZE_6BIT,
|
||||
SPI_FRAME_SIZE_7BIT,
|
||||
SPI_FRAME_SIZE_8BIT,
|
||||
SPI_FRAME_SIZE_9BIT,
|
||||
SPI_FRAME_SIZE_10BIT,
|
||||
SPI_FRAME_SIZE_11BIT,
|
||||
SPI_FRAME_SIZE_12BIT,
|
||||
SPI_FRAME_SIZE_13BIT,
|
||||
SPI_FRAME_SIZE_14BIT,
|
||||
SPI_FRAME_SIZE_15BIT,
|
||||
SPI_FRAME_SIZE_16BIT,
|
||||
SPI_FRAME_SIZE_17BIT,
|
||||
SPI_FRAME_SIZE_18BIT,
|
||||
SPI_FRAME_SIZE_19BIT,
|
||||
SPI_FRAME_SIZE_20BIT,
|
||||
SPI_FRAME_SIZE_21BIT,
|
||||
SPI_FRAME_SIZE_22BIT,
|
||||
SPI_FRAME_SIZE_23BIT,
|
||||
SPI_FRAME_SIZE_24BIT,
|
||||
SPI_FRAME_SIZE_25BIT,
|
||||
SPI_FRAME_SIZE_26BIT,
|
||||
SPI_FRAME_SIZE_27BIT,
|
||||
SPI_FRAME_SIZE_28BIT,
|
||||
SPI_FRAME_SIZE_29BIT,
|
||||
SPI_FRAME_SIZE_30BIT,
|
||||
SPI_FRAME_SIZE_31BIT,
|
||||
SPI_FRAME_SIZE_32BIT,
|
||||
}enum_FrameSize_t;
|
||||
|
||||
/* work mode */
|
||||
typedef enum
|
||||
{
|
||||
SPI_WORK_MODE_0, /* Idle: Low ; sample: first edge */
|
||||
SPI_WORK_MODE_1, /* Idle: Low ; sample: second edge */
|
||||
SPI_WORK_MODE_2, /* Idle: High; sample: first edge */
|
||||
SPI_WORK_MODE_3, /* Idle: High; sample: second edge */
|
||||
}enum_Work_Mode_t;
|
||||
|
||||
/* Instruct Length */
|
||||
typedef enum
|
||||
{
|
||||
INST_0BIT, /* none Instruct */
|
||||
INST_4BIT, /* 4bit Instruct */
|
||||
INST_8BIT, /* 8bit Instruct */
|
||||
INST_16BIT, /* 16bit Instruct */
|
||||
}enum_InstructLength_t;
|
||||
|
||||
/* Address Length */
|
||||
typedef enum
|
||||
{
|
||||
ADDR_0BIT, /* none Address */
|
||||
ADDR_4BIT, /* 4bit Address */
|
||||
ADDR_8BIT, /* 8bit Address */
|
||||
ADDR_12BIT, /* 12bit Address */
|
||||
ADDR_16BIT, /* 16bit Address */
|
||||
ADDR_20BIT, /* 20bit Address */
|
||||
ADDR_24BIT, /* 24bit Address */
|
||||
ADDR_28BIT, /* 28bit Address */
|
||||
ADDR_32BIT, /* 32bit Address */
|
||||
}enum_AddressLength_t;
|
||||
|
||||
/* Transfer Type */
|
||||
typedef enum
|
||||
{
|
||||
INST_ADDR_X1, /* Instruct and Address use X1 mode */
|
||||
INST_1X_ADDR_XX, /* Instruct usb 1X mode, Address use X2/X4 mode */
|
||||
INST_ADDR_XX, /* Instruct and Address use X2/X4 mode */
|
||||
}enum_TransferType_t;
|
||||
|
||||
/* 2X2/3X Select */
|
||||
typedef enum
|
||||
{
|
||||
Wire_X2 = 1, /* X2 mode */
|
||||
Wire_X4, /* X4 mode */
|
||||
Wire_X8, /* X8 mode */
|
||||
}enum_Wire_X2X4_t;
|
||||
|
||||
/* Wire type */
|
||||
typedef enum
|
||||
{
|
||||
Wire_Read, /* Wire_Reade */
|
||||
Wire_Write, /* Wire_Write */
|
||||
}enum_Wire_Type_t;
|
||||
|
||||
/* TX-RX endian */
|
||||
typedef enum{
|
||||
TX_RX_Endian_4321, /* keep origin trans sequence */
|
||||
TX_RX_Endian_2143, /* TX: MCU writes 0x12345678 to DR, then SPI-core shifts the data as 0x56781234 */
|
||||
/* RX: input from SPI-bus is 0x12-0x34-0x56-0x78, MCU reads from DR is:
|
||||
32-bits frame size: 0x56781234
|
||||
16-bits frame size: 0x12340000, 0x56780000
|
||||
8-bits frame size: 0x00120000, 0x00340000, 0x00560000, 0x00780000 */
|
||||
TX_RX_Endian_1234, /* TX: MCU writes 0x12345678 to DR, then SPI-core shifts the data as 0x78563412 */
|
||||
/* RX: input from SPI-bus is 0x12-0x34-0x56-0x78, MCU reads from DR is:
|
||||
32-bits frame size: 0x78563412
|
||||
16-bits frame size: 0x34120000, 0x78560000
|
||||
8-bits frame size: 0x12000000, 0x34000000, 0x56000000, 0x78000000 */
|
||||
} enum_TX_RX_Endian_t;
|
||||
|
||||
/*
|
||||
* @brief SPI Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Work_Mode; /* This parameter can be a value of @ref SPI_WORK_MODE */
|
||||
|
||||
uint32_t Frame_Size; /* This parameter can be a value of @ref enum_FrameSize_t */
|
||||
|
||||
uint32_t BaudRate_Prescaler; /* This parameter can be a value 2 ~ 65534 */
|
||||
|
||||
uint32_t TxFIFOEmpty_Threshold; /* This parameter can be a value 0 ~ 64 */
|
||||
|
||||
uint32_t RxFIFOFull_Threshold; /* This parameter can be a value 0 ~ 64 */
|
||||
}struct_SPIInit_t;
|
||||
|
||||
/*
|
||||
* @brief SPI Multiple wire transfer parameter
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Wire_X2X4X8; /* This parameter can be a value of @ref enum_Wire_X2X4_t */
|
||||
|
||||
uint32_t ReceiveWaitCycles; /* This parameter can be a 5bit value */
|
||||
|
||||
uint32_t InstructLength; /* This parameter can be a value of @ref enum_InstructLength_t */
|
||||
uint16_t Instruct; /* This parameter can be a 16bit value */
|
||||
|
||||
uint32_t AddressLength; /* This parameter can be a value of @ref enum_AddressLength_t */
|
||||
uint32_t Address; /* This parameter can be a 32bit value */
|
||||
|
||||
uint32_t TransferType; /* This parameter can be a value of @ref enum_TransferType_t */
|
||||
|
||||
}struct_MultipleWire_t;
|
||||
|
||||
/*
|
||||
* @brief SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __SPI_HandleTypeDef
|
||||
{
|
||||
struct_SPI_t *SPIx; /*!< SPI registers base address */
|
||||
|
||||
struct_SPIInit_t Init; /*!< SPI communication parameters */
|
||||
|
||||
struct_MultipleWire_t MultWireParam; /*!< SPI Multiple wire transfer parameter */
|
||||
/*!< Used for multi-line transmission */
|
||||
|
||||
void (*TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< Tx complete Callback */
|
||||
void (*RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< Rx complete Callback */
|
||||
|
||||
volatile uint32_t u32_TxSize; /*!< SPI Transmit parameters in interrupt */
|
||||
volatile uint32_t u32_TxCount;
|
||||
union {
|
||||
volatile void *p_data;
|
||||
volatile uint8_t *p_u8;
|
||||
volatile uint16_t *p_u16;
|
||||
volatile uint32_t *p_u32;
|
||||
} u_TxData;
|
||||
volatile bool b_TxBusy;
|
||||
|
||||
volatile uint32_t u32_RxSize; /*!< SPI Receive parameters in interrupt */
|
||||
volatile uint32_t u32_RxCount;
|
||||
union {
|
||||
volatile void *p_data;
|
||||
volatile uint8_t *p_u8;
|
||||
volatile uint16_t *p_u16;
|
||||
volatile uint32_t *p_u32;
|
||||
} u_RxData;
|
||||
volatile bool b_RxBusy;
|
||||
}SPI_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* SPI DDR Enable/Disable/Div */
|
||||
#define __SPI_DDR_ENABLE(__SPIx__) (__SPIx__->CTRL2.DDR_EN = 1)
|
||||
#define __SPI_DDR_DISABLE(__SPIx__) (__SPIx__->CTRL2.DDR_EN = 0)
|
||||
|
||||
#define __SPI_DDR_DRIVE_DIV(__SPIx__, __DIV__) (__SPIx__->TED = __DIV__)
|
||||
|
||||
|
||||
/* SPI Enable/Disable */
|
||||
#define __SPI_ENABLE(__SPIx__) (__SPIx__->SSI_EN = 1)
|
||||
#define __SPI_DISABLE(__SPIx__) (__SPIx__->SSI_EN = 0)
|
||||
|
||||
/* SPI Enable/Disable */
|
||||
#define __SPI_CS_SET(__SPIx__) (__SPIx__->SER = 1)
|
||||
#define __SPI_CS_RELEASE(__SPIx__) (__SPIx__->SER = 0)
|
||||
|
||||
/* Master Standard<72><64>Dual<61><6C>Quad<61><64>Octal mode */
|
||||
#define __SPI_SET_MODE_X1(__SPIx__) (__SPIx__->CTRL0.SPI_FRF = 0)
|
||||
#define __SPI_SET_MODE_X2(__SPIx__) (__SPIx__->CTRL0.SPI_FRF = 1)
|
||||
#define __SPI_SET_MODE_X4(__SPIx__) (__SPIx__->CTRL0.SPI_FRF = 2)
|
||||
#define __SPI_SET_MODE_X8(__SPIx__) (__SPIx__->CTRL0.SPI_FRF = 3)
|
||||
#define __SPI_SET_MODE_X2X4X8(__SPIx__, __WIDTH__) (__SPIx__->CTRL0.SPI_FRF = __WIDTH__)
|
||||
|
||||
/* Slave Standard<72><64>Dual<61><6C>Quad<61><64>Octal mode */
|
||||
#define __SPI_SLAVE_SET_MODE_X1(__SPIx__) do{ __SPIx__->CTRL2.SLV_DUAL_MODE = 0; \
|
||||
__SPIx__->CTRL2.SLV_QUAD_MODE = 0;}while(0)
|
||||
#define __SPI_SLAVE_SET_MODE_X2(__SPIx__) do{ __SPIx__->CTRL2.SLV_DUAL_MODE = 1; \
|
||||
__SPIx__->CTRL2.SLV_QUAD_MODE = 0;}while(0)
|
||||
#define __SPI_SLAVE_SET_MODE_X4(__SPIx__) do{ __SPIx__->CTRL2.SLV_DUAL_MODE = 0; \
|
||||
__SPIx__->CTRL2.SLV_QUAD_MODE = 1;}while(0)
|
||||
/* SPI Slave output Enable */
|
||||
#define __SPI_SLAVE_OUTPUT_ENABLE(__SPIx__) (__SPIx__->CTRL0.SLV_OE = 1)
|
||||
#define __SPI_SLAVE_OUTPUT_DISABLE(__SPIx__) (__SPIx__->CTRL0.SLV_OE = 0)
|
||||
|
||||
/* Transfer mode */
|
||||
#define __SPI_TMODE_RxTx(__SPIx__) (__SPIx__->CTRL0.TMOD = 0)
|
||||
#define __SPI_TMODE_Tx_ONLY(__SPIx__) (__SPIx__->CTRL0.TMOD = 1)
|
||||
#define __SPI_TMODE_Rx_ONLY(__SPIx__) (__SPIx__->CTRL0.TMOD = 2)
|
||||
#define __SPI_TMODE_FLASH_READ(__SPIx__) (__SPIx__->CTRL0.TMOD = 3)
|
||||
|
||||
/* Data Frame Size */
|
||||
#define __SPI_DATA_FRAME_SIZE(__SPIx__, __SIZE__) (__SPIx__->CTRL0.DFS_32 = __SIZE__)
|
||||
#define __SPI_DATA_FRAME_SIZE_GET(__SPIx__) (__SPIx__->CTRL0.DFS_32)
|
||||
|
||||
/* Receive data size */
|
||||
#define __SPI_RECEIVE_SIZE(__SPIx__, __SIZE__) (__SPIx__->CTRL1.NDF = __SIZE__)
|
||||
|
||||
/* RxFIFO_FULL_THRESHOLD */
|
||||
/* TxFIFO_EMPTY_THRESHOLD */
|
||||
#define __SPI_RxFIFO_FULL_THRESHOLD(__SPIx__, __THRESHOLD__) (__SPIx__->RXFTLR = __THRESHOLD__)
|
||||
#define __SPI_TxFIFO_EMPTY_THRESHOLD(__SPIx__, __THRESHOLD__) (__SPIx__->TXFTLR = __THRESHOLD__)
|
||||
|
||||
/* Get Rx/Tx FIFO current level */
|
||||
#define __SPI_GET_RxFIFO_LEVEL(__SPIx__) (__SPIx__->RXFLR)
|
||||
#define __SPI_GET_TxFIFO_LEVEL(__SPIx__) (__SPIx__->TXFLR)
|
||||
|
||||
/* DMA Enable/Disable, level */
|
||||
#define __SPI_DMA_RX_ENABLE(__SPIx__) (__SPIx__->DMACR.RDMAE = 1)
|
||||
#define __SPI_DMA_TX_ENABLE(__SPIx__) (__SPIx__->DMACR.TDMAE = 1)
|
||||
#define __SPI_DMA_RX_DISABLE(__SPIx__) (__SPIx__->DMACR.RDMAE = 0)
|
||||
#define __SPI_DMA_TX_DISABLE(__SPIx__) (__SPIx__->DMACR.TDMAE = 0)
|
||||
#define __SPI_DMA_RX_LEVEL(__SPIx__, __LEVEL__) (__SPIx__->DMARDLR = __LEVEL__)
|
||||
#define __SPI_DMA_TX_LEVEL(__SPIx__, __LEVEL__) (__SPIx__->DMATDLR = __LEVEL__)
|
||||
|
||||
/* SPI busy status */
|
||||
#define __SPI_IS_BUSY(__SPIx__) (__SPIx__->SR.SR_BIT.BUSY)
|
||||
|
||||
/* Tx/Rx FIFO status */
|
||||
#define __SPI_IS_RxFIFO_EMPTY(__SPIx__) (__SPIx__->SR.SR_BIT.RFNE == 0)
|
||||
#define __SPI_IS_RxFIFO_NOT_EMPTY(__SPIx__) (__SPIx__->SR.SR_BIT.RFNE == 1)
|
||||
#define __SPI_IS_RxFIFO_FULL(__SPIx__) (__SPIx__->SR.SR_BIT.RFF == 1)
|
||||
#define __SPI_IS_TxFIFO_EMPTY(__SPIx__) (__SPIx__->SR.SR_BIT.TFE == 1)
|
||||
#define __SPI_IS_TxFIFO_FULL(__SPIx__) (__SPIx__->SR.SR_BIT.TFNF == 0)
|
||||
|
||||
/* Tx/Rx FIFO interrupt */
|
||||
#define __SPI_TxFIFO_EMPTY_INT_ENABLE(__SPIx__) (__SPIx__->IMR.TXEIM = 1)
|
||||
#define __SPI_RxFIFO_FULL_INT_ENABLE(__SPIx__) (__SPIx__->IMR.RXFIM = 1)
|
||||
|
||||
#define __SPI_TxFIFO_EMPTY_INT_DISABLE(__SPIx__) (__SPIx__->IMR.TXEIM = 0)
|
||||
#define __SPI_RxFIFO_FULL_INT_DISABLE(__SPIx__) (__SPIx__->IMR.RXFIM = 0)
|
||||
|
||||
#define __SPI_TxFIFO_EMPTY_INT_STATUS(__SPIx__) (__SPIx__->ISR.ISR_BIT.TXEIS)
|
||||
#define __SPI_RxFIFO_FULL_INT_STATUS(__SPIx__) (__SPIx__->ISR.ISR_BIT.RXFIS)
|
||||
|
||||
/* __SPI_RX_SAMPLE_DLY */
|
||||
#define __SPI_RX_SAMPLE_DLY(__SPIx__, __DELAY__) (__SPIx__->RX_SAMPLE_DLY = __DELAY__)
|
||||
|
||||
/* SPI Master CS Toggle Enable */
|
||||
#define __SPI_CS_TOGGLE_ENABLE(__SPIx__) (__SPIx__->CTRL0.SSTE = 1)
|
||||
#define __SPI_CS_TOGGLE_DISABLE(__SPIx__) (__SPIx__->CTRL0.SSTE = 0)
|
||||
|
||||
/* SPI TX endian setting */
|
||||
#define __SPI_TX_ENDIAN_SET(__SPIx__, v) (__SPIx__->CTRL2.TX_ENDIAN = v)
|
||||
/* SPI RX endian setting */
|
||||
#define __SPI_RX_ENDIAN_SET(__SPIx__, v) (__SPIx__->CTRL2.RX_ENDIAN = v)
|
||||
|
||||
/*-----------------------------------------------------------------------------------*/
|
||||
/* Master Exported functions --------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------------------------------*/
|
||||
|
||||
/* spi_IRQHandler */
|
||||
void spi_master_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* spi_master_init */
|
||||
void spi_master_init(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* Master Standard mode Transmit/Receive */
|
||||
/* blocking<6E><67>Interrupt<70><74>DMA mode */
|
||||
void spi_master_transmit_X1(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_master_transmit_X1_IT(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_master_transmit_X1_DMA(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void spi_master_receive_X1(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
|
||||
void spi_master_readflash_X1(SPI_HandleTypeDef *hspi, uint16_t *fp_CMD_ADDR, uint32_t fu32_CMDLegnth, uint8_t *fp_Data, uint16_t fu16_Size);
|
||||
void spi_master_readflash_X1_IT(SPI_HandleTypeDef *hspi, uint8_t *fp_CMD_ADDR, uint32_t fu32_CMDLegnth, uint8_t *fp_Data, uint16_t fu16_Size);
|
||||
void spi_master_readflash_X1_DMA(SPI_HandleTypeDef *hspi, uint8_t *fp_CMD_ADDR, uint32_t fu32_CMDLegnth, uint16_t fu16_Size);
|
||||
|
||||
/* Master Dual<61><6C>Quad mode Transmit/Receive */
|
||||
/* blocking<6E><67>Interrupt<70><74>DMA mode */
|
||||
void spi_master_transmit_X2X4X8(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_master_transmit_X2X4X8_IT(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_master_transmit_X2X4X8_DMA(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void spi_master_receive_X2X4X8(SPI_HandleTypeDef *hspi, void *fp_Data, uint16_t fu16_Size);
|
||||
void spi_master_receive_X2X4X8_IT(SPI_HandleTypeDef *hspi, void *fp_Data, uint16_t fu16_Size);
|
||||
void spi_master_receive_X2X4X8_DMA(SPI_HandleTypeDef *hspi, uint16_t fu16_Size);
|
||||
|
||||
/* spi_master_MultWireConfig */
|
||||
/* spi_slave_MultWireConfig */
|
||||
void spi_master_MultWireConfig(SPI_HandleTypeDef *hspi, enum_Wire_Type_t fe_type);
|
||||
void spi_slave_MultWireConfig(SPI_HandleTypeDef *hspi, enum_Wire_Type_t fe_type);
|
||||
|
||||
/*-----------------------------------------------------------------------------------*/
|
||||
/* Slave Exported functions ---------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------------------------------*/
|
||||
|
||||
/* spi_slave_IRQHandler */
|
||||
void spi_slave_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* spi_slave_init */
|
||||
void spi_slave_init(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* Slave Standard mode Transmit/Receive */
|
||||
/* blocking<6E><67>Interrupt<70><74>DMA mode */
|
||||
void spi_slave_transmit(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_slave_transmit_IT(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_slave_transmit_DMA(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void spi_slave_receive(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_slave_receive_IT(SPI_HandleTypeDef *hspi, void *fp_Data, uint32_t fu32_Size);
|
||||
void spi_slave_receive_DMA(SPI_HandleTypeDef *hspi);
|
||||
|
||||
#endif
|
||||
118
fr3092_mcu/components/drivers/peripheral/Inc/driver_tick.h
Normal file
118
fr3092_mcu/components/drivers/peripheral/Inc/driver_tick.h
Normal file
@ -0,0 +1,118 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_tick.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of System Tick HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_TICK_H__
|
||||
#define __DRIVER_TICK_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup Tick_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Tick Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SMP : 1;
|
||||
uint32_t UPD : 1;
|
||||
uint32_t CMP_EN : 1;
|
||||
uint32_t RST : 1;
|
||||
uint32_t rsv_0 : 28;
|
||||
}REG_TickControl_t;
|
||||
|
||||
/* Tick Sleep Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SLP_ON : 1;
|
||||
uint32_t SLP_CORR_EN : 1;
|
||||
uint32_t DELTA : 1;
|
||||
uint32_t rsv_0 : 29;
|
||||
}REG_TickSleepControl_t;
|
||||
|
||||
/* Tick Interrupt Register */
|
||||
typedef union
|
||||
{
|
||||
uint32_t Word;
|
||||
struct {
|
||||
uint32_t SLP : 1;
|
||||
uint32_t TGT : 1;
|
||||
uint32_t rsv_0 : 30;
|
||||
}Bits;
|
||||
}REG_TickInt_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile REG_TickControl_t CTL; /* Offset 0x00 */
|
||||
volatile REG_TickSleepControl_t SLP_CTL; /* Offset 0x04 */
|
||||
volatile uint32_t CLK_SMP; /* Offset 0x08 */
|
||||
volatile uint32_t FINE_SMP; /* Offset 0x0C */
|
||||
volatile uint32_t CLK_CORR; /* Offset 0x10 */
|
||||
volatile uint32_t FINE_CORR; /* Offset 0x14 */
|
||||
volatile uint32_t CLK_TGT; /* Offset 0x18 */
|
||||
volatile uint32_t FINE_TGT; /* Offset 0x1C */
|
||||
volatile uint32_t CLK_UPD; /* Offset 0x20 */
|
||||
volatile REG_TickInt_t INT_CTL; /* Offset 0x24 */
|
||||
volatile REG_TickInt_t INT_STA; /* Offset 0x28 */
|
||||
volatile REG_TickInt_t INT_RAW; /* Offset 0x2C */
|
||||
}struct_Tick_t;
|
||||
|
||||
#define Tick ((struct_Tick_t *)(SYSTEM_TIMER_BASE))
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Tick_Initialization_Config_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Initialization<6F><6E>Config Section Start ################################ */
|
||||
|
||||
/* Tick Interrupt Type */
|
||||
typedef enum
|
||||
{
|
||||
TICK_INT_TYPE_SLP = (1<<0),
|
||||
TICK_INT_TYPE_TGT = (1<<1),
|
||||
}enum_TickIntType_t;
|
||||
|
||||
/*
|
||||
* @brief Tick handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*TickTargetCallback)(void); /*!< Tick reach target Callback */
|
||||
void (*TickSleepCallback)(void); /*!< wake up frome sleep Callback */
|
||||
}TICK_HandleTypeDef;
|
||||
|
||||
/* ################################ Initialization<6F><6E>Config Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#define TICK_FINE_VALUE_MAX (1000)
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void tick_IRQHandler(TICK_HandleTypeDef *handle);
|
||||
|
||||
void tick_init(TICK_HandleTypeDef *handle);
|
||||
|
||||
void tick_get(uint32_t *clk, uint32_t *fine);
|
||||
void tick_set_target(uint32_t clk, uint32_t fine);
|
||||
void tick_set_target_IT(uint32_t clk, uint32_t fine);
|
||||
void tick_start_corr(uint32_t clk, uint32_t fine);
|
||||
|
||||
#endif
|
||||
79
fr3092_mcu/components/drivers/peripheral/Inc/driver_timer.h
Normal file
79
fr3092_mcu/components/drivers/peripheral/Inc/driver_timer.h
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
* @file driver_timer.h
|
||||
* @author FreqChip Firmware Team
|
||||
* @version V1.0.0
|
||||
* @date 2021
|
||||
* @brief Header file of TImer HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 FreqChip.
|
||||
* All rights reserved.
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __DRIVER_TIMER_H__
|
||||
#define __DRIVER_TIMER_H__
|
||||
|
||||
#include "fr30xx.h"
|
||||
|
||||
/** @addtogroup Timer_Registers_Section
|
||||
* @{
|
||||
*/
|
||||
/* ################################ Register Section Start ################################ */
|
||||
|
||||
/* Timer Control Register */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ENABLE : 1;
|
||||
uint32_t MODE : 1;
|
||||
uint32_t INT_MASK : 1;
|
||||
uint32_t rsv_0 : 29;
|
||||
}REG_Control_t;
|
||||
|
||||
|
||||
/* -------------------------------------------------*/
|
||||
/* Timer Register */
|
||||
/* -------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t LoadCount; /* Offset 0x00 */
|
||||
volatile uint32_t CurrentValue; /* Offset 0x04 */
|
||||
volatile REG_Control_t Control; /* Offset 0x08 */
|
||||
volatile uint32_t IntClear; /* Offset 0x0C */
|
||||
volatile uint32_t IntStatus; /* Offset 0x10 */
|
||||
}struct_Timer_t;
|
||||
|
||||
#define Timer0 ((struct_Timer_t *)(TIM0_BASE))
|
||||
#define Timer1 ((struct_Timer_t *)(TIM1_BASE))
|
||||
#define Timer2 ((struct_Timer_t *)(TIM2_BASE))
|
||||
#define Timer3 ((struct_Timer_t *)(TIM3_BASE))
|
||||
|
||||
/* ################################ Register Section END ################################## */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* timer_init */
|
||||
void timer_init(struct_Timer_t *TIMERx, uint32_t fu32_LoadCount);
|
||||
|
||||
/* timer_int_enable */
|
||||
/* timer_int_disable */
|
||||
/* timer_int_clear */
|
||||
/* timer_int_status */
|
||||
void timer_int_enable(struct_Timer_t *TIMERx);
|
||||
void timer_int_disable(struct_Timer_t *TIMERx);
|
||||
void timer_int_clear(struct_Timer_t *TIMERx);
|
||||
bool timer_int_status(struct_Timer_t *TIMERx);
|
||||
|
||||
/* timer_start */
|
||||
/* timer_stop */
|
||||
void timer_start(struct_Timer_t *TIMERx);
|
||||
void timer_stop(struct_Timer_t *TIMERx);
|
||||
|
||||
/* timer_get_CurrentCount */
|
||||
uint32_t timer_get_CurrentCount(struct_Timer_t *TIMERx);
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user