116 lines
3.9 KiB
C
116 lines
3.9 KiB
C
/*
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******************************************************************************
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* @file driver_sha.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2022
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* @brief Header file of sha module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_SHA_H__
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#define __DRIVER_SHA_H__
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#include "fr30xx.h"
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/** @addtogroup SHA_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/*SHA CTRL REG 0x00*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t MODE : 3;//001->SHA-1;010->SHA-256;011->SHA-224;100->SHA-512;101->SHA-384;110->SHA-512/256;111->SHA-512/224
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uint32_t INIT_EN : 1;//set this bit to encode thhe messgae with the initial value of A-H(A-E when mask= 010)
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uint32_t ISR_EN : 1;//interrupt enable
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uint32_t ENDIAN_MODE : 1;//message endian mode 0->big endian 1->little endian
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uint32_t CALCULATE : 1;//cpu write this bit to enable calculate.read this bit to verify whether the encoding is complete
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uint32_t RSV : 25;
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} Bits;
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} REG_SHA_CTRL_t;
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/*SHA INT STATE REG 0x04*/
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typedef volatile union
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{
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volatile uint32_t Word;
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struct
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{
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uint32_t INT_DONE : 1;//this bit is set by SHA finishing encoding the message and writing the digest to the base address
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uint32_t INT_ERROR : 1;//this bit is set by SHA select error mode
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uint32_t RSV : 30;
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} Bits;
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} REG_SHA_INT_STATE_t;
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/* ----------------------------------------------*/
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/* SHA Registers */
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/* ----------------------------------------------*/
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typedef struct
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{
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volatile REG_SHA_CTRL_t SHA_CTRL; /* Offset 0x00 */
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volatile REG_SHA_INT_STATE_t SHA_INT_STATE; /* Offset 0x04 */
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volatile uint32_t HASH_VAL_L[8]; /* Offset 0x08 - 0x24*/
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volatile uint32_t HASH_VAL_H[8]; /* Offset 0x28 - 0x44*/
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volatile uint32_t DATA_1[16]; /* Offset 0x48 -0x84 */
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volatile uint32_t DATA_2[16]; /* Offset 0x88-0xb4*/
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}struct_SEC_SHA_t;
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#define SEC_SHA_OFFSET 0x1000
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#define SEC_SHA ((struct_SEC_SHA_t *)(SEC_BASE + SEC_SHA_OFFSET))
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/* ################################ Register Section END ################################ */
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/**
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* @}
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*/
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/** @addtogroup ADC_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization, Config Section Start ################################ */
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typedef enum{
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SHA_1 = 1,
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SHA_256 = 2,
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SHA_224 = 3,
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SHA_512 = 4,
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SHA_384 = 5,
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SHA_512_OR_256 = 6,
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SHA_512_OR_224 = 7
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}enum_sha_mode_t;
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typedef enum{
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SHA_BIG_ENDIAN = 0,
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SHA_LITTLE_ENDIAN = 1
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}enum_sha_endian_t;
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#define SHA_256_BLOCK_SIZE (64)
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#define SHA_512_BLOCK_SIZE (128)
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/* ################################ Initialization, Config Section END ################################ */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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#define __SHA_GET_INT_DONE_FALG() (SEC_SHA->SHA_INT_STATE.Bits.INT_DONE)
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#define __SHA_INT_ERROR() (SEC_SHA->SHA_INT_STATE.Bits.INT_ERROR == 1)
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/* Exported functions --------------------------------------------------------*/
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/* sha init */
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void sha_init(uint8_t Mode);
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/* sha updata */
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void sha_update(uint8_t *fp8_Data, uint32_t fu32_Size);
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/* sha_final */
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void sha_final(uint8_t *DataOut);
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#endif
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