800*320工程文件+初始demo提交
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236
SW/components/drivers/peripheral/Inc/driver_spdif.h
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236
SW/components/drivers/peripheral/Inc/driver_spdif.h
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/*
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******************************************************************************
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* @file driver_spdif.h
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* @author FreqChip Firmware Team
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* @version V1.0.0
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* @date 2023
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* @brief Header file of SPDIF module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 FreqChip.
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* All rights reserved.
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******************************************************************************
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*/
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#ifndef __DRIVER_SPDIF_H__
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#define __DRIVER_SPDIF_H__
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#include "fr30xx.h"
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/** @addtogroup SPDIF_Registers_Section
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* @{
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*/
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/* ################################ Register Section Start ################################ */
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/* SPDIF CTRL REG */
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typedef struct
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{
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uint32_t TSAMPLERATE : 8;
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uint32_t SFR_ENABLE : 1;
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uint32_t SPDIF_ENABLE : 1;
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uint32_t FIFO_ENABLE : 1;
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uint32_t CLK_ENABLE : 1;
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uint32_t TR_MODE : 1;
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uint32_t PARITY_CHECK : 1;
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uint32_t PARITYGEN : 1;
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uint32_t VALIDITY_CHECK : 1;
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uint32_t CHANNEL_MODE : 1;
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uint32_t DUPLICATE : 1;
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uint32_t SETPREAMBB : 1;
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uint32_t rsv_0 : 2;
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uint32_t PARITY_MASK : 1;
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uint32_t UNDERR_MASK : 1;
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uint32_t OVERR_MASK : 1;
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uint32_t EMPTY_MASK : 1;
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uint32_t ALEMPTY_MASK : 1;
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uint32_t FULL_MASK : 1;
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uint32_t ALFULL_MASK : 1;
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uint32_t SYNCERR_MASK : 1;
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uint32_t LOCK_MASK : 1;
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uint32_t BEGIN_MASK : 1;
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uint32_t INTREQ_MASK : 1;
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} REG_SPDIF_CTRL_t;
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/* SPDIF INT REG */
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typedef struct
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{
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uint32_t RSAMPLERATE : 8;
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uint32_t PREAMBLEDEL : 4;
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uint32_t rsv_0 : 9;
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uint32_t PARITYO : 1;
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uint32_t TDATA_UNDERR : 1;
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uint32_t RDATA_OVERR : 1;
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uint32_t FIFO_EMPTY : 1;
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uint32_t FIFO_ALEMPTY : 1;
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uint32_t FIFO_FULL : 1;
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uint32_t FIFO_ALFULL : 1;
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uint32_t SYNC_ERR : 1;
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uint32_t LOCK : 1;
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uint32_t BLOCK_BEGIN : 1;
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uint32_t rsv_1 : 1;
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} REG_SPDIF_INT_t;
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/* SPDIF FIFO CTRL REG */
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typedef struct
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{
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uint32_t ALEMPTY_THRESHOLD : 7;
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uint32_t rsv_0 : 1;
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uint32_t HALFULL_THRESHOLD : 7;
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uint32_t rsv_1 : 1;
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uint32_t PARITY_INT_TYPE : 1;
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uint32_t UNDERR_INT_TYPE : 1;
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uint32_t OVERR_INT_TYPE : 1;
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uint32_t FF_EMPTY_INT_TYPE : 1;
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uint32_t FF_ALEMPTY_INT_TYPE : 1;
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uint32_t FF_FULL_INT_TYPE : 1;
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uint32_t FF_ALFULL_INT_TYPE : 1;
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uint32_t SYNCERR_INT_TYPE : 1;
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uint32_t LOCK_INT_TYPE : 1;
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uint32_t BLOCK_BEGIN_INT_TYPE : 1;
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uint32_t rsv_2 : 6;
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} REG_SPDIF_FIFO_CTRL_t;
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typedef struct
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{
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volatile REG_SPDIF_CTRL_t SPDIF_CTRL; /* Offset 0x00 */
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volatile uint32_t SPDIF_INT_CLEAR; /* Offset 0x04 */
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volatile REG_SPDIF_FIFO_CTRL_t SPDIF_FIFO_CTRL; /* Offset 0x08 */
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volatile uint32_t SPDIF_INT_STS; /* Offset 0x0C */
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volatile uint32_t SPDIF_FIFO_DATA; /* Offset 0x10 */
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}struct_SPDIF_t;
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#define SPDIF ((struct_SPDIF_t *)SPDIF_BASE)
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/* ################################ Register Section END ################################## */
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/**
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* @}
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*/
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/** @addtogroup SPDIF_Initialization_Config_Section
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* @{
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*/
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/* ################################ Initialization_Config Section Start ################################ */
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/* Interrupt Status */
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typedef enum
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{
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PARITY_FLAG = 0x200000,
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UNDERR_FLAG = 0x400000,
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OVERR_FLAG = 0x800000,
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EMPTY_FLAG = 0x1000000,
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ALEMPTY_FLAG = 0x2000000,
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FULL_FLAG = 0x4000000,
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ALFULL_FLAG = 0x8000000,
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SYNCERR_FLAG = 0x10000000,
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LOCK_FLAG = 0x20000000,
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BEGIN_FLAG = 0x40000000,
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RIGHT_LEFT = 0x80000000,
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}enum_SPDIF_INT_Index_t;
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/* MonoStere Select */
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typedef enum
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{
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SPDIF_STEREO,
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SPDIF_MONO,
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}enum_SPDIF_MonoStere_Sel_t;
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/*
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* @brief SPDIF Init Structure definition
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*/
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typedef struct
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{
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uint8_t TxSampleRate; /*!< Specifies the internal Send sample rate.
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This parameter The value can be a value 0~0x7F*/
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uint8_t CH_Mode; /*!< Specifies the internal Channel selection.
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This parameter can be a value of @ref enum_SPDIF_MonoStere_Sel_t*/
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uint8_t RSAMPLERATE; /*!< Specifies the internal Send receive rate.
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This parameter The value can be a value 0~0x7F*/
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uint8_t PREAMBLEDEL; /*!< Specifies the internal Leader B delay.
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This parameter The value can be a value 0~0xF*/
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uint8_t ALFIFOEmpty_Threshold; /*!< Specifies the internal FIFO Almost EMPTY Level.
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This parameter The value can be a value 0~0x3F*/
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uint8_t HALFIFOFull_Threshold; /*!< Specifies the internal FIFO Half FULL Level.
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This parameter The value can be a value 0~0x3F*/
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}struct_SPDIF_Init_t;
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/*
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* @brief SPDIF handle Structure definition
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*/
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typedef struct __SPDIF_HandleTypeDef
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{
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struct_SPDIF_Init_t Init; /*!< SPDIF communication parameters */
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void (*TxCallback)(struct __SPDIF_HandleTypeDef *hspdif); /*!< Callback */
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void (*RxCallback)(struct __SPDIF_HandleTypeDef *hspdif); /*!< Callback */
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volatile bool b_TxBusy; /*!< SPDIF Receive and Send parameters in interrupt */
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volatile bool b_RxBusy;
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volatile uint32_t *p_TxData;
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volatile uint32_t u32_TxCount;
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volatile uint32_t u32_TxSize;
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volatile uint32_t *p_RxData;
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volatile uint32_t u32_RxCount;
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}SPDIF_HandleTypeDef;
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/* ################################ Initialization_Config Section END ################################## */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* SPDIF Enable Diable */
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#define __SPDIF_ENABLE() (SPDIF->SPDIF_CTRL.SPDIF_ENABLE = 1)
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#define __SPDIF_DISABLE() (SPDIF->SPDIF_CTRL.SPDIF_ENABLE = 0)
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/* FIFO/TxFIFO level */
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#define __SPDIF_FIFO_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_STS = __LEVEL__)
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/* FIFO HALFULL and ALEMPTY Threshold level */
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#define __SPDIF_FIFO_HALF_FULL_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_CTRL.HALFULL_THRESHOLD = __LEVEL__)
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#define __SPDIF_FIFO_ALMOST_EMPTY_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_CTRL.ALEMPTY_THRESHOLD = __LEVEL__)
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/* Get Interrupt Status */
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#define __SPDIF_GET_INT_STATUS() (SPDIF->SPDIF_INT_STS)
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/* FIFO Interrupt ALEMPTY ALFULL Enable and Disable */
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#define __SPDIF_ENABLE_ALEMPTY_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 1; \
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SPDIF->SPDIF_CTRL.ALEMPTY_MASK = 1;}while(0)
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#define __SPDIF_DISABLE_ALEMPTY_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 0; \
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SPDIF->SPDIF_CTRL.ALEMPTY_MASK = 0;}while(0)
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#define __SPDIF_ENABLE_ALFULL_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 1; \
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SPDIF->SPDIF_CTRL.SYNCERR_MASK = 1; \
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SPDIF->SPDIF_CTRL.ALFULL_MASK = 1;}while(0)
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#define __SPDIF_DISABLE_ALFULL_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 0; \
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SPDIF->SPDIF_CTRL.SYNCERR_MASK = 0; \
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SPDIF->SPDIF_CTRL.ALFULL_MASK = 0;}while(0)
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/* Get FIFO Interrupt Enable */
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#define __SPDIF_IS_INT_ALEMPTY() (SPDIF->SPDIF_CTRL.ALEMPTY_MASK)
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#define __SPDIF_IS_INT_ALFULL() (SPDIF->SPDIF_CTRL.ALFULL_MASK)
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#define __SPDIF_IS_INT_SYNCERR() (SPDIF->SPDIF_CTRL.SYNCERR_MASK)
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/* TR MODE */
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#define __SPDIF_Tx_MODE() (SPDIF->SPDIF_CTRL.TR_MODE = 1)
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#define __SPDIF_Rx_MODE() (SPDIF->SPDIF_CTRL.TR_MODE = 0)
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/* Exported functions -------------------------------------------------------------------------*/
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void spdif_init(SPDIF_HandleTypeDef *hspdif);
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bool spdif_msg_send(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data, uint32_t fu32_Size);
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bool spdif_msg_send_IT(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data, uint32_t fu32_Size);
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bool spdif_msg_receive(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data);
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bool spdif_msg_receive_IT(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data);
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void SPDIF_IRQHandler(SPDIF_HandleTypeDef *hspdif);
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#endif
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