/* ****************************************************************************** * @file driver_spdif.h * @author FreqChip Firmware Team * @version V1.0.0 * @date 2023 * @brief Header file of SPDIF module. ****************************************************************************** * @attention * * Copyright (c) 2023 FreqChip. * All rights reserved. ****************************************************************************** */ #ifndef __DRIVER_SPDIF_H__ #define __DRIVER_SPDIF_H__ #include "fr30xx.h" /** @addtogroup SPDIF_Registers_Section * @{ */ /* ################################ Register Section Start ################################ */ /* SPDIF CTRL REG */ typedef struct { uint32_t TSAMPLERATE : 8; uint32_t SFR_ENABLE : 1; uint32_t SPDIF_ENABLE : 1; uint32_t FIFO_ENABLE : 1; uint32_t CLK_ENABLE : 1; uint32_t TR_MODE : 1; uint32_t PARITY_CHECK : 1; uint32_t PARITYGEN : 1; uint32_t VALIDITY_CHECK : 1; uint32_t CHANNEL_MODE : 1; uint32_t DUPLICATE : 1; uint32_t SETPREAMBB : 1; uint32_t rsv_0 : 2; uint32_t PARITY_MASK : 1; uint32_t UNDERR_MASK : 1; uint32_t OVERR_MASK : 1; uint32_t EMPTY_MASK : 1; uint32_t ALEMPTY_MASK : 1; uint32_t FULL_MASK : 1; uint32_t ALFULL_MASK : 1; uint32_t SYNCERR_MASK : 1; uint32_t LOCK_MASK : 1; uint32_t BEGIN_MASK : 1; uint32_t INTREQ_MASK : 1; } REG_SPDIF_CTRL_t; /* SPDIF INT REG */ typedef struct { uint32_t RSAMPLERATE : 8; uint32_t PREAMBLEDEL : 4; uint32_t rsv_0 : 9; uint32_t PARITYO : 1; uint32_t TDATA_UNDERR : 1; uint32_t RDATA_OVERR : 1; uint32_t FIFO_EMPTY : 1; uint32_t FIFO_ALEMPTY : 1; uint32_t FIFO_FULL : 1; uint32_t FIFO_ALFULL : 1; uint32_t SYNC_ERR : 1; uint32_t LOCK : 1; uint32_t BLOCK_BEGIN : 1; uint32_t rsv_1 : 1; } REG_SPDIF_INT_t; /* SPDIF FIFO CTRL REG */ typedef struct { uint32_t ALEMPTY_THRESHOLD : 7; uint32_t rsv_0 : 1; uint32_t HALFULL_THRESHOLD : 7; uint32_t rsv_1 : 1; uint32_t PARITY_INT_TYPE : 1; uint32_t UNDERR_INT_TYPE : 1; uint32_t OVERR_INT_TYPE : 1; uint32_t FF_EMPTY_INT_TYPE : 1; uint32_t FF_ALEMPTY_INT_TYPE : 1; uint32_t FF_FULL_INT_TYPE : 1; uint32_t FF_ALFULL_INT_TYPE : 1; uint32_t SYNCERR_INT_TYPE : 1; uint32_t LOCK_INT_TYPE : 1; uint32_t BLOCK_BEGIN_INT_TYPE : 1; uint32_t rsv_2 : 6; } REG_SPDIF_FIFO_CTRL_t; typedef struct { volatile REG_SPDIF_CTRL_t SPDIF_CTRL; /* Offset 0x00 */ volatile uint32_t SPDIF_INT_CLEAR; /* Offset 0x04 */ volatile REG_SPDIF_FIFO_CTRL_t SPDIF_FIFO_CTRL; /* Offset 0x08 */ volatile uint32_t SPDIF_INT_STS; /* Offset 0x0C */ volatile uint32_t SPDIF_FIFO_DATA; /* Offset 0x10 */ }struct_SPDIF_t; #define SPDIF ((struct_SPDIF_t *)SPDIF_BASE) /* ################################ Register Section END ################################## */ /** * @} */ /** @addtogroup SPDIF_Initialization_Config_Section * @{ */ /* ################################ Initialization_Config Section Start ################################ */ /* Interrupt Status */ typedef enum { PARITY_FLAG = 0x200000, UNDERR_FLAG = 0x400000, OVERR_FLAG = 0x800000, EMPTY_FLAG = 0x1000000, ALEMPTY_FLAG = 0x2000000, FULL_FLAG = 0x4000000, ALFULL_FLAG = 0x8000000, SYNCERR_FLAG = 0x10000000, LOCK_FLAG = 0x20000000, BEGIN_FLAG = 0x40000000, RIGHT_LEFT = 0x80000000, }enum_SPDIF_INT_Index_t; /* MonoStere Select */ typedef enum { SPDIF_STEREO, SPDIF_MONO, }enum_SPDIF_MonoStere_Sel_t; /* * @brief SPDIF Init Structure definition */ typedef struct { uint8_t TxSampleRate; /*!< Specifies the internal Send sample rate. This parameter The value can be a value 0~0x7F*/ uint8_t CH_Mode; /*!< Specifies the internal Channel selection. This parameter can be a value of @ref enum_SPDIF_MonoStere_Sel_t*/ uint8_t RSAMPLERATE; /*!< Specifies the internal Send receive rate. This parameter The value can be a value 0~0x7F*/ uint8_t PREAMBLEDEL; /*!< Specifies the internal Leader B delay. This parameter The value can be a value 0~0xF*/ uint8_t ALFIFOEmpty_Threshold; /*!< Specifies the internal FIFO Almost EMPTY Level. This parameter The value can be a value 0~0x3F*/ uint8_t HALFIFOFull_Threshold; /*!< Specifies the internal FIFO Half FULL Level. This parameter The value can be a value 0~0x3F*/ }struct_SPDIF_Init_t; /* * @brief SPDIF handle Structure definition */ typedef struct __SPDIF_HandleTypeDef { struct_SPDIF_Init_t Init; /*!< SPDIF communication parameters */ void (*TxCallback)(struct __SPDIF_HandleTypeDef *hspdif); /*!< Callback */ void (*RxCallback)(struct __SPDIF_HandleTypeDef *hspdif); /*!< Callback */ volatile bool b_TxBusy; /*!< SPDIF Receive and Send parameters in interrupt */ volatile bool b_RxBusy; volatile uint32_t *p_TxData; volatile uint32_t u32_TxCount; volatile uint32_t u32_TxSize; volatile uint32_t *p_RxData; volatile uint32_t u32_RxCount; }SPDIF_HandleTypeDef; /* ################################ Initialization_Config Section END ################################## */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* SPDIF Enable Diable */ #define __SPDIF_ENABLE() (SPDIF->SPDIF_CTRL.SPDIF_ENABLE = 1) #define __SPDIF_DISABLE() (SPDIF->SPDIF_CTRL.SPDIF_ENABLE = 0) /* FIFO/TxFIFO level */ #define __SPDIF_FIFO_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_STS = __LEVEL__) /* FIFO HALFULL and ALEMPTY Threshold level */ #define __SPDIF_FIFO_HALF_FULL_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_CTRL.HALFULL_THRESHOLD = __LEVEL__) #define __SPDIF_FIFO_ALMOST_EMPTY_LEVEL(__LEVEL__) (SPDIF->SPDIF_FIFO_CTRL.ALEMPTY_THRESHOLD = __LEVEL__) /* Get Interrupt Status */ #define __SPDIF_GET_INT_STATUS() (SPDIF->SPDIF_INT_STS) /* FIFO Interrupt ALEMPTY ALFULL Enable and Disable */ #define __SPDIF_ENABLE_ALEMPTY_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 1; \ SPDIF->SPDIF_CTRL.ALEMPTY_MASK = 1;}while(0) #define __SPDIF_DISABLE_ALEMPTY_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 0; \ SPDIF->SPDIF_CTRL.ALEMPTY_MASK = 0;}while(0) #define __SPDIF_ENABLE_ALFULL_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 1; \ SPDIF->SPDIF_CTRL.SYNCERR_MASK = 1; \ SPDIF->SPDIF_CTRL.ALFULL_MASK = 1;}while(0) #define __SPDIF_DISABLE_ALFULL_INT() do{ SPDIF->SPDIF_CTRL.INTREQ_MASK = 0; \ SPDIF->SPDIF_CTRL.SYNCERR_MASK = 0; \ SPDIF->SPDIF_CTRL.ALFULL_MASK = 0;}while(0) /* Get FIFO Interrupt Enable */ #define __SPDIF_IS_INT_ALEMPTY() (SPDIF->SPDIF_CTRL.ALEMPTY_MASK) #define __SPDIF_IS_INT_ALFULL() (SPDIF->SPDIF_CTRL.ALFULL_MASK) #define __SPDIF_IS_INT_SYNCERR() (SPDIF->SPDIF_CTRL.SYNCERR_MASK) /* TR MODE */ #define __SPDIF_Tx_MODE() (SPDIF->SPDIF_CTRL.TR_MODE = 1) #define __SPDIF_Rx_MODE() (SPDIF->SPDIF_CTRL.TR_MODE = 0) /* Exported functions -------------------------------------------------------------------------*/ void spdif_init(SPDIF_HandleTypeDef *hspdif); bool spdif_msg_send(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data, uint32_t fu32_Size); bool spdif_msg_send_IT(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data, uint32_t fu32_Size); bool spdif_msg_receive(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data); bool spdif_msg_receive_IT(SPDIF_HandleTypeDef *hspdif, uint32_t *fp_Data); void SPDIF_IRQHandler(SPDIF_HandleTypeDef *hspdif); #endif